diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/changelog crystalhd-0.0~git20101029.6df10a0/debian/changelog --- crystalhd-0.0~git20101012.a3a83b8/debian/changelog 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/changelog 2010-10-29 18:16:26.000000000 +0000 @@ -1,13 +1,12 @@ -crystalhd (1:0.0~git20101012.a3a83b8-1~) hardy; urgency=low +crystalhd (1:0.0~git20101029.6df10a0-1~) hardy; urgency=low - * Upload for XBMC PPA. - * Don't include gstreamer plugin. - * Fix dh addons options for older version of debhelper. + * Upload to XBMC PPA. + * This is really version 1:0.0~git20100815.6df10a0-1~ with the date changed. - -- Andres Mejia Tue, 12 Oct 2010 20:20:02 -0400 + -- Andres Mejia Fri, 29 Oct 2010 13:50:31 -0400 -crystalhd (1:0.0~git20101012.a3a83b8-1) unstable; urgency=low +crystalhd (1:0.0~git20100815.6df10a0-1) unstable; urgency=low * Initial release. (Closes: #577130) - -- Andres Mejia Mon, 13 Sep 2010 13:54:52 -0400 + -- Andres Mejia Mon, 16 Aug 2010 01:56:06 -0400 diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/control crystalhd-0.0~git20101029.6df10a0/debian/control --- crystalhd-0.0~git20101012.a3a83b8/debian/control 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/control 2010-10-29 18:16:26.000000000 +0000 @@ -1,15 +1,14 @@ Source: crystalhd -Priority: optional -Maintainer: Andres Mejia -Uploaders: Ouattara Oumar Aziz (alias wattazoum) -Build-Depends: debhelper (>= 7.0.50~), - quilt (>= 0.46-7~), - dkms +Priority: extra +Maintainer: Debian multimedia packages maintainers +Uploaders: Andres Mejia , + Ouattara Oumar Aziz (alias wattazoum) +Build-Depends: debhelper (>= 7.0.50~), quilt (>= 0.46-7~), Standards-Version: 3.9.1 Section: libs Homepage: http://www.broadcom.com/support/crystal_hd/ -Vcs-Git: git://git.debian.org/git/collab-maint/crystalhd.git -Vcs-Browser: http://git.debian.org/?p=collab-maint/crystalhd.git +Vcs-Git: git://git.debian.org/git/pkg-multimedia/crystalhd.git +Vcs-Browser: http://git.debian.org/?p=pkg-multimedia/crystalhd.git Package: libcrystalhd-dev Section: libdevel @@ -24,6 +23,7 @@ This package contains the files necessary for development. Package: libcrystalhd3 +Section: libs Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} Description: Crystal HD Video Decoder (shared library) @@ -32,26 +32,3 @@ systems. . This package contains the shared library. - -Package: crystalhd-dkms -Section: kernel -Architecture: linux-any -Depends: ${shlibs:Depends}, ${misc:Depends}, dkms -Suggests: linux-headers -Description: Crystal HD Video Decoder (Linux kernel driver) - Crystal HD Solution is a product offered by Broadcom. It is used to enable - flawless playback of 1080p high definition video across a wide range of - systems. - . - This package contains the crystalhd Linux kernel driver. - -# Package: gstreamer0.10-crystalhd -# Section: video -# Architecture: any -# Depends: ${shlibs:Depends}, ${misc:Depends} -# Description: Crystal HD Video Decoder (GStreamer plugin) -# Crystal HD Solution is a product offered by Broadcom. It is used to enable -# flawless playback of 1080p high definition video across a wide range of -# systems. -# . -# This package contains the crystalhd GStreamer plugin. diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/crystalhd-dkms.dkms crystalhd-0.0~git20101029.6df10a0/debian/crystalhd-dkms.dkms --- crystalhd-0.0~git20101012.a3a83b8/debian/crystalhd-dkms.dkms 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/crystalhd-dkms.dkms 1970-01-01 00:00:00.000000000 +0000 @@ -1,11 +0,0 @@ -# DKMS configuration for crystalhd - -PACKAGE_NAME="crystalhd" -PACKAGE_VERSION="#MODULE_VERSION#" -BUILT_MODULE_NAME[0]="$PACKAGE_NAME" -BUILT_MODULE_LOCATION[0]=driver/linux -DEST_MODULE_LOCATION[0]="/updates/dkms/" -AUTOINSTALL=yes - -MAKE[0]="cd driver/linux && ./configure && make" -CLEAN="make -C driver/linux clean distclean" diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/crystalhd-dkms.install crystalhd-0.0~git20101029.6df10a0/debian/crystalhd-dkms.install --- crystalhd-0.0~git20101012.a3a83b8/debian/crystalhd-dkms.install 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/crystalhd-dkms.install 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -usr/src diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/crystalhd-get-orig-source crystalhd-0.0~git20101029.6df10a0/debian/crystalhd-get-orig-source --- crystalhd-0.0~git20101012.a3a83b8/debian/crystalhd-get-orig-source 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/crystalhd-get-orig-source 2010-10-29 18:16:26.000000000 +0000 @@ -3,8 +3,8 @@ # Script used to generate the orig source tarball for crystalhd. CRYSTALHD_GIT_URL="git://git.wilsonet.com/crystalhd.git" -CRYSTALHD_GIT_COMMIT="a3a83b8cee454bafd83ccaaa5e35029d6c409c9d" -DATE_RETRIEVED="20101012" +CRYSTALHD_GIT_COMMIT="6df10a0599b5adf7e6f08529f0954a3fa24ad0ad" +DATE_RETRIEVED="20100815" COMMIT_SHORT_FORM="$(echo $CRYSTALHD_GIT_COMMIT | \ sed -e 's/^\([[:xdigit:]]\{,7\}\).*/\1/')" CRYSTALHD_VERSION="0.0~git${DATE_RETRIEVED}.${COMMIT_SHORT_FORM}" @@ -12,29 +12,8 @@ git clone "$CRYSTALHD_GIT_URL" "crystalhd-${CRYSTALHD_VERSION}" cd "crystalhd-${CRYSTALHD_VERSION}" git checkout "$CRYSTALHD_GIT_COMMIT" -rm -rf .git firmware -find . -name .gitignore -delete - -# Setup build systems -autoreconf -vif driver/linux -cd filters/gst/gst-plugin -./autogen.sh -make clean distclean -cd ../../../.. - -# Remove temp files and other cruft from source tarball -# The find command snippet here was taken from debhelper's dh_clean command -# with some modification to delete more unneeded files. -echo "Removing temp files and other cruft from source tarball" -find crystalhd-${CRYSTALHD_VERSION} \( \( -type f -a \ - \( -name '#*#' -o -name '.*~' -o -name '*~' -o -name DEADJOE \ - -o -name '*.orig' -o -name '*.rej' -o -name '*.bak' \ - -o -name '.*.orig' -o -name .*.rej -o -name '.SUMS' \ - -o -name TAGS -o \( -path '*/.deps/*' -a -name '*.P' \) \ - -o -name config.status -o -name config.cache -o -name config.log \ - \) -exec rm -f "{}" \; \) -o \ - \( -type d -a -name autom4te.cache -prune -exec rm -rf "{}" \; \) \) - -# Generate tarball +rm -rf .git .gitignore driver examples filters firmware include/flea \ + export-driver-for-staging.sh +cd .. tar --exclude-vcs -czf "crystalhd_${CRYSTALHD_VERSION}.orig.tar.gz" \ "crystalhd-${CRYSTALHD_VERSION}/" diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/gstreamer0.10-crystalhd.install crystalhd-0.0~git20101029.6df10a0/debian/gstreamer0.10-crystalhd.install --- crystalhd-0.0~git20101012.a3a83b8/debian/gstreamer0.10-crystalhd.install 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/gstreamer0.10-crystalhd.install 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -usr/lib/gstreamer-0.10/*.so diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/rules crystalhd-0.0~git20101029.6df10a0/debian/rules --- crystalhd-0.0~git20101012.a3a83b8/debian/rules 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/rules 2010-10-29 18:16:26.000000000 +0000 @@ -1,37 +1,13 @@ #!/usr/bin/make -f - -UPSTREAM_VERSION = $(shell dpkg-parsechangelog | grep -G '^Version' | \ - cut -d ' ' -f 2 | sed 's/^[^:]:*//' | sed 's/-.*$$//') - -EXTRA_INCLUDES = -I$(CURDIR)/include \ - -I$(CURDIR)/linux_lib/libcrystalhd - -EXTRA_LD_PATH = -L$(CURDIR)/linux_lib/libcrystalhd - %: - dh --with quilt --with dkms $@ + dh --with quilt $@ override_dh_auto_build: make -C linux_lib/libcrystalhd -# cd filters/gst/gst-plugin && \ -# ./configure --prefix=/usr CFLAGS="$(EXTRA_INCLUDES)" \ -# LDFLAGS="$(EXTRA_LD_PATH)" -# make -C filters/gst/gst-plugin override_dh_auto_install: make install -C linux_lib/libcrystalhd DESTDIR=$(CURDIR)/debian/tmp -# make install -C filters/gst/gst-plugin DESTDIR=$(CURDIR)/debian/tmp - mkdir -p $(CURDIR)/debian/tmp/usr/src/crystalhd-$(UPSTREAM_VERSION) - cp -rf driver $(CURDIR)/debian/tmp/usr/src/crystalhd-$(UPSTREAM_VERSION) - cp -rf include $(CURDIR)/debian/tmp/usr/src/crystalhd-$(UPSTREAM_VERSION) - rm -f $(CURDIR)/debian/tmp/usr/src/crystalhd-$(UPSTREAM_VERSION)/driver/linux/bcm_70012_dev.sh - rm -f $(CURDIR)/debian/tmp/usr/src/crystalhd-$(UPSTREAM_VERSION)/driver/linux/bcm_70012_run.sh override_dh_auto_clean: dh_clean make clean -C linux_lib/libcrystalhd - [ ! -f filters/gst/gst-plugin/Makefile ] || \ - make clean distclean -C filters/gst/gst-plugin - -override_dh_dkms: - dh_dkms -V $(UPSTREAM_VERSION) diff -Nru crystalhd-0.0~git20101012.a3a83b8/debian/watch crystalhd-0.0~git20101029.6df10a0/debian/watch --- crystalhd-0.0~git20101012.a3a83b8/debian/watch 2010-10-29 18:16:26.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/debian/watch 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -# Upstream currently has no releases. diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/20-crystalhd.rules crystalhd-0.0~git20101029.6df10a0/driver/linux/20-crystalhd.rules --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/20-crystalhd.rules 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/20-crystalhd.rules 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -KERNEL=="crystalhd", MODE="0666" diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/bcm_70012_dev.sh crystalhd-0.0~git20101029.6df10a0/driver/linux/bcm_70012_dev.sh --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/bcm_70012_dev.sh 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/bcm_70012_dev.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,56 +0,0 @@ -#!/bin/bash -# -# Author: Prasad Bolisetty -# -# Script to load broadcom 70012 module and create device node. -# -# - -bcm_dev_bin="bcm70012" -bcm_dev_name="crystalhd" -bcm_node="/dev/crystalhd" - -if ! whoami | grep root > /dev/null ; then - echo " Login as root and try.." - exit 1; -fi - -bcm_pci_id=`lspci -d 14e4:1612` -if [ $? -ne 0 -o -z "$bcm_pci_id" ]; then - echo "BCM 70012 not installed.." - exit 1; -fi - -if lsmod | grep $bcm_dev_bin > /dev/null ; then - echo "Stopping Broadcom MediaPC 70012 Module" - rmmod $bcm_dev_bin >& /dev/null - if [ $? -ne 0 ]; then - echo "Failed to stop: Close applications and try again. " - exit 1; - fi -fi - -bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` - -if [ -z "$bcm_major" ]; then - modinfo $bcm_dev_bin >& /dev/null - if [ $? -ne 0 ]; then - echo "Broadcom MediaPC 70012 Kernel Module not installed" - exit 1; - fi - modprobe $bcm_dev_bin >& /dev/null - bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` - if [ $? -ne 0 -o -z "$bcm_major" ]; then - echo "Error($bcm_major): Loading Broadcom MediaPC 70012 Module" - rmmod $bcm_dev_bin >& /dev/null - exit 1; - fi -fi -if [ -c $bcm_node ]; then - rm -f $bcm_node >& /dev/null -fi - -mknod -m 666 $bcm_node c $bcm_major 0 - -echo "Broadcom MediaPC 70012 Module loaded" - diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/bcm_70012_run.sh crystalhd-0.0~git20101029.6df10a0/driver/linux/bcm_70012_run.sh --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/bcm_70012_run.sh 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/bcm_70012_run.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,47 +0,0 @@ -#!/bin/bash -# -# Author: Prasad Bolisetty -# -# Script to load broadcom 70012 module and create device node. -# -# - -bcm_dev_bin="crystalhd" -bcm_dev_bin_ko="crystalhd.ko" -bcm_dev_name="crystalhd" -bcm_node="/dev/crystalhd" - -if ! whoami | grep root > /dev/null ; then - echo " Login as root and try.." - exit 1; -fi - - -if /sbin/lsmod | grep $bcm_dev_bin > /dev/null ; then - echo "Stopping Broadcom Crystal HD (BCM70012) Module" - /sbin/rmmod $bcm_dev_bin >& /dev/null - if [ $? -ne 0 ]; then - echo "Failed to stop: Close applications and try again. " - exit 1; - fi -fi - -bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` - -if [ -z "$bcm_major" ]; then - /sbin/insmod $bcm_dev_bin_ko >& /dev/null - bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` - if [ $? -ne 0 -o -z "$bcm_major" ]; then - echo "Error($bcm_major): Loading Broadcom Crystal HD (BCM70012) Module" - rmmod $bcm_dev_bin >& /dev/null - exit 1; - fi -fi -if [ -c $bcm_node ]; then - rm -f $bcm_node >& /dev/null -fi - -mknod -m 666 $bcm_node c $bcm_major 0 - -echo "Broadcom Crystal HD (BCM70012) Module loaded" - diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/configure crystalhd-0.0~git20101029.6df10a0/driver/linux/configure --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/configure 2010-10-12 20:47:16.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/configure 1970-01-01 00:00:00.000000000 +0000 @@ -1,2903 +0,0 @@ -#! /bin/sh -# Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.67. -# -# -# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, -# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software -# Foundation, Inc. -# -# -# This configure script is free software; the Free Software Foundation -# gives unlimited permission to copy, distribute and modify it. -## -------------------- ## -## M4sh Initialization. ## -## -------------------- ## - -# Be more Bourne compatible -DUALCASE=1; export DUALCASE # for MKS sh -if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : - emulate sh - NULLCMD=: - # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which - # is contrary to our usage. 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See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#include "crystalhd_lnx.h" - -static struct crystalhd_user *bc_cproc_get_uid(struct crystalhd_cmd *ctx) -{ - struct crystalhd_user *user = NULL; - int i; - - for (i = 0; i < BC_LINK_MAX_OPENS; i++) { - if (!ctx->user[i].in_use) { - user = &ctx->user[i]; - break; - } - } - - return user; -} - -static int bc_cproc_get_user_count(struct crystalhd_cmd *ctx) -{ - int i, count = 0; - - for (i = 0; i < BC_LINK_MAX_OPENS; i++) { - if (ctx->user[i].in_use) - count++; - } - - return count; -} - -static void bc_cproc_mark_pwr_state(struct crystalhd_cmd *ctx) -{ - int i; - - for (i = 0; i < BC_LINK_MAX_OPENS; i++) { - if (!ctx->user[i].in_use) - continue; - if ((ctx->user[i].mode & 0xFF) == DTS_DIAG_MODE || - (ctx->user[i].mode & 0xFF) == DTS_PLAYBACK_MODE) { - ctx->pwr_state_change = 1; - break; - } - } -} - -static BC_STATUS bc_cproc_notify_mode(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - struct device *dev = chddev(); - int rc = 0, i = 0; - - if (!ctx || !idata) { - dev_err(dev, "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - if (ctx->user[idata->u_id].mode != DTS_MODE_INV) { - dev_err(dev, "Close the handle first..\n"); - return BC_STS_ERR_USAGE; - } - - if ((idata->udata.u.NotifyMode.Mode && 0xFF) == DTS_MONITOR_MODE) { - ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; - return BC_STS_SUCCESS; - } - - if (ctx->state != BC_LINK_INVALID) { - dev_err(dev, "Link invalid state notify mode %d \n", ctx->state); - return BC_STS_ERR_USAGE; - } - /* Check for duplicate playback sessions..*/ - for (i = 0; i < BC_LINK_MAX_OPENS; i++) { - if ((ctx->user[i].mode & 0xFF) == DTS_DIAG_MODE || - (ctx->user[i].mode & 0xFF) == DTS_PLAYBACK_MODE) { - dev_err(dev, "multiple playback sessions are not " - "supported..\n"); - return BC_STS_ERR_USAGE; - } - } - ctx->cin_wait_exit = 0; - - ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; - /* Create list pools */ - rc = crystalhd_create_elem_pool(ctx->adp, BC_LINK_ELEM_POOL_SZ); - if (rc) - return BC_STS_ERROR; - /* Setup mmap pool for uaddr sgl mapping..*/ - rc = crystalhd_create_dio_pool(ctx->adp, BC_LINK_MAX_SGLS); - if (rc) - return BC_STS_ERROR; - - /* Setup Hardware DMA rings */ - return crystalhd_hw_setup_dma_rings(ctx->hw_ctx); -} - -static BC_STATUS bc_cproc_get_version(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - if (!ctx || !idata) { - dev_err(chddev(), "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - idata->udata.u.VerInfo.DriverMajor = crystalhd_kmod_major; - idata->udata.u.VerInfo.DriverMinor = crystalhd_kmod_minor; - idata->udata.u.VerInfo.DriverRevision = crystalhd_kmod_rev; - return BC_STS_SUCCESS; -} - - -static BC_STATUS bc_cproc_get_hwtype(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) -{ - if (!ctx || !idata) { - dev_err(chddev(), "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - crystalhd_pci_cfg_rd(ctx->adp, 0, 2, - (uint32_t *)&idata->udata.u.hwType.PciVenId); - crystalhd_pci_cfg_rd(ctx->adp, 2, 2, - (uint32_t *)&idata->udata.u.hwType.PciDevId); - crystalhd_pci_cfg_rd(ctx->adp, 8, 1, - (uint32_t *)&idata->udata.u.hwType.HwRev); - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_reg_rd(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - if (!ctx || !idata) - return BC_STS_INV_ARG; - idata->udata.u.regAcc.Value = ctx->hw_ctx->pfnReadDevRegister(ctx->adp, - idata->udata.u.regAcc.Offset); - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_reg_wr(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - if (!ctx || !idata) - return BC_STS_INV_ARG; - - ctx->hw_ctx->pfnWriteDevRegister(ctx->adp, idata->udata.u.regAcc.Offset, - idata->udata.u.regAcc.Value); - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_link_reg_rd(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - if (!ctx || !idata) - return BC_STS_INV_ARG; - - idata->udata.u.regAcc.Value = ctx->hw_ctx->pfnReadFPGARegister(ctx->adp, - idata->udata.u.regAcc.Offset); - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_link_reg_wr(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - if (!ctx || !idata) - return BC_STS_INV_ARG; - - ctx->hw_ctx->pfnWriteFPGARegister(ctx->adp, idata->udata.u.regAcc.Offset, - idata->udata.u.regAcc.Value); - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_mem_rd(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - if (!ctx || !idata || !idata->add_cdata) - return BC_STS_INV_ARG; - - if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { - dev_err(chddev(), "insufficient buffer\n"); - return BC_STS_INV_ARG; - } - sts = ctx->hw_ctx->pfnDevDRAMRead(ctx->hw_ctx, idata->udata.u.devMem.StartOff, - idata->udata.u.devMem.NumDwords, - (uint32_t *)idata->add_cdata); - return sts; - -} - -static BC_STATUS bc_cproc_mem_wr(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - if (!ctx || !idata || !idata->add_cdata) - return BC_STS_INV_ARG; - - if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { - dev_err(chddev(), "insufficient buffer\n"); - return BC_STS_INV_ARG; - } - - sts = ctx->hw_ctx->pfnDevDRAMWrite(ctx->hw_ctx, idata->udata.u.devMem.StartOff, - idata->udata.u.devMem.NumDwords, - (uint32_t *)idata->add_cdata); - return sts; -} - -static BC_STATUS bc_cproc_cfg_rd(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - uint32_t ix, cnt, off, len; - BC_STATUS sts = BC_STS_SUCCESS; - uint32_t *temp; - - if (!ctx || !idata) - return BC_STS_INV_ARG; - - temp = (uint32_t *) idata->udata.u.pciCfg.pci_cfg_space; - off = idata->udata.u.pciCfg.Offset; - len = idata->udata.u.pciCfg.Size; - - if (len <= 4) { - sts = crystalhd_pci_cfg_rd(ctx->adp, off, len, temp); - return sts; - } - - /* Truncate to dword alignment..*/ - len = 4; - cnt = idata->udata.u.pciCfg.Size / len; - for (ix = 0; ix < cnt; ix++) { - sts = crystalhd_pci_cfg_rd(ctx->adp, off, len, &temp[ix]); - if (sts != BC_STS_SUCCESS) { - dev_err(chddev(), "config read : %d\n", sts); - return sts; - } - off += len; - } - - return sts; -} - -static BC_STATUS bc_cproc_cfg_wr(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - uint32_t ix, cnt, off, len; - BC_STATUS sts = BC_STS_SUCCESS; - uint32_t *temp; - - if (!ctx || !idata) - return BC_STS_INV_ARG; - - temp = (uint32_t *) idata->udata.u.pciCfg.pci_cfg_space; - off = idata->udata.u.pciCfg.Offset; - len = idata->udata.u.pciCfg.Size; - - if (len <= 4) - return crystalhd_pci_cfg_wr(ctx->adp, off, len, temp[0]); - - /* Truncate to dword alignment..*/ - len = 4; - cnt = idata->udata.u.pciCfg.Size / len; - for (ix = 0; ix < cnt; ix++) { - sts = crystalhd_pci_cfg_wr(ctx->adp, off, len, temp[ix]); - if (sts != BC_STS_SUCCESS) { - dev_err(chddev(), "config write : %d\n", sts); - return sts; - } - off += len; - } - - return sts; -} - -static BC_STATUS bc_cproc_download_fw(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - dev_dbg(chddev(), "Downloading FW\n"); - - if (!ctx || !idata || !idata->add_cdata || !idata->add_cdata_sz) { - dev_err(chddev(), "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - if (ctx->state != BC_LINK_INVALID) { - dev_err(chddev(), "Link invalid state download fw %d \n", ctx->state); - return BC_STS_ERR_USAGE; - } - - sts = ctx->hw_ctx->pfnFWDwnld(ctx->hw_ctx, (uint8_t *)idata->add_cdata, - idata->add_cdata_sz); - - if (sts != BC_STS_SUCCESS) { - dev_info(chddev(), "Firmware Download Failure!! - %d\n", sts); - } else - ctx->state |= BC_LINK_INIT; - - ctx->hw_ctx->FwCmdCnt = 0; - return sts; -} - -/* - * We use the FW_CMD interface to sync up playback state with application - * and firmware. This function will perform the required pre and post - * processing of the Firmware commands. - * - * Pause - - * Disable capture after decoder pause. - * Resume - - * First enable capture and issue decoder resume command. - * Flush - - * Abort pending input transfers and issue decoder flush command. - * - */ -static BC_STATUS bc_cproc_do_fw_cmd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) -{ - struct device *dev = chddev(); - BC_STATUS sts; - uint32_t *cmd; - - if (!(ctx->state & BC_LINK_INIT)) { - dev_err(dev, "Link invalid state do fw cmd %d \n", ctx->state); - return BC_STS_ERR_USAGE; - } - - cmd = idata->udata.u.fwCmd.cmd; - - /* Pre-Process */ - if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { - if (!cmd[3]) { - ctx->state &= ~BC_LINK_PAUSED; - ctx->hw_ctx->pfnIssuePause(ctx->hw_ctx, false); - } - } else if (cmd[0] == eCMD_C011_DEC_CHAN_FLUSH) { - dev_dbg(dev, "Flush issued\n"); - if (cmd[3]) - ctx->cin_wait_exit = 1; - } - - sts = ctx->hw_ctx->pfnDoFirmwareCmd(ctx->hw_ctx, &idata->udata.u.fwCmd); - - if (sts != BC_STS_SUCCESS) { - dev_info(dev, "fw cmd %x failed\n", cmd[0]); - return sts; - } - - /* Post-Process */ - if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { - if (cmd[3]) { - ctx->state |= BC_LINK_PAUSED; - ctx->hw_ctx->pfnIssuePause(ctx->hw_ctx, true); - } - } - - return sts; -} - -static void bc_proc_in_completion(crystalhd_dio_req *dio_hnd, - wait_queue_head_t *event, BC_STATUS sts) -{ - if (!dio_hnd || !event) { - dev_err(chddev(), "%s: Invalid Arg\n", __func__); - return; - } - if (sts == BC_STS_IO_USER_ABORT) - return; - - dio_hnd->uinfo.comp_sts = sts; - dio_hnd->uinfo.ev_sts = 1; - crystalhd_set_event(event); -} - -static BC_STATUS bc_cproc_codein_sleep(struct crystalhd_cmd *ctx) -{ - wait_queue_head_t sleep_ev; - int rc = 0; - - if (ctx->state & BC_LINK_SUSPEND) - return BC_STS_IO_USER_ABORT; - - if (ctx->cin_wait_exit) { - ctx->cin_wait_exit = 0; - return BC_STS_CMD_CANCELLED; - } - crystalhd_create_event(&sleep_ev); - crystalhd_wait_on_event(&sleep_ev, 0, 100, rc, false); - if (rc == -EINTR) - return BC_STS_IO_USER_ABORT; - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_hw_txdma(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata, - crystalhd_dio_req *dio) -{ - struct device *dev = chddev(); - uint32_t tx_listid = 0; - BC_STATUS sts = BC_STS_SUCCESS; - wait_queue_head_t event; - int rc = 0; - - if (!ctx || !idata || !dio) { - dev_err(dev, "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - crystalhd_create_event(&event); - - ctx->tx_list_id = 0; - /* msleep_interruptible(2000); */ - sts = crystalhd_hw_post_tx(ctx->hw_ctx, dio, bc_proc_in_completion, - &event, &tx_listid, - idata->udata.u.ProcInput.Encrypted); - - while (sts == BC_STS_BUSY) { - sts = bc_cproc_codein_sleep(ctx); - if (sts != BC_STS_SUCCESS) - break; - sts = crystalhd_hw_post_tx(ctx->hw_ctx, dio, - bc_proc_in_completion, - &event, &tx_listid, - idata->udata.u.ProcInput.Encrypted); - } - if (sts != BC_STS_SUCCESS) { - dev_dbg(dev, "_hw_txdma returning sts:%d\n", sts); - return sts; - } - if (ctx->cin_wait_exit) - ctx->cin_wait_exit = 0; - - ctx->tx_list_id = tx_listid; - - /* _post() succeeded.. wait for the completion. */ - crystalhd_wait_on_event(&event, (dio->uinfo.ev_sts), 3000, rc, false); - ctx->tx_list_id = 0; - if (!rc) { - return dio->uinfo.comp_sts; - } else if (rc == -EBUSY) { - dev_dbg(dev, "_tx_post() T/O \n"); - sts = BC_STS_TIMEOUT; - } else if (rc == -EINTR) { - dev_dbg(dev, "Tx Wait Signal int.\n"); - sts = BC_STS_IO_USER_ABORT; - } else { - sts = BC_STS_IO_ERROR; - } - - /* We are cancelling the IO from the same context as the _post(). - * so no need to wait on the event again.. the return itself - * ensures the release of our resources. - */ - crystalhd_hw_cancel_tx(ctx->hw_ctx, tx_listid); - - return sts; -} - -/* Helper function to check on user buffers */ -static BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, uint32_t ub_sz, - uint32_t uv_off, bool en_422) -{ - struct device *dev = chddev(); - if (!ubuff || !ub_sz) { - dev_err(dev, "%s->Invalid Arg %p %x\n", - ((pin) ? "TX" : "RX"), ubuff, ub_sz); - return BC_STS_INV_ARG; - } - - /* Check for alignment */ - if (((uintptr_t)ubuff) & 0x03) { - dev_err(dev, "%s-->Un-aligned address not implemented yet.. %p \n", - ((pin) ? "TX" : "RX"), ubuff); - return BC_STS_NOT_IMPL; - } - if (pin) - return BC_STS_SUCCESS; - - if (!en_422 && !uv_off) { - dev_err(dev, "Need UV offset for 420 mode.\n"); - return BC_STS_INV_ARG; - } - - if (en_422 && uv_off) { - dev_err(dev, "UV offset in 422 mode ??\n"); - return BC_STS_INV_ARG; - } - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_proc_input(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) -{ - struct device *dev = chddev(); - void *ubuff; - uint32_t ub_sz; - crystalhd_dio_req *dio_hnd = NULL; - BC_STATUS sts = BC_STS_SUCCESS; - - if (!ctx || !idata) { - dev_err(dev, "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - ubuff = idata->udata.u.ProcInput.pDmaBuff; - ub_sz = idata->udata.u.ProcInput.BuffSz; - - sts = bc_cproc_check_inbuffs(1, ubuff, ub_sz, 0, 0); - if (sts != BC_STS_SUCCESS) - return sts; - - sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, 0, 0, 1, &dio_hnd); - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "dio map - %d \n", sts); - return sts; - } - - if (!dio_hnd) - return BC_STS_ERROR; - - sts = bc_cproc_hw_txdma(ctx, idata, dio_hnd); - - crystalhd_unmap_dio(ctx->adp, dio_hnd); - - return sts; -} - -static BC_STATUS bc_cproc_add_cap_buff(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - struct device *dev = chddev(); - void *ubuff; - uint32_t ub_sz, uv_off; - bool en_422; - crystalhd_dio_req *dio_hnd = NULL; - BC_STATUS sts = BC_STS_SUCCESS; - - if (!ctx || !idata) { - dev_err(dev, "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - ubuff = idata->udata.u.RxBuffs.YuvBuff; - ub_sz = idata->udata.u.RxBuffs.YuvBuffSz; - uv_off = idata->udata.u.RxBuffs.UVbuffOffset; - en_422 = idata->udata.u.RxBuffs.b422Mode; - - sts = bc_cproc_check_inbuffs(0, ubuff, ub_sz, uv_off, en_422); - - if (sts != BC_STS_SUCCESS) - return sts; - - sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, uv_off, - en_422, 0, &dio_hnd); - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "dio map - %d \n", sts); - return sts; - } - - if (!dio_hnd) - return BC_STS_ERROR; - - sts = crystalhd_hw_add_cap_buffer(ctx->hw_ctx, dio_hnd, (ctx->state == BC_LINK_READY)); - if ((sts != BC_STS_SUCCESS) && (sts != BC_STS_BUSY)) { - crystalhd_unmap_dio(ctx->adp, dio_hnd); - return sts; - } - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_fmt_change(struct crystalhd_cmd *ctx, - crystalhd_dio_req *dio) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - sts = crystalhd_hw_add_cap_buffer(ctx->hw_ctx, dio, 0); - if (sts != BC_STS_SUCCESS) - return sts; - - ctx->state |= BC_LINK_FMT_CHG; - if (ctx->state == BC_LINK_READY) - sts = crystalhd_hw_start_capture(ctx->hw_ctx); - - return sts; -} - -static BC_STATUS bc_cproc_fetch_frame(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - struct device *dev = chddev(); - crystalhd_dio_req *dio = NULL; - BC_STATUS sts = BC_STS_SUCCESS; - BC_DEC_OUT_BUFF *frame; - - if (!ctx || !idata) { - dev_err(dev, "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - if (!(ctx->state & BC_LINK_CAP_EN)) { - dev_dbg(dev, "Capture not enabled..%x\n", ctx->state); - return BC_STS_ERR_USAGE; - } - - frame = &idata->udata.u.DecOutData; - - sts = crystalhd_hw_get_cap_buffer(ctx->hw_ctx, &frame->PibInfo, &dio); - if (sts != BC_STS_SUCCESS) - return (ctx->state & BC_LINK_SUSPEND) ? BC_STS_IO_USER_ABORT : sts; - - frame->Flags = dio->uinfo.comp_flags; - - if (frame->Flags & COMP_FLAG_FMT_CHANGE) - return bc_cproc_fmt_change(ctx, dio); - - frame->OutPutBuffs.YuvBuff = dio->uinfo.xfr_buff; - frame->OutPutBuffs.YuvBuffSz = dio->uinfo.xfr_len; - frame->OutPutBuffs.UVbuffOffset = dio->uinfo.uv_offset; - frame->OutPutBuffs.b422Mode = dio->uinfo.b422mode; - - frame->OutPutBuffs.YBuffDoneSz = dio->uinfo.y_done_sz; - frame->OutPutBuffs.UVBuffDoneSz = dio->uinfo.uv_done_sz; - - crystalhd_unmap_dio(ctx->adp, dio); - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_start_capture(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - ctx->state |= BC_LINK_CAP_EN; - - if( idata->udata.u.RxCap.PauseThsh ) - ctx->hw_ctx->PauseThreshold = idata->udata.u.RxCap.PauseThsh; - else - ctx->hw_ctx->PauseThreshold = HW_PAUSE_THRESHOLD; - - if( idata->udata.u.RxCap.ResumeThsh ) - ctx->hw_ctx->ResumeThreshold = idata->udata.u.RxCap.ResumeThsh; - else - ctx->hw_ctx->ResumeThreshold = HW_RESUME_THRESHOLD; - - printk(KERN_DEBUG "start_capture: pause_th:%d, resume_th:%d\n", ctx->hw_ctx->PauseThreshold, ctx->hw_ctx->ResumeThreshold); - - ctx->hw_ctx->DrvTotalFrmCaptured = 0; - - ctx->hw_ctx->DefaultPauseThreshold = ctx->hw_ctx->PauseThreshold; // used to restore on FMTCH - - ctx->hw_ctx->pfnNotifyHardware(ctx->hw_ctx, BC_EVENT_START_CAPTURE); - - if (ctx->state == BC_LINK_READY) - return crystalhd_hw_start_capture(ctx->hw_ctx); - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_flush_cap_buffs(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - struct device *dev = chddev(); - crystalhd_rx_dma_pkt *rpkt; - - if (!ctx || !idata) { - dev_err(dev, "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - if (!(ctx->state & BC_LINK_CAP_EN)) - return BC_STS_ERR_USAGE; - - /* We should ack flush even when we are in paused/suspend state */ -// if (!(ctx->state & BC_LINK_READY)) -// return crystalhd_hw_stop_capture(&ctx->hw_ctx); - - dev_dbg(dev, "number of rx success %u and failure %u\n", ctx->hw_ctx->stats.rx_success, ctx->hw_ctx->stats.rx_errors); - if(idata->udata.u.FlushRxCap.bDiscardOnly) { - // just flush without unmapping and then resume - crystalhd_hw_stop_capture(ctx->hw_ctx, false); - while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_actq)) != NULL) - crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); - - while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_rdyq)) != NULL) - crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); - crystalhd_hw_start_capture(ctx->hw_ctx); - } else { - ctx->state &= ~(BC_LINK_CAP_EN|BC_LINK_FMT_CHG); - crystalhd_hw_stop_capture(ctx->hw_ctx, true); - } - - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_get_stats(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - BC_DTS_STATS *stats; - struct crystalhd_hw_stats hw_stats; - uint32_t pic_width; - uint8_t flags = 0; - bool readTxOnly = false; - unsigned long irqflags; - - if (!ctx || !idata) { - dev_err(chddev(), "%s: Invalid Arg\n", __func__); - return BC_STS_INV_ARG; - } - - crystalhd_hw_stats(ctx->hw_ctx, &hw_stats); - - stats = &idata->udata.u.drvStat; - stats->drvRLL = hw_stats.rdyq_count; - stats->drvFLL = hw_stats.freeq_count; - stats->DrvTotalFrmDropped = hw_stats.rx_errors; - stats->DrvTotalHWErrs = hw_stats.rx_errors + hw_stats.tx_errors; - stats->intCount = hw_stats.num_interrupts; - stats->DrvIgnIntrCnt = hw_stats.num_interrupts - - hw_stats.dev_interrupts; - stats->TxFifoBsyCnt = hw_stats.cin_busy; - stats->pauseCount = hw_stats.pause_cnt; - - /* Indicate that we are checking stats on the input buffer for a single threaded application */ - /* this will prevent the HW from going to low power because we assume that once we have told the application */ - /* that we have space in the HW, the app is going to try to DMA. And if we block that DMA, a single threaded application */ - /* will deadlock */ - if(stats->DrvNextMDataPLD & BC_BIT(31)) - { - flags |= 0x08; - // Also for single threaded applications, check to see if we have reduced the power down - // pause threshold to too low and increase it if the RLL is close to the threshold -/* if(pDrvStat->drvRLL >= pDevExt->pHwExten->PauseThreshold) - pDevExt->pHwExten->PauseThreshold++; - PeekNextTS = TRUE;*/ - } - - /* also indicate that we are just checking stats and not posting */ - /* This allows multi-threaded applications to be placed into low power state */ - /* because eveentually the RX thread will wake up the HW when needed */ - flags |= 0x04; - - if (ctx->pwr_state_change) - stats->pwr_state_change = 1; - if (ctx->state & BC_LINK_PAUSED) - stats->DrvPauseTime = 1; - - // use bit 29 of the input status to indicate that we are trying to read VC1 status - // This is important for the BCM70012 which uses a different input queue for VC1 - if(stats->DrvcpbEmptySize & BC_BIT(29)) - flags = 0x2; - // Bit 30 is used to indicate that we are reading only the TX stats and to not touch the Ready list - if(stats->DrvcpbEmptySize & BC_BIT(30)) - readTxOnly = true; - - spin_lock_irqsave(&ctx->hw_ctx->lock, irqflags); - ctx->hw_ctx->pfnCheckInputFIFO(ctx->hw_ctx, 0, &stats->DrvcpbEmptySize, - false, &flags); - spin_unlock_irqrestore(&ctx->hw_ctx->lock, irqflags); - - /* status peek ahead to retreive the next decoded frame timestamp */ -// if (!readTxOnly && stats->drvRLL && (stats->DrvNextMDataPLD & BC_BIT(31))) { - if (!readTxOnly && stats->drvRLL) { - pic_width = stats->DrvNextMDataPLD & 0xffff; - stats->DrvNextMDataPLD = 0; - if (pic_width <= 1920) { - // get fetch lock to make sure that fetch is not in progress as wel peek - if(down_interruptible(&ctx->hw_ctx->fetch_sem)) - goto get_out; - if(ctx->hw_ctx->pfnPeekNextDeodedFr(ctx->hw_ctx,&stats->DrvNextMDataPLD, &stats->picNumFlags, pic_width)) { - // Check in case we dropped a picture here - crystalhd_hw_stats(ctx->hw_ctx, &hw_stats); - stats->drvRLL = hw_stats.rdyq_count; - stats->drvFLL = hw_stats.freeq_count; - } - up(&ctx->hw_ctx->fetch_sem); - } - } - -get_out: - return BC_STS_SUCCESS; -} - -static BC_STATUS bc_cproc_reset_stats(struct crystalhd_cmd *ctx, - crystalhd_ioctl_data *idata) -{ - crystalhd_hw_stats(ctx->hw_ctx, NULL); - - return BC_STS_SUCCESS; -} - -/*=============== Cmd Proc Table.. ======================================*/ -static const crystalhd_cmd_tbl_t g_crystalhd_cproc_tbl[] = { - { BCM_IOC_GET_VERSION, bc_cproc_get_version, 0}, - { BCM_IOC_GET_HWTYPE, bc_cproc_get_hwtype, 0}, - { BCM_IOC_REG_RD, bc_cproc_reg_rd, 0}, - { BCM_IOC_REG_WR, bc_cproc_reg_wr, 0}, - { BCM_IOC_FPGA_RD, bc_cproc_link_reg_rd, 0}, - { BCM_IOC_FPGA_WR, bc_cproc_link_reg_wr, 0}, - { BCM_IOC_MEM_RD, bc_cproc_mem_rd, 0}, - { BCM_IOC_MEM_WR, bc_cproc_mem_wr, 0}, - { BCM_IOC_RD_PCI_CFG, bc_cproc_cfg_rd, 0}, - { BCM_IOC_WR_PCI_CFG, bc_cproc_cfg_wr, 1}, - { BCM_IOC_FW_DOWNLOAD, bc_cproc_download_fw, 1}, - { BCM_IOC_FW_CMD, bc_cproc_do_fw_cmd, 1}, - { BCM_IOC_PROC_INPUT, bc_cproc_proc_input, 1}, - { BCM_IOC_ADD_RXBUFFS, bc_cproc_add_cap_buff, 1}, - { BCM_IOC_FETCH_RXBUFF, bc_cproc_fetch_frame, 1}, - { BCM_IOC_START_RX_CAP, bc_cproc_start_capture, 1}, - { BCM_IOC_FLUSH_RX_CAP, bc_cproc_flush_cap_buffs, 1}, - { BCM_IOC_GET_DRV_STAT, bc_cproc_get_stats, 0}, - { BCM_IOC_RST_DRV_STAT, bc_cproc_reset_stats, 0}, - { BCM_IOC_NOTIFY_MODE, bc_cproc_notify_mode, 0}, - { BCM_IOC_END, NULL}, -}; - -/*=============== Cmd Proc Functions.. ===================================*/ - -/** - * crystalhd_suspend - Power management suspend request. - * @ctx: Command layer context. - * @idata: Iodata - required for internal use. - * - * Return: - * status - * - * 1. Set the state to Suspend. - * 2. Flush the Rx Buffers it will unmap all the buffers and - * stop the RxDMA engine. - * 3. Cancel The TX Io and Stop Dma Engine. - * 4. Put the DDR in to deep sleep. - * 5. Stop the hardware putting it in to Reset State. - * - * Current gstreamer frame work does not provide any power management - * related notification to user mode decoder plug-in. As a work-around - * we pass on the power mangement notification to our plug-in by completing - * all outstanding requests with BC_STS_IO_USER_ABORT return code. - */ -BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) -{ - struct device *dev = chddev(); - BC_STATUS sts = BC_STS_SUCCESS; - - if (!ctx || !idata) { - dev_err(dev, "Invalid Parameters\n"); - return BC_STS_ERROR; - } - - if (ctx->state & BC_LINK_SUSPEND) - return BC_STS_SUCCESS; - - if (ctx->state == BC_LINK_INVALID) { - dev_dbg(dev, "Nothing To Do Suspend Success\n"); - return BC_STS_SUCCESS; - } - - ctx->state |= BC_LINK_SUSPEND; - - bc_cproc_mark_pwr_state(ctx); - - if (ctx->state & BC_LINK_CAP_EN) { - idata->udata.u.FlushRxCap.bDiscardOnly = true; - sts = bc_cproc_flush_cap_buffs(ctx, idata); - if (sts != BC_STS_SUCCESS) - return sts; - } - - if (ctx->tx_list_id) { - sts = crystalhd_hw_cancel_tx(ctx->hw_ctx, ctx->tx_list_id); - if (sts != BC_STS_SUCCESS) - return sts; - } - - sts = crystalhd_hw_suspend(ctx->hw_ctx); - if (sts != BC_STS_SUCCESS) - return sts; - - dev_info(dev, "Crystal HD suspend success\n"); - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_resume - Resume frame capture. - * @ctx: Command layer contextx. - * - * Return: - * status - * - * - * Resume frame capture. - * - * PM_Resume can't resume the playback state back to pre-suspend state - * because we don't keep video clip related information within driver. - * To get back to the pre-suspend state App will re-open the device and - * start a new playback session from the pre-suspend clip position. - * - */ -BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx) -{ - dev_info(chddev(), "crystalhd_resume Success %x\n", ctx->state); - - bc_cproc_mark_pwr_state(ctx); - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_user_open - Create application handle. - * @ctx: Command layer contextx. - * @user_ctx: User ID context. - * - * Return: - * status - * - * Creates an application specific UID and allocates - * application specific resources. HW layer initialization - * is done for the first open request. - */ -BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, - struct crystalhd_user **user_ctx) -{ - struct device *dev = chddev(); - struct crystalhd_user *uc; - - if (!ctx || !user_ctx) { - dev_err(dev, "Invalid arg..\n"); - return BC_STS_INV_ARG; - } - - uc = bc_cproc_get_uid(ctx); - if (!uc) { - dev_info(dev, "No free user context...\n"); - return BC_STS_BUSY; - } - - dev_info(dev, "Opening new user[%x] handle\n", uc->uid); - - uc->mode = DTS_MODE_INV; - uc->in_use = 0; - - if(ctx->hw_ctx == NULL) { - ctx->hw_ctx = (struct crystalhd_hw*)kmalloc(sizeof(struct crystalhd_hw), GFP_KERNEL); - if(ctx->hw_ctx != NULL) - memset(ctx->hw_ctx, 0, sizeof(struct crystalhd_hw)); - else - return BC_STS_ERROR; - - crystalhd_hw_open(ctx->hw_ctx, ctx->adp); - } - - uc->in_use = 1; - - *user_ctx = uc; - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_user_close - Close application handle. - * @ctx: Command layer contextx. - * @uc: User ID context. - * - * Return: - * status - * - * Closer aplication handle and release app specific - * resources. - */ -BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc) -{ - uint32_t mode = uc->mode; - - ctx->user[uc->uid].mode = DTS_MODE_INV; - ctx->user[uc->uid].in_use = 0; - - dev_info(chddev(), "Closing user[%x] handle with mode %x\n", uc->uid, mode); - - if (((mode & 0xFF) == DTS_DIAG_MODE) || - ((mode & 0xFF) == DTS_PLAYBACK_MODE) || - ((bc_cproc_get_user_count(ctx) == 0) && (ctx->hw_ctx != NULL))) { - ctx->cin_wait_exit = 1; - ctx->pwr_state_change = 0; - // Stop the HW Capture just in case flush did not get called before stop - crystalhd_hw_stop_capture(ctx->hw_ctx, true); - crystalhd_hw_free_dma_rings(ctx->hw_ctx); - crystalhd_destroy_dio_pool(ctx->adp); - crystalhd_delete_elem_pool(ctx->adp); - ctx->state = BC_LINK_INVALID; - crystalhd_hw_close(ctx->hw_ctx, ctx->adp); - kfree(ctx->hw_ctx); - ctx->hw_ctx = NULL; - } /*else if (bc_cproc_get_user_count(ctx)) { - return BC_STS_SUCCESS; - }*/ - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_setup_cmd_context - Setup Command layer resources. - * @ctx: Command layer contextx. - * @adp: Adapter context - * - * Return: - * status - * - * Called at the time of driver load. - */ -BC_STATUS __devinit crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, - struct crystalhd_adp *adp) -{ - struct device *dev = &adp->pdev->dev; - int i = 0; - - if (!ctx || !adp) { - dev_err(dev, "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - if (ctx->adp) - dev_dbg(dev, "Resetting Cmd context delete missing..\n"); - - ctx->adp = adp; - for (i = 0; i < BC_LINK_MAX_OPENS; i++) { - ctx->user[i].uid = i; - ctx->user[i].in_use = 0; - ctx->user[i].mode = DTS_MODE_INV; - } - - ctx->hw_ctx = (struct crystalhd_hw*)kmalloc(sizeof(struct crystalhd_hw), GFP_KERNEL); - - memset(ctx->hw_ctx, 0, sizeof(struct crystalhd_hw)); - - /*Open and Close the Hardware to put it in to sleep state*/ - crystalhd_hw_open(ctx->hw_ctx, ctx->adp); - crystalhd_hw_close(ctx->hw_ctx, ctx->adp); - kfree(ctx->hw_ctx); - ctx->hw_ctx = NULL; - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_delete_cmd_context - Release Command layer resources. - * @ctx: Command layer contextx. - * - * Return: - * status - * - * Called at the time of driver un-load. - */ -BC_STATUS __devexit crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) -{ - dev_dbg(chddev(), "Deleting Command context..\n"); - - ctx->adp = NULL; - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_get_cmd_proc - Cproc table lookup. - * @ctx: Command layer contextx. - * @cmd: IOCTL command code. - * @uc: User ID context. - * - * Return: - * command proc function pointer - * - * This function checks the process context, application's - * mode of operation and returns the function pointer - * from the cproc table. - */ -crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, - struct crystalhd_user *uc) -{ - struct device *dev = chddev(); - crystalhd_cmd_proc cproc = NULL; - unsigned int i, tbl_sz; - - if (!ctx) { - dev_err(dev, "Invalid arg.. Cmd[%d]\n", cmd); - return NULL; - } - - if ((cmd != BCM_IOC_GET_DRV_STAT) && (ctx->state & BC_LINK_SUSPEND)) { - dev_err(dev, "Invalid State [suspend Set].. Cmd[%d]\n", cmd); - return NULL; - } - - tbl_sz = sizeof(g_crystalhd_cproc_tbl) / sizeof(crystalhd_cmd_tbl_t); - for (i = 0; i < tbl_sz; i++) { - if (g_crystalhd_cproc_tbl[i].cmd_id == cmd) { - if ((uc->mode == DTS_MONITOR_MODE) && - (g_crystalhd_cproc_tbl[i].block_mon)) { - dev_info(dev, "Blocking cmd %d \n", cmd); - break; - } - cproc = g_crystalhd_cproc_tbl[i].cmd_proc; - break; - } - } - - return cproc; -} - -/** - * crystalhd_cmd_interrupt - ISR entry point - * @ctx: Command layer contextx. - * - * Return: - * TRUE: If interrupt from CrystalHD device. - * - * - * ISR entry point from OS layer. - */ -bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx) -{ - if (!ctx) { - printk(KERN_ERR "%s: Invalid arg..\n", __func__); - return false; - } - - // If HW has not been initialized then all interrupts are spurious - if ((ctx->hw_ctx == NULL) || (ctx->hw_ctx->pfnFindAndClearIntr == NULL)) - return false; - - return ctx->hw_ctx->pfnFindAndClearIntr(ctx->adp, ctx->hw_ctx); -} diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_cmds.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_cmds.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_cmds.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_cmds.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,91 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_cmds . h - * - * Description: - * BCM70010 Linux driver user command interfaces. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#ifndef _CRYSTALHD_CMDS_H_ -#define _CRYSTALHD_CMDS_H_ - -/* - * NOTE:: This is the main interface file between the Linux layer - * and the harware layer. This file will use the definitions - * from _dts_glob and dts_defs etc.. which are defined for - * windows. - */ - -#include "crystalhd_hw.h" -#include "crystalhd_misc.h" - -extern struct device * chddev(void); - -enum _crystalhd_state{ - BC_LINK_INVALID = 0x00, - BC_LINK_INIT = 0x01, - BC_LINK_CAP_EN = 0x02, - BC_LINK_FMT_CHG = 0x04, - BC_LINK_SUSPEND = 0x10, - BC_LINK_PAUSED = 0x20, - BC_LINK_READY = (BC_LINK_INIT | BC_LINK_CAP_EN | BC_LINK_FMT_CHG), -}; - -struct crystalhd_user { - uint32_t uid; - uint32_t in_use; - uint32_t mode; -}; - -#define DTS_MODE_INV (-1) - -struct crystalhd_cmd { - uint32_t state; - struct crystalhd_adp *adp; - struct crystalhd_user user[BC_LINK_MAX_OPENS]; - - spinlock_t ctx_lock; - uint32_t tx_list_id; - uint32_t cin_wait_exit; - uint32_t pwr_state_change; - struct crystalhd_hw *hw_ctx; -}; - -typedef BC_STATUS (*crystalhd_cmd_proc)(struct crystalhd_cmd *, crystalhd_ioctl_data *); - -typedef struct _crystalhd_cmd_tbl { - uint32_t cmd_id; - const crystalhd_cmd_proc cmd_proc; - uint32_t block_mon; -} crystalhd_cmd_tbl_t; - - -BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata); -BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx); -crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, - struct crystalhd_user *uc); -BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx); -BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc); -BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp); -BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx); -bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx); - -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_flea_ddr.c crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_flea_ddr.c --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_flea_ddr.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_flea_ddr.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,734 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2010, Broadcom Corporation. - * - * Name: crystalhd_flea_ddr . c - * - * Description: - * BCM70015 generic DDR routines - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#include "crystalhd_hw.h" -#include "crystalhd_flea_ddr.h" - -//#include "bchp_ddr23_ctl_regs_0.h" -//#include "bchp_ddr23_phy_byte_lane_0.h" -//#include "bchp_ddr23_phy_byte_lane_1.h" -//#include "bchp_ddr23_phy_control_regs.h" -//#include "bchp_pri_arb_control_regs.h" -//#include "bchp_pri_client_regs.h" - -// RTS Programming Values for all Clients -// column legend -// [0]: 1=Program, 0=Default; -// [1]: Blockout Count; -// [2]: Critical Period; -// [3]: Priority; -// [4]: Access Mode -// Default mode for clients is best effort - -uint32_t rts_prog_vals[21][5] = { - {1, 130, 130, 6, 1}, // Deblock ( 0) - {1, 1469, 1469, 9, 1}, // Cabac ( 1) - {1, 251, 251, 4, 1}, // Iloop ( 2) - {1, 842, 842, 5, 1}, // Oloop ( 3) - {1, 1512, 1512, 10, 1}, // Symb_Int ( 4) - {1, 43, 43, 14, 1}, // Mcomp ( 5) - {1, 1318, 1318, 11, 1}, // XPT_0 ( 6) - {1, 4320, 4320, 16, 1}, // XPT_1 ( 7) - {1, 5400, 5400, 17, 0}, // XPT_2 ( 8) - {1, 1080, 1080, 18, 1}, // ARM ( 9) - {1, 691, 691, 7, 0}, // MEM_DMA (10) - {1, 1382, 1382, 15, 0}, // SHARF (11) - {1, 346, 346, 2, 0}, // BVN (12) - {1, 1728, 1728, 13, 1}, // RxDMA3 (13) - {1, 864, 864, 8, 1}, // TxDMA (14) - {1, 173, 173, 3, 1}, // MetaDMA (15) - {1, 2160, 2160, 19, 1}, // DirectDMA (16) - {1, 10800, 10800, 20, 1}, // MSA (17) - {1, 216, 216, 1, 1}, // TRACE (18) - {1, 1598, 1598, 12, 0}, // refresh1 (19) - { 0, 0, 0, 0, 0}, //(20) -}; - -void crystalhd_flea_ddr_pll_config(struct crystalhd_hw* hw, int32_t *speed_grade, int32_t num_plls, uint32_t tmode) -{ - uint32_t PLL_NDIV_INT[2]; - uint32_t PLL_M1DIV[2]; - int32_t i; - uint32_t tmp; - uint32_t config; - uint32_t timeout; - uint32_t skip_init[2]; // completely skip initialization - //uint32_t offset[2]; - uint32_t skip_pll_setup; - uint32_t poll_cnt; - - skip_init[0] = 0; - skip_init[1] = 0; - - // If the test mode is not 0 then skip the PLL setups too. - if (tmode != 0){ - skip_pll_setup = 1; - } - else { - skip_pll_setup = 0; - } - - // Use this scratch register in DDR0 - which should reset to 0 - as a simple symaphore for the test - // to monitor if and when the Initialization of the DDR is complete - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_SCRATCH, 0); - - if (!skip_pll_setup) { - for(i=0;ipfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, - (0 << 0) | //PWRDWN - (0 << 1) | //REFCOMP_PWRDWN - (1 << 2) | //ARESET - (1 << 3) | //DRESET - (0 << 4) | //ENB_CLKOUT - (0 << 5) | //BYPEN ??? - (0 << 6) | //PWRDWN_CH1 - (0 << 8) | //DLY_CH1 - (0 << 10)| //VCO_RNG - (1 << 31) //DIV2 CLK RESET - ); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER, - (1 << 0) | //P1DIV - (1 << 4) | //P2DIV - (PLL_NDIV_INT[i] << 8) | //NDIV_INT - (1 << 24) //BYPASS_SDMOD - ); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER, - (PLL_M1DIV[i] << 24) //M1DIV - ); - - config = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); - config &= 0xfffffffb; //clear ARESET - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); - } - - //poll for lock - for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS); - while((timeout>0) && ((tmp & 0x1) == 0)){ - msleep_interruptible(1); - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS); - timeout--; - } - if (timeout<=0) - printk("Timed out waiting for DDR Controller PLL %d to lock\n",i); - } - - //deassert PLL digital reset - for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); - config &= 0xfffffff7; //clear DRESET - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); - } - - //deassert reset of logic - for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); - config &= 0x7fffffff; //clear logic reset - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); - } - } // end (skip_pll_setup) - - //run VDL calibration for all byte lanes - for(i=0;ipfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); - tmp = ( - (1 << 0) | //calib_fast - (1 << 1) //calib_once - ); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); - - - if (!skip_pll_setup){ //VDLs might not lock if clocks are bypassed - timeout=100; - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); - while((timeout>0) && ((tmp & 0x3) == 0x0)){ - msleep_interruptible(1); - timeout--; - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); - } - if ((tmp & 0x3) != 0x3) - printk("VDL calibration did not finish or did not lock!\n"); - timeout=100; - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS); - while((timeout>0) && ((tmp & 0x3) == 0x0)){ - msleep_interruptible(1); - timeout--; - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS); - } - if ((tmp & 0x3) != 0x3) - printk("VDL calibration did not finish or did not lock!\n"); - - if(timeout<=0){ - printk("DDR PHY %d VDL Calibration failed\n",i); - } - } - else { - msleep_interruptible(1); - } - - //clear VDL calib settings - tmp = 0; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); - - //override the ADDR/CTRL VDLs with results from Bytelane #0 - //if tmode other than zero then set the VDL compensations to max values of 0x1ff. - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); - tmp = (tmp >> 4) & 0x3ff; - // If in other than tmode 0 then set the VDL override settings to max. - if (tmode) { - tmp = 0x3ff; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3, 0x1003f); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_UPDATE_VDL, BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK); - } - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE, - (((tmp & 0x3f0) >> 4) << 0) | // step override value - (1 << 16) | // override enable - (1 << 20) // override force ; no update vdl required - ); - - /* NAREN added support for ZQ Calibration */ - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, 0); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK); - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL); - - poll_cnt = 0; - while(1) - { - if(!(tmp & BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK)) - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL); - else - break; - - if(poll_cnt++ > 100) - break; - } - - if(tmode) { - // Set fields addr_ovr_en and dq_pvr_en to '1'. Set all *_override_val fields to 0xf - ZQ_PVT_COMP_CTL - tmp = ( ( 1 << 25) | // addr_ovr_en - ( 1 << 24) | // dq_ovr_en - (0xf << 12) | // addr_pd_override_val - (0xf << 8) | // addr_nd_override_val - (0xf << 4) | // dq_pd_override_val - (0xf << 0) ); // dq_nd_override_val - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, tmp); - // Drive_PAD_CTL register. Set field selrxdrv and slew to 0; - tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL); - tmp &= (0xfffffffe); //clear bits 0 and 1. - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL,tmp); - } - }//for(i=0.. -} - -void crystalhd_flea_ddr_ctrl_init(struct crystalhd_hw *hw, - int32_t port, - int32_t ddr3, - int32_t speed_grade, - int32_t col, - int32_t bank, - int32_t row, - uint32_t tmode) -{ - //uint32_t offset; - //uint32_t arb_refresh_addr; - uint32_t port_int; - - uint32_t data; - - //DDR2 Parameters - uint8_t tRCD = 0; - uint8_t tRP = 0; - uint8_t tRRD = 0; - uint8_t tWR = 0; - uint8_t tWTR = 0; - uint8_t tCAS = 0; - uint8_t tWL = 0; - uint8_t tRTP = 0; - uint8_t tRAS = 0; - uint8_t tFAW = 0; - uint8_t tRFC = 0; - uint8_t INTLV_BYTES = 0; - uint8_t INTLV_DISABLE = 0; - uint8_t CTRL_BITS = 0; - uint8_t ALLOW_PICTMEM_RD = 0; - uint8_t DIS_DQS_ODT = 0; - uint8_t CS0_ONLY = 0; - uint8_t EN_ODT_EARLY = 0; - uint8_t EN_ODT_LATE = 0; - uint8_t USE_CHR_HGT = 0; - uint8_t DIS_ODT = 0; - uint8_t EN_2T_TIMING = 0; - uint8_t CWL = 0; - uint8_t DQ_WIDTH = 0; - - uint8_t DM_IDLE_MODE = 0; - uint8_t CTL_IDLE_MODE = 0; - uint8_t DQ_IDLE_MODE = 0; - - uint8_t DIS_LATENCY_CTRL = 0; - - uint8_t PSPLIT = 0; - uint8_t DSPLIT = 0; - - // For each controller port, 0 and 1. - for (port_int=0; port_int < 1; ++port_int) { -#if 0 - printk("******************************************************\n"); - printk("* Configuring DDR23 at addr=0x%x, speed grade [%s]\n",0, - ((speed_grade == DDR2_667MHZ) && (tmode == 0)) ? "667MHZ": - ((speed_grade == DDR2_533MHZ) && (tmode == 0)) ? "533MHZ": - ((speed_grade == DDR2_400MHZ) && (tmode == 0)) ? "400MHZ": - ((speed_grade == DDR2_333MHZ) && (tmode == 0)) ? "333MHZ": - ((speed_grade == DDR2_266MHZ) && (tmode == 0)) ? "266MHZ": "400MHZ" ); -#endif - // Written in this manner to prevent table lookup in Memory for embedded MIPS code. - // Cannot use memory until it is inited! Case statements with greater than 5 cases use memory tables - // when optimized. Tony O 9/18/07 - // Note if not in test mode 0, choose the slowest clock speed. - if (speed_grade == DDR2_200MHZ) { - tRCD = 3; - tRP = 3; - tRRD = 2; - tWR = 3; - tWTR = 2; - tCAS = 4; - tWL = 3; - tRTP = 2; - tRAS = 8; - tFAW = 10; - if (bank == BANK_SIZE_4) - tRFC = 21; - else //BANK_SIZE_8 - tRFC = 26; - } - else if (speed_grade == DDR2_266MHZ ) { - tRCD = 4; - tRP = 4; - tRRD = 3; - tWR = 4; - tWTR = 2; - tCAS = 4; - tWL = 3; - tRTP = 2; - tRAS = 11; - tFAW = 14; - if (bank == BANK_SIZE_4) - tRFC = 28; - else //BANK_SIZE_8 - tRFC = 34; - } - else if (speed_grade == DDR2_333MHZ) { - tRCD = 4; - tRP = 4; - tRRD = 4; - tWR = 5; - tWTR = 3; - tCAS = 4; - tWL = 3; - tRTP = 3; - tRAS = 14; - tFAW = 17; - if (bank == BANK_SIZE_4) - tRFC = 35; - else //BANK_SIZE_8 - tRFC = 43; - } - else if ((speed_grade == DDR2_400MHZ) || (tmode != 0)) { // -25E timing - tRCD = 6; - tRP = 6; - tRRD = 4; - tWR = 6; - tWTR = 4; - tCAS = ddr3 ? 6 : 5; - tWL = ddr3 ? 5 : 4; - tRTP = 3; - tRAS = 18; - tFAW = 20; - if (bank == BANK_SIZE_4) - tRFC = 42; - else //BANK_SIZE_8 - tRFC = 52; - CWL = tWL - 5; - } - else if (speed_grade == DDR2_533MHZ) { // -187E timing - tRCD = 7; - tRP = 7; - tRRD = 6; - tWR = 8; - tWTR = 4; - tCAS = 7; - tWL = tCAS - 1; - tRTP = 4; - tRAS = 22; - tFAW = 24; - tRFC = 68; - CWL = tWL - 5; - } - else if (speed_grade == DDR2_667MHZ) { // -15E timing - tRCD = 9; - tRP = 9; - tRRD = 5;// 4/5 - tWR = 10; - tWTR = 5; - tCAS = 9; - tWL = 7; - tRTP = 5; - tRAS = 24; - tFAW = 30; // 20/30 - tRFC = 74; - CWL = tWL - 5; - } - else - printk("init: CANNOT HAPPEN - Memory DDR23 Ctrl_init failure. Incorrect speed grade type [%d]\n", speed_grade); - - CTRL_BITS = 0; // Control Bit for CKE signal - EN_2T_TIMING = 0; - INTLV_DISABLE = ddr3 ? 1:0; // disable for DDR3, enable for DDR2 - INTLV_BYTES = 0; - ALLOW_PICTMEM_RD = 0; - DIS_DQS_ODT = 0; - CS0_ONLY = 0; - EN_ODT_EARLY = 0; - EN_ODT_LATE = 0; - USE_CHR_HGT = 0; - DIS_ODT = 0; - - //Power Saving Controls - DM_IDLE_MODE = 0; - CTL_IDLE_MODE = 0; - DQ_IDLE_MODE = 0; - - //Latency Control Setting - DIS_LATENCY_CTRL = 0; - - // ****** Start of Grain/Flea specific fixed settings ***** - CS0_ONLY = 1 ; // 16-bit mode only - INTLV_DISABLE = 1 ; // Interleave is always disabled - DQ_WIDTH = 16 ; - // ****** End of Grain specific fixed settings ***** - -#if 0 - printk("* DDR23 Config: CAS: %d, tRFC: %d, INTLV: %d, WIDTH: %d\n", - tCAS,tRFC,INTLV_BYTES,DQ_WIDTH); - printk("******************************************************\n"); -#endif - //Disable refresh - data = ((0x68 << 0) | //Refresh period - (0x0 << 12) //disable refresh - ); - - hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, data); - - // DecSd_Ddr2Param1 - data = 0; - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trcd, tRCD); // trcd - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trp, tRP); // trp - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trrd, tRRD); // trrd - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twr, tWR); // twr - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twtr, tWTR); // twtr - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, tcas, tCAS); // tcas - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twl, tWL); // twl - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trtp, tRTP); // trtp - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS1, data ); - - //DecSd_Ddr2Param3 - deassert reset only - data = 0; - //DEBUG_PRINT(PARAMS3, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, data ); - - // Reset must be deasserted 500us before CKE. This needs - // to be reflected in the CFE. (add delay here) - - //DecSd_Ddr2Param2 - data = 0; - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, tras, tRAS); // tras - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, tfaw, tFAW); // tfaw - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, trfc, tRFC); // trfc - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, bank_bits, bank & 1); // 0 = bank size of 4K == 2bits, 1 = bank size of 8k == 3 bits - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, allow_pictmem_rd, ALLOW_PICTMEM_RD); - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, cs0_only, CS0_ONLY); - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, dis_itlv, INTLV_DISABLE); // #disable interleave - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, il_sel, INTLV_BYTES); // #bytes per interleave - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, sd_col_bits, col & 3); // column bits, 0 = 9, 1= 10, 2 or 3 = 11 bits - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, clke, CTRL_BITS); // Control Bit for CKE signal - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, use_chr_hgt, USE_CHR_HGT); - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, row_bits, row & 1); // row size 1 is 16K for 2GB device, otherwise 0 and 8k sized - - //DEBUG_PRINT(PARAMS2, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, data ); - - //DecSd_Ddr2Param3. - data = 0; - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_en, DIS_ODT ? 0 : 1); - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_le_adj, EN_ODT_EARLY ? 1 : 0); - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_te_adj, EN_ODT_LATE ? 1 : 0); - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, cmd_2t, EN_2T_TIMING ? 1: 0); // 2T timing is disabled - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, ddr_bl, ddr3 ? 1: 0); // 0 for DDR2, 1 for DDR3 - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_mode, ddr3 ? 1:0); // ddr3 preamble - SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, ddr3_reset, ddr3 ? 0:1); // ddr3 reset - - //DEBUG_PRINT(PARAMS3, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, data ); - } // for( port_int......) - - data = 0; - SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, slew, 1); - SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, seltxdrv_ci, 1); - SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, sel_sstl18, ddr3 ? 0 : 1); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL, data ); - - data = 0; - SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, slew, 0); - SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, selrxdrv, 0); - SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, seltxdrv_ci, 0); - SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, sel_sstl18, ddr3 ? 0 : 1); - SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, rt60b, 0); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, data ); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, data ); - - data = 0; - - if (speed_grade == DDR2_667MHZ) { - data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK) | ((2 << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK)); - } else { - data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK) | ((1 << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK)); - } - - data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK) | ((((DIS_DQS_ODT || DIS_ODT) ? 0:1) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK)); - data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK) | (((EN_ODT_EARLY ? 1 : 0) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK)); - data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK) | (((DIS_ODT ? 0:1) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK)); - data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK) | (((EN_ODT_EARLY ? 1 : 0) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK)); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL, data); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, ddr3 ? 1 : 0); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, ddr3 ? 1 : 0); - - // Disable unused clocks - - for (port_int=0; port_int<1; ++port_int) { // For Grain - // Changes for Grain/Flea - //offset = 0; - //arb_refresh_addr = BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0; - //offset += GLOBAL_REG_RBUS_START; - // Changes for Grain - till here - - if (ddr3) { - data = (CWL & 0x07) << 3; - //DEBUG_PRINT(LOAD_EMODE2_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD, data ); - - data = 0; - //DEBUG_PRINT(LOAD_EMODE3_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD, data ); - - data = 6; // was 4; - //DEBUG_PRINT(LOAD_EMODE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); - - data = 0x1100; // Reset DLL - data += ((tWR-4) << 9); - data += ((tCAS-4) << 4); - //DEBUG_PRINT(LOAD_MODE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); - - - data = 0x0400; // long calibration - //DEBUG_PRINT(ZQ_CALIBRATE, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE, data ); - - msleep_interruptible(1); - } - else - { - //DecSd_RegSdPrechCmd // Precharge - data = 0; - //DEBUG_PRINT(PRECHARGE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); - - //DEBUG_PRINT(PRECHARGE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); - - //DecSd_RegSdLdModeCmd //Clear EMODE 2,3 - data = 0; - //DEBUG_PRINT(LOAD_EMODE2_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD, data ); - - //DEBUG_PRINT(LOAD_EMODE3_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD, data ); - - //DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; enable OCD - data = 0x3C0; - //DEBUG_PRINT(LOAD_EMODE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); - - //DecSd_RegSdLdModeCmd - data = 0x102; // Reset DLL - data += ((tWR-1) << 9); - data += (tCAS << 4); - //DEBUG_PRINT(LOAD_MODE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); - - //DecSd_RegSdPrechCmd // Precharge - data = 0; - //DEBUG_PRINT(PRECHARGE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); - - //DEBUG_PRINT(PRECHARGE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); - - //DecSd_RegSdRefCmd // Refresh - data = 0x69; - //DEBUG_PRINT(REFRESH_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, data ); - - //DEBUG_PRINT(REFRESH_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, data ); - - //DecSd_RegSdLdModeCmd - data = 0x002; // Un-Reset DLL - data += ((tWR-1) << 9); - data += (tCAS << 4); - //DEBUG_PRINT(LOAD_MODE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); - - //DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; enable OCD - data = 0x3C0; - //DEBUG_PRINT(LOAD_EMODE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); - - //DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; disable OCD - data = 0x40; - //DEBUG_PRINT(LOAD_EMODE_CMD, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); - } - - //Enable refresh - data = ((0x68 << 0) | //Refresh period - (0x1 << 12) //enable refresh - ); - if (tmode == 0) { - //MemSysRegWr(arb_refresh_addr + GLOBAL_REG_RBUS_START,data); - hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0,data); - } - - //offset = 0; - //offset += GLOBAL_REG_RBUS_START; - - // Use this scratch register in DDR0 as a simple symaphore for the test - // to monitor if and when the Initialization of the DDR is complete. Seeing a non zero value - // indicates DDR init complete. This code is ONLY for the MIPS. It has no affect in init.c - // The MIPS executes this code and we wait until DDR 1 is inited before setting the semaphore. - if ( port_int == 1) - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_SCRATCH, 0xff); - - //Setup the Arbiter Data and Pict Buffer split if specified - if (port_int==0) { //only need to do this once - //where is the pict buff split (2 bits) - //0 = always mem_a, 1 = (<128 is mem_a), 2 = (<64 is mem_a), 3 = always mem_b - PSPLIT = 0; - - //0 = 32MB, 1 = 64MB, 2 = 128 MB, 3 = 256MB, 4=512MB - DSPLIT = 4; - - data = 0; - data += DSPLIT; - data += PSPLIT<< 4; - // MemSysRegWr (PRI_ARB_CONTROL_REGS_CONC_CTL + offset, data ); - } - - if (DIS_LATENCY_CTRL == 1){ - //set the work limit to the maximum - //DEBUG_PRINT(LATENCY, data); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LATENCY, 0x3ff ); - } - } // for (port_int=0...... ) - - return; -} - -void crystalhd_flea_ddr_arb_rts_init(struct crystalhd_hw *hw) -{ - uint32_t addr_cnt; - uint32_t addr_ctrl; - uint32_t i; - - addr_cnt = BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT; - addr_ctrl = BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL; - - //Go through the various clients and program them - for(i=0;i<21;i++){ - if (rts_prog_vals[i][0] > 0) { - hw->pfnWriteDevRegister(hw->adp, addr_cnt, - (rts_prog_vals[i][1]) | //Blockout Count - (rts_prog_vals[i][2] << 16) //Critical Period - ); - hw->pfnWriteDevRegister(hw->adp, addr_ctrl, - (rts_prog_vals[i][3]) | //Priority Level - (rts_prog_vals[i][4] << 8) //Access Mode - ); - } - addr_cnt+=8; - addr_ctrl+=8; - } -} diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_flea_ddr.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_flea_ddr.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_flea_ddr.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_flea_ddr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,73 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2010, Broadcom Corporation. - * - * Name: crystalhd_flea_ddr . h - * - * Description: - * BCM70015 generic DDR routines - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#undef BRCM_ALIGN -#define BRCM_ALIGN(c,r,f) 0 - -#define MEM_SYS_NUM_DDR_PLLS 2; - -//extern uint32_t rts_prog_vals[][5]; - -typedef enum DDR2_SPEED_GRADE { - DDR2_400MHZ = 0x0, - DDR2_333MHZ = 0x1, - DDR2_266MHZ = 0x2, - DDR2_200MHZ = 0x3, - DDR2_533MHZ = 0x4, - DDR2_667MHZ = 0x5 -} eDDR2_SPEED_GRADE; - -typedef enum SD_COL_SIZE { - COL_BITS_9 = 0x0, - COL_BITS_10 = 0x1, - COL_BITS_11 = 0x2, -} eSD_COL_SIZE; - -typedef enum SD_BANK_SIZE { - BANK_SIZE_4 = 0x0, - BANK_SIZE_8 = 0x1, -} eSD_BANK_SIZE; - -typedef enum SD_ROW_SIZE { - ROW_SIZE_8K = 0x0, - ROW_SIZE_16K = 0x1, -} eSD_ROW_SIZE; - -//DDR PHY PLL init routine -void crystalhd_flea_ddr_pll_config(struct crystalhd_hw* hw, int32_t *speed_grade, int32_t num_plls, uint32_t tmode); - -//DDR controller init routine -void crystalhd_flea_ddr_ctrl_init(struct crystalhd_hw *hw, - int32_t port, - int32_t ddr3, - int32_t speed_grade, - int32_t col, - int32_t bank, - int32_t row, - uint32_t tmode ); - -////RTS Init routines -void crystalhd_flea_ddr_arb_rts_init(struct crystalhd_hw *hw); diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_fleafuncs.c crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_fleafuncs.c --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_fleafuncs.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_fleafuncs.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,2952 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_fleafuncs.c - * - * Description: - * BCM70015 Linux driver HW layer. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#include -#include -#include -#include -#include -#include "crystalhd_hw.h" -#include "crystalhd_fleafuncs.h" -#include "crystalhd_lnx.h" -#include "bc_defines.h" -#include "FleaDefs.h" -#include "crystalhd_flea_ddr.h" - -#define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) - -void crystalhd_flea_core_reset(struct crystalhd_hw *hw) -{ - unsigned int pollCnt=0,regVal=0; - - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_core_reset]: Starting core reset\n"); - - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC3_RESET_CTRL, 0x01); - - pollCnt=0; - while (1) - { - pollCnt++; - regVal=0; - - msleep_interruptible(1); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC3_RESET_CTRL); - - if(!(regVal & 0x01)) - { - /* - -- Bit is 0, Reset is completed. Which means that - -- wait for sometime and then allow other accesses. - */ - msleep_interruptible(1); - break; - } - - if(pollCnt > MAX_VALID_POLL_CNT) - { - printk("!!FATAL ERROR!! Core Reset Failure\n"); - break; - } - } - - msleep_interruptible(5); - - return; -} - -void crystalhd_flea_disable_interrupts(struct crystalhd_hw *hw) -{ - FLEA_MASK_REG IntrMaskReg; - /* - -- Mask everything except the reserved bits. - */ - IntrMaskReg.WholeReg =0xffffffff; - IntrMaskReg.Reserved1=0; - IntrMaskReg.Reserved2=0; - IntrMaskReg.Reserved3=0; - IntrMaskReg.Reserved4=0; - - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_MSK_SET_REG, IntrMaskReg.WholeReg); - - return; -} - -void crystalhd_flea_enable_interrupts(struct crystalhd_hw *hw) -{ - FLEA_MASK_REG IntrMaskReg; - /* - -- Clear The Mask for everything except the reserved bits. - */ - IntrMaskReg.WholeReg =0xffffffff; - IntrMaskReg.Reserved1=0; - IntrMaskReg.Reserved2=0; - IntrMaskReg.Reserved3=0; - IntrMaskReg.Reserved4=0; - - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_MSK_CLR_REG, IntrMaskReg.WholeReg); - - return; -} - -void crystalhd_flea_clear_interrupts(struct crystalhd_hw *hw) -{ - FLEA_INTR_STS_REG IntrStsValue; - - IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); - - if(IntrStsValue.WholeReg) - { - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); - } - - return; -} - -bool crystalhd_flea_detect_ddr3(struct crystalhd_hw *hw) -{ - uint32_t regVal = 0; - - /*Set the Multiplexer to select the GPIO-6*/ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0); - - /*Make sure that the bits-24:27 are reset*/ - if(regVal & 0x0f000000) - { - regVal = regVal & 0xf0ffffff; /*Clear bit 24-27 for selecting GPIO_06*/ - hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, regVal); - } - - regVal=0; - /*Set the Direction of GPIO-6*/ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_GIO_IODIR_LO); - - if(!(regVal & BC_BIT(6))) - { - /*Set the Bit number 6 to make the GPIO6 as input*/ - regVal |= BC_BIT(6); - hw->pfnWriteDevRegister(hw->adp, BCHP_GIO_IODIR_LO, regVal); - } - - regVal=0; - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_GIO_DATA_LO); - - /*If this bit is clear then have DDR-3 else we have DDR-2*/ - if(!(regVal & BC_BIT(6))) - { - dev_dbg(&hw->adp->pdev->dev,"DDR-3 Detected\n"); - return true; - } - dev_dbg(&hw->adp->pdev->dev,"DDR-2 Detected\n"); - return false; -} - -void crystalhd_flea_init_dram(struct crystalhd_hw *hw) -{ - int32_t ddr2_speed_grade[2]; - uint32_t sd_0_col_size, sd_0_bank_size, sd_0_row_size; - uint32_t sd_1_col_size, sd_1_bank_size, sd_1_row_size; - uint32_t ddr3_mode[2]; - uint32_t regVal; - bool bDDR3Detected=false; //Should be filled in using the detection logic. Default to DDR2 - - // On all designs we are using DDR2 or DDR3 x16 and running at a max of 400Mhz - // Only one bank of DDR supported. The other is a dummy - - ddr2_speed_grade[0] = DDR2_400MHZ; - ddr2_speed_grade[1] = DDR2_400MHZ; - sd_0_col_size = COL_BITS_10; - sd_0_bank_size = BANK_SIZE_8; - sd_0_row_size = ROW_SIZE_8K; // DDR2 - // sd_0_row_size = ROW_SIZE_16K; // DDR3 - sd_1_col_size = COL_BITS_10; - sd_1_bank_size = BANK_SIZE_8; - sd_1_row_size = ROW_SIZE_8K; - ddr3_mode[0] = 0; - ddr3_mode[1] = 0; - - bDDR3Detected = crystalhd_flea_detect_ddr3(hw); - if(bDDR3Detected) - { - ddr3_mode[0] = 1; - sd_0_row_size = ROW_SIZE_16K; // DDR3 - sd_1_row_size = ROW_SIZE_16K; // DDR3 - - } - - // Step 1. PLL Init - crystalhd_flea_ddr_pll_config(hw, ddr2_speed_grade, 1, 0); // only need to configure PLLs in TM0 - - // Step 2. DDR CTRL Init - crystalhd_flea_ddr_ctrl_init(hw, 0, ddr3_mode[0], ddr2_speed_grade[0], sd_0_col_size, sd_0_bank_size, sd_0_row_size, 0); - - // Step 3 RTS Init - Real time scheduling memory arbiter - crystalhd_flea_ddr_arb_rts_init(hw); - - // NAREN turn off ODT. The REF1 and SV1 and most customer designs allow this. - // IF SOMEONE COMPLAINS ABOUT MEMORY OR DATA CORRUPTION LOOK HERE FIRST - - //hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, 0x02, false); - - /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3); - regVal &= ~(BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, regVal);*/ - - /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL); - regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_seltxdrv_ci_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL); - regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, regVal);*/ - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE); - regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL, regVal); - - return; -} - -uint32_t crystalhd_flea_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) -{ - uint32_t baseAddr = reg_off >> 16; - void *regAddr; - - if (!adp) { - printk(KERN_ERR "%s: Invalid args\n", __func__); - return 0; - } - - if(baseAddr == 0 || baseAddr == FLEA_GISB_DIRECT_BASE) // Direct Mapped Region - { - regAddr = adp->i2o_addr + (reg_off & 0x0000FFFF); - if(regAddr > (adp->i2o_addr + adp->pci_i2o_len)) { - dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", - __func__, reg_off); - return 0; - } - return readl(regAddr); - } - else // non directly mapped region - { - if(adp->pci_i2o_len < 0xFFFF) { - printk("Un-expected mapped region size\n"); - return 0; - } - regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_ADDRESS; - writel(reg_off | 0x10000000, regAddr); - regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_DATA; - return readl(regAddr); - } -} - -void crystalhd_flea_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) -{ - uint32_t baseAddr = reg_off >> 16; - void *regAddr; - - if (!adp) { - printk(KERN_ERR "%s: Invalid args\n", __func__); - return; - } - - if(baseAddr == 0 || baseAddr == FLEA_GISB_DIRECT_BASE) // Direct Mapped Region - { - regAddr = adp->i2o_addr + (reg_off & 0x0000FFFF); - if(regAddr > (adp->i2o_addr + adp->pci_i2o_len)) { - dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", - __func__, reg_off); - return ; - } - writel(val, regAddr); - } - else // non directly mapped region - { - if(adp->pci_i2o_len < 0xFFFF) { - printk("Un-expected mapped region size\n"); - return; - } - regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_ADDRESS; - writel(reg_off | 0x10000000, regAddr); - regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_DATA; - writel(val, regAddr); - } -} - -/** -* crystalhd_flea_mem_rd - Read data from DRAM area. -* @adp: Adapter instance -* @start_off: Start offset. -* @dw_cnt: Count in dwords. -* @rd_buff: Buffer to copy the data from dram. -* -* Return: -* Status. -* -* Dram read routine. -*/ -BC_STATUS crystalhd_flea_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, - uint32_t dw_cnt, uint32_t *rd_buff) -{ - uint32_t ix = 0; - uint32_t addr = start_off, base; - - if (!hw || !rd_buff) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - if( hw->FleaPowerState == FLEA_PS_LP_COMPLETE ) { - //printk(KERN_ERR "%s: Flea power down, cann't read memory.\n", __func__); - return BC_STS_BUSY; - } - - if((start_off + dw_cnt * 4) > FLEA_TOTAL_DRAM_SIZE) { - printk(KERN_ERR "Access beyond DRAM limit at Addr 0x%x and size 0x%x words\n", start_off, dw_cnt); - return BC_STS_ERROR; - } - - /* Set the base addr for the 512kb window */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, - (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); - - for (ix = 0; ix < dw_cnt; ix++) { - rd_buff[ix] = readl(hw->adp->mem_addr + (addr & ~BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)); - base = addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK; - addr += 4; // DWORD access at all times - if (base != (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)) { - /* Set the base addr for next 512kb window */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, - (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); - } - } - return BC_STS_SUCCESS; -} - -/** -* crystalhd_flea_mem_wr - Write data to DRAM area. -* @adp: Adapter instance -* @start_off: Start offset. -* @dw_cnt: Count in dwords. -* @wr_buff: Data Buffer to be written. -* -* Return: -* Status. -* -* Dram write routine. -*/ -BC_STATUS crystalhd_flea_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, - uint32_t dw_cnt, uint32_t *wr_buff) -{ - uint32_t ix = 0; - uint32_t addr = start_off, base; - uint32_t temp; - - if (!hw || !wr_buff) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - if( hw->FleaPowerState == FLEA_PS_LP_COMPLETE ) { - //printk(KERN_ERR "%s: Flea power down, cann't write memory.\n", __func__); - return BC_STS_BUSY; - } - - if((start_off + dw_cnt * 4) > FLEA_TOTAL_DRAM_SIZE) { - printk("Access beyond DRAM limit at Addr 0x%x and size 0x%x words\n", start_off, dw_cnt); - return BC_STS_ERROR; - } - - /* Set the base addr for the 512kb window */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, - (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); - - for (ix = 0; ix < dw_cnt; ix++) { - writel(wr_buff[ix], hw->adp->mem_addr + (addr & ~BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)); - base = addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK; - addr += 4; // DWORD access at all times - if (base != (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)) { - /* Set the base addr for next 512kb window */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, - (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); - } - } - - /*Dummy Read To Flush Memory Arbitrator*/ - crystalhd_flea_mem_rd(hw, start_off, 1, &temp); - return BC_STS_SUCCESS; -} - - -static -void crystalhd_flea_runtime_power_up(struct crystalhd_hw *hw) -{ - uint32_t regVal; - uint64_t currTick; - uint32_t totalTick_Hi; - uint32_t TickSpentInPD_Hi; - uint64_t temp_64; - long totalTick_Hi_f; - long TickSpentInPD_Hi_f; - - //printk("RT PU \n"); - - // NAREN This function restores clocks and power to the DRAM and to the core to bring the decoder back up to full operation - /* Start the DRAM controller clocks first */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); - regVal &= ~(BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); - - // Delay to allow the DRAM clock to stabilize - udelay(25); - - /* Power Up PHY and start clocks on DRAM device */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); - regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, - ~(BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK)); - - // Delay to allow the PLL to lock - udelay(25); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK ); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK ); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK ); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, regVal); - - /* Start Refresh Cycles from controller */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0); - regVal |= BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, regVal); - - /* turn off self-refresh */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); - regVal &= ~(BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); - - udelay(5); - - /* Issue refresh cycle */ - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); - - /* Enable the ARM AVD and BLINK clocks */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); - - regVal &= ~(BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK); - - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, 0x03000000); - - /* Start arbiter */ - hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable); - -#ifdef _POWER_HANDLE_AVD_WATCHDOG_ - /* Restore Watchdog timers */ - // Make sure the timeouts do not happen - //Outer Loop Watchdog timer - hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR, hw->OLWatchDogTimer); - - ////Inner Loop Watchdog timer - hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR, hw->ILWatchDogTimer); - -#endif - - //printk("RT Power Up Flea Complete\n"); - - rdtscll(currTick); - - hw->TickSpentInPD += (currTick - hw->TickStartInPD); - - temp_64 = (hw->TickSpentInPD)>>24; - TickSpentInPD_Hi = (uint32_t)(temp_64); - TickSpentInPD_Hi_f = (long)TickSpentInPD_Hi; - - temp_64 = (currTick - hw->TickCntDecodePU)>>24; - totalTick_Hi = (uint32_t)(temp_64); - totalTick_Hi_f = (long)totalTick_Hi; - - if( totalTick_Hi_f <= 0 ) - { - temp_64 = (hw->TickSpentInPD); - TickSpentInPD_Hi = (uint32_t)(temp_64); - TickSpentInPD_Hi_f = (long)TickSpentInPD_Hi; - - temp_64 = (currTick - hw->TickCntDecodePU); - totalTick_Hi = (uint32_t)(temp_64); - totalTick_Hi_f = (long)totalTick_Hi; - } - - if( totalTick_Hi_f <= 0 ) - { - printk("totalTick_Hi_f <= 0, set hw->PDRatio = 60\n"); - hw->PDRatio = 60; - } - else - hw->PDRatio = (TickSpentInPD_Hi_f * 100) / totalTick_Hi_f; - - //printk("Ticks currently spent in PD: 0x%llx Total: 0x%llx Ratio %d,\n", - // hw->TickSpentInPD, (currTick - hw->TickCntDecodePU), hw->PDRatio); - - /* NAREN check if the PD ratio is greater than 75. If so, try to increase the PauseThreshold to improve the ratio */ - /* never go higher than the default threshold */ - if((hw->PDRatio > 75) && (hw->PauseThreshold < hw->DefaultPauseThreshold)) - { - //printk("Current PDRatio:%u, PauseThreshold:%u, DefaultPauseThreshold:%u, incress PauseThreshold.\n", - // hw->PDRatio, hw->PauseThreshold, hw->DefaultPauseThreshold); - hw->PauseThreshold++; - } - else - { - //printk("Current PDRatio:%u, PauseThreshold:%u, DefaultPauseThreshold:%u, don't incress PauseThreshold.\n", - // hw->PDRatio, hw->PauseThreshold, hw->DefaultPauseThreshold); - } - - return; -} - -static -void crystalhd_flea_runtime_power_dn(struct crystalhd_hw *hw) -{ - uint32_t regVal; - uint32_t pollCnt; - - //printk("RT PD \n"); - - hw->DrvPauseCnt++; - - // NAREN This function stops the decoder clocks including the AVD, ARM and DRAM - // It powers down the DRAM device and places the DRAM into self-refresh - -#ifdef _POWER_HANDLE_AVD_WATCHDOG_ - // Make sure the timeouts do not happen - // Because the AVD drops to a debug prompt and stops decoding if it hits any watchdogs - //Outer Loop Watchdog timer - regVal = hw->pfnReadDevRegister(hw->adp, - BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR); - - hw->OLWatchDogTimer = regVal; - hw->pfnWriteDevRegister(hw->adp, - BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR, - 0xffffffff); - - //Inner Loop Watchdog timer - regVal = hw->pfnReadDevRegister(hw->adp, - BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR); - - hw->ILWatchDogTimer = regVal; - hw->pfnWriteDevRegister(hw->adp, - BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR, - 0xffffffff); -#endif - - // Stop memory arbiter first to freese memory access - hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable); - - // delay at least 15us for memory transactions to complete - // udelay(15); - - /* Wait for MEMC to become idle. Continue even if we are no since worst case this would just mean higher power consumption */ - pollCnt=0; - while (pollCnt++ <= 400) //200 - { - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); - - if(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK) - { - // udelay(10); - break; - } - udelay(10); - } - - /*If we failed Start the arbiter and return*/ - if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK)) - { - printk("RT PD : failed Start the arbiter and return.\n"); - hw->pfnWriteDevRegister(hw->adp, - BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, - BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable); - return; - } - - /* Disable the AVD, ARM and BLINK clocks*/ - /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); - - regVal |= BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; - - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regValE);*/ - - /* turn on self-refresh */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); - regVal |= BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); - - /* Issue refresh cycle */ - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); - - /* Stop Refresh Cycles from controller */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0); - regVal &= ~(BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK); - hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, regVal); - - /* Check if we are in self-refresh. Continue even if we are no since worst case this would just mean higher power consumption */ - pollCnt=0; - while(pollCnt++ < 100) - { - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); - - if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK)) - break; - } - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); - - regVal |= BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; - - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); - - /* Power down PHY and stop clocks on DRAM */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - - regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK; - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - - regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK; - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL); - regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL); - regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL); - regVal |= BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK | - BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK | - BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK | - BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, regVal); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); - regVal |= BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL); - regVal |= BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, regVal); - - /* Finally clock off the DRAM controller */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); - regVal |= BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); - - // udelay(20); - - //printk("RT Power Down Flea Complete\n"); - - // Measure how much time we spend in idle - rdtscll(hw->TickStartInPD); - - return; -} - -bool crystalhd_flea_detect_fw_alive(struct crystalhd_hw *hw) -{ - uint32_t pollCnt = 0; - uint32_t hbCnt = 0; - uint32_t heartBeatReg1 = 0; - uint32_t heartBeatReg2 = 0; - bool bRetVal = false; - - heartBeatReg1 = hw->pfnReadDevRegister(hw->adp, HEART_BEAT_REGISTER); - while(1) - { - heartBeatReg2 = hw->pfnReadDevRegister(hw->adp, HEART_BEAT_REGISTER); - if(heartBeatReg1 != heartBeatReg2) { - hbCnt++; - heartBeatReg1 = heartBeatReg2; - } - - if(hbCnt >= HEART_BEAT_POLL_CNT) { - bRetVal = true; - break; - } - - pollCnt++; - if(pollCnt >= FLEA_MAX_POLL_CNT) { - bRetVal = false; - break; - } - - msleep_interruptible(1); - } - - return bRetVal; -} - -void crystalhd_flea_handle_PicQSts_intr(struct crystalhd_hw *hw) -{ - uint32_t newChBitmap=0; - - newChBitmap = hw->pfnReadDevRegister(hw->adp, RX_DMA_PIC_QSTS_MBOX); - - hw->PicQSts = newChBitmap; - - /* -- For link we were enabling the capture on format change - -- For Flea, we will get a PicQSts interrupt where we will - -- enable the capture. */ - - if(hw->RxCaptureState != 1) - { - hw->RxCaptureState = 1; - } -} - -void crystalhd_flea_update_tx_buff_info(struct crystalhd_hw *hw) -{ - TX_INPUT_BUFFER_INFO TxBuffInfo; - uint32_t ReadSzInDWords=0; - - ReadSzInDWords = (sizeof(TxBuffInfo) - sizeof(TxBuffInfo.Reserved))/4; - hw->pfnDevDRAMRead(hw, hw->TxBuffInfoAddr, ReadSzInDWords, (uint32_t*)&TxBuffInfo); - - if(TxBuffInfo.DramBuffAdd % 4) - { - printk("Tx Err:: DWORD UNAligned Tx Addr. Not Updating\n"); - return; - } - - hw->TxFwInputBuffInfo.DramBuffAdd = TxBuffInfo.DramBuffAdd; - hw->TxFwInputBuffInfo.DramBuffSzInBytes = TxBuffInfo.DramBuffSzInBytes; - hw->TxFwInputBuffInfo.Flags = TxBuffInfo.Flags; - hw->TxFwInputBuffInfo.HostXferSzInBytes = TxBuffInfo.HostXferSzInBytes; - hw->TxFwInputBuffInfo.SeqNum = TxBuffInfo.SeqNum; - - return; -} - -// was HWFleaNotifyFllChange -void crystalhd_flea_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext) -{ - unsigned long flags = 0; - uint32_t freeListLen = 0; - /* - * When we are doing the cleanup we should update DRAM only if the - * firmware is running. So Detect the heart beat. - */ - if(bCleanupContext && (!crystalhd_flea_detect_fw_alive(hw))) - return; - - spin_lock_irqsave(&hw->lock, flags); - freeListLen = crystalhd_dioq_count(hw->rx_freeq); - hw->pfnDevDRAMWrite(hw, hw->FleaFLLUpdateAddr, 1, &freeListLen); - spin_unlock_irqrestore(&hw->lock, flags); - - return; -} - - -static -void crystalhd_flea_init_power_state(struct crystalhd_hw *hw) -{ - hw->FleaEnablePWM = false; // disable by default - hw->FleaPowerState = FLEA_PS_NONE; -} - -static -bool crystalhd_flea_set_power_state(struct crystalhd_hw *hw, - FLEA_POWER_STATES NewState) -{ - bool StChangeSuccess=false; - uint32_t tempFLL = 0; - uint32_t freeListLen = 0; - BC_STATUS sts; - crystalhd_rx_dma_pkt *rx_pkt = NULL; - - freeListLen = crystalhd_dioq_count(hw->rx_freeq); - - switch(NewState) - { - case FLEA_PS_ACTIVE: - { - /*Transition to Active State*/ - if(hw->FleaPowerState == FLEA_PS_LP_PENDING) - { - StChangeSuccess = true; - hw->FleaPowerState = FLEA_PS_ACTIVE; - /* Write the correct FLL to FW */ - hw->pfnDevDRAMWrite(hw, - hw->FleaFLLUpdateAddr, - 1, - &freeListLen); - // We need to check to post here because we may never get a context to post otherwise - if(hw->PicQSts != 0) - { - rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); - if (rx_pkt) - sts = hw->pfnPostRxSideBuff(hw, rx_pkt); - } - //printk(" Success\n"); - - }else if(hw->FleaPowerState == FLEA_PS_LP_COMPLETE){ - crystalhd_flea_runtime_power_up(hw); - StChangeSuccess = true; - hw->FleaPowerState = FLEA_PS_ACTIVE; - /* Write the correct FLL to FW */ - hw->pfnDevDRAMWrite(hw, - hw->FleaFLLUpdateAddr, - 1, - &freeListLen); - /* Now check if we missed processing PiQ and TXFIFO interrupts when we were in power down */ - if (hw->PwrDwnPiQIntr) - { - crystalhd_flea_handle_PicQSts_intr(hw); - hw->PwrDwnPiQIntr = false; - } - // We need to check to post here because we may never get a context to post otherwise - if(hw->PicQSts != 0) - { - rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); - if (rx_pkt) - sts = hw->pfnPostRxSideBuff(hw, rx_pkt); - } - if (hw->PwrDwnTxIntr) - { - crystalhd_flea_update_tx_buff_info(hw); - hw->PwrDwnTxIntr = false; - } - - } - break; - } - - case FLEA_PS_LP_PENDING: - { - if(hw->FleaPowerState != FLEA_PS_ACTIVE) - { - break; - } - - //printk(" Success\n"); - - StChangeSuccess = true; - /* Write 0 FLL to FW to prevent it from sending PQ*/ - hw->pfnDevDRAMWrite(hw, - hw->FleaFLLUpdateAddr, - 1, - &tempFLL); - hw->FleaPowerState = FLEA_PS_LP_PENDING; - break; - } - - case FLEA_PS_LP_COMPLETE: - { - if( (hw->FleaPowerState == FLEA_PS_ACTIVE) || - (hw->FleaPowerState == FLEA_PS_LP_PENDING)) { - /* Write 0 FLL to FW to prevent it from sending PQ*/ - hw->pfnDevDRAMWrite(hw, - hw->FleaFLLUpdateAddr, - 1, - &tempFLL); - crystalhd_flea_runtime_power_dn(hw); - StChangeSuccess = true; - hw->FleaPowerState = FLEA_PS_LP_COMPLETE; - - } - break; - } - default: - break; - } - - return StChangeSuccess; -} - -/* -* Look At Different States and List Status and decide on -* Next Logical State To Be In. -*/ -static -void crystalhd_flea_set_next_power_state(struct crystalhd_hw *hw, - FLEA_STATE_CH_EVENT PowerEvt) -{ - FLEA_POWER_STATES NextPS; - NextPS = hw->FleaPowerState; - - if( hw->FleaEnablePWM == false ) - { - hw->FleaPowerState = FLEA_PS_ACTIVE; - return; - } - -// printk("Trying Power State Transition from %x Because Of Event:%d \n", -// hw->FleaPowerState, -// PowerEvt); - - if(PowerEvt == FLEA_EVT_STOP_DEVICE) - { - hw->FleaPowerState = FLEA_PS_STOPPED; - return; - } - - if(PowerEvt == FLEA_EVT_START_DEVICE) - { - hw->FleaPowerState = FLEA_PS_ACTIVE; - return; - } - - switch(hw->FleaPowerState) - { - case FLEA_PS_ACTIVE: - { - if(PowerEvt == FLEA_EVT_FLL_CHANGE) - { - /*Ready List Was Decremented. */ - //printk("1:TxL0Sts:%x TxL1Sts:%x EmptyCnt:%x RxL0Sts:%x RxL1Sts:%x FwCmdCnt:%x\n", - // hw->TxList0Sts, - // hw->TxList1Sts, - // hw->EmptyCnt, - // hw->rx_list_sts[0], - // hw->rx_list_sts[1], - // hw->FwCmdCnt); - - if( (hw->TxList0Sts == ListStsFree) && - (hw->TxList1Sts == ListStsFree) && - (!hw->EmptyCnt) && /*We have Not Indicated Any Empty Fifo to Application*/ - (!hw->SingleThreadAppFIFOEmpty) && /*for single threaded apps*/ - (!(hw->rx_list_sts[0] && rx_waiting_y_intr)) && - (!(hw->rx_list_sts[1] && rx_waiting_y_intr)) && - (!hw->FwCmdCnt)) - { - NextPS = FLEA_PS_LP_COMPLETE; - }else{ - NextPS = FLEA_PS_LP_PENDING; - } - } - - break; - } - - case FLEA_PS_LP_PENDING: - { - if( (PowerEvt == FLEA_EVT_FW_CMD_POST) || - (PowerEvt == FLEA_EVT_FLL_CHANGE)) - { - NextPS = FLEA_PS_ACTIVE; - }else if(PowerEvt == FLEA_EVT_CMD_COMP){ - - //printk("2:TxL0Sts:%x TxL1Sts:%x EmptyCnt:%x STAppFIFOEmpty:%x RxL0Sts:%x RxL1Sts:%x FwCmdCnt:%x\n", - // hw->TxList0Sts, - // hw->TxList1Sts, - // hw->EmptyCnt, - // hw->SingleThreadAppFIFOEmpty, - // hw->rx_list_sts[0], - // hw->rx_list_sts[1], - // hw->FwCmdCnt); - - if( (hw->TxList0Sts == ListStsFree) && - (hw->TxList1Sts == ListStsFree) && - (!hw->EmptyCnt) && /*We have Not Indicated Any Empty Fifo to Application*/ - (!hw->SingleThreadAppFIFOEmpty) && /*for single threaded apps*/ - (!(hw->rx_list_sts[0] && rx_waiting_y_intr)) && - (!(hw->rx_list_sts[1] && rx_waiting_y_intr)) && - (!hw->FwCmdCnt)) - { - NextPS = FLEA_PS_LP_COMPLETE; - } - } - break; - } - case FLEA_PS_LP_COMPLETE: - { - if( (PowerEvt == FLEA_EVT_FLL_CHANGE) || - (PowerEvt == FLEA_EVT_FW_CMD_POST)) - { - NextPS = FLEA_PS_ACTIVE; - } - - break; - } - default: - { - printk("Invalid Flea Power State %x\n", - hw->FleaPowerState); - - break; - } - } - - if(hw->FleaPowerState != NextPS) - { - //printk("%s:State Transition [FromSt:%x ToSt:%x] Because Of Event:%d \n", - // __FUNCTION__, - // hw->FleaPowerState, - // NextPS, - // PowerEvt); - - crystalhd_flea_set_power_state(hw,NextPS); - } - - return; -} - -//// was FleaSetRxPicFireAddr -//static -//void crystalhd_flea_set_rx_pic_fire_addr(struct crystalhd_hw *hw, uint32_t BorshContents) -//{ -// hw->FleaRxPicDelAddr = BorshContents + 1 + HOST_TO_FW_PIC_DEL_INFO_ADDR; -// hw->FleaFLLUpdateAddr = BorshContents + 1 + HOST_TO_FW_FLL_ADDR; -// -// return; -//} - -void crystalhd_flea_init_temperature_measure (struct crystalhd_hw *hw, bool bTurnOn) -{ - hw->TemperatureRegVal=0; - - if(bTurnOn) { - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x3); - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x203); - } else { - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x103); - } - - return; -} - -// was HwFleaUpdateTempInfo -void crystalhd_flea_update_temperature(struct crystalhd_hw *hw) -{ - uint32_t regVal = 0; - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_TEMP_MON_STATUS); - hw->TemperatureRegVal = regVal; - - return; -} - -/** -* crystalhd_flea_download_fw - Write data to DRAM area. -* @adp: Adapter instance -* @pBuffer: Buffer pointer for the FW data. -* @buffSz: data size in bytes. -* -* Return: -* Status. -* -* Flea firmware download routine. -*/ -BC_STATUS crystalhd_flea_download_fw(struct crystalhd_hw *hw, uint8_t *pBuffer, uint32_t buffSz) -{ - uint32_t pollCnt=0,regVal=0; - uint32_t borchStachAddr=0; - uint32_t *pCmacSig=NULL,cmacOffset=0,i=0; - //uint32_t BuffSz = (BuffSzInDWords * 4); - //uint32_t HBCnt=0; - - bool bRetVal = true; - - dev_dbg(&hw->adp->pdev->dev, "[%s]: Sz:%d\n", __func__, buffSz); - -///* -//-- Step 1. Enable the SRCUBBING and DRAM SCRAMBLING -//-- Step 2. Poll for SCRAM_KEY_DONE_INT. -//-- Step 3. Write the BORCH and STARCH addresses. -//-- Step 4. Write the firmware to DRAM. -//-- Step 5. Write the CMAC to SCRUB->CMAC registers. -//-- Step 6. Write the ARM run bit to 1. -//-- Step 7. Poll for BOOT verification done interrupt. -//*/ - -// /* First validate that we got data in the FW buffer */ - if (buffSz == 0) - return BC_STS_ERROR; - -//-- Step 1. Enable the SRCUBBING and DRAM SCRAMBLING. -// Can we set both the bits at the same time?? Security Arch Doc describes the steps -// and the first step is to enable scrubbing and then scrambling. - - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 1. Enable scrubbing\n"); - - //Enable Scrubbing - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE); - regVal |= SCRUB_ENABLE_BIT; - hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE, regVal); - - //Enable Scrambling - regVal |= DRAM_SCRAM_ENABLE_BIT; - hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE, regVal); - - -//-- Step 2. Poll for SCRAM_KEY_DONE_INT. - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 2. Poll for SCRAM_KEY_DONE_INT\n"); - - pollCnt=0; - while(pollCnt < FLEA_MAX_POLL_CNT) - { - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_STATUS); - - if(regVal & SCRAM_KEY_DONE_INT_BIT) - break; - - pollCnt++; - msleep_interruptible(1); /*1 Milli Sec delay*/ - } - - //-- Will Assert when we do not see SCRAM_KEY_DONE_INTTERRUPT - if(!(regVal & SCRAM_KEY_DONE_INT_BIT)) - { - dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 2. Did not get scram key done interrupt.\n"); - return BC_STS_ERROR; - } - - /*Clear the interrupts by writing the register value back*/ - regVal &= 0x00FFFFFF; //Mask off the reserved bits.[24-31] - hw->pfnWriteDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_CLEAR, regVal); - -//-- Step 3. Write the BORCH and STARCH addresses. - borchStachAddr = GetScrubEndAddr(buffSz); - - hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_BORCH_END_ADDRESS, borchStachAddr); - hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_STARCH_END_ADDRESS, borchStachAddr); - - /* - * Now the command address is - * relative to firmware file size. - */ - //FWIFSetFleaCmdAddr(pHWExt->pFwExt, - // borchStachAddr+1+DDRADDR_4_FWCMDS); - - hw->fwcmdPostAddr = borchStachAddr+1+DDRADDR_4_FWCMDS; - hw->fwcmdPostMbox = FW_CMD_POST_MBOX; - hw->fwcmdRespMbox = FW_CMD_RES_MBOX; - //FleaSetRxPicFireAddr(pHWExt,borchStachAddr); - hw->FleaRxPicDelAddr = borchStachAddr + 1 + HOST_TO_FW_PIC_DEL_INFO_ADDR; - hw->FleaFLLUpdateAddr = borchStachAddr + 1 + HOST_TO_FW_FLL_ADDR; - - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 3. Write the BORCH and STARCH addresses. %x:%x, %x:%x\n", - BCHP_SCRUB_CTRL_BORCH_END_ADDRESS, - borchStachAddr, - BCHP_SCRUB_CTRL_STARCH_END_ADDRESS, - borchStachAddr ); - -//-- Step 4. Write the firmware to DRAM. [Without the Signature, 32-bit access to DRAM] - - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 4. Write the firmware to DRAM. Sz:%d Bytes\n", - buffSz - FLEA_FW_SIG_LEN_IN_BYTES - LENGTH_FIELD_SIZE); - - hw->pfnDevDRAMWrite(hw, FW_DOWNLOAD_START_ADDR, (buffSz - FLEA_FW_SIG_LEN_IN_BYTES - LENGTH_FIELD_SIZE)/4, (uint32_t *)pBuffer); - -// -- Step 5. Write the signature to CMAC register. -/* --- This is what we need to write to CMAC registers. -================================================================================== -Register Offset Boot Image CMAC - Value -================================================================================== -BCHP_SCRUB_CTRL_BI_CMAC_31_0 0x000f600c CMAC Bits[31:0] -BCHP_SCRUB_CTRL_BI_CMAC_63_32 0x000f6010 CMAC Bits[63:32] -BCHP_SCRUB_CTRL_BI_CMAC_95_64 0x000f6014 CMAC Bits[95:64] -BCHP_SCRUB_CTRL_BI_CMAC_127_96 0x000f6018 CMAC Bits[127:96] -================================================================================== -*/ - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 5. Write the signature to CMAC register.\n"); - cmacOffset = buffSz - FLEA_FW_SIG_LEN_IN_BYTES; - pCmacSig = (uint32_t *) &pBuffer[cmacOffset]; - - for(i=0;i < FLEA_FW_SIG_LEN_IN_DWORD;i++) - { - uint32_t offSet = (BCHP_SCRUB_CTRL_BI_CMAC_127_96 - (i * 4)); - - hw->pfnWriteDevRegister(hw->adp, offSet, bswap_32_1(*pCmacSig)); - - pCmacSig++; - } - -//-- Step 6. Write the ARM run bit to 1. -// We need a write back because we do not want to change other bits - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 6. Write the ARM run bit to 1.\n"); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL); - regVal |= ARM_RUN_REQ_BIT; - hw->pfnWriteDevRegister(hw->adp, BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL, regVal); - -//-- Step 7. Poll for Boot Verification done/failure interrupt. - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Poll for Boot Verification done/failure interrupt.\n"); - - pollCnt=0; - while(1) - { - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_STATUS); - - if(regVal & BOOT_VER_FAIL_BIT ) //|| regVal & SHARF_ERR_INTR) - { - dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Error bit occured. RetVal:%x\n", regVal); - - bRetVal = false; - break; - } - - if(regVal & BOOT_VER_DONE_BIT) - { - dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Done RetVal:%x\n", regVal); - - bRetVal = true; /*This is the only place we return TRUE from*/ - break; - } - - pollCnt++; - if( pollCnt >= FLEA_MAX_POLL_CNT ) - { - dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Both done and failure bits are not set.\n"); - bRetVal = false; - break; - } - - msleep_interruptible(1); /*1 Milli Sec delay*/ - } - - if( !bRetVal ) - { - dev_info(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Firmware image signature failure.\n"); - return BC_STS_ERROR; - } - - /*Clear the interrupts by writing the register value back*/ - regVal &= 0x00FFFFFF; //Mask off the reserved bits.[24-31] - hw->pfnWriteDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_CLEAR, regVal); - - msleep_interruptible(10); /*10 Milli Sec delay*/ - -/* --- It was seen on Dell390 systems that the firmware command was fired before the --- firmware was actually ready to accept the firmware commands. The driver did --- not recieve a response for the firmware commands and this was causing the DIL to timeout --- ,reclaim the resources and crash. The following code looks for the heartbeat and --- to make sure that we return from this function only when we get the heart beat making sure --- that the firmware is running. -*/ - - /* - * By default enable everything except the RX_MBOX_WRITE_WRKARND [scratch workaround] - * to be backward compatible. The firmware will enable the workaround - * by writing to scratch 5. In future the firmware can disable the workarounds - * and we will not have to WHQL the driver at all. - */ - //hw->EnWorkArounds = RX_PIC_Q_STS_WRKARND | RX_DRAM_WRITE_WRKARND; - bRetVal = crystalhd_flea_detect_fw_alive(hw); - if( !bRetVal ) - { - dev_info(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 8. Detect firmware heart beat failed.\n"); - return BC_STS_ERROR; - } - - /*if(bRetVal == TRUE) - { - ULONG EnaWorkArnds; - hw->pfnReadDevRegister(hw->adp, - RX_POST_CONFIRM_SCRATCH, - &EnaWorkArnds); - - if( ((EnaWorkArnds & 0xffff0000) >> 16) == FLEA_WORK_AROUND_SIG) - { - pHWExt->EnWorkArounds = EnaWorkArnds & 0xffff; - DebugPrint(BRCM_COMP_ID, - BRCM_DBG_LEVEL, - "WorkArounds Enable Value[%x]\n",pHWExt->EnWorkArounds); - } - }*/ - - dev_info(&hw->adp->pdev->dev, "[%s]: Complete.\n", __func__); - return BC_STS_SUCCESS; -} - -bool crystalhd_flea_start_device(struct crystalhd_hw *hw) -{ - uint32_t regVal = 0; - bool bRetVal = false; - - /* - -- Issue Core reset to bring in the default values in place - */ - crystalhd_flea_core_reset(hw); - - /* - -- If the gisb arbitar register is not set to some other value - -- and the firmware crashes, we see a NMI since the hardware did - -- not respond to a register read at all. The PCI-E trace confirms the problem. - -- Right now we are setting the register values to 0x7e00 and will check later - -- what should be the correct value to program. - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_GISB_ARB_TIMER, 0xd80); - - /* - -- Disable all interrupts - */ - crystalhd_flea_clear_interrupts(hw); - crystalhd_flea_disable_interrupts(hw); - - /* - -- Enable the option for getting the done count in - -- Rx DMA engine. - */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_DMA_DEBUG_OPTIONS_REG); - regVal |= 0x10; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_DMA_DEBUG_OPTIONS_REG, regVal); - - /* - -- Enable the TX DMA Engine once on startup. - -- This is a new bit added. - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_CTRL, 0x01); - - /* - -- Enable the RX3 DMA Engine once on startup. - -- This is a new bit added. - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_DMA_CTRL, 0x01); - - /* - -- Set the Run bit for RX-Y and RX-UV DMA engines. - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, 0x01); - - /* - -- Make sure Early L1 is disabled - NAREN - This will not prevent the device from entering L1 under active mode - */ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC_PERST_CLOCK_CTRL); - regVal &= ~BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_MASK; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC_PERST_CLOCK_CTRL, regVal); - - crystalhd_flea_init_dram(hw); - - msleep_interruptible(5); - - // Enable the Single Shot Transaction on PCI by disabling the - // bit 29 of transaction configuration register - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PCIE_TL_TRANSACTION_CONFIGURATION); - regVal &= (~(BC_BIT(29))); - hw->pfnWriteDevRegister(hw->adp, BCHP_PCIE_TL_TRANSACTION_CONFIGURATION, regVal); - - crystalhd_flea_init_temperature_measure(hw,true); - - crystalhd_flea_init_power_state(hw); - crystalhd_flea_set_next_power_state(hw, FLEA_EVT_START_DEVICE); - - /* - -- Enable all interrupts - */ - crystalhd_flea_clear_interrupts(hw); - crystalhd_flea_enable_interrupts(hw); - - /* - -- This is the only time we set this pointer for Flea. - -- Since there is no stop the pointer is not reset anytime.... - -- except for fatal errors. - */ - hw->rx_list_post_index = 0; - hw->RxCaptureState = 0; - - msleep_interruptible(1); - - return bRetVal; -} - - -bool crystalhd_flea_stop_device(struct crystalhd_hw *hw) -{ - uint32_t regVal=0, pollCnt=0; - - /* - -- Issue the core reset so that we - -- make sure there is nothing running. - */ - crystalhd_flea_core_reset(hw); - - crystalhd_flea_init_temperature_measure(hw, false); - - /* - -- If the gisb arbitrater register is not set to some other value - -- and the firmware crashes, we see a NMI since the hardware did - -- not respond to a register read at all. The PCI-E trace confirms the problem. - -- Right now we are setting the register values to 0x7e00 and will check later - -- what should be the correct value to program. - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_GISB_ARB_TIMER, 0xd80); - - /* - -- Disable the TX DMA Engine once on shutdown. - -- This is a new bit added. - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_CTRL, 0x0); - - /* - -- Disable the RX3 DMA Engine once on Stop. - -- This is a new bit added. - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_DMA_CTRL, 0x0); - - /* - -- Clear the RunStop Bit For RX DMA Control - */ - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, 0x0); - - hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, 0x0); - - // * Wait for MEMC to become idle - pollCnt=0; - while (1) - { - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); - - if(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK) - break; - - pollCnt++; - if(pollCnt >= 100) - break; - - msleep_interruptible(1); - } - - /*First Disable the AVD and ARM before disabling the DRAM*/ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); - - regVal = BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; - - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); - - /* - -- Disable the interrupt after disabling the ARM and AVD. - -- We should be able to access the registers because we still - -- have not disabled the clock for blink block. We disable the - -- blick 108 abd 216 clock at the end of this function. - */ - crystalhd_flea_clear_interrupts(hw); - crystalhd_flea_disable_interrupts(hw); - - /*Now try disabling the DRAM.*/ - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); - - regVal |= BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK; - - // * disable CKE - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); - - // * issue refresh command - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); - - pollCnt=0; - while(1) - { - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); - - if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK)) - break; - - pollCnt++; - if(pollCnt >= 100) - break; - - msleep_interruptible(1); - } - - // * Enable DDR clock, DM and READ_ENABLE pads power down and force into the power down - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK | - BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK); - - // * Power down BL LDO cells - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, - BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, - BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK); - - // * Enable DDR control signal pad power down and force into the power down - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, - BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK | - BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK); - - // * Disable ddr phy clock - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, - BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK); - - // * Disable PLL output - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, - regVal & ~BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_MASK); - - // * Power down addr_ctl LDO cells - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, - BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK); - - // * Power down the PLL - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); - - hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, - regVal | BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK); - - // shut down the PLL1 - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PLL1_CTRL); - - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PLL1_CTRL, - regVal | BCHP_CLK_PLL1_CTRL_POWERDOWN_MASK); - - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PLL0_ARM_DIV, 0xff); - - regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); - - regVal |= BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_MASK | - BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_MASK | - BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_MASK | - BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_MASK; - - hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); - - crystalhd_flea_set_next_power_state(hw, FLEA_EVT_STOP_DEVICE); - return true; -} - -bool -crystalhd_flea_wake_up_hw(struct crystalhd_hw *hw) -{ - if(hw->FleaPowerState != FLEA_PS_ACTIVE) - { - crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); - } - - // Now notify HW of the number of entries in the Free List - // This starts up the channel bitmap delivery - crystalhd_flea_notify_fll_change(hw, false); - - hw->WakeUpDecodeDone = true; - - return true; -} - -bool crystalhd_flea_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags) -{ - uint32_t regVal=0; - TX_INPUT_BUFFER_INFO *pTxBuffInfo; - uint32_t FlagsAddr=0; - - *empty_sz = 0; -// *DramAddrOut=0; - - - /* Add condition here to wake up the HW in case some application is trying to do TX before starting RX - like FP */ - /* To prevent deadlocks. We are called here from Synchronized context so we can safely call this directly */ - - if(hw->WakeUpDecodeDone != true) - { - // Only wake up the HW if we are either being called from a single threaded app - like FP - // or if we are not checking for the input buffer size as just a test - if(*flags == 0) - crystalhd_flea_wake_up_hw(hw); - else { - *empty_sz = 2 * 1024 * 1024; // FW Buffer size - //*DramAddrOut=0; - *flags=0; - return false; - } - } - - /* if we have told the app that we have buffer empty then we cannot go to low power */ - if((hw->FleaPowerState != FLEA_PS_ACTIVE) && !hw->SingleThreadAppFIFOEmpty) - { - //*TxBuffSzOut=0; - //*DramAddrOut=0; - *empty_sz = 0; - *flags=0; - //printk("PD can't Tx\n"); - return true; /*Indicate FULL*/ - } - - - if(hw->TxFwInputBuffInfo.Flags & DFW_FLAGS_TX_ABORT) - { - *empty_sz=0; - //*DramAddrOut=0; - *flags |= DFW_FLAGS_TX_ABORT; - return true; - } - - if( (hw->TxFwInputBuffInfo.DramBuffSzInBytes < needed_sz) - ||(!hw->TxFwInputBuffInfo.DramBuffAdd)) - { - *empty_sz=0; - //*DramAddrOut=0; - *flags=0; - return true; /*Indicate FULL*/ - } - - if(hw->TxFwInputBuffInfo.DramBuffAdd % 4) - { - /* - -- Indicate Full if we get a non-dowrd aligned address. - -- This will avoid us posting the command to firmware and - -- The TX will timeout and we will close the application properly. - -- This avoids a illegal operation as far as the TX is concerned. - */ - printk("TxSDRAM-Destination Address Not DWORD Aligned:%x\n",hw->TxFwInputBuffInfo.DramBuffAdd); - return true; - } - - /* - -- We got everything correctly from the firmware and hence we should be - -- able to do the DMA. Indicate what app wants to hear. - -- Firmware SAYS: I AM HUNGRY, GIVE ME FOOD. :) - */ - *empty_sz=hw->TxFwInputBuffInfo.DramBuffSzInBytes; - //*dramAddrOut=pHWExt->TxFwInputBuffInfo.DramBuffAdd; -// printk("empty size is %d\n", *empty_sz); - - /* If we are just checking stats and are not actually going to DMA, don't increment */ - /* But we have to account for single threaded apps */ - if((*flags & 0x08) == 0x08) - { - // This is a synchronized function - // NAREN - In single threaded mode, if we have less than a defined size of buffer - // ask the firmware to wrap around. To prevent deadlocks. - if(hw->TxFwInputBuffInfo.DramBuffSzInBytes < TX_WRAP_THRESHOLD) - { - pTxBuffInfo = (TX_INPUT_BUFFER_INFO *) (0); - FlagsAddr = hw->TxBuffInfoAddr + ((uintptr_t) (&pTxBuffInfo->Flags)); - // Read Modify the Flags to ask the FW to WRAP - hw->pfnDevDRAMRead(hw,FlagsAddr,1,®Val); - regVal |= DFW_FLAGS_WRAP; - hw->pfnDevDRAMWrite(hw,FlagsAddr,1,®Val); - - // Indicate Busy to the application because we have to get new buffers from FW - *empty_sz=0; - // *DramAddrOut=0; - *flags=0; - // Wait for the next interrupt from the HW - hw->TxFwInputBuffInfo.DramBuffSzInBytes = 0; - hw->TxFwInputBuffInfo.DramBuffAdd = 0; - return true; - } - else - hw->SingleThreadAppFIFOEmpty = true; - } - else if((*flags & 0x04) != 0x04) - hw->EmptyCnt++; //OS_INTERLOCK_INCREMENT(&pHWExt->EmptyCnt); - - // Different from our Windows implementation - // set bit 7 of the flags field to indicate that we have to use the destination address for TX - *flags |= BC_BIT(7); - - return false; /*Indicate Empty*/ -} - -BC_STATUS crystalhd_flea_fw_cmd_post_proc(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) -{ - BC_STATUS sts = BC_STS_SUCCESS; - DecRspChannelStartVideo *st_rsp = NULL; - C011_TS_RSP *pGenRsp = NULL; - DecRspChannelChannelOpen *pRsp = NULL; - - pGenRsp = (C011_TS_RSP *) fw_cmd->rsp; - - switch (fw_cmd->cmd[0]) { - case eCMD_C011_DEC_CHAN_STREAM_OPEN: - hw->channelNum = pGenRsp->ulParams[2]; - - dev_dbg(&hw->adp->pdev->dev, "Snooped Stream Open Cmd For ChNo:%x\n", hw->channelNum); - break; - case eCMD_C011_DEC_CHAN_OPEN: - pRsp = (DecRspChannelChannelOpen *)pGenRsp; - hw->channelNum = pRsp->ChannelID; - - /* used in Flea to update the Tx Buffer stats */ - hw->TxBuffInfoAddr = pRsp->transportStreamCaptureAddr; - hw->TxFwInputBuffInfo.DramBuffAdd=0; - hw->TxFwInputBuffInfo.DramBuffSzInBytes=0; - hw->TxFwInputBuffInfo.Flags=0; - hw->TxFwInputBuffInfo.HostXferSzInBytes=0; - hw->TxFwInputBuffInfo.SeqNum=0; - - /* NAREN Init power management states here when we start the channel */ - hw->PwrDwnTxIntr = false; - hw->PwrDwnPiQIntr = false; - hw->EmptyCnt = 0; - hw->SingleThreadAppFIFOEmpty = false; - - dev_dbg(&hw->adp->pdev->dev, "Snooped ChOpen Cmd For ChNo:%x TxBuffAddr:%x\n", - hw->channelNum, - hw->TxBuffInfoAddr); - break; - case eCMD_C011_DEC_CHAN_START_VIDEO: - st_rsp = (DecRspChannelStartVideo *)fw_cmd->rsp; - hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; - hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; - - dev_dbg(&hw->adp->pdev->dev, "Snooping CHAN_START_VIDEO command to get the Addr of Del/Rel Queue\n"); - dev_dbg(&hw->adp->pdev->dev, "DelQAddr:%x RelQAddr:%x\n", - hw->pib_del_Q_addr, hw->pib_rel_Q_addr); - break; - default: - break; - } - return sts; -} - -BC_STATUS crystalhd_flea_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) -{ - struct device *dev; - uint32_t cnt = 0, cmd_res_addr; - uint32_t *cmd_buff, *res_buff; - wait_queue_head_t fw_cmd_event; - int rc = 0; - BC_STATUS sts; - unsigned long flags; - - crystalhd_create_event(&fw_cmd_event); - - if (!hw || !fw_cmd) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &hw->adp->pdev->dev; - - dev_dbg(dev, "%s entered\n", __func__); - - cmd_buff = fw_cmd->cmd; - res_buff = fw_cmd->rsp; - - if (!cmd_buff || !res_buff) { - dev_err(dev, "Invalid Parameters for F/W Command\n"); - return BC_STS_INV_ARG; - } - - hw->fwcmd_evt_sts = 0; - hw->pfw_cmd_event = &fw_cmd_event; - hw->FwCmdCnt++; - - if(hw->FleaPowerState != FLEA_PS_ACTIVE) - { - crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FW_CMD_POST); - } - - spin_lock_irqsave(&hw->lock, flags); - - /*Write the command to the memory*/ - hw->pfnDevDRAMWrite(hw, hw->fwcmdPostAddr, FW_CMD_BUFF_SZ, cmd_buff); - - /*Memory Read for memory arbitrator flush*/ - hw->pfnDevDRAMRead(hw, hw->fwcmdPostAddr, 1, &cnt); - - /* Write the command address to mailbox */ - hw->pfnWriteDevRegister(hw->adp, hw->fwcmdPostMbox, hw->fwcmdPostAddr); - - spin_unlock_irqrestore(&hw->lock, flags); - - msleep_interruptible(50); - - // FW commands should complete even if we got a signal from the upper layer - crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, - 20000, rc, true); - - if (!rc) { - sts = BC_STS_SUCCESS; - } else if (rc == -EBUSY) { - dev_err(dev, "Firmware command T/O\n"); - sts = BC_STS_TIMEOUT; - } else if (rc == -EINTR) { - dev_info(dev, "FwCmd Wait Signal - Can Never Happen\n"); - sts = BC_STS_IO_USER_ABORT; - } else { - dev_err(dev, "FwCmd IO Error.\n"); - sts = BC_STS_IO_ERROR; - } - - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "FwCmd Failed.\n"); - return sts; - } - - spin_lock_irqsave(&hw->lock, flags); - - /*Get the Responce Address*/ - cmd_res_addr = hw->pfnReadDevRegister(hw->adp, hw->fwcmdRespMbox); - - /*Read the Response*/ - hw->pfnDevDRAMRead(hw, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); - - spin_unlock_irqrestore(&hw->lock, flags); - - if (res_buff[2] != 0) { - dev_err(dev, "res_buff[2] != C011_RET_SUCCESS\n"); - return BC_STS_FW_CMD_ERR; - } - - sts = crystalhd_flea_fw_cmd_post_proc(hw, fw_cmd); - if (sts != BC_STS_SUCCESS) - dev_err(dev, "crystalhd_fw_cmd_post_proc Failed.\n"); - - return sts; - -} - -void crystalhd_flea_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) -{ - uint32_t y_dn_sz_reg, uv_dn_sz_reg; - - if (!list_index) { - y_dn_sz_reg = BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT; - uv_dn_sz_reg = BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT; - } else { - y_dn_sz_reg = BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT; - uv_dn_sz_reg = BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT; - } - - *y_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, y_dn_sz_reg); - *uv_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, uv_dn_sz_reg); - - return ; -} - -BC_STATUS crystalhd_flea_hw_pause(struct crystalhd_hw *hw, bool state) -{ - //printk("%s: Set flea to power down.\n", __func__); - crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); - return BC_STS_SUCCESS; -} - -bool crystalhd_flea_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth) -{ - unsigned long flags = 0; - crystalhd_dioq_t *ioq; - crystalhd_elem_t *tmp; - crystalhd_rx_dma_pkt *rpkt; - - *meta_payload = 0; - - ioq = hw->rx_rdyq; - spin_lock_irqsave(&ioq->lock, flags); - - if ((ioq->count > 0) && (ioq->head != (crystalhd_elem_t *)&ioq->head)) { - tmp = ioq->head; - spin_unlock_irqrestore(&ioq->lock, flags); - rpkt = (crystalhd_rx_dma_pkt *)tmp->data; - if (rpkt) { - flea_GetPictureInfo(hw, rpkt, picNumFlags, meta_payload); - //printk("%s: flea_GetPictureInfo Pic#:%d\n", __func__, PicNumber); - } - return true; - } - spin_unlock_irqrestore(&ioq->lock, flags); - - return false; - -} - -void crystalhd_flea_clear_rx_errs_intrs(struct crystalhd_hw *hw) -/* --- Clears all the errors and interrupt on RX DMA engine. -*/ -{ - uint32_t ulRegVal; - FLEA_INTR_STS_REG IntrToClear,IntrSts; - - IntrToClear.WholeReg = 0; - IntrSts.WholeReg = 0; - - IntrSts.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); - if(IntrSts.WholeReg) - { - ulRegVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS); - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, ulRegVal); - ulRegVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS); - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, ulRegVal); - - IntrToClear.L0UVRxDMADone = IntrSts.L0UVRxDMADone; - IntrToClear.L0UVRxDMAErr = IntrSts.L0UVRxDMAErr; - IntrToClear.L0YRxDMADone = IntrSts.L0YRxDMADone; - IntrToClear.L0YRxDMAErr = IntrSts.L0YRxDMAErr; - IntrToClear.L1UVRxDMADone = IntrSts.L1UVRxDMADone; - IntrToClear.L1UVRxDMAErr = IntrSts.L1UVRxDMAErr; - IntrToClear.L1YRxDMADone = IntrSts.L1YRxDMADone; - IntrToClear.L1YRxDMAErr = IntrSts.L1YRxDMAErr; - - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrToClear.WholeReg); - - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); - } - return; -} - - -void crystalhd_flea_stop_rx_dma_engine(struct crystalhd_hw *hw) -{ - FLEA_INTR_STS_REG IntrStsValue; - bool failedL0 = true, failedL1 = true; - uint32_t pollCnt = 0; - - hw->RxCaptureState = 2; - - if((hw->rx_list_sts[0] == sts_free) && (hw->rx_list_sts[1] == sts_free)) { - hw->RxCaptureState = 0; - return; // Nothing to be done - } - - if(hw->rx_list_sts[0] == sts_free) - failedL0 = false; - if(hw->rx_list_sts[1] == sts_free) - failedL1 = false; - - while(1) - { - IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); - - if(hw->rx_list_sts[0] != sts_free) { - if( (IntrStsValue.L0YRxDMADone) || (IntrStsValue.L0YRxDMAErr) || - (IntrStsValue.L0UVRxDMADone) || (IntrStsValue.L0UVRxDMAErr) ) - { - failedL0 = false; - } - } - else - failedL0 = false; - - if(hw->rx_list_sts[1] != sts_free) { - if( (IntrStsValue.L1YRxDMADone) || (IntrStsValue.L1YRxDMAErr) || - (IntrStsValue.L1UVRxDMADone) || (IntrStsValue.L1UVRxDMAErr) ) - { - failedL1 = false; - } - } - else - failedL1 = false; - - msleep_interruptible(10); - - if(pollCnt >= MAX_VALID_POLL_CNT) - break; - - if((failedL0 == false) && (failedL1 == false)) - break; - - pollCnt++; - } - - if(failedL0 || failedL1) - printk("Failed to stop RX DMA\n"); - - hw->RxCaptureState = 0; - - crystalhd_flea_clear_rx_errs_intrs(hw); -} - -BC_STATUS crystalhd_flea_hw_fire_rxdma(struct crystalhd_hw *hw, - crystalhd_rx_dma_pkt *rx_pkt) -{ - struct device *dev; - addr_64 desc_addr; - unsigned long flags; - PIC_DELIVERY_HOST_INFO PicDeliInfo; - uint32_t BuffSzInDwords; - - if (!hw || !rx_pkt) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &hw->adp->pdev->dev; - - if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { - dev_err(dev, "List Out Of bounds %x\n", hw->rx_list_post_index); - return BC_STS_INV_ARG; - } - - if(hw->RxCaptureState != 1) { - printk("Capture not enabled\n"); - return BC_STS_BUSY; - } - - spin_lock_irqsave(&hw->rx_lock, flags); - if (hw->rx_list_sts[hw->rx_list_post_index]) { - spin_unlock_irqrestore(&hw->rx_lock, flags); - return BC_STS_BUSY; - } - - if (!TEST_BIT(hw->PicQSts, hw->channelNum)) { - // NO pictures available for this channel - spin_unlock_irqrestore(&hw->rx_lock, flags); - return BC_STS_BUSY; - } - - CLEAR_BIT(hw->PicQSts, hw->channelNum); - - desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; - - PicDeliInfo.ListIndex = hw->rx_list_post_index; - PicDeliInfo.RxSeqNumber = hw->RxSeqNum; - PicDeliInfo.HostDescMemLowAddr_Y = desc_addr.low_part; - PicDeliInfo.HostDescMemHighAddr_Y = desc_addr.high_part; - - if (rx_pkt->uv_phy_addr) { - /* Program the UV descriptor */ - desc_addr.full_addr = rx_pkt->uv_phy_addr; - PicDeliInfo.HostDescMemLowAddr_UV = desc_addr.low_part; - PicDeliInfo.HostDescMemHighAddr_UV = desc_addr.high_part; - } - - rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; - hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; - if (rx_pkt->uv_phy_addr) - hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; - hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; - - spin_unlock_irqrestore(&hw->rx_lock, flags); - - crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); - - BuffSzInDwords = (sizeof (PicDeliInfo) - sizeof(PicDeliInfo.Reserved))/4; - - /* - -- Write the parameters in DRAM. - */ - spin_lock_irqsave(&hw->lock, flags); - hw->pfnDevDRAMWrite(hw, hw->FleaRxPicDelAddr, BuffSzInDwords, (uint32_t*)&PicDeliInfo); - hw->pfnWriteDevRegister(hw->adp, RX_POST_MAILBOX, hw->channelNum); - spin_unlock_irqrestore(&hw->lock, flags); - - hw->RxSeqNum++; - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_flea_hw_post_cap_buff(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt *rx_pkt) -{ - BC_STATUS sts = crystalhd_flea_hw_fire_rxdma(hw, rx_pkt); - - if (sts != BC_STS_SUCCESS) - crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, false, rx_pkt->pkt_tag); - - hw->pfnNotifyFLLChange(hw, false); - - return sts; -} - -void crystalhd_flea_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr) -{ - uint32_t dma_cntrl; - uint32_t first_desc_u_addr, first_desc_l_addr; - TX_INPUT_BUFFER_INFO TxBuffInfo; - uint32_t WrAddr=0, WrSzInDWords=0; - - hw->EmptyCnt--; - hw->SingleThreadAppFIFOEmpty = false; - - // For FLEA, first update the HW with the DMA parameters - WrSzInDWords = (sizeof(TxBuffInfo.DramBuffAdd) + - sizeof(TxBuffInfo.DramBuffSzInBytes) + - sizeof(TxBuffInfo.HostXferSzInBytes))/4; - - /*Make the DramBuffSz as Zero skip first ULONG*/ - WrAddr = hw->TxBuffInfoAddr; - hw->TxFwInputBuffInfo.DramBuffAdd = TxBuffInfo.DramBuffAdd = 0; - hw->TxFwInputBuffInfo.DramBuffSzInBytes = TxBuffInfo.DramBuffSzInBytes = 0; - TxBuffInfo.HostXferSzInBytes = hw->TxFwInputBuffInfo.HostXferSzInBytes; - - hw->pfnDevDRAMWrite(hw, WrAddr, WrSzInDWords, (uint32_t *)&TxBuffInfo); - - if (list_id == 0) { - first_desc_u_addr = BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0; - first_desc_l_addr = BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0; - } else { - first_desc_u_addr = BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1; - first_desc_l_addr = BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1; - } - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS); - if (!(dma_cntrl & BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK)) { - dma_cntrl |= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; - hw->pfnWriteFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - - hw->pfnWriteFPGARegister(hw->adp, first_desc_u_addr, desc_addr.high_part); - - hw->pfnWriteFPGARegister(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); - /* Be sure we set the valid bit ^^^^ */ - - return; -} - -BC_STATUS crystalhd_flea_stop_tx_dma_engine(struct crystalhd_hw *hw) -{ - struct device *dev; - uint32_t dma_cntrl, cnt = 30; - uint32_t l1 = 1, l2 = 1; - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS); - - dev = &hw->adp->pdev->dev; - - dev_dbg(dev, "Stopping TX DMA Engine..\n"); - - if (!(dma_cntrl & BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK)) { - dev_dbg(dev, "Already Stopped\n"); - return BC_STS_SUCCESS; - } - - crystalhd_flea_disable_interrupts(hw); - - /* Issue stop to HW */ - dma_cntrl &= ~BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; - hw->pfnWriteFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - - dev_dbg(dev, "Cleared the DMA Start bit\n"); - - /* Poll for 3seconds (30 * 100ms) on both the lists..*/ - while ((l1 || l2) && cnt) { - - if (l1) { - l1 = hw->pfnReadFPGARegister(hw->adp, - BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0); - l1 &= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; - } - - if (l2) { - l2 = hw->pfnReadFPGARegister(hw->adp, - BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1); - l2 &= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; - } - - msleep_interruptible(100); - - cnt--; - } - - if (!cnt) { - dev_err(dev, "Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); - crystalhd_flea_enable_interrupts(hw); - return BC_STS_ERROR; - } - - hw->TxList0Sts = ListStsFree; - hw->TxList1Sts = ListStsFree; - - hw->tx_list_post_index = 0; - dev_dbg(dev, "stopped TX DMA..\n"); - crystalhd_flea_enable_interrupts(hw); - - return BC_STS_SUCCESS; -} - -static void crystalhd_flea_update_tx_done_to_fw(struct crystalhd_hw *hw) -{ - struct device *dev; - uint32_t regVal = 0; - uint32_t seqNumAddr = 0; - uint32_t seqVal = 0; - TX_INPUT_BUFFER_INFO *pTxBuffInfo; - - dev = &hw->adp->pdev->dev; - /* - -- first update the sequence number and then update the - -- scratch. - */ - pTxBuffInfo = (TX_INPUT_BUFFER_INFO *) (0); - seqNumAddr = hw->TxBuffInfoAddr + ((uintptr_t) (&pTxBuffInfo->SeqNum)); - - //Read the seqnece number - hw->pfnDevDRAMRead(hw, seqNumAddr, 1, ®Val); - - seqVal = regVal; - regVal++; - - //Increment and Write back to same memory location. - hw->pfnDevDRAMWrite(hw, seqNumAddr, 1, ®Val); - - regVal = hw->pfnReadDevRegister(hw->adp, INDICATE_TX_DONE_REG); - regVal++; - hw->pfnWriteDevRegister(hw->adp, INDICATE_TX_DONE_REG, regVal); - - dev_dbg(dev, "TxUpdate[SeqNum DRAM Addr:%x] SeqNum:%x ScratchValue:%x\n", - seqNumAddr, seqVal, regVal); - - return; -} - -bool crystalhd_flea_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) -{ - uint32_t err_mask, tmp; - - err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; - - if (!(err_sts & err_mask)) - return false; - - dev_err(&hw->adp->pdev->dev, "Error on Tx-L0 %x\n", err_sts); - - tmp = err_mask; - - if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) - tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; - - if (tmp) { - /* reset list index.*/ - hw->tx_list_post_index = 0; - } - - tmp = err_sts & err_mask; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS, tmp); - - return true; -} - -bool crystalhd_flea_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) -{ - uint32_t err_mask, tmp; - - err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; - - if (!(err_sts & err_mask)) - return false; - - dev_err(&hw->adp->pdev->dev, "Error on Tx-L1 %x\n", err_sts); - - tmp = err_mask; - - if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) - tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; - - if (tmp) { - /* reset list index.*/ - hw->tx_list_post_index = 0; - } - - tmp = err_sts & err_mask; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS, tmp); - - return true; -} - -void crystalhd_flea_tx_isr(struct crystalhd_hw *hw, FLEA_INTR_STS_REG int_sts) -{ - uint32_t err_sts; - - if (int_sts.L0TxDMADone) { - hw->TxList0Sts &= ~TxListWaitingForIntr; - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_SUCCESS); - } - - if (int_sts.L1TxDMADone) { - hw->TxList1Sts &= ~TxListWaitingForIntr; - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_SUCCESS); - } - - if (!(int_sts.L0TxDMAErr || int_sts.L1TxDMAErr)) - /* No error mask set.. */ - return; - - /* Handle Tx errors. */ - err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS); - - if (crystalhd_flea_tx_list0_handler(hw, err_sts)) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_ERROR); - - if (crystalhd_flea_tx_list1_handler(hw, err_sts)) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_ERROR); - - hw->stats.tx_errors++; -} - -bool crystalhd_flea_rx_list0_handler(struct crystalhd_hw *hw, - FLEA_INTR_STS_REG int_sts, - uint32_t y_err_sts, - uint32_t uv_err_sts) -{ - uint32_t tmp; - list_sts tmp_lsts; - - if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) - return false; - - tmp_lsts = hw->rx_list_sts[0]; - - /* Y0 - DMA */ - tmp = y_err_sts & GET_Y0_ERR_MSK; - if (int_sts.L0YRxDMADone) - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; - } - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { - // Can never happen for Flea - printk("FLEA fifo full - impossible\n"); - hw->rx_list_sts[0] &= ~rx_y_mask; - hw->rx_list_sts[0] |= rx_y_error; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[0] &= ~rx_y_mask; - hw->rx_list_sts[0] |= rx_y_error; - hw->rx_list_post_index = 0; - } - - /* UV0 - DMA */ - tmp = uv_err_sts & GET_UV0_ERR_MSK; - if (int_sts.L0UVRxDMADone) - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; - } - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { - // Can never happen for Flea - printk("FLEA fifo full - impossible\n"); - hw->rx_list_sts[0] &= ~rx_uv_mask; - hw->rx_list_sts[0] |= rx_uv_error; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[0] &= ~rx_uv_mask; - hw->rx_list_sts[0] |= rx_uv_error; - hw->rx_list_post_index = 0; - } - - if (y_err_sts & GET_Y0_ERR_MSK) { - tmp = y_err_sts & GET_Y0_ERR_MSK; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, tmp); - } - - if (uv_err_sts & GET_UV0_ERR_MSK) { - tmp = uv_err_sts & GET_UV0_ERR_MSK; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, tmp); - } - - return (tmp_lsts != hw->rx_list_sts[0]); -} - -bool crystalhd_flea_rx_list1_handler(struct crystalhd_hw *hw, - FLEA_INTR_STS_REG int_sts, - uint32_t y_err_sts, - uint32_t uv_err_sts) -{ - uint32_t tmp; - list_sts tmp_lsts; - - if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) - return false; - - tmp_lsts = hw->rx_list_sts[1]; - - /* Y1 - DMA */ - tmp = y_err_sts & GET_Y1_ERR_MSK; - if (int_sts.L1YRxDMADone) - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; - } - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { - // Can never happen for Flea - printk("FLEA fifo full - impossible\n"); - hw->rx_list_sts[1] &= ~rx_y_mask; - hw->rx_list_sts[1] |= rx_y_error; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[1] &= ~rx_y_mask; - hw->rx_list_sts[1] |= rx_y_error; - hw->rx_list_post_index = 0; - } - - /* UV1 - DMA */ - tmp = uv_err_sts & GET_UV1_ERR_MSK; - if (int_sts.L1UVRxDMADone) - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; - } - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { - // Can never happen for Flea - printk("FLEA fifo full - impossible\n"); - hw->rx_list_sts[1] &= ~rx_uv_mask; - hw->rx_list_sts[1] |= rx_uv_error; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[1] &= ~rx_uv_mask; - hw->rx_list_sts[1] |= rx_uv_error; - hw->rx_list_post_index = 0; - } - - if (y_err_sts & GET_Y1_ERR_MSK) { - tmp = y_err_sts & GET_Y1_ERR_MSK; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, tmp); - } - - if (uv_err_sts & GET_UV1_ERR_MSK) { - tmp = uv_err_sts & GET_UV1_ERR_MSK; - hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, tmp); - } - - return (tmp_lsts != hw->rx_list_sts[1]); -} - -void crystalhd_flea_rx_isr(struct crystalhd_hw *hw, FLEA_INTR_STS_REG intr_sts) -{ - unsigned long flags; - uint32_t i, list_avail = 0; - BC_STATUS comp_sts = BC_STS_NO_DATA; - uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; - bool ret = 0; - - if (!hw) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return; - } - - if (!(intr_sts.L0YRxDMADone || intr_sts.L1YRxDMADone || intr_sts.L0UVRxDMADone || intr_sts.L1UVRxDMADone || - intr_sts.L0YRxDMAErr || intr_sts.L1YRxDMAErr || intr_sts.L0UVRxDMAErr || intr_sts.L1UVRxDMAErr)) - return; - - spin_lock_irqsave(&hw->rx_lock, flags); - - y_err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS); - uv_err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS); - - for (i = 0; i < DMA_ENGINE_CNT; i++) { - /* Update States..*/ - if (i == 0) - ret = crystalhd_flea_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); - else - ret = crystalhd_flea_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); - if (ret) { - switch (hw->rx_list_sts[i]) { - case sts_free: - comp_sts = BC_STS_SUCCESS; - list_avail = 1; - hw->stats.rx_success++; - break; - case rx_y_error: - case rx_uv_error: - case rx_sts_error: - /* We got error on both or Y or uv. */ - hw->stats.rx_errors++; - hw->pfnHWGetDoneSize(hw, i, &y_dn_sz, &uv_dn_sz); - dev_info(&hw->adp->pdev->dev, "list_index:%x " - "rx[%d] rxtot[%d] Y:%x UV:%x Int:%x YDnSz:%x " - "UVDnSz:%x\n", i, hw->stats.rx_errors, - hw->stats.rx_errors + hw->stats.rx_success, - y_err_sts, uv_err_sts, intr_sts.WholeReg, - y_dn_sz, uv_dn_sz); - hw->rx_list_sts[i] = sts_free; - comp_sts = BC_STS_ERROR; - break; - default: - /* Wait for completion..*/ - comp_sts = BC_STS_NO_DATA; - break; - } - } - /* handle completion...*/ - if (comp_sts != BC_STS_NO_DATA) { - crystalhd_rx_pkt_done(hw, i, comp_sts); - comp_sts = BC_STS_NO_DATA; - } - } - - spin_unlock_irqrestore(&hw->rx_lock, flags); - - if (list_avail) - crystalhd_hw_start_capture(hw); -} - -bool crystalhd_flea_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw) -{ - FLEA_INTR_STS_REG IntrStsValue; - bool bIntFound = false; - bool bPostRxBuff = false; - bool bSomeCmdDone = false; - crystalhd_rx_dma_pkt *rx_pkt; - - bool rc = false; - - if (!adp || !hw->dev_started) - return rc; - - IntrStsValue.WholeReg=0; - - IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); - - if(!IntrStsValue.WholeReg) - return rc; /*Not Our interrupt*/ - - /*If any of the bit is set we have a problem*/ - if(IntrStsValue.HaltIntr || IntrStsValue.PcieTgtCaAttn || IntrStsValue.PcieTgtUrAttn) - { - printk("Bad HW Error in CrystalHD Driver\n"); - return rc; - } - - // Our interrupt - hw->stats.num_interrupts++; - rc = true; - - /* NAREN When In Power Down state, only interrupts possible are TXFIFO and PiQ */ - /* Save the state of these interrupts to process them when we resume from power down */ - if(hw->FleaPowerState == FLEA_PS_LP_COMPLETE) - { - if(IntrStsValue.ArmMbox1Int) - { - hw->PwrDwnPiQIntr = true; - bIntFound = true; - } - - if(IntrStsValue.ArmMbox2Int) - { - hw->PwrDwnTxIntr = true; - bIntFound = true; - } - - /*Write End Of Interrupt for PCIE*/ - if(bIntFound) - { - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); - } - return (bIntFound); - } - - /* - -- Arm Mail box Zero interrupt is - -- BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 - */ - if(IntrStsValue.ArmMbox0Int) - { - //HWFWCmdComplete(pHWExt,IntrBmp); - /*Set the Event and the status flag*/ - if (hw->pfw_cmd_event) { - hw->fwcmd_evt_sts = 1; - crystalhd_set_event(hw->pfw_cmd_event); - } - bIntFound = true; - bSomeCmdDone = true; - hw->FwCmdCnt--; - } - - /* Rx interrupts */ - crystalhd_flea_rx_isr(hw, IntrStsValue); - - if( IntrStsValue.L0YRxDMADone || IntrStsValue.L1YRxDMADone || IntrStsValue.L0UVRxDMADone || IntrStsValue.L1UVRxDMADone || IntrStsValue.L0YRxDMAErr || IntrStsValue.L1YRxDMAErr ) - { - bSomeCmdDone = true; - } - - - /* Tx interrupts*/ - crystalhd_flea_tx_isr(hw, IntrStsValue); - - /* - -- Indicate the TX Done to Flea Firmware. - */ - if(IntrStsValue.L0TxDMADone || IntrStsValue.L1TxDMADone || IntrStsValue.L0TxDMAErr || IntrStsValue.L1TxDMAErr) - { - crystalhd_flea_update_tx_done_to_fw(hw); - bSomeCmdDone = true; - } - /* - -- We are doing this here because we processed the interrupts. - -- We might want to change the PicQSts bitmap in any of the interrupts. - -- This should be done before trying to post the next RX buffer. - -- NOTE: ArmMbox1Int is BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 - */ - if(IntrStsValue.ArmMbox1Int) - { - //pHWExt->FleaBmpIntrCnt++; - crystalhd_flea_update_temperature(hw); - crystalhd_flea_handle_PicQSts_intr(hw); - bPostRxBuff = true; - bIntFound = true; - } - - if(IntrStsValue.ArmMbox2Int) - { - crystalhd_flea_update_temperature(hw); - crystalhd_flea_update_tx_buff_info(hw); - bIntFound = true; - } - - /*Write End Of Interrupt for PCIE*/ - if(rc) - { - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); - hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); - } - - // Try to post RX Capture buffer from ISR context - if(bPostRxBuff) { - rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); - if (rx_pkt) - hw->pfnPostRxSideBuff(hw, rx_pkt); - } - - if( (hw->FleaPowerState == FLEA_PS_LP_PENDING) && (bSomeCmdDone)) - { - //printk("interrupt_handle: current PS:%d, bSomeCmdDone%d\n", hw->FleaPowerState,bSomeCmdDone); - crystalhd_flea_set_next_power_state(hw, FLEA_EVT_CMD_COMP); - } - - ///* NAREN place the device in low power mode if we have not started playing video */ - //if((hw->FleaPowerState == FLEA_PS_ACTIVE) && (hw->WakeUpDecodeDone != true)) - //{ - // if((hw->ReadyListLen == 0) && (hw->FreeListLen == 0)) - // { - // crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); - // printk("ISR Idle\n"); - // } - //} - - return rc; -} - -/* This function cannot be called from ISR context since it uses APIs that can sleep */ -bool flea_GetPictureInfo(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt * rx_pkt, - uint32_t *PicNumber, uint64_t *PicMetaData) -{ - struct device *dev = &hw->adp->pdev->dev; - uint32_t PicInfoLineNum = 0, offset = 0, size = 0; - PBC_PIC_INFO_BLOCK pPicInfoLine = NULL; - uint32_t tmpYBuffData; - unsigned long res = 0; - uint32_t widthField = 0; - bool rtVal = true; - - void *tmpPicInfo = NULL; - crystalhd_dio_req *dio = rx_pkt->dio_req; - *PicNumber = 0; - *PicMetaData = 0; - - if (!dio) - goto getpictureinfo_err_nosem; - -// if(down_interruptible(&hw->fetch_sem)) -// goto getpictureinfo_err_nosem; - - tmpPicInfo = kmalloc(2 * sizeof(BC_PIC_INFO_BLOCK) + 16, GFP_KERNEL); // since copy_from_user can sleep anyway - if(tmpPicInfo == NULL) - goto getpictureinfo_err; - dio->pib_va = kmalloc(32, GFP_KERNEL); // temp buffer of 32 bytes for the rest; - if(dio->pib_va == NULL) - goto getpictureinfo_err; - - offset = (rx_pkt->dio_req->uinfo.y_done_sz * 4) - PIC_PIB_DATA_OFFSET_FROM_END; - res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff + offset), 4); - if (res != 0) - goto getpictureinfo_err; - PicInfoLineNum = *(uint32_t*)(dio->pib_va); - if (PicInfoLineNum > 1092) { - dev_err(dev, "Invalid Line Number[%x], DoneSz:0x%x Bytes\n", - (int)PicInfoLineNum, rx_pkt->dio_req->uinfo.y_done_sz * 4); - goto getpictureinfo_err; - } - - offset = (rx_pkt->dio_req->uinfo.y_done_sz * 4) - PIC_WIDTH_OFFSET_FROM_END; - res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff + offset), 4); - if (res != 0) - goto getpictureinfo_err; - widthField = *(uint32_t*)(dio->pib_va); - - hw->PICWidth = widthField & 0x3FFFFFFF; // bit 31 is FMT Change, bit 30 is EOS - if (hw->PICWidth > 2048) { - dev_err(dev, "Invalid width [%d]\n", hw->PICWidth); - goto getpictureinfo_err; - } - - /* calc pic info line offset */ - if (dio->uinfo.b422mode) { - size = 2 * sizeof(BC_PIC_INFO_BLOCK); - offset = (PicInfoLineNum * hw->PICWidth * 2) + 4; - } else { - size = sizeof(BC_PIC_INFO_BLOCK); - offset = (PicInfoLineNum * hw->PICWidth) + 4; - } - - res = copy_from_user(tmpPicInfo, (void *)(dio->uinfo.xfr_buff+offset), size); - if (res != 0) - goto getpictureinfo_err; - - pPicInfoLine = (PBC_PIC_INFO_BLOCK)(tmpPicInfo); - - *PicMetaData = pPicInfoLine->timeStamp; - - if(widthField & PIB_EOS_DETECTED_BIT) - { - dev_dbg(dev, "Got EOS flag.\n"); - hw->DrvEosDetected = 1; - *(uint32_t *)(dio->pib_va) = 0xFFFFFFFF; - res = copy_to_user((void *)(dio->uinfo.xfr_buff), dio->pib_va, 4); - if (res != 0) - goto getpictureinfo_err; - } - else - { - if( hw->DrvEosDetected == 1 ) - hw->DrvCancelEosFlag = 1; - - hw->DrvEosDetected = 0; - res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff), 4); - if (res != 0) - goto getpictureinfo_err; - - tmpYBuffData = *(uint32_t *)(dio->pib_va); - pPicInfoLine->ycom = tmpYBuffData; - res = copy_to_user((void *)(dio->uinfo.xfr_buff+offset), tmpPicInfo, size); - if (res != 0) - goto getpictureinfo_err; - - *(uint32_t *)(dio->pib_va) = PicInfoLineNum; - res = copy_to_user((void *)(dio->uinfo.xfr_buff), dio->pib_va, 4); - if (res != 0) - goto getpictureinfo_err; - } - - if(widthField & PIB_FORMAT_CHANGE_BIT) - { - rx_pkt->flags = 0; - rx_pkt->flags |= COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE; - - rx_pkt->pib.picture_number = pPicInfoLine->picture_number; - rx_pkt->pib.width = pPicInfoLine->width; - rx_pkt->pib.height = pPicInfoLine->height; - rx_pkt->pib.chroma_format = pPicInfoLine->chroma_format; - rx_pkt->pib.pulldown = pPicInfoLine->pulldown; - rx_pkt->pib.flags = pPicInfoLine->flags; - rx_pkt->pib.sess_num = pPicInfoLine->sess_num; - rx_pkt->pib.aspect_ratio = pPicInfoLine->aspect_ratio; - rx_pkt->pib.colour_primaries = pPicInfoLine->colour_primaries; - rx_pkt->pib.picture_meta_payload = pPicInfoLine->picture_meta_payload; - rx_pkt->pib.frame_rate = pPicInfoLine->frame_rate; - rx_pkt->pib.custom_aspect_ratio_width_height = pPicInfoLine->custom_aspect_ratio_width_height; - rx_pkt->pib.n_drop = pPicInfoLine->n_drop; - rx_pkt->pib.ycom = pPicInfoLine->ycom; - hw->PICHeight = rx_pkt->pib.height; - hw->PICWidth = rx_pkt->pib.width; - hw->LastPicNo=0; - hw->LastTwoPicNo=0; - hw->PDRatio = 0; // NAREN - reset PD ratio to start measuring for new clip - hw->PauseThreshold = hw->DefaultPauseThreshold; - hw->TickSpentInPD = 0; - rdtscll(hw->TickCntDecodePU); - - dev_dbg(dev, "[FMT CH] DoneSz:0x%x, PIB:%x %x %x %x %x %x %x %x %x %x\n", - rx_pkt->dio_req->uinfo.y_done_sz * 4, - rx_pkt->pib.picture_number, - rx_pkt->pib.aspect_ratio, - rx_pkt->pib.chroma_format, - rx_pkt->pib.colour_primaries, - rx_pkt->pib.frame_rate, - rx_pkt->pib.height, - rx_pkt->pib.width, - rx_pkt->pib.n_drop, - rx_pkt->pib.pulldown, - rx_pkt->pib.ycom); - rtVal = false; - } - - if(pPicInfoLine->flags & FLEA_DECODE_ERROR_FLAG) - { - *PicNumber = 0; - } else { - /* get pic number and flags */ - if (dio->uinfo.b422mode) - offset = (PicInfoLineNum * hw->PICWidth * 2); - else - offset = (PicInfoLineNum * hw->PICWidth); - - res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), 4); - if (res != 0) - goto getpictureinfo_err; - - *PicNumber = *(uint32_t *)(dio->pib_va); - } - - if(dio->pib_va) - kfree(dio->pib_va); - if(tmpPicInfo) - kfree(tmpPicInfo); - -// up(&hw->fetch_sem); - - return rtVal; - -getpictureinfo_err: -// up(&hw->fetch_sem); - -getpictureinfo_err_nosem: - if(dio->pib_va) - kfree(dio->pib_va); - if(tmpPicInfo) - kfree(tmpPicInfo); - - *PicNumber = 0; - *PicMetaData = 0; - - return false; -} - -uint32_t flea_GetRptDropParam(struct crystalhd_hw *hw, void* pRxDMAReq) -{ - uint32_t PicNumber = 0,result = 0; - uint64_t PicMetaData = 0; - - if(flea_GetPictureInfo(hw, (crystalhd_rx_dma_pkt *)pRxDMAReq, - &PicNumber, &PicMetaData)) - result = PicNumber; - - return result; -} - -bool crystalhd_flea_notify_event(struct crystalhd_hw *hw, BRCM_EVENT EventCode) -{ - switch(EventCode) - { - case BC_EVENT_START_CAPTURE: - { - crystalhd_flea_wake_up_hw(hw); - break; - } - default: - break; - } - - return true; -} diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_fleafuncs.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_fleafuncs.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_fleafuncs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_fleafuncs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,62 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_fleafuncs . h - * - * Description: - * BCM70015 Linux driver hardware layer. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#ifndef _CRYSTALHD_FLEAFUNCS_H_ -#define _CRYSTALHD_FLEAFUNCS_H_ - -#include "FleaDefs.h" - -#define FW_CMD_BUFF_SZ 64 - -bool crystalhd_flea_start_device(struct crystalhd_hw *hw); -bool crystalhd_flea_stop_device(struct crystalhd_hw *hw); -bool crystalhd_flea_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw); -uint32_t crystalhd_flea_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); // Done -void crystalhd_flea_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); // Done -bool crystalhd_flea_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags); -BC_STATUS crystalhd_flea_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff); // Done -BC_STATUS crystalhd_flea_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff); // Done -BC_STATUS crystalhd_flea_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); -BC_STATUS crystalhd_flea_download_fw(struct crystalhd_hw* hw, uint8_t* buffer, uint32_t sz); -void crystalhd_flea_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz); -BC_STATUS crystalhd_flea_hw_pause(struct crystalhd_hw *hw, bool state); -bool crystalhd_flea_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth); -BC_STATUS crystalhd_flea_hw_post_cap_buff(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt *rx_pkt); -void crystalhd_flea_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr); -void crystalhd_flea_stop_rx_dma_engine(struct crystalhd_hw *hw); -BC_STATUS crystalhd_flea_stop_tx_dma_engine(struct crystalhd_hw *hw); -bool crystalhd_flea_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts); -bool crystalhd_flea_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts); -void crystalhd_flea_tx_isr(struct crystalhd_hw *hw, FLEA_INTR_STS_REG int_sts); -bool crystalhd_flea_rx_list0_handler(struct crystalhd_hw *hw,FLEA_INTR_STS_REG int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); -bool crystalhd_flea_rx_list1_handler(struct crystalhd_hw *hw,FLEA_INTR_STS_REG int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); -void crystalhd_flea_rx_isr(struct crystalhd_hw *hw, FLEA_INTR_STS_REG intr_sts); -void crystalhd_flea_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext); -bool crystalhd_flea_notify_event(struct crystalhd_hw *hw, BRCM_EVENT EventCode); - -bool flea_GetPictureInfo(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt * rx_pkt, - uint32_t *PicNumber, uint64_t *PicMetaData); -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_fw_if.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_fw_if.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_fw_if.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_fw_if.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,390 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_fw_if . h - * - * Description: - * BCM70012 Firmware interface definitions. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#ifndef _CRYSTALHD_FW_IF_H_ -#define _CRYSTALHD_FW_IF_H_ - -#include - -/* TBD: Pull in only required defs into this file.. */ - -/* User Data Header */ -typedef struct user_data { - struct user_data *next; - uint32_t type; - uint32_t size; -} UD_HDR; - - - -/*------------------------------------------------------* - * MPEG Extension to the PPB * - *------------------------------------------------------*/ -typedef struct { - uint32_t to_be_defined; - uint32_t valid; - - /* Always valid, defaults to picture size if no - sequence display extension in the stream. */ - uint32_t display_horizontal_size; - uint32_t display_vertical_size; - - /* MPEG_VALID_PANSCAN - Offsets are a copy values from the MPEG stream. */ - uint32_t offset_count; - int32_t horizontal_offset[3]; - int32_t vertical_offset[3]; - - /* MPEG_VALID_USERDATA - User data is in the form of a linked list. */ - int32_t userDataSize; - UD_HDR *userData; - -} PPB_MPEG; - - -/*------------------------------------------------------* - * VC1 Extension to the PPB * - *------------------------------------------------------*/ -typedef struct { - uint32_t to_be_defined; - uint32_t valid; - - /* Always valid, defaults to picture size if no - sequence display extension in the stream. */ - uint32_t display_horizontal_size; - uint32_t display_vertical_size; - - /* VC1 pan scan windows */ - uint32_t num_panscan_windows; - int32_t ps_horiz_offset[4]; - int32_t ps_vert_offset[4]; - int32_t ps_width[4]; - int32_t ps_height[4]; - - /* VC1_VALID_USERDATA - User data is in the form of a linked list. */ - int32_t userDataSize; - UD_HDR *userData; - -} PPB_VC1; - -/*------------------------------------------------------* - * H.264 Extension to the PPB * - *------------------------------------------------------*/ - -/** - * @brief Film grain SEI message. - * - * Content of the film grain SEI message. - */ - -/* maximum number of model-values as for Thomson spec(standard says 5) */ -#define MAX_FGT_MODEL_VALUE (3) - -/* maximum number of intervals(as many as 256 intervals?) */ -#define MAX_FGT_VALUE_INTERVAL (256) - -typedef struct FGT_SEI { - struct FGT_SEI *next; - unsigned char model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; - unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL]; - unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL]; - - unsigned char cancel_flag; /* Cancel flag: 1 no film grain. */ - unsigned char model_id; /* Model id. */ - - /* +unused SE based on Thomson spec */ - unsigned char color_desc_flag; /* Separate color descrition flag. */ - unsigned char bit_depth_luma; /* Bit depth luma minus 8. */ - unsigned char bit_depth_chroma; /* Bit depth chroma minus 8. */ - unsigned char full_range_flag; /* Full range flag. */ - unsigned char color_primaries; /* Color primaries. */ - unsigned char transfer_charact; /* Transfer characteristics. */ - unsigned char matrix_coeff; /*< Matrix coefficients. */ - /* -unused SE based on Thomson spec */ - - unsigned char blending_mode_id; /* Blending mode. */ - unsigned char log2_scale_factor; /* Log2 scale factor (2-7). */ - unsigned char comp_flag[3]; /* Components [0,2] parameters present flag. */ - unsigned char num_intervals_minus1[3]; /* Number of intensity level intervals. */ - unsigned char num_model_values[3]; /* Number of model values. */ - uint16_t repetition_period; /* Repetition period (0-16384) */ - -} FGT_SEI; - -typedef struct { - /* 'valid' specifies which fields (or sets of - * fields) below are valid. If the corresponding - * bit in 'valid' is NOT set then that field(s) - * is (are) not initialized. */ - uint32_t valid; - - int32_t poc_top; /* POC for Top Field/Frame */ - int32_t poc_bottom; /* POC for Bottom Field */ - uint32_t idr_pic_id; - - /* H264_VALID_PANSCAN */ - uint32_t pan_scan_count; - int32_t pan_scan_left[3]; - int32_t pan_scan_right[3]; - int32_t pan_scan_top[3]; - int32_t pan_scan_bottom[3]; - - /* H264_VALID_CT_TYPE */ - uint32_t ct_type_count; - uint32_t ct_type[3]; - - /* H264_VALID_SPS_CROP */ - int32_t sps_crop_left; - int32_t sps_crop_right; - int32_t sps_crop_top; - int32_t sps_crop_bottom; - - /* H264_VALID_VUI */ - uint32_t chroma_top; - uint32_t chroma_bottom; - - /* H264_VALID_USER */ - uint32_t user_data_size; - UD_HDR *user_data; - - /* H264 VALID FGT */ - FGT_SEI *pfgt; - -} PPB_H264; - -typedef struct { - /* Common fields. */ - uint32_t picture_number; /* Ordinal display number */ - uint32_t video_buffer; /* Video (picbuf) number */ - uint32_t video_address; /* Address of picbuf Y */ - uint32_t video_address_uv; /* Address of picbuf UV */ - uint32_t video_stripe; /* Picbuf stripe */ - uint32_t video_width; /* Picbuf width */ - uint32_t video_height; /* Picbuf height */ - - uint32_t channel_id; /* Decoder channel ID */ - uint32_t status; /* reserved */ - uint32_t width; /* pixels */ - uint32_t height; /* pixels */ - uint32_t chroma_format; /* see above */ - uint32_t pulldown; /* see above */ - uint32_t flags; /* see above */ - uint32_t pts; /* 32 LSBs of PTS */ - uint32_t protocol; /* protocolXXX (above) */ - - uint32_t frame_rate; /* see above */ - uint32_t matrix_coeff; /* see above */ - uint32_t aspect_ratio; /* see above */ - uint32_t colour_primaries; /* see above */ - uint32_t transfer_char; /* see above */ - uint32_t pcr_offset; /* 45kHz if PCR type; else 27MHz */ - uint32_t n_drop; /* Number of pictures to be dropped */ - - uint32_t custom_aspect_ratio_width_height; - /* upper 16-bits is Y and lower 16-bits is X */ - - uint32_t picture_tag; /* Indexing tag from BUD packets */ - uint32_t picture_done_payload; - uint32_t picture_meta_payload; - uint32_t reserved[1]; - - /* Protocol-specific extensions. */ - union { - PPB_H264 h264; - PPB_MPEG mpeg; - PPB_VC1 vc1; - } other; - -} PPB; - -typedef struct { - uint32_t bFormatChange; - uint32_t resolution; - uint32_t channelId; - uint32_t ppbPtr; - int32_t ptsStcOffset; - uint32_t zeroPanscanValid; - uint32_t dramOutBufAddr; - uint32_t yComponent; - PPB ppb; - -} C011_PIB; - -typedef struct -{ - uint32_t eCmd; // eC011_TS_CMD - uint32_t ulParams[63]; -} C011_TS_CMD, C011_TS_RSP; - -typedef struct { - uint32_t command; - uint32_t sequence; - uint32_t status; - uint32_t picBuf; - uint32_t picRelBuf; - uint32_t picInfoDeliveryQ; - uint32_t picInfoReleaseQ; - uint32_t channelStatus; - uint32_t userDataDeliveryQ; - uint32_t userDataReleaseQ; - uint32_t transportStreamCaptureAddr; - uint32_t asyncEventQ; - -} DecRspChannelStartVideo; - -typedef struct -{ - uint32_t command; - uint32_t sequence; - uint32_t status; - uint32_t ChannelID; - uint32_t picBuf; - uint32_t picRelBuf; - uint32_t picInfoDeliveryQ; - uint32_t picInfoReleaseQ; - uint32_t channelStatus; - uint32_t userDataDeliveryQ; - uint32_t userDataReleaseQ; - uint32_t transportStreamCaptureAddr; - uint32_t asyncEventQ; -}DecRspChannelChannelOpen; - -#define eCMD_C011_CMD_BASE (0x73763000) - -/* host commands */ -typedef enum { - eCMD_TS_GET_NEXT_PIC = 0x7376F100, /* debug get next picture */ - eCMD_TS_GET_LAST_PIC = 0x7376F102, /* debug get last pic status */ - eCMD_TS_READ_WRITE_MEM = 0x7376F104, /* debug read write memory */ - - /* New API commands */ - /* General commands */ - eCMD_C011_INIT = eCMD_C011_CMD_BASE + 0x01, - eCMD_C011_RESET = eCMD_C011_CMD_BASE + 0x02, - eCMD_C011_SELF_TEST = eCMD_C011_CMD_BASE + 0x03, - eCMD_C011_GET_VERSION = eCMD_C011_CMD_BASE + 0x04, - eCMD_C011_GPIO = eCMD_C011_CMD_BASE + 0x05, - eCMD_C011_DEBUG_SETUP = eCMD_C011_CMD_BASE + 0x06, - - /* Decoding commands */ - eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100, - eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, - eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, - eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, - eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, - eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105, - eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, - eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107, - eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108, - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109, - eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, - eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, - eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, - eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E, - eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, - eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, - eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111, - eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, - eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, - eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, - eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, - eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, - eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, - eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, - eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, - eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A, - eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B, - eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C, - eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, - eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E, - eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, - eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, - eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121, - eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122, - eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, - eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124, - eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125, - eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126, - eCMD_C011_DEC_CHAN_SET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x127, - eCMD_C011_DEC_CHAN_GET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x128, - eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129, - eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A, - eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B, - eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, - eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, - eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E, - eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, - eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, - eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131, - eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + 0x132, - eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, - eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, - eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135, - eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136, - eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137, - eCMD_C011_DEC_CHAN_SET_VID_PID = eCMD_C011_CMD_BASE + 0x138, - eCMD_C011_DEC_CHAN_SET_PAN_SCAN_MODE = eCMD_C011_CMD_BASE + 0x139, - eCMD_C011_DEC_CHAN_START_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x140, - eCMD_C011_DEC_CHAN_STOP_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x141, - eCMD_C011_DEC_CHAN_SET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x142, - eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143, - eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144, - eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145, - eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, - eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + 0x147, - eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148, - eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149, - eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST - = eCMD_C011_CMD_BASE + 0x150, - - /* Decoder RevD commands */ - eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color space conversion */ - eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181, - eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182, - /* Note: 0x183 not implemented yet in Rev D main */ - eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + 0x183, - - /* Decoder 7412 commands (7412-only) */ - eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190, - eCMD_C011_DEC_CHAN_SET_SESSION_KEY = eCMD_C011_CMD_BASE + 0x191, - eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK = eCMD_C011_CMD_BASE + 0x192, - - eCMD_C011_DEC_CHAN_CUSTOM_VIDOUT = eCMD_C011_CMD_BASE + 0x1FF, - - /* Encoding commands */ - eCMD_C011_ENC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x200, - eCMD_C011_ENC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x201, - eCMD_C011_ENC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x202, - eCMD_C011_ENC_CHAN_CONTROL = eCMD_C011_CMD_BASE + 0x203, - eCMD_C011_ENC_CHAN_STATISTICS = eCMD_C011_CMD_BASE + 0x204, - - eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210, - -} eC011_TS_CMD; - -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_hw.c crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_hw.c --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_hw.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_hw.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1048 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_hw . c - * - * Description: - * BCM70012/BCM70015 Linux driver hardware layer. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#include -#include -#include -#include -#include -#include "crystalhd_lnx.h" -#include "crystalhd_linkfuncs.h" -#include "crystalhd_fleafuncs.h" - -#define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) - -BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp) -{ - struct device *dev; - if (!hw || !adp) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - if (hw->dev_started) - return BC_STS_SUCCESS; - - dev = &adp->pdev->dev; - hw->PauseThreshold = BC_RX_LIST_CNT - 2; - hw->DefaultPauseThreshold = BC_RX_LIST_CNT - 2; - hw->ResumeThreshold = 3; - - // Setup HW specific functions appropriately - if (adp->pdev->device == BC_PCI_DEVID_FLEA) { - dev_dbg(dev, "crystalhd_hw_open: setting up functions, device = Flea\n"); - hw->pfnStartDevice = crystalhd_flea_start_device; - hw->pfnStopDevice = crystalhd_flea_stop_device; - hw->pfnFindAndClearIntr = crystalhd_flea_hw_interrupt_handle; - hw->pfnReadDevRegister = crystalhd_flea_reg_rd; // Done - hw->pfnWriteDevRegister = crystalhd_flea_reg_wr; // Done - hw->pfnReadFPGARegister = crystalhd_flea_reg_rd; // Done - hw->pfnWriteFPGARegister = crystalhd_flea_reg_wr; // Done - hw->pfnCheckInputFIFO = crystalhd_flea_check_input_full; - hw->pfnDevDRAMRead = crystalhd_flea_mem_rd; // Done - hw->pfnDevDRAMWrite = crystalhd_flea_mem_wr; // Done - hw->pfnDoFirmwareCmd = crystalhd_flea_do_fw_cmd; - hw->pfnFWDwnld = crystalhd_flea_download_fw; - hw->pfnHWGetDoneSize = crystalhd_flea_get_dnsz; - hw->pfnIssuePause = crystalhd_flea_hw_pause; - hw->pfnPeekNextDeodedFr = crystalhd_flea_peek_next_decoded_frame; - hw->pfnPostRxSideBuff = crystalhd_flea_hw_post_cap_buff; - hw->pfnStartTxDMA = crystalhd_flea_start_tx_dma_engine; - hw->pfnStopTxDMA = crystalhd_flea_stop_tx_dma_engine; - hw->pfnStopRXDMAEngines = crystalhd_flea_stop_rx_dma_engine; - hw->pfnNotifyFLLChange = crystalhd_flea_notify_fll_change; - hw->pfnNotifyHardware = crystalhd_flea_notify_event; - } else { - dev_dbg(dev, "crystalhd_hw_open: setting up functions, device = Link\n"); - hw->pfnStartDevice = crystalhd_link_start_device; - hw->pfnStopDevice = crystalhd_link_stop_device; - hw->pfnFindAndClearIntr = crystalhd_link_hw_interrupt_handle; - hw->pfnReadDevRegister = link_dec_reg_rd; - hw->pfnWriteDevRegister = link_dec_reg_wr; - hw->pfnReadFPGARegister = crystalhd_link_reg_rd; - hw->pfnWriteFPGARegister = crystalhd_link_reg_wr; - hw->pfnCheckInputFIFO = crystalhd_link_check_input_full; - hw->pfnDevDRAMRead = crystalhd_link_mem_rd; - hw->pfnDevDRAMWrite = crystalhd_link_mem_wr; - hw->pfnDoFirmwareCmd = crystalhd_link_do_fw_cmd; - hw->pfnFWDwnld = crystalhd_link_download_fw; - hw->pfnHWGetDoneSize = crystalhd_link_get_dnsz; - hw->pfnIssuePause = crystalhd_link_hw_pause; - hw->pfnPeekNextDeodedFr = crystalhd_link_peek_next_decoded_frame; - hw->pfnPostRxSideBuff = crystalhd_link_hw_post_cap_buff; - hw->pfnStartTxDMA = crystalhd_link_start_tx_dma_engine; - hw->pfnStopTxDMA = crystalhd_link_stop_tx_dma_engine; - hw->pfnStopRXDMAEngines = crystalhd_link_stop_rx_dma_engine; - hw->pfnNotifyFLLChange = crystalhd_link_notify_fll_change; - hw->pfnNotifyHardware = crystalhd_link_notify_event; - } - - hw->adp = adp; - spin_lock_init(&hw->lock); - spin_lock_init(&hw->rx_lock); - sema_init(&hw->fetch_sem, 1); - - // Seed for error checking and debugging. Random numbers */ - hw->tx_ioq_tag_seed = 0x70023070; - hw->rx_pkt_tag_seed = 0x70029070; - - hw->stop_pending = 0; - hw->pfnStartDevice(hw); - hw->dev_started = true; - - dev_dbg(dev, "Opening HW. hw:0x%lx, hw->adp:0x%lx\n", - (uintptr_t)hw, (uintptr_t)(hw->adp)); - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw, struct crystalhd_adp *adp) -{ - if (!hw) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_SUCCESS; - } - - if (!hw->dev_started) - return BC_STS_SUCCESS; - - /* Stop and DDR sleep will happen in here */ - // Only stop the HW if we are the last user - if(adp->cfg_users == 1) - crystalhd_hw_suspend(hw); - - hw->dev_started = false; - - return BC_STS_SUCCESS; -} - -crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw) -{ - unsigned long flags = 0; - crystalhd_rx_dma_pkt *temp = NULL; - - if (!hw) - return NULL; - - spin_lock_irqsave(&hw->lock, flags); - temp = hw->rx_pkt_pool_head; - if (temp) { - hw->rx_pkt_pool_head = hw->rx_pkt_pool_head->next; - temp->dio_req = NULL; - temp->pkt_tag = 0; - temp->flags = 0; - } - spin_unlock_irqrestore(&hw->lock, flags); - - return temp; -} - -void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, - crystalhd_rx_dma_pkt *pkt) -{ - unsigned long flags = 0; - - if (!hw || !pkt) - return; - - spin_lock_irqsave(&hw->lock, flags); - pkt->next = hw->rx_pkt_pool_head; - hw->rx_pkt_pool_head = pkt; - spin_unlock_irqrestore(&hw->lock, flags); -} - -/* - * Call back from TX - IOQ deletion. - * - * This routine will release the TX DMA rings allocated - * druing setup_dma rings interface. - * - * Memory is allocated per DMA ring basis. This is just - * a place holder to be able to create the dio queues. - */ -void crystalhd_tx_desc_rel_call_back(void *context, void *data) -{ -} - -/* - * Rx Packet release callback.. - * - * Release All user mapped capture buffers and Our DMA packets - * back to our free pool. The actual cleanup of the DMA - * ring descriptors happen during dma ring release. - */ -void crystalhd_rx_pkt_rel_call_back(void *context, void *data) -{ - struct crystalhd_hw *hw = (struct crystalhd_hw *)context; - crystalhd_rx_dma_pkt *pkt = (crystalhd_rx_dma_pkt *)data; - - if (!pkt || !hw) { - printk(KERN_ERR "%s: Invalid arg - %p %p\n", __func__, hw, pkt); - return; - } - - if (pkt->dio_req) - crystalhd_unmap_dio(hw->adp, pkt->dio_req); - - crystalhd_hw_free_rx_pkt(hw, pkt); -} - -#define crystalhd_hw_delete_ioq(adp, q) \ - if (q) { \ - crystalhd_delete_dioq(adp, q); \ - q = NULL; \ - } - -void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw) -{ - if (!hw) - return; - - crystalhd_hw_delete_ioq(hw->adp, hw->tx_actq); - crystalhd_hw_delete_ioq(hw->adp, hw->tx_freeq); - crystalhd_hw_delete_ioq(hw->adp, hw->rx_actq); - crystalhd_hw_delete_ioq(hw->adp, hw->rx_freeq); - crystalhd_hw_delete_ioq(hw->adp, hw->rx_rdyq); -} - -#define crystalhd_hw_create_ioq(sts, hw, q, cb) \ -do { \ - sts = crystalhd_create_dioq(hw->adp, &q, cb, hw); \ - if (sts != BC_STS_SUCCESS) \ - goto hw_create_ioq_err; \ -} while (0) - -/* - * Create IOQs.. - * - * TX - Active & Free - * RX - Active, Ready and Free. - */ -BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - if (!hw) { - printk(KERN_ERR "%s: Invalid Arg!!\n", __func__); - return BC_STS_INV_ARG; - } - - crystalhd_hw_create_ioq(sts, hw, hw->tx_freeq, - crystalhd_tx_desc_rel_call_back); - crystalhd_hw_create_ioq(sts, hw, hw->tx_actq, - crystalhd_tx_desc_rel_call_back); - - crystalhd_hw_create_ioq(sts, hw, hw->rx_freeq, - crystalhd_rx_pkt_rel_call_back); - crystalhd_hw_create_ioq(sts, hw, hw->rx_rdyq, - crystalhd_rx_pkt_rel_call_back); - crystalhd_hw_create_ioq(sts, hw, hw->rx_actq, - crystalhd_rx_pkt_rel_call_back); - - return sts; - -hw_create_ioq_err: - crystalhd_hw_delete_ioqs(hw); - - return sts; -} - -BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw) -{ - struct device *dev; - unsigned int i; - void *mem; - size_t mem_len; - dma_addr_t phy_addr; - BC_STATUS sts = BC_STS_SUCCESS; - crystalhd_rx_dma_pkt *rpkt; - - if (!hw || !hw->adp) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &hw->adp->pdev->dev; - - sts = crystalhd_hw_create_ioqs(hw); - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "Failed to create IOQs..\n"); - return sts; - } - - mem_len = BC_LINK_MAX_SGLS * sizeof(dma_descriptor); - - for (i = 0; i < BC_TX_LIST_CNT; i++) { - mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); - if (mem) { - memset(mem, 0, mem_len); - } else { - dev_err(dev, "Insufficient Memory For TX\n"); - crystalhd_hw_free_dma_rings(hw); - return BC_STS_INSUFF_RES; - } - /* rx_pkt_pool -- static memory allocation */ - hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = mem; - hw->tx_pkt_pool[i].desc_mem.phy_addr = phy_addr; - hw->tx_pkt_pool[i].desc_mem.sz = BC_LINK_MAX_SGLS * - sizeof(dma_descriptor); - hw->tx_pkt_pool[i].list_tag = 0; - - /* Add TX dma requests to Free Queue..*/ - sts = crystalhd_dioq_add(hw->tx_freeq, - &hw->tx_pkt_pool[i], false, 0); - if (sts != BC_STS_SUCCESS) { - crystalhd_hw_free_dma_rings(hw); - return sts; - } - } - - for (i = 0; i < BC_RX_LIST_CNT; i++) { - rpkt = kzalloc(sizeof(*rpkt), GFP_KERNEL); - if (!rpkt) { - dev_err(dev, "Insufficient Memory For RX\n"); - crystalhd_hw_free_dma_rings(hw); - return BC_STS_INSUFF_RES; - } - - mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); - if (mem) { - memset(mem, 0, mem_len); - } else { - dev_err(dev, "Insufficient Memory For RX\n"); - crystalhd_hw_free_dma_rings(hw); - return BC_STS_INSUFF_RES; - } - rpkt->desc_mem.pdma_desc_start = mem; - rpkt->desc_mem.phy_addr = phy_addr; - rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * sizeof(dma_descriptor); - rpkt->pkt_tag = hw->rx_pkt_tag_seed + i; - crystalhd_hw_free_rx_pkt(hw, rpkt); - } - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw) -{ - unsigned int i; - crystalhd_rx_dma_pkt *rpkt = NULL; - - if (!hw || !hw->adp) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - /* Delete all IOQs.. */ - crystalhd_hw_delete_ioqs(hw); - - for (i = 0; i < BC_TX_LIST_CNT; i++) { - if (hw->tx_pkt_pool[i].desc_mem.pdma_desc_start) { - bc_kern_dma_free(hw->adp, - hw->tx_pkt_pool[i].desc_mem.sz, - hw->tx_pkt_pool[i].desc_mem.pdma_desc_start, - hw->tx_pkt_pool[i].desc_mem.phy_addr); - - hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = NULL; - } - } - - dev_dbg(&hw->adp->pdev->dev, "Releasing RX Pkt pool\n"); - for (i = 0; i < BC_RX_LIST_CNT; i++) { - rpkt = crystalhd_hw_alloc_rx_pkt(hw); - if (!rpkt) - break; - bc_kern_dma_free(hw->adp, rpkt->desc_mem.sz, - rpkt->desc_mem.pdma_desc_start, - rpkt->desc_mem.phy_addr); - kfree(rpkt); - } - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, - uint32_t list_id, BC_STATUS cs) -{ - tx_dma_pkt *tx_req; - - if (!hw || !list_id) { - printk(KERN_ERR "%s: Invalid Arg!!\n", __func__); - return BC_STS_INV_ARG; - } - - tx_req = (tx_dma_pkt *)crystalhd_dioq_find_and_fetch(hw->tx_actq, list_id); - if (!tx_req) { - if (cs != BC_STS_IO_USER_ABORT) - dev_err(&hw->adp->pdev->dev, "Find/Fetch: no req!\n"); - return BC_STS_NO_DATA; - } - - if (tx_req->call_back) { - tx_req->call_back(tx_req->dio_req, tx_req->cb_event, cs); - tx_req->dio_req = NULL; - tx_req->cb_event = NULL; - tx_req->call_back = NULL; - } else { - dev_dbg(&hw->adp->pdev->dev, "Missing Tx Callback - %X\n", - tx_req->list_tag); - } - - /* Now put back the tx_list back in FreeQ */ - tx_req->list_tag = 0; - - return crystalhd_dioq_add(hw->tx_freeq, tx_req, false, 0); -} - -BC_STATUS crystalhd_hw_fill_desc(crystalhd_dio_req *ioreq, - dma_descriptor *desc, - dma_addr_t desc_paddr_base, - uint32_t sg_cnt, uint32_t sg_st_ix, - uint32_t sg_st_off, uint32_t xfr_sz, - struct device *dev, uint32_t destDRAMaddr) -{ - uint32_t count = 0, ix = 0, sg_ix = 0, len = 0, last_desc_ix = 0; - dma_addr_t desc_phy_addr = desc_paddr_base; - addr_64 addr_temp; - uint32_t curDRAMaddr = destDRAMaddr; - - if (!ioreq || !desc || !desc_paddr_base || !xfr_sz || - (!sg_cnt && !ioreq->uinfo.dir_tx)) { - dev_err(dev, "%s: Invalid Args\n", __func__); - return BC_STS_INV_ARG; - } - - for (ix = 0; ix < sg_cnt; ix++) { - - /* Setup SGLE index. */ - sg_ix = ix + sg_st_ix; - - /* Get SGLE length */ - len = crystalhd_get_sgle_len(ioreq, sg_ix); - if (len % 4) { - dev_err(dev, "unsupported len in sg %d %d %d\n", - len, sg_ix, sg_cnt); - return BC_STS_NOT_IMPL; - } - /* Setup DMA desc with Phy addr & Length at current index. */ - addr_temp.full_addr = crystalhd_get_sgle_paddr(ioreq, sg_ix); - if (sg_ix == sg_st_ix) { - addr_temp.full_addr += sg_st_off; - len -= sg_st_off; - } - memset(&desc[ix], 0, sizeof(desc[ix])); - desc[ix].buff_addr_low = addr_temp.low_part; - desc[ix].buff_addr_high = addr_temp.high_part; - desc[ix].dma_dir = ioreq->uinfo.dir_tx; // RX dma_dir = 0, TX dma_dir = 1 - - /* Chain DMA descriptor. */ - addr_temp.full_addr = desc_phy_addr + sizeof(dma_descriptor); - desc[ix].next_desc_addr_low = addr_temp.low_part; - desc[ix].next_desc_addr_high = addr_temp.high_part; - - if ((count + len) > xfr_sz) - len = xfr_sz - count; - - /* Debug.. */ - if ((!len) || (len > crystalhd_get_sgle_len(ioreq, sg_ix))) { - dev_err(dev, "inv-len(%x) Ix(%d) count:%x xfr_sz:%x " - "sg_cnt:%d\n", len, ix, count, xfr_sz, sg_cnt); - return BC_STS_ERROR; - } - /* Length expects Multiple of 4 */ - desc[ix].xfer_size = (len / 4); - - count += len; - // If TX fill in the destination DRAM address if needed - if(ioreq->uinfo.dir_tx) { - desc[ix].sdram_buff_addr = curDRAMaddr; - curDRAMaddr = destDRAMaddr + count; - } - else - desc[ix].sdram_buff_addr = 0; - - desc_phy_addr += sizeof(dma_descriptor); - } - - last_desc_ix = ix - 1; - - if (ioreq->fb_size) { - memset(&desc[ix], 0, sizeof(desc[ix])); - addr_temp.full_addr = ioreq->fb_pa; - desc[ix].buff_addr_low = addr_temp.low_part; - desc[ix].buff_addr_high = addr_temp.high_part; - desc[ix].dma_dir = ioreq->uinfo.dir_tx; - desc[ix].xfer_size = 1; - desc[ix].fill_bytes = 4 - ioreq->fb_size; - count += ioreq->fb_size; - // If TX fill in the destination DRAM address if needed - if(ioreq->uinfo.dir_tx) { - desc[ix].sdram_buff_addr = curDRAMaddr; - curDRAMaddr = destDRAMaddr + count; - } - else - desc[ix].sdram_buff_addr = 0; - last_desc_ix++; - } - - /* setup last descriptor..*/ - desc[last_desc_ix].last_rec_indicator = 1; - desc[last_desc_ix].next_desc_addr_low = 0; - desc[last_desc_ix].next_desc_addr_high = 0; - desc[last_desc_ix].intr_enable = 1; - - if (count != xfr_sz) { - dev_err(dev, "interal error sz curr:%x exp:%x\n", - count, xfr_sz); - return BC_STS_ERROR; - } - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_xlat_sgl_to_dma_desc(crystalhd_dio_req *ioreq, - pdma_desc_mem pdesc_mem, - uint32_t *uv_desc_index, - struct device *dev, uint32_t destDRAMaddr) -{ - dma_descriptor *desc = NULL; - dma_addr_t desc_paddr_base = 0; - uint32_t sg_cnt = 0, sg_st_ix = 0, sg_st_off = 0; - uint32_t xfr_sz = 0; - BC_STATUS sts = BC_STS_SUCCESS; - - /* Check params.. */ - if (!ioreq || !pdesc_mem || !uv_desc_index) { - dev_err(dev, "%s: Invalid Args\n", __func__); - return BC_STS_INV_ARG; - } - - if (!pdesc_mem->sz || !pdesc_mem->pdma_desc_start || - !ioreq->sg || (!ioreq->sg_cnt && !ioreq->uinfo.dir_tx)) { - dev_err(dev, "%s: Invalid Args\n", __func__); - return BC_STS_INV_ARG; - } - - if ((ioreq->uinfo.dir_tx) && (ioreq->uinfo.uv_offset)) { - dev_err(dev, "%s: UV offset for TX??\n", __func__); - return BC_STS_INV_ARG; - - } - - desc = pdesc_mem->pdma_desc_start; - desc_paddr_base = pdesc_mem->phy_addr; - - if (ioreq->uinfo.dir_tx || (ioreq->uinfo.uv_offset == 0)) { - sg_cnt = ioreq->sg_cnt; - xfr_sz = ioreq->uinfo.xfr_len; - } else { - sg_cnt = ioreq->uinfo.uv_sg_ix + 1; - xfr_sz = ioreq->uinfo.uv_offset; - } - - sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, - sg_st_ix, sg_st_off, xfr_sz, dev, destDRAMaddr); - - if ((sts != BC_STS_SUCCESS) || !ioreq->uinfo.uv_offset) - return sts; - - /* Prepare for UV mapping.. */ - desc = &pdesc_mem->pdma_desc_start[sg_cnt]; - desc_paddr_base = pdesc_mem->phy_addr + - (sg_cnt * sizeof(dma_descriptor)); - - /* Done with desc addr.. now update sg stuff.*/ - sg_cnt = ioreq->sg_cnt - ioreq->uinfo.uv_sg_ix; - xfr_sz = ioreq->uinfo.xfr_len - ioreq->uinfo.uv_offset; - sg_st_ix = ioreq->uinfo.uv_sg_ix; - sg_st_off = ioreq->uinfo.uv_sg_off; - - sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, - sg_st_ix, sg_st_off, xfr_sz, dev, destDRAMaddr); - if (sts != BC_STS_SUCCESS) - return sts; - - *uv_desc_index = sg_st_ix; - - return sts; -} - -BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, - uint32_t list_index, - BC_STATUS comp_sts) -{ - crystalhd_rx_dma_pkt *rx_pkt = NULL; - uint32_t y_dw_dnsz, uv_dw_dnsz; - BC_STATUS sts = BC_STS_SUCCESS; - uint64_t currTick; - - uint32_t totalTick_Hi; - uint32_t TickSpentInPD_Hi; - uint64_t temp_64; - int32_t totalTick_Hi_f; - int32_t TickSpentInPD_Hi_f; - - if (!hw || list_index >= DMA_ENGINE_CNT) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq, - hw->rx_pkt_tag_seed + list_index); - if (!rx_pkt) { - dev_err(&hw->adp->pdev->dev, "Act-Q: PostIx:%x L0Sts:%x " - "L1Sts:%x current L:%x tag:%x comp:%x\n", - hw->rx_list_post_index, hw->rx_list_sts[0], - hw->rx_list_sts[1], list_index, - hw->rx_pkt_tag_seed + list_index, comp_sts); - return BC_STS_INV_ARG; - } - - if (comp_sts == BC_STS_SUCCESS) - { - hw->DrvTotalFrmCaptured++; - - hw->pfnHWGetDoneSize(hw, list_index, &y_dw_dnsz, &uv_dw_dnsz); - rx_pkt->dio_req->uinfo.y_done_sz = y_dw_dnsz; - rx_pkt->flags = COMP_FLAG_DATA_VALID; - if (rx_pkt->uv_phy_addr) - rx_pkt->dio_req->uinfo.uv_done_sz = uv_dw_dnsz; - crystalhd_dioq_add(hw->rx_rdyq, rx_pkt, true, - hw->rx_pkt_tag_seed + list_index); - - if( hw->adp->pdev->device == BC_PCI_DEVID_FLEA) - { - //printk("pre-PD state %x RLL %x Ptsh %x ratio %d currentPS %d\n", - // hw->FleaPowerState, crystalhd_dioq_count(hw->rx_rdyq) , hw->PauseThreshold, hw->PDRatio, hw->FleaPowerState); - if(hw->FleaPowerState == FLEA_PS_ACTIVE) - { - if(crystalhd_dioq_count(hw->rx_rdyq) >= hw->PauseThreshold) - { - hw->pfnIssuePause(hw, true); - hw->hw_pause_issued = true; - } - /* NAREN check if the PD ratio is less than 50. If so, try to reduce the PauseThreshold to improve the ratio */ - /* never go lower than 6 pictures */ - /* Only do this when we have some data to determine PDRatio */ - /* For now assume that if we have captured 100 pictures then we should have enough data for the analysis to start */ - if((hw->PDRatio < 50) && (hw->PauseThreshold > 6) && (hw->DrvTotalFrmCaptured > 100)) - { - //printk("Current PDRatio:%u, PauseThreshold:%u, DrvTotalFrmCaptured:%u decress PauseThreshold\n", - // hw->PDRatio, hw->PauseThreshold, hw->DrvTotalFrmCaptured); - hw->PauseThreshold--; - } - else { - rdtscll(currTick); - - temp_64 = (hw->TickSpentInPD)>>24; - TickSpentInPD_Hi = (uint32_t)(temp_64); - TickSpentInPD_Hi_f = (int32_t)TickSpentInPD_Hi; - - temp_64 = (currTick - hw->TickCntDecodePU)>>24; - totalTick_Hi = (uint32_t)(temp_64); - totalTick_Hi_f = (int32_t)totalTick_Hi; - - if( totalTick_Hi_f <= 0 ) - { - temp_64 = (hw->TickSpentInPD); - TickSpentInPD_Hi = (uint32_t)(temp_64); - TickSpentInPD_Hi_f = (int32_t)TickSpentInPD_Hi; - - temp_64 = (currTick - hw->TickCntDecodePU); - totalTick_Hi = (uint32_t)(temp_64); - totalTick_Hi_f = (int32_t)totalTick_Hi; - } - - if( totalTick_Hi_f <= 0 ) - { - printk("totalTick_Hi_f <= 0, set hw->PDRatio = 60\n"); - hw->PDRatio = 60; - } - else - hw->PDRatio = (TickSpentInPD_Hi_f * 100) / totalTick_Hi_f; - - //printk("Current PDRatio:%u, PauseThreshold:%u, DrvTotalFrmCaptured:%u don't decress PauseThreshold\n", - // hw->PDRatio, hw->PauseThreshold, hw->DrvTotalFrmCaptured); - - //hw->PDRatio = ((uint32_t)(hw->TickSpentInPD))/((uint32_t)(currTick - hw->TickCntDecodePU)/100); - } - } - } - else if( hw->hw_pause_issued == false ) - { -// if(crystalhd_dioq_count(hw->rx_rdyq) > hw->PauseThreshold)//HW_PAUSE_THRESHOLD -// { -// dev_info(&hw->adp->pdev->dev, "HW PAUSE\n"); -// hw->pfnIssuePause(hw, true); -// hw->hw_pause_issued = true; -// } - } - - return sts; - } - /* Check if we can post this DIO again. */ - return hw->pfnPostRxSideBuff(hw, rx_pkt); -} - -BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, crystalhd_dio_req *ioreq, - hw_comp_callback call_back, - wait_queue_head_t *cb_event, uint32_t *list_id, - uint8_t data_flags) -{ - struct device *dev; - tx_dma_pkt *tx_dma_packet = NULL; - uint32_t low_addr, high_addr; - addr_64 desc_addr; - BC_STATUS sts, add_sts; - uint32_t dummy_index = 0; - unsigned long flags; - uint8_t list_posted; - uint8_t local_flags = data_flags; - bool rc; - uint32_t destDRAMaddr = 0; - - if (!hw || !ioreq || !call_back || !cb_event || !list_id) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &hw->adp->pdev->dev; - - /* - * Since we hit code in busy condition very frequently, - * we will check the code in status first before - * checking the availability of free elem. - * - * This will avoid the Q fetch/add in normal condition. - */ - - rc = hw->pfnCheckInputFIFO(hw, ioreq->uinfo.xfr_len, - &dummy_index, false, &local_flags); - - if (rc) { - hw->stats.cin_busy++; - return BC_STS_BUSY; - } - - if(local_flags & BC_BIT(7)) - destDRAMaddr = hw->TxFwInputBuffInfo.DramBuffAdd; - - /* Get a list from TxFreeQ */ - tx_dma_packet = (tx_dma_pkt *)crystalhd_dioq_fetch(hw->tx_freeq); - if (!tx_dma_packet) { - dev_err(dev, "No empty elements..\n"); - return BC_STS_ERR_USAGE; - } - - sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, - &tx_dma_packet->desc_mem, - &dummy_index, dev, destDRAMaddr); - if (sts != BC_STS_SUCCESS) { - add_sts = crystalhd_dioq_add(hw->tx_freeq, tx_dma_packet, - false, 0); - if (add_sts != BC_STS_SUCCESS) - dev_err(dev, "double fault..\n"); - - return sts; - } - - desc_addr.full_addr = tx_dma_packet->desc_mem.phy_addr; - low_addr = desc_addr.low_part; - high_addr = desc_addr.high_part; - - tx_dma_packet->call_back = call_back; - tx_dma_packet->cb_event = cb_event; - tx_dma_packet->dio_req = ioreq; - - spin_lock_irqsave(&hw->lock, flags); - - list_posted = hw->tx_list_post_index; - - *list_id = tx_dma_packet->list_tag = hw->tx_ioq_tag_seed + - hw->tx_list_post_index; - - - if( hw->tx_list_post_index % DMA_ENGINE_CNT) { - hw->TxList1Sts |= TxListWaitingForIntr; - } - else { - hw->TxList0Sts |= TxListWaitingForIntr; - } - - hw->tx_list_post_index = (hw->tx_list_post_index + 1) % DMA_ENGINE_CNT; - - /* Insert in Active Q..*/ - crystalhd_dioq_add(hw->tx_actq, tx_dma_packet, false, - tx_dma_packet->list_tag); - - /* - * Interrupt will come as soon as you write - * the valid bit. So be ready for that. All - * the initialization should happen before that. - */ - - // Save the transfer length - hw->TxFwInputBuffInfo.HostXferSzInBytes = ioreq->uinfo.xfr_len; - - hw->pfnStartTxDMA(hw, list_posted, desc_addr); - - spin_unlock_irqrestore(&hw->lock, flags); - - return BC_STS_SUCCESS; -} - -/* - * This is a force cancel and we are racing with ISR. - * - * Will try to remove the req from ActQ before ISR gets it. - * If ISR gets it first then the completion happens in the - * normal path and we will return _STS_NO_DATA from here. - * - * FIX_ME: Not Tested the actual condition.. - */ -BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id) -{ - unsigned long flags; - if (!hw || !list_id) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - spin_lock_irqsave(&hw->lock, flags); - hw->pfnStopTxDMA(hw); - spin_unlock_irqrestore(&hw->lock, flags); - crystalhd_hw_tx_req_complete(hw, list_id, BC_STS_IO_USER_ABORT); - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, - crystalhd_dio_req *ioreq, bool en_post) -{ - crystalhd_rx_dma_pkt *rpkt; - uint32_t tag, uv_desc_ix = 0; - BC_STATUS sts; - - if (!hw || !ioreq) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - rpkt = crystalhd_hw_alloc_rx_pkt(hw); - if (!rpkt) { - dev_err(&hw->adp->pdev->dev, "Insufficient resources\n"); - return BC_STS_INSUFF_RES; - } - - rpkt->dio_req = ioreq; - tag = rpkt->pkt_tag; - - sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem, - &uv_desc_ix, &hw->adp->pdev->dev, 0); - if (sts != BC_STS_SUCCESS) - return sts; - - rpkt->uv_phy_addr = 0; - - /* Store the address of UV in the rx packet for post*/ - if (uv_desc_ix) - rpkt->uv_phy_addr = rpkt->desc_mem.phy_addr + - (sizeof(dma_descriptor) * (uv_desc_ix + 1)); - - if (en_post && !hw->hw_pause_issued) { - sts = hw->pfnPostRxSideBuff(hw, rpkt); - } - else { - sts = crystalhd_dioq_add(hw->rx_freeq, rpkt, false, tag); - hw->pfnNotifyFLLChange(hw, false); - } - - return sts; -} - -BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, - C011_PIB *pib, - crystalhd_dio_req **ioreq) -{ - crystalhd_rx_dma_pkt *rpkt; - uint32_t timeout = BC_PROC_OUTPUT_TIMEOUT / 1000; - uint32_t sig_pending = 0; - - if (!hw || !ioreq || !pib) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - rpkt = crystalhd_dioq_fetch_wait(hw, timeout, &sig_pending); - - if( hw->adp->pdev->device == BC_PCI_DEVID_FLEA) - { - //printk("pre-PU state %x RLL %x Rtsh %x, currentPS %d,\n", - // hw->FleaPowerState, crystalhd_dioq_count(hw->rx_rdyq) , hw->ResumeThreshold, hw->FleaPowerState); - if( (hw->FleaPowerState == FLEA_PS_LP_PENDING) || - (hw->FleaPowerState == FLEA_PS_LP_COMPLETE)) - { - if(crystalhd_dioq_count(hw->rx_rdyq) <= hw->ResumeThreshold) - hw->pfnIssuePause(hw, false); /*Need this Notification For Flea*/ - hw->hw_pause_issued = false; - } - } - else if( hw->hw_pause_issued) - { -// if(crystalhd_dioq_count(hw->rx_rdyq) < hw->PauseThreshold ) //HW_RESUME_THRESHOLD -// { -// dev_info(&hw->adp->pdev->dev, "HW RESUME with rdy list %u \n",crystalhd_dioq_count(hw->rx_rdyq)); -// hw->pfnIssuePause(hw, false); -// hw->hw_pause_issued = false; -// } - } - - if (!rpkt) { - if (sig_pending) { - return BC_STS_IO_USER_ABORT; - } else { - return BC_STS_TIMEOUT; - } - } - - rpkt->dio_req->uinfo.comp_flags = rpkt->flags; - - if (rpkt->flags & COMP_FLAG_PIB_VALID) - { - pib->ppb.picture_number = rpkt->pib.picture_number; - pib->ppb.width = rpkt->pib.width; - pib->ppb.height = rpkt->pib.height; - pib->ppb.chroma_format = rpkt->pib.chroma_format; - pib->ppb.pulldown = rpkt->pib.pulldown; - pib->ppb.flags = rpkt->pib.flags; - pib->ptsStcOffset = rpkt->pib.sess_num; - pib->ppb.aspect_ratio = rpkt->pib.aspect_ratio; - pib->ppb.colour_primaries = rpkt->pib.colour_primaries; - pib->ppb.picture_meta_payload = rpkt->pib.picture_meta_payload; - pib->resolution = rpkt->pib.frame_rate; - } - - *ioreq = rpkt->dio_req; - - crystalhd_hw_free_rx_pkt(hw, rpkt); - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw) -{ - crystalhd_rx_dma_pkt *rx_pkt; - BC_STATUS sts; - uint32_t i; - - if (!hw) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - /* This is start of capture.. Post to both the lists.. */ - for (i = 0; i < DMA_ENGINE_CNT; i++) { - rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); - if (!rx_pkt) - return BC_STS_NO_DATA; - sts = hw->pfnPostRxSideBuff(hw, rx_pkt); - if (BC_STS_SUCCESS != sts) - break; - - } - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw, bool unmap) -{ - void *temp = NULL; - - if (!hw) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - hw->pfnStopRXDMAEngines(hw); - - if(!unmap) - return BC_STS_SUCCESS; - - // Clear up Active, Ready and Free lists one by one and release resources - do { - temp = crystalhd_dioq_fetch(hw->rx_actq); - if (temp) - crystalhd_rx_pkt_rel_call_back(hw, temp); - } while (temp); - - do { - temp = crystalhd_dioq_fetch(hw->rx_rdyq); - if (temp) - crystalhd_rx_pkt_rel_call_back(hw, temp); - } while (temp); - - do { - temp = crystalhd_dioq_fetch(hw->rx_freeq); - if (temp) - crystalhd_rx_pkt_rel_call_back(hw, temp); - } while (temp); - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw) -{ - if (!hw) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - if (!hw->pfnStopDevice(hw)) { - dev_err(&hw->adp->pdev->dev, "Failed to Stop Device!!\n"); - return BC_STS_ERROR; - } - - return BC_STS_SUCCESS; -} - -void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats) -{ - if (!hw) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return; - } - - /* if called w/NULL stats, its a req to zero out the stats */ - if (!stats) { - hw->DrvTotalFrmCaptured = 0; - memset(&hw->stats, 0, sizeof(hw->stats)); - return; - } - - hw->stats.freeq_count = crystalhd_dioq_count(hw->rx_freeq); - hw->stats.rdyq_count = crystalhd_dioq_count(hw->rx_rdyq); - memcpy(stats, &hw->stats, sizeof(*stats)); -} diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_hw.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_hw.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_hw.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_hw.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,552 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_hw . h - * - * Description: - * BCM70012 Linux driver hardware layer. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#ifndef _CRYSTALHD_HW_H_ -#define _CRYSTALHD_HW_H_ -#define DEBUG 1 - -#include -#include -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24) -#include -#else -#include -#endif -#include "crystalhd_fw_if.h" -#include "crystalhd_misc.h" -#include "DriverFwShare.h" -#include "FleaDefs.h" - -/* HW constants..*/ -#define DMA_ENGINE_CNT 2 -#define MAX_PIB_Q_DEPTH 64 -#define MIN_PIB_Q_DEPTH 2 -#define WR_POINTER_OFF 4 -#define MAX_VALID_POLL_CNT 1000 - -#define TX_WRAP_THRESHOLD 128 * 1024 - -#define NUMBER_OF_TRANSFERS_TX_SIDE 1 -#define NUMBER_OF_TRANSFERS_RX_SIDE 2 - -typedef struct _BC_DRV_PIC_INFO_{ - C011_PIB DecoPIB; - struct _BC_DRV_PIC_INFO_ *Flink; -} BC_DRV_PIC_INFO, *PBC_DRV_PIC_INFO; - -typedef union _desc_low_addr_reg_ { - struct { -#ifdef __LITTLE_ENDIAN_BITFIELD - uint32_t list_valid:1; - uint32_t reserved:4; - uint32_t low_addr:27; -#else - uint32_t low_addr:27; - uint32_t reserved:4; - uint32_t list_valid:1; -#endif - }; - - uint32_t whole_reg; - -} desc_low_addr_reg; - -typedef struct _dma_descriptor_ { /* 8 32-bit values */ -#ifdef __LITTLE_ENDIAN_BITFIELD - /* 0th u32 */ - uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ - uint32_t res0:4; /* bits 28-31: Reserved */ - - /* 1st u32 */ - uint32_t buff_addr_low; /* 1 buffer address low */ - uint32_t buff_addr_high; /* 2 buffer address high */ - - /* 3rd u32 */ - uint32_t res2:2; /* 0-1 - Reserved */ - uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ - uint32_t res3:6; /* 25-30 reserved */ - uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ - - /* 4th u32 */ - uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ - uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ - uint32_t res4:25; /* 3 - 27 Reserved bits */ - uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ - uint32_t dma_dir:1; /* 30 bit DMA Direction */ - uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ - - /* 5th u32 */ - uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ - - /* 6th u32 */ - uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ - - /* 7th u32 */ - uint32_t res8; /* Last 32bits reserved */ -#else - /* 0th u32 */ - uint32_t res0:4; /* bits 28-31: Reserved */ - uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ - - /* 1st u32 */ - uint32_t buff_addr_low; /* 1 buffer address low */ - uint32_t buff_addr_high; /* 2 buffer address high */ - - /* 3rd u32 */ - uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ - uint32_t res3:6; /* 25-30 reserved */ - uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ - uint32_t res2:2; /* 0-1 - Reserved */ - - /* 4th u32 */ - uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ - uint32_t dma_dir:1; /* 30 bit DMA Direction */ - uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ - uint32_t res4:25; /* 3 - 27 Reserved bits */ - uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ - uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ - - /* 5th u32 */ - uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ - - /* 6th u32 */ - uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ - - /* 7th u32 */ - uint32_t res8; /* Last 32bits reserved */ -#endif -} dma_descriptor, *pdma_descriptor; - -/* - * We will allocate the memory in 4K pages - * the linked list will be a list of 32 byte descriptors. - * The virtual address will determine what should be freed. - */ -typedef struct _dma_desc_mem_ { - pdma_descriptor pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */ - dma_addr_t phy_addr; /* physical address of each DMA desc */ - uint32_t sz; - struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */ - -} dma_desc_mem, *pdma_desc_mem; - -typedef enum _list_sts_ { - sts_free = 0, - - /* RX-Y Bits 0:7 */ - rx_waiting_y_intr = 0x00000001, - rx_y_error = 0x00000004, - - /* RX-UV Bits 8:16 */ - rx_waiting_uv_intr = 0x0000100, - rx_uv_error = 0x0000400, - - rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr), - rx_sts_error = (rx_y_error|rx_uv_error), - - rx_y_mask = 0x000000FF, - rx_uv_mask = 0x0000FF00, - -} list_sts; - - -typedef enum _INTERRUPT_STATUS_ -{ - NO_INTERRUPT = 0x0000, - FPGA_RX_L0_DMA_DONE = 0x0001, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - FPGA_RX_L1_DMA_DONE = 0x0002, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - FPGA_TX_L0_DMA_DONE = 0x0004, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - FPGA_TX_L1_DMA_DONE = 0x0008, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - DECO_PIB_INTR = 0x0010, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - DECO_FMT_CHANGE = 0x0020, - DECO_MBOX_RESP = 0x0040, - DECO_RESUME_FRM_INTER_PAUSE = 0x0080, /*Not Handled in DPC Need to Fire Rx cmds on resume from Pause*/ -}INTERRUPT_STATUS; - -typedef enum _ERR_STATUS_ -{ - NO_ERROR =0, - RX_Y_DMA_ERR_L0 =0x0001,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - RX_UV_DMA_ERR_L0 =0x0002,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - RX_Y_DMA_ERR_L1 =0x0004,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - RX_UV_DMA_ERR_L1 =0x0008,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - TX_DMA_ERR_L0 =0x0010,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - TX_DMA_ERR_L1 =0x0020,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ - FW_CMD_ERROR =0x0040, - DROP_REPEATED =0x0080, - DROP_FLEA_FMTCH =0x0100,/*We do not want to deliver the flea dummy frame*/ - DROP_DATA_ERROR =0x0200,//We were not able to get the PIB correctly so drop the frame. - DROP_SIZE_ERROR =0x0400,//We were not able to get the size properly from hardware. - FORCE_CANCEL =0x8000 -}ERROR_STATUS; - -typedef enum _LIST_STATUS_ -{ - ListStsFree=0, // Initial state and state the buffer is moved to Ready Buffer list. - RxListWaitingForYIntr=1, // When the Y Descriptor is posted. - RxListWaitingForUVIntr=2, // When the UV descriptor is posted. - TxListWaitingForIntr =4, -}LIST_STATUS; - -typedef struct _RX_LIST_{ - LIST_STATUS ListSts; - //LIST_ENTRY ActiveList; - uint32_t ActiveListLen; - uint32_t ListLockInd; /* To Be Filled up During Init */ - uint32_t ulDiscCount; /* Discontinuity On this list */ - uint32_t RxYFirstDescLADDRReg; /* First Desc Low Addr Y */ - uint32_t RxYFirstDescUADDRReg; /* First Desc UPPER Addr Y */ - uint32_t RxYCurDescLADDRReg; /* Current Desc Low Addr Y */ - uint32_t RxYCurDescUADDRReg; /* First Desc Low Addr Y */ - uint32_t RxYCurByteCntRemReg; /* Cur Byte Cnt Rem Y */ - - uint32_t RxUVFirstDescLADDRReg; /* First Desc Low Addr UV */ - uint32_t RxUVFirstDescUADDRReg; /* First Desc UPPER Addr UV */ - uint32_t RxUVCurDescLADDRReg; /* Current Desc Low Addr UV */ - uint32_t RxUVCurDescUADDRReg; /* Current Desc UPPER Addr UV */ - uint32_t RxUVCurByteCntRemReg; /* Cur Byte Cnt Rem UV */ -}RX_DMA_LIST,*PRX_DMA_LIST; - -typedef struct _tx_dma_pkt_ { - dma_desc_mem desc_mem; - hw_comp_callback call_back; - crystalhd_dio_req *dio_req; - wait_queue_head_t *cb_event; - uint32_t list_tag; - -} tx_dma_pkt; - -typedef struct _crystalhd_rx_dma_pkt { - dma_desc_mem desc_mem; - crystalhd_dio_req *dio_req; - uint32_t pkt_tag; - uint32_t flags; - BC_PIC_INFO_BLOCK pib; - dma_addr_t uv_phy_addr; - struct _crystalhd_rx_dma_pkt *next; - -} crystalhd_rx_dma_pkt; - -struct crystalhd_hw_stats{ - uint32_t rx_errors; - uint32_t tx_errors; - uint32_t freeq_count; - uint32_t rdyq_count; - uint32_t num_interrupts; - uint32_t dev_interrupts; - uint32_t cin_busy; - uint32_t pause_cnt; - uint32_t rx_success; -}; - -typedef enum _DECODER_STATE_ -{ - DECO_OPERATIONAL = 0, /* We start with this state.ST_FW_DWNLD,ST_CAPTURE,STOP_CAPTURE */ - DECO_INTER_PAUSED = 1, /* Driver Issued Pause To Decoder */ - DECO_INTER_PAUSE_IN_PROGRESS = 2, /* Pause CMD is pending with F/W */ - DECO_INTER_RESUME_IN_PROGRESS = 3, /* Resume CMD is pending with F/W */ - DECO_STOPPED_BY_APP = 4 /* After STOP Video I do not want to Throttle Decoder.So Special State */ -}DECO_STATE; - -// -// These events can be used to notify the hardware layer -// to set up it adapter in proper state...or for anyother -// purpose for that matter. -// We will use this for intermediae events as defined below - -typedef enum _BRCM_EVENT_{ - BC_EVENT_ADAPTER_INIT_FAILED =0, - BC_EVENT_ADAPTER_INIT_SUCCESS =1, - BC_EVENT_FW_DNLD_STARTED =2, - BC_EVENT_FW_DNLD_ERR =3, - BC_EVENT_FW_DNLD_DONE =4, - BC_EVENT_SYS_SHUT_DOWN =5, - BC_EVENT_START_CAPTURE =6, - BC_EVENT_START_CAPTURE_IMMI =7, - BC_EVENT_STOP_CAPTURE =8, /* Stop Capturing the Rx buffers Stop the DMA engines UnMapBuffers Discard Free and Ready list */ - BC_EVENT_DO_CLEANUP =9, /* Total Cleanup Rx And Tx side */ - BC_DISCARD_RX_BUFFERS =10 /* Move all the Ready buffers to free list. Stop RX DMA. Post Rx Side buffers. */ -}BRCM_EVENT,*PBRCM_EVENT; - -struct crystalhd_hw; // forward declaration for the types - -//typedef void* (*HW_VERIFY_DEVICE)(struct crystalhd_adp*); -//typedef bool (*HW_INIT_DEVICE_RESOURCES)(struct crystalhd_adp*); -//typedef bool (*HW_CLEAN_DEVICE_RESOURCES)(struct crystalhd_adp*); -typedef bool (*HW_START_DEVICE)(struct crystalhd_hw*); -typedef bool (*HW_STOP_DEVICE)(struct crystalhd_hw*); -/* typedef bool (*HW_XLAT_AND_FIRE_SGL)(struct crystalhd_adp*,PVOID,PSCATTER_GATHER_LIST,uint32_t); */ -/* typedef bool (*HW_RX_XLAT_SGL)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ -typedef bool (*HW_FIND_AND_CLEAR_INTR)(struct crystalhd_adp*,struct crystalhd_hw*); -typedef uint32_t (*HW_READ_DEVICE_REG)(struct crystalhd_adp*,uint32_t); -typedef void (*HW_WRITE_DEVICE_REG)(struct crystalhd_adp*,uint32_t,uint32_t); -typedef uint32_t (*HW_READ_FPGA_REG)(struct crystalhd_adp*,uint32_t); -typedef void (*HW_WRITE_FPGA_REG)(struct crystalhd_adp*,uint32_t,uint32_t); -typedef BC_STATUS (*HW_READ_DEV_MEM)(struct crystalhd_hw*,uint32_t,uint32_t,uint32_t*); -typedef BC_STATUS (*HW_WRITE_DEV_MEM)(struct crystalhd_hw*,uint32_t,uint32_t,uint32_t*); -/* typedef bool (*HW_INIT_DRAM)(struct crystalhd_adp*); */ -/* typedef bool (*HW_DISABLE_INTR)(struct crystalhd_adp*); */ -/* typedef bool (*HW_ENABLE_INTR)(struct crystalhd_adp*); */ -typedef BC_STATUS (*HW_POST_RX_SIDE_BUFF)(struct crystalhd_hw*,crystalhd_rx_dma_pkt*); -typedef bool (*HW_CHECK_INPUT_FIFO)(struct crystalhd_hw*, uint32_t, uint32_t*,bool,uint8_t*); -typedef void (*HW_START_TX_DMA)(struct crystalhd_hw*, uint8_t, addr_64); -typedef BC_STATUS (*HW_STOP_TX_DMA)(struct crystalhd_hw*); -/* typedef bool (*HW_EVENT_NOTIFICATION)(struct crystalhd_adp*,BRCM_EVENT); */ -/* typedef bool (*HW_RX_POST_INTR_PROCESSING)(struct crystalhd_adp*,uint32_t,uint32_t); */ -typedef void (*HW_GET_DONE_SIZE)(struct crystalhd_hw *hw, uint32_t, uint32_t*, uint32_t*); -/* typedef bool (*HW_ADD_DRP_TO_FREE_LIST)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ -typedef crystalhd_dio_req* (*HW_FETCH_DONE_BUFFERS)(struct crystalhd_adp*,bool); -/* typedef bool (*HW_ADD_ROLLBACK_RXBUF)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ -typedef bool (*HW_PEEK_NEXT_DECODED_RXBUF)(struct crystalhd_hw*,uint64_t*,uint32_t*,uint32_t); -typedef BC_STATUS (*HW_FW_PASSTHRU_CMD)(struct crystalhd_hw*,PBC_FW_CMD); -/* typedef bool (*HW_CANCEL_FW_CMDS)(struct crystalhd_adp*,OS_CANCEL_CALLBACK); */ -/* typedef void* (*HW_GET_FW_DONE_OS_CMD)(struct crystalhd_adp*); */ -/* typedef PBC_DRV_PIC_INFO (*SEARCH_FOR_PIB)(struct crystalhd_adp*,bool,uint32_t); */ -/* typedef bool (*HW_DO_DRAM_PWR_MGMT)(struct crystalhd_adp*); */ -typedef BC_STATUS (*HW_FW_DOWNLOAD)(struct crystalhd_hw*,uint8_t*,uint32_t); -typedef BC_STATUS (*HW_ISSUE_DECO_PAUSE)(struct crystalhd_hw*, bool); -typedef void (*HW_STOP_DMA_ENGINES)(struct crystalhd_hw*); -/* -typedef BOOLEAN (*FIRE_RX_REQ_TO_HW) (PHW_EXTENSION,PRX_DMA_LIST); -typedef BOOLEAN (*PIC_POST_PROC) (PHW_EXTENSION,PRX_DMA_LIST,PULONG); -typedef BOOLEAN (*HW_ISSUE_DECO_PAUSE) (PHW_EXTENSION,BOOLEAN,BOOLEAN); -typedef BOOLEAN (*FIRE_TX_CMD_TO_HW) (PCONTEXT_FOR_POST_TX); -*/ -typedef void (*NOTIFY_FLL_CHANGE)(struct crystalhd_hw*,bool); -typedef bool (*HW_EVENT_NOTIFICATION)(struct crystalhd_hw*, BRCM_EVENT); - -struct crystalhd_hw { - tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT]; - spinlock_t lock; - - uint32_t tx_ioq_tag_seed; - uint32_t tx_list_post_index; - - crystalhd_rx_dma_pkt *rx_pkt_pool_head; - uint32_t rx_pkt_tag_seed; - - bool dev_started; - struct crystalhd_adp *adp; - - wait_queue_head_t *pfw_cmd_event; - int fwcmd_evt_sts; - - uint32_t pib_del_Q_addr; - uint32_t pib_rel_Q_addr; - uint32_t channelNum; - - crystalhd_dioq_t *tx_freeq; - crystalhd_dioq_t *tx_actq; - - /* Rx DMA Engine Specific Locks */ - spinlock_t rx_lock; - uint32_t rx_list_post_index; - list_sts rx_list_sts[DMA_ENGINE_CNT]; - crystalhd_dioq_t *rx_rdyq; - crystalhd_dioq_t *rx_freeq; - crystalhd_dioq_t *rx_actq; - uint32_t stop_pending; - - uint32_t hw_pause_issued; - - uint32_t fwcmdPostAddr; - uint32_t fwcmdPostMbox; - uint32_t fwcmdRespMbox; - - /* HW counters.. */ - struct crystalhd_hw_stats stats; - - /* Picture Information Block Management Variables */ - uint32_t PICWidth; /* Pic Width Recieved On Format Change for link/With WidthField On Flea*/ - uint32_t PICHeight; /* Pic Height Recieved on format change[Link and Flea]/Not Used in Flea*/ - uint32_t LastPicNo; /* For Repeated Frame Detection */ - uint32_t LastTwoPicNo; /* For Repeated Frame Detection on Interlace clip*/ - uint32_t LastSessNum; /* For Session Change Detection */ - - struct semaphore fetch_sem; // semaphore between fetch and probe of the next picture information, since both will be in process context - - uint32_t RxCaptureState; // 0 if capture is not enabled, 1 if capture is enabled, 2 if stop rxdma is pending - - // BCM70015 mods - uint32_t PicQSts; /* This is the bitmap given by PiCQSts Interrupt*/ - uint32_t TxBuffInfoAddr; /* Address of the TX Fifo in DRAM*/ - uint32_t FleaRxPicDelAddr; /* Memory address where the pictures are fired*/ - uint32_t FleaFLLUpdateAddr; /* Memory Address where FLL is updated*/ - uint32_t FleaBmpIntrCnt; - uint32_t RxSeqNum; - uint32_t DrvEosDetected; - uint32_t DrvCancelEosFlag; - - uint32_t SkipDropBadFrames; - uint32_t TemperatureRegVal; - TX_INPUT_BUFFER_INFO TxFwInputBuffInfo; - - DECO_STATE DecoderSt; /* Weather the decoder is paused or not*/ - uint32_t PauseThreshold; - uint32_t ResumeThreshold; - - uint32_t RxListPointer; /* Treat the Rx List As Circular List */ - LIST_STATUS TxList0Sts; - LIST_STATUS TxList1Sts; - - uint32_t FleaEnablePWM; - uint32_t FleaWaitFirstPlaybackNotify; - FLEA_POWER_STATES FleaPowerState; - uint32_t EmptyCnt; - bool SingleThreadAppFIFOEmpty; - bool PwrDwnTxIntr; /* Got an TX FIFO status interrupt when in power down state */ - bool PwrDwnPiQIntr; /* Got a Picture Q interrupt when in power down state */ - uint32_t OLWatchDogTimer; - uint32_t ILWatchDogTimer; - uint32_t FwCmdCnt; - bool WakeUpDecodeDone; /* Used to indicate that the HW is awake to RX is running so we can actively manage power */ - - uint64_t TickCntDecodePU; /* Time when we first powered up to decode */ - uint64_t TickSpentInPD; /* Total amount of time spent in PD */ - uint64_t TickStartInPD; /* Tick count when we start in PD */ - uint32_t PDRatio; /* % of time spent in power down. Goal is to keep this close to 50 */ - uint32_t DefaultPauseThreshold; /* default threshold to set when we start power management */ - -// uint32_t FreeListLen; -// uint32_t ReadyListLen; - -// -// Counters needed for monitoring purposes. -// These counters are per session and will be reset to zero in -// start capture. -// - uint32_t DrvPauseCnt; /* Number of Times the driver has issued pause.*/ - //uint32_t DrvServiceIntrCnt; /* Number of interrutps the driver serviced. */ - //uint32_t DrvIgnIntrCnt; /* Number of Interrupts Driver Ignored.NOT OUR INTR. */ - //uint32_t DrvTotalFrmDropped; /* Number of frames dropped by the driver.*/ - uint32_t DrvTotalFrmCaptured; /* Numner of Good Frames Captured*/ - //uint32_t DrvTotalHWErrs; /* Total HW Errors.*/ - //uint32_t DrvTotalPIBFlushCnt; /* Number of Times the driver flushed PIB Queues.*/ - //uint32_t DrvMissedPIBCnt; /* Number of Frames for which the PIB was not found.*/ - //uint64_t TickCntOnPause; - //uint32_t TotalTimeInPause; /* In Milliseconds */ - //uint32_t RepeatedFramesCnt; -// - -// HW_VERIFY_DEVICE pfnVerifyDevice; -// HW_INIT_DEVICE_RESOURCES pfnInitDevResources; -// HW_CLEAN_DEVICE_RESOURCES pfnCleanDevResources; - HW_START_DEVICE pfnStartDevice; - HW_STOP_DEVICE pfnStopDevice; -// HW_XLAT_AND_FIRE_SGL pfnTxXlatAndFireSGL; -// HW_RX_XLAT_SGL pfnRxXlatSgl; - HW_FIND_AND_CLEAR_INTR pfnFindAndClearIntr; - HW_READ_DEVICE_REG pfnReadDevRegister; - HW_WRITE_DEVICE_REG pfnWriteDevRegister; - HW_READ_FPGA_REG pfnReadFPGARegister; - HW_WRITE_FPGA_REG pfnWriteFPGARegister; - HW_READ_DEV_MEM pfnDevDRAMRead; - HW_WRITE_DEV_MEM pfnDevDRAMWrite; -// HW_INIT_DRAM pfnInitDRAM; -// HW_DISABLE_INTR pfnDisableIntr; -// HW_ENABLE_INTR pfnEnableIntr; - HW_POST_RX_SIDE_BUFF pfnPostRxSideBuff; - HW_CHECK_INPUT_FIFO pfnCheckInputFIFO; - HW_START_TX_DMA pfnStartTxDMA; - HW_STOP_TX_DMA pfnStopTxDMA; - HW_GET_DONE_SIZE pfnHWGetDoneSize; -// HW_EVENT_NOTIFICATION pfnNotifyHardware; -// HW_ADD_DRP_TO_FREE_LIST pfnAddRxDRPToFreeList; -// HW_FETCH_DONE_BUFFERS pfnFetchReadyRxDRP; -// HW_ADD_ROLLBACK_RXBUF pfnRollBackRxBuf; - HW_PEEK_NEXT_DECODED_RXBUF pfnPeekNextDeodedFr; - HW_FW_PASSTHRU_CMD pfnDoFirmwareCmd; -// HW_GET_FW_DONE_OS_CMD pfnGetFWDoneCmdOsCntxt; -// HW_CANCEL_FW_CMDS pfnCancelFWCmds; -// SEARCH_FOR_PIB pfnSearchPIB; -// HW_DO_DRAM_PWR_MGMT pfnDRAMPwrMgmt; - HW_FW_DOWNLOAD pfnFWDwnld; - HW_ISSUE_DECO_PAUSE pfnIssuePause; - HW_STOP_DMA_ENGINES pfnStopRXDMAEngines; -// FIRE_RX_REQ_TO_HW pfnFireRx; -// PIC_POST_PROC pfnPostProcessPicture; -// FIRE_TX_CMD_TO_HW pfnFireTx; - NOTIFY_FLL_CHANGE pfnNotifyFLLChange; - HW_EVENT_NOTIFICATION pfnNotifyHardware; -}; - -crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw); -void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt *pkt); -void crystalhd_tx_desc_rel_call_back(void *context, void *data); -void crystalhd_rx_pkt_rel_call_back(void *context, void *data); -void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw); -BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw); -BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp); -BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw, struct crystalhd_adp *adp); -BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw); -BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw); -BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, uint32_t list_id, BC_STATUS cs); -BC_STATUS crystalhd_hw_fill_desc(crystalhd_dio_req *ioreq, - dma_descriptor *desc, - dma_addr_t desc_paddr_base, - uint32_t sg_cnt, uint32_t sg_st_ix, - uint32_t sg_st_off, uint32_t xfr_sz, - struct device *dev, uint32_t destDRAMaddr); -BC_STATUS crystalhd_xlat_sgl_to_dma_desc(crystalhd_dio_req *ioreq, - pdma_desc_mem pdesc_mem, - uint32_t *uv_desc_index, - struct device *dev, uint32_t destDRAMaddr); -BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, - uint32_t list_index, - BC_STATUS comp_sts); -BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, crystalhd_dio_req *ioreq, - hw_comp_callback call_back, - wait_queue_head_t *cb_event, uint32_t *list_id, - uint8_t data_flags); -BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id); -BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,crystalhd_dio_req *ioreq, bool en_post); -BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,C011_PIB *pib,crystalhd_dio_req **ioreq); -BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); -BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw, bool unmap); -BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); -void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats); - -#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) - -#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) - -#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) - -#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) - -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_linkfuncs.c crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_linkfuncs.c --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_linkfuncs.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_linkfuncs.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,2056 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_hw . c - * - * Description: - * BCM70010 Linux driver HW layer. - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#include -#include -#include -#include -#include "crystalhd_hw.h" -#include "crystalhd_lnx.h" -#include "crystalhd_linkfuncs.h" -#include "bc_defines.h" - -#define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) - -/** -* link_dec_reg_rd - Read 70010's device register. -* @adp: Adapter instance -* @reg_off: Register offset. -* -* Return: -* 32bit value read -* -* 70010's device register read routine. This interface use -* 70010's device access range mapped from BAR-2 (4M) of PCIe -* configuration space. -*/ -uint32_t link_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) -{ - if (!adp) { - printk(KERN_ERR "%s: Invalid args\n", __func__); - return 0; - } - - if (reg_off > adp->pci_mem_len) { - dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", - __func__, reg_off); - return 0; - } - - return readl(adp->mem_addr + reg_off); -} - -/** -* link_dec_reg_wr - Write 70010's device register -* @adp: Adapter instance -* @reg_off: Register offset. -* @val: Dword value to be written. -* -* Return: -* none. -* -* 70010's device register write routine. This interface use -* 70010's device access range mapped from BAR-2 (4M) of PCIe -* configuration space. -*/ -void link_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) -{ - if (!adp) { - printk(KERN_ERR "%s: Invalid args\n", __func__); - return; - } - - if (reg_off > adp->pci_mem_len) { - dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", - __func__, reg_off); - return; - } - - writel(val, adp->mem_addr + reg_off); - - /* the udelay is required for latest 70012, not for others... :( */ - udelay(8); -} - -/** -* crystalhd_reg_rd - Read 70012's device register. -* @adp: Adapter instance -* @reg_off: Register offset. -* -* Return: -* 32bit value read -* -* 70012 device register read routine. This interface use -* 70012's device access range mapped from BAR-1 (64K) of PCIe -* configuration space. -* -*/ -uint32_t crystalhd_link_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) -{ - if (!adp) { - printk(KERN_ERR "%s: Invalid args\n", __func__); - return 0; - } - - if (reg_off > adp->pci_i2o_len) { - dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", - __func__, reg_off); - return 0; - } - - return readl(adp->i2o_addr + reg_off); -} - -/** -* crystalhd_reg_wr - Write 70012's device register -* @adp: Adapter instance -* @reg_off: Register offset. -* @val: Dword value to be written. -* -* Return: -* none. -* -* 70012 device register write routine. This interface use -* 70012's device access range mapped from BAR-1 (64K) of PCIe -* configuration space. -* -*/ -void crystalhd_link_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) -{ - if (!adp) { - printk(KERN_ERR "%s: Invalid args\n", __func__); - return; - } - - if (reg_off > adp->pci_i2o_len) { - dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", - __func__, reg_off); - return; - } - - writel(val, adp->i2o_addr + reg_off); -} - -inline uint32_t crystalhd_link_dram_rd(struct crystalhd_hw *hw, uint32_t mem_off) -{ - hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); - return hw->pfnReadDevRegister(hw->adp, (0x00380000 | (mem_off & 0x0007FFFF))); -} - -inline void crystalhd_link_dram_wr(struct crystalhd_hw *hw, uint32_t mem_off, uint32_t val) -{ - hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); - hw->pfnWriteDevRegister(hw->adp, (0x00380000 | (mem_off & 0x0007FFFF)), val); -} - -/** -* crystalhd_link_mem_rd - Read data from DRAM area. -* @adp: Adapter instance -* @start_off: Start offset. -* @dw_cnt: Count in dwords. -* @rd_buff: Buffer to copy the data from dram. -* -* Return: -* Status. -* -* Dram read routine. -*/ -BC_STATUS crystalhd_link_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, - uint32_t dw_cnt, uint32_t *rd_buff) -{ - uint32_t ix = 0; - - if (!hw || !rd_buff) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - for (ix = 0; ix < dw_cnt; ix++) - rd_buff[ix] = crystalhd_link_dram_rd(hw, (start_off + (ix * 4))); - - return BC_STS_SUCCESS; -} - -/** -* crystalhd_link_mem_wr - Write data to DRAM area. -* @adp: Adapter instance -* @start_off: Start offset. -* @dw_cnt: Count in dwords. -* @wr_buff: Data Buffer to be written. -* -* Return: -* Status. -* -* Dram write routine. -*/ -BC_STATUS crystalhd_link_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, - uint32_t dw_cnt, uint32_t *wr_buff) -{ - uint32_t ix = 0; - - if (!hw || !wr_buff) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - for (ix = 0; ix < dw_cnt; ix++) - crystalhd_link_dram_wr(hw, (start_off + (ix * 4)), wr_buff[ix]); - - return BC_STS_SUCCESS; -} - -void crystalhd_link_enable_uarts(struct crystalhd_hw *hw) -{ - hw->pfnWriteDevRegister(hw->adp, UartSelectA, BSVS_UART_STREAM); - hw->pfnWriteDevRegister(hw->adp, UartSelectB, BSVS_UART_DEC_OUTER); -} - -void crystalhd_link_start_dram(struct crystalhd_hw *hw) -{ - hw->pfnWriteDevRegister(hw->adp, SDRAM_PARAM, ((40 / 5 - 1) << 0) | - /* tras (40ns tras)/(5ns period) -1 ((15/5 - 1) << 4) | // trcd */ - ((15 / 5 - 1) << 7) | /* trp */ - ((10 / 5 - 1) << 10) | /* trrd */ - ((15 / 5 + 1) << 12) | /* twr */ - ((2 + 1) << 16) | /* twtr */ - ((70 / 5 - 2) << 19) | /* trfc */ - (0 << 23)); - - hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); - hw->pfnWriteDevRegister(hw->adp, SDRAM_EXT_MODE, 2); - hw->pfnWriteDevRegister(hw->adp, SDRAM_MODE, 0x132); - hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); - hw->pfnWriteDevRegister(hw->adp, SDRAM_REFRESH, 0); - hw->pfnWriteDevRegister(hw->adp, SDRAM_REFRESH, 0); - hw->pfnWriteDevRegister(hw->adp, SDRAM_MODE, 0x32); - /* setting the refresh rate here */ - hw->pfnWriteDevRegister(hw->adp, SDRAM_REF_PARAM, ((1 << 12) | 96)); -} - - -bool crystalhd_link_bring_out_of_rst(struct crystalhd_hw *hw) -{ - link_misc_perst_deco_ctrl rst_deco_cntrl; - link_misc_perst_clk_ctrl rst_clk_cntrl; - uint32_t temp; - - /* - * Link clocks: MISC_PERST_CLOCK_CTRL Clear PLL power down bit, - * delay to allow PLL to lock Clear alternate clock, stop clock bits - */ - rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.pll_pwr_dn = 0; - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - msleep_interruptible(50); - - rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.stop_core_clk = 0; - rst_clk_cntrl.sel_alt_clk = 0; - - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - msleep_interruptible(50); - - /* - * Bus Arbiter Timeout: GISB_ARBITER_TIMER - * Set internal bus arbiter timeout to 40us based on core clock speed - * (63MHz * 40us = 0x9D8) - */ - hw->pfnWriteFPGARegister(hw->adp, GISB_ARBITER_TIMER, 0x9D8); - - /* - * Decoder clocks: MISC_PERST_DECODER_CTRL - * Enable clocks while 7412 reset is asserted, delay - * De-assert 7412 reset - */ - rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); - rst_deco_cntrl.stop_bcm_7412_clk = 0; - rst_deco_cntrl.bcm7412_rst = 1; - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); - msleep_interruptible(50); - - rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); - rst_deco_cntrl.bcm7412_rst = 0; - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); - msleep_interruptible(50); - - /* Disable OTP_CONTENT_MISC to 0 to disable all secure modes */ - hw->pfnWriteFPGARegister(hw->adp, OTP_CONTENT_MISC, 0); - - /* Clear bit 29 of 0x404 */ - temp = hw->pfnReadFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION); - temp &= ~BC_BIT(29); - hw->pfnWriteFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); - - /* 2.5V regulator must be set to 2.6 volts (+6%) */ - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_VREG_CTRL, 0xF3); - - return true; -} - -bool crystalhd_link_put_in_reset(struct crystalhd_hw *hw) -{ - link_misc_perst_deco_ctrl rst_deco_cntrl; - link_misc_perst_clk_ctrl rst_clk_cntrl; - uint32_t temp; - - /* - * Decoder clocks: MISC_PERST_DECODER_CTRL - * Assert 7412 reset, delay - * Assert 7412 stop clock - */ - rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); - rst_deco_cntrl.stop_bcm_7412_clk = 1; - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); - msleep_interruptible(50); - - /* Bus Arbiter Timeout: GISB_ARBITER_TIMER - * Set internal bus arbiter timeout to 40us based on core clock speed - * (6.75MHZ * 40us = 0x10E) - */ - hw->pfnWriteFPGARegister(hw->adp, GISB_ARBITER_TIMER, 0x10E); - - /* Link clocks: MISC_PERST_CLOCK_CTRL - * Stop core clk, delay - * Set alternate clk, delay, set PLL power down - */ - rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.stop_core_clk = 1; - rst_clk_cntrl.sel_alt_clk = 1; - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - msleep_interruptible(50); - - rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); - rst_clk_cntrl.pll_pwr_dn = 1; - hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); - - /* - * Read and restore the Transaction Configuration Register - * after core reset - */ - temp = hw->pfnReadFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION); - - /* - * Link core soft reset: MISC3_RESET_CTRL - * - Write BIT[0]=1 and read it back for core reset to take place - */ - hw->pfnWriteFPGARegister(hw->adp, MISC3_RESET_CTRL, 1); - rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC3_RESET_CTRL); - msleep_interruptible(50); - - /* restore the transaction configuration register */ - hw->pfnWriteFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); - - return true; -} - -void crystalhd_link_disable_interrupts(struct crystalhd_hw *hw) -{ - intr_mask_reg intr_mask; - intr_mask.whole_reg = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_MSK_STS_REG); - intr_mask.mask_pcie_err = 1; - intr_mask.mask_pcie_rbusmast_err = 1; - intr_mask.mask_pcie_rgr_bridge = 1; - intr_mask.mask_rx_done = 1; - intr_mask.mask_rx_err = 1; - intr_mask.mask_tx_done = 1; - intr_mask.mask_tx_err = 1; - hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_MSK_SET_REG, intr_mask.whole_reg); - - return; -} - -void crystalhd_link_enable_interrupts(struct crystalhd_hw *hw) -{ - intr_mask_reg intr_mask; - intr_mask.whole_reg = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_MSK_STS_REG); - intr_mask.mask_pcie_err = 1; - intr_mask.mask_pcie_rbusmast_err = 1; - intr_mask.mask_pcie_rgr_bridge = 1; - intr_mask.mask_rx_done = 1; - intr_mask.mask_rx_err = 1; - intr_mask.mask_tx_done = 1; - intr_mask.mask_tx_err = 1; - hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_MSK_CLR_REG, intr_mask.whole_reg); - - return; -} - -void crystalhd_link_clear_errors(struct crystalhd_hw *hw) -{ - uint32_t reg; - - /* Writing a 1 to a set bit clears that bit */ - reg = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS); - if (reg) - hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, reg); - - reg = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS); - if (reg) - hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, reg); - - reg = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS); - if (reg) - hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, reg); -} - -void crystalhd_link_clear_interrupts(struct crystalhd_hw *hw) -{ - uint32_t intr_sts = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_STATUS); - - if (intr_sts) { - hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_CLR_REG, intr_sts); - - /* Write End Of Interrupt for PCIE */ - hw->pfnWriteFPGARegister(hw->adp, INTR_EOI_CTRL, 1); - } -} - -void crystalhd_link_soft_rst(struct crystalhd_hw *hw) -{ - uint32_t val; - - /* Assert c011 soft reset*/ - hw->pfnWriteDevRegister(hw->adp, DecHt_HostSwReset, 0x00000001); - msleep_interruptible(50); - - /* Release c011 soft reset*/ - hw->pfnWriteDevRegister(hw->adp, DecHt_HostSwReset, 0x00000000); - - /* Disable Stuffing..*/ - val = hw->pfnReadFPGARegister(hw->adp, MISC2_GLOBAL_CTRL); - val |= BC_BIT(8); - hw->pfnWriteFPGARegister(hw->adp, MISC2_GLOBAL_CTRL, val); -} - -bool crystalhd_link_load_firmware_config(struct crystalhd_hw *hw) -{ - uint32_t i = 0, reg; - - hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19)); - - hw->pfnWriteFPGARegister(hw->adp, AES_CMD, 0); - hw->pfnWriteFPGARegister(hw->adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF)); - hw->pfnWriteFPGARegister(hw->adp, AES_CMD, 0x1); - - for (i = 0; i < 100; ++i) { - reg = hw->pfnReadFPGARegister(hw->adp, AES_STATUS); - if (reg & 0x1) - return true; - msleep_interruptible(10); - } - - return false; -} - - -bool crystalhd_link_start_device(struct crystalhd_hw *hw) -{ - uint32_t dbg_options, glb_cntrl = 0, reg_pwrmgmt = 0; - struct device *dev; - - if (!hw) - return -EINVAL; - - dev = &hw->adp->pdev->dev; - - dev_dbg(dev, "Starting Crystal HD BCM70012 Device\n"); - - if (!crystalhd_link_bring_out_of_rst(hw)) { - dev_err(dev, "Failed To Bring BCM70012 Out Of Reset\n"); - return false; - } - - crystalhd_link_disable_interrupts(hw); - - crystalhd_link_clear_errors(hw); - - crystalhd_link_clear_interrupts(hw); - - crystalhd_link_enable_interrupts(hw); - - /* Enable the option for getting the total no. of DWORDS - * that have been transfered by the RXDMA engine - */ - dbg_options = hw->pfnReadFPGARegister(hw->adp, MISC1_DMA_DEBUG_OPTIONS_REG); - dbg_options |= 0x10; - hw->pfnWriteFPGARegister(hw->adp, MISC1_DMA_DEBUG_OPTIONS_REG, dbg_options); - - /* Enable PCI Global Control options */ - glb_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC2_GLOBAL_CTRL); - glb_cntrl |= 0x100; - glb_cntrl |= 0x8000; - hw->pfnWriteFPGARegister(hw->adp, MISC2_GLOBAL_CTRL, glb_cntrl); - - crystalhd_link_enable_interrupts(hw); - - crystalhd_link_soft_rst(hw); - crystalhd_link_start_dram(hw); - crystalhd_link_enable_uarts(hw); - - // Disable L1 ASPM while video is playing as this causes performance problems otherwise - reg_pwrmgmt = hw->pfnReadFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); - reg_pwrmgmt &= ~ASPM_L1_ENABLE; - - hw->pfnWriteFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, reg_pwrmgmt); - - return true; -} - -bool crystalhd_link_stop_device(struct crystalhd_hw *hw) -{ - uint32_t reg; - BC_STATUS sts; - - dev_dbg(&hw->adp->pdev->dev, "Stopping Crystal HD BCM70012 Device\n"); - sts = crystalhd_link_put_ddr2sleep(hw); - if (sts != BC_STS_SUCCESS) { - dev_err(&hw->adp->pdev->dev, "Failed to Put DDR To Sleep!!\n"); - return BC_STS_ERROR; - } - - /* Clear and disable interrupts */ - crystalhd_link_disable_interrupts(hw); - crystalhd_link_clear_errors(hw); - crystalhd_link_clear_interrupts(hw); - - if (!crystalhd_link_put_in_reset(hw)) - dev_err(&hw->adp->pdev->dev, "Failed to Put Link To Reset State\n"); - - reg = hw->pfnReadFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); - reg |= ASPM_L1_ENABLE; - hw->pfnWriteFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, reg); - - /* Set PCI Clk Req */ - reg = hw->pfnReadFPGARegister(hw->adp, PCIE_CLK_REQ_REG); - reg |= PCI_CLK_REQ_ENABLE; - hw->pfnWriteFPGARegister(hw->adp, PCIE_CLK_REQ_REG, reg); - - return true; -} - -uint32_t link_GetPicInfoLineNum(crystalhd_dio_req *dio, uint8_t *base) -{ - uint32_t PicInfoLineNum = 0; - - if (dio->uinfo.b422mode == MODE422_YUY2) { - PicInfoLineNum = ((uint32_t)(*(base + 6)) & 0xff) - | (((uint32_t)(*(base + 4)) << 8) & 0x0000ff00) - | (((uint32_t)(*(base + 2)) << 16) & 0x00ff0000) - | (((uint32_t)(*(base + 0)) << 24) & 0xff000000); - } else if (dio->uinfo.b422mode == MODE422_UYVY) { - PicInfoLineNum = ((uint32_t)(*(base + 7)) & 0xff) - | (((uint32_t)(*(base + 5)) << 8) & 0x0000ff00) - | (((uint32_t)(*(base + 3)) << 16) & 0x00ff0000) - | (((uint32_t)(*(base + 1)) << 24) & 0xff000000); - } else { - PicInfoLineNum = ((uint32_t)(*(base + 3)) & 0xff) - | (((uint32_t)(*(base + 2)) << 8) & 0x0000ff00) - | (((uint32_t)(*(base + 1)) << 16) & 0x00ff0000) - | (((uint32_t)(*(base + 0)) << 24) & 0xff000000); - } - - return PicInfoLineNum; -} - -uint32_t link_GetMode422Data(crystalhd_dio_req *dio, - PBC_PIC_INFO_BLOCK pPicInfoLine, int type) -{ - int i; - uint32_t offset = 0, val = 0; - uint8_t *tmp; - tmp = (uint8_t *)&val; - - if (type == 1) - offset = OFFSETOF(BC_PIC_INFO_BLOCK, picture_meta_payload); - else if (type == 2) - offset = OFFSETOF(BC_PIC_INFO_BLOCK, height); - else - offset = 0; - - if (dio->uinfo.b422mode == MODE422_YUY2) { - for (i = 0; i < 4; i++) - ((uint8_t*)tmp)[i] = - ((uint8_t*)pPicInfoLine)[(offset + i) * 2]; - } else if (dio->uinfo.b422mode == MODE422_UYVY) { - for (i = 0; i < 4; i++) - ((uint8_t*)tmp)[i] = - ((uint8_t*)pPicInfoLine)[(offset + i) * 2 + 1]; - } - - return val; -} - -uint32_t link_GetMetaDataFromPib(crystalhd_dio_req *dio, - PBC_PIC_INFO_BLOCK pPicInfoLine) -{ - uint32_t picture_meta_payload = 0; - - if (dio->uinfo.b422mode) - picture_meta_payload = link_GetMode422Data(dio, pPicInfoLine, 1); - else - picture_meta_payload = pPicInfoLine->picture_meta_payload; - - return BC_SWAP32(picture_meta_payload); -} - -uint32_t link_GetHeightFromPib(crystalhd_dio_req *dio, - PBC_PIC_INFO_BLOCK pPicInfoLine) -{ - uint32_t height = 0; - - if (dio->uinfo.b422mode) - height = link_GetMode422Data(dio, pPicInfoLine, 2); - else - height = pPicInfoLine->height; - - return BC_SWAP32(height); -} - -/* This function cannot be called from ISR context since it uses APIs that can sleep */ -bool link_GetPictureInfo(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, crystalhd_dio_req *dio, - uint32_t *PicNumber, uint64_t *PicMetaData) -{ - uint32_t PicInfoLineNum = 0, HeightInPib = 0, offset = 0, size = 0; - PBC_PIC_INFO_BLOCK pPicInfoLine = NULL; - uint32_t pic_number = 0; - uint8_t *tmp = (uint8_t *)&pic_number; - int i; - unsigned long res = 0; - - dev_dbg(&hw->adp->pdev->dev, "getting Picture Info\n"); - - *PicNumber = 0; - *PicMetaData = 0; - - if (!dio || !picWidth) - goto getpictureinfo_err_nosem; - -// if(down_interruptible(&hw->fetch_sem)) -// goto getpictureinfo_err_nosem; - - dio->pib_va = kmalloc(2 * sizeof(BC_PIC_INFO_BLOCK) + 16, GFP_KERNEL); // since copy_from_user can sleep anyway - if(dio->pib_va == NULL) - goto getpictureinfo_err; - - res = copy_from_user(dio->pib_va, (void *)dio->uinfo.xfr_buff, 8); - if (res != 0) - goto getpictureinfo_err; - - /* - * -- Ajitabh[01-16-2009]: Strictly check against done size. - * -- we have seen that the done size sometimes comes less without - * -- any error indicated to the driver. So we change the limit - * -- to check against the done size rather than the full buffer size - * -- this way we will always make sure that the PIB is recieved by - * -- the driver. - */ - /* Limit = Base + pRxDMAReq->RxYDMADesc.RxBuffSz; */ - /* Limit = Base + (pRxDMAReq->RxYDoneSzInDword * 4); */ -// Limit = dio->uinfo.xfr_buff + dio->uinfo.xfr_len; - - PicInfoLineNum = link_GetPicInfoLineNum(dio, dio->pib_va); - if (PicInfoLineNum > 1092) { - dev_dbg(&hw->adp->pdev->dev, "Invalid Line Number[%x]\n", (int)PicInfoLineNum); - goto getpictureinfo_err; - } - - /* - * -- Ajitabh[01-16-2009]: Added the check for validating the - * -- PicInfoLine Number. This function is only called for link so we - * -- do not have to check for height+1 or (Height+1)/2 as we are doing - * -- in DIL. In DIL we need that because for flea firmware is padding - * -- the data to make it 16 byte aligned. This Validates the reception - * -- of PIB itself. - */ - if (picHeight) { - if ((PicInfoLineNum != picHeight) && - (PicInfoLineNum != picHeight/2)) { - dev_dbg(&hw->adp->pdev->dev, "PicInfoLineNum[%d] != PICHeight " - "Or PICHeight/2 [%d]\n", - (int)PicInfoLineNum, picHeight); - goto getpictureinfo_err; - } - } - - /* calc pic info line offset */ - if (dio->uinfo.b422mode) { - size = 2 * sizeof(BC_PIC_INFO_BLOCK); - offset = (PicInfoLineNum * picWidth * 2) + 8; - } else { - size = sizeof(BC_PIC_INFO_BLOCK); - offset = (PicInfoLineNum * picWidth) + 4; - } - - res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), size); - if (res != 0) - goto getpictureinfo_err; - pPicInfoLine = (PBC_PIC_INFO_BLOCK)(dio->pib_va); - -// if (((uint8_t *)pPicInfoLine < Base) || -// ((uint8_t *)pPicInfoLine > Limit)) { -// dev_err(dev, "Base Limit Check Failed for Extracting " -// "the PIB\n"); -// goto getpictureinfo_err; -// } - - /* - * -- Ajitabh[01-16-2009]: - * We have seen that the data gets shifted for some repeated frames. - * To detect those we use PicInfoLineNum and compare it with height. - */ - - HeightInPib = link_GetHeightFromPib(dio, pPicInfoLine); - if ((PicInfoLineNum != HeightInPib) && - (PicInfoLineNum != HeightInPib / 2)) { - printk("Height Match Failed: HeightInPIB[%d] " - "PicInfoLineNum[%d]\n", - (int)HeightInPib, (int)PicInfoLineNum); - goto getpictureinfo_err; - } - - /* get pic meta data from pib */ - *PicMetaData = link_GetMetaDataFromPib(dio, pPicInfoLine); - /* get pic number from pib */ - /* calc pic info line offset */ - if (dio->uinfo.b422mode) - offset = (PicInfoLineNum * picWidth * 2); - else - offset = (PicInfoLineNum * picWidth); - - res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), 12); - if (res != 0) - goto getpictureinfo_err; - - if (dio->uinfo.b422mode == MODE422_YUY2) { - for (i = 0; i < 4; i++) - ((uint8_t *)tmp)[i] = ((uint8_t *)dio->pib_va)[i * 2]; - } else if (dio->uinfo.b422mode == MODE422_UYVY) { - for (i = 0; i < 4; i++) - ((uint8_t *)tmp)[i] = ((uint8_t *)dio->pib_va)[(i * 2) + 1]; - } else - pic_number = *(uint32_t *)(dio->pib_va); - - *PicNumber = BC_SWAP32(pic_number); - - if(dio->pib_va) - kfree(dio->pib_va); - -// up(&hw->fetch_sem); - - return true; - -getpictureinfo_err: -// up(&hw->fetch_sem); - -getpictureinfo_err_nosem: - if(dio->pib_va) - kfree(dio->pib_va); - *PicNumber = 0; - *PicMetaData = 0; - - return false; -} - -uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void* pRxDMAReq) -{ - uint32_t PicNumber = 0, result = 0; - uint64_t PicMetaData = 0; - - if(link_GetPictureInfo(hw, picHeight, picWidth, ((crystalhd_rx_dma_pkt *)pRxDMAReq)->dio_req, - &PicNumber, &PicMetaData)) - result = PicNumber; - - return result; -} - -/* -* This function gets the next picture metadata payload -* from the decoded picture in ReadyQ (if there was any) -* and returns it. THIS IS ONLY USED FOR LINK. -*/ -bool crystalhd_link_peek_next_decoded_frame(struct crystalhd_hw *hw, - uint64_t *meta_payload, uint32_t *picNumFlags, - uint32_t PicWidth) -{ - uint32_t PicNumber = 0; - unsigned long flags = 0; - crystalhd_dioq_t *ioq; - crystalhd_elem_t *tmp; - crystalhd_rx_dma_pkt *rpkt; - - *meta_payload = 0; - - ioq = hw->rx_rdyq; - spin_lock_irqsave(&ioq->lock, flags); - - if ((ioq->count > 0) && (ioq->head != (crystalhd_elem_t *)&ioq->head)) { - tmp = ioq->head; - spin_unlock_irqrestore(&ioq->lock, flags); - rpkt = (crystalhd_rx_dma_pkt *)tmp->data; - if (rpkt) { - // We are in process context here and have to check if we have repeated pictures - // Drop repeated pictures or garbabge pictures here - // This is because if we advertize a valid picture here, but later drop it - // It will cause single threaded applications to hang, or errors in applications that expect - // pictures not to be dropped once we have advertized their availability - - // If format change packet, then return with out checking anything - if (!(rpkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE))) { - link_GetPictureInfo(hw, hw->PICHeight, hw->PICWidth, rpkt->dio_req, - &PicNumber, meta_payload); - if(!PicNumber || (PicNumber == hw->LastPicNo) || (PicNumber == hw->LastTwoPicNo)) { - // discard picture - if(PicNumber != 0) { - hw->LastTwoPicNo = hw->LastPicNo; - hw->LastPicNo = PicNumber; - } - rpkt = crystalhd_dioq_fetch(hw->rx_rdyq); - if (rpkt) { - crystalhd_dioq_add(hw->rx_freeq, rpkt, false, rpkt->pkt_tag); - rpkt = NULL; - } - *meta_payload = 0; - } - return true; - // Do not update the picture numbers here since they will be updated on the actual fetch of a valid picture - } - else - return false; // don't use the meta_payload information - } - else - return false; - } - spin_unlock_irqrestore(&ioq->lock, flags); - - return false; -} - -bool crystalhd_link_check_input_full(struct crystalhd_hw *hw, - uint32_t needed_sz, uint32_t *empty_sz, - bool b_188_byte_pkts, uint8_t *flags) -{ - uint32_t base, end, writep, readp; - uint32_t cpbSize, cpbFullness, fifoSize; - - if (*flags & 0x02) { /* ASF Bit is set */ - base = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Base); - end = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2End); - writep = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Wrptr); - readp = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Rdptr); - } else if (b_188_byte_pkts) { /*Encrypted 188 byte packets*/ - base = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Base); - end = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0End); - writep = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Wrptr); - readp = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Rdptr); - } else { - base = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinBase); - end = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinEnd); - writep = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinWrPtr); - readp = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinRdPtr); - } - - cpbSize = end - base; - if (writep >= readp) - cpbFullness = writep - readp; - else - cpbFullness = (end - base) - (readp - writep); - - fifoSize = cpbSize - cpbFullness; - - - if (fifoSize < BC_INFIFO_THRESHOLD) - { - *empty_sz = 0; - return true; - } - - if (needed_sz > (fifoSize - BC_INFIFO_THRESHOLD)) - { - *empty_sz = 0; - return true; - } - *empty_sz = fifoSize - BC_INFIFO_THRESHOLD; - - return false; -} - -bool crystalhd_link_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) -{ - uint32_t err_mask, tmp; - - err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; - - if (!(err_sts & err_mask)) - return false; - - dev_err(&hw->adp->pdev->dev, "Error on Tx-L0 %x\n", err_sts); - - tmp = err_mask; - - if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) - tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; - - if (tmp) { - /* reset list index.*/ - hw->tx_list_post_index = 0; - } - - tmp = err_sts & err_mask; - hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); - - return true; -} - -bool crystalhd_link_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) -{ - uint32_t err_mask, tmp; - - err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | - MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; - - if (!(err_sts & err_mask)) - return false; - - dev_err(&hw->adp->pdev->dev, "Error on Tx-L1 %x\n", err_sts); - - tmp = err_mask; - - if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) - tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; - - if (tmp) { - /* reset list index.*/ - hw->tx_list_post_index = 0; - } - - tmp = err_sts & err_mask; - hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); - - return true; -} - -void crystalhd_link_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts) -{ - uint32_t err_sts; - - if (int_sts & INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, - BC_STS_SUCCESS); - - if (int_sts & INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, - BC_STS_SUCCESS); - - if (!(int_sts & (INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK | - INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK))) - /* No error mask set.. */ - return; - - /* Handle Tx errors. */ - err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS); - - if (crystalhd_link_tx_list0_handler(hw, err_sts)) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, - BC_STS_ERROR); - - if (crystalhd_link_tx_list1_handler(hw, err_sts)) - crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, - BC_STS_ERROR); - - hw->stats.tx_errors++; -} - -void crystalhd_link_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr) -{ - uint32_t dma_cntrl; - uint32_t first_desc_u_addr, first_desc_l_addr; - - if (list_id == 0) { - first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST0; - first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST0; - } else { - first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST1; - first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST1; - } - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp,MISC1_TX_SW_DESC_LIST_CTRL_STS); - if (!(dma_cntrl & DMA_START_BIT)) { - dma_cntrl |= DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - - hw->pfnWriteFPGARegister(hw->adp, first_desc_u_addr, desc_addr.high_part); - - hw->pfnWriteFPGARegister(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); - /* Be sure we set the valid bit ^^^^ */ - return; -} - -/* _CHECK_THIS_ - * - * Verify if the Stop generates a completion interrupt or not. - * if it does not generate an interrupt, then add polling here. - */ -BC_STATUS crystalhd_link_stop_tx_dma_engine(struct crystalhd_hw *hw) -{ - struct device *dev; - uint32_t dma_cntrl, cnt = 30; - uint32_t l1 = 1, l2 = 1; - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS); - - dev = &hw->adp->pdev->dev; - - dev_dbg(dev, "Stopping TX DMA Engine..\n"); - - if (!(dma_cntrl & DMA_START_BIT)) { - dev_dbg(dev, "Already Stopped\n"); - return BC_STS_SUCCESS; - } - - crystalhd_link_disable_interrupts(hw); - - /* Issue stop to HW */ - dma_cntrl &= ~DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); - - dev_dbg(dev, "Cleared the DMA Start bit\n"); - - /* Poll for 3seconds (30 * 100ms) on both the lists..*/ - while ((l1 || l2) && cnt) { - - if (l1) { - l1 = hw->pfnReadFPGARegister(hw->adp, - MISC1_TX_FIRST_DESC_L_ADDR_LIST0); - l1 &= DMA_START_BIT; - } - - if (l2) { - l2 = hw->pfnReadFPGARegister(hw->adp, - MISC1_TX_FIRST_DESC_L_ADDR_LIST1); - l2 &= DMA_START_BIT; - } - - msleep_interruptible(100); - - cnt--; - } - - if (!cnt) { - dev_err(dev, "Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); - crystalhd_link_enable_interrupts(hw); - return BC_STS_ERROR; - } - - hw->tx_list_post_index = 0; - dev_dbg(dev, "stopped TX DMA..\n"); - crystalhd_link_enable_interrupts(hw); - - return BC_STS_SUCCESS; -} - -uint32_t crystalhd_link_get_pib_avail_cnt(struct crystalhd_hw *hw) -{ - /* - * Position of the PIB Entries can be found at - * 0th and the 1st location of the Circular list. - */ - uint32_t Q_addr; - uint32_t pib_cnt, r_offset, w_offset; - - Q_addr = hw->pib_del_Q_addr; - - /* Get the Read Pointer */ - crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); - - /* Get the Write Pointer */ - crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); - - if (r_offset == w_offset) - return 0; /* Queue is empty */ - - if (w_offset > r_offset) - pib_cnt = w_offset - r_offset; - else - pib_cnt = (w_offset + MAX_PIB_Q_DEPTH) - - (r_offset + MIN_PIB_Q_DEPTH); - - if (pib_cnt > MAX_PIB_Q_DEPTH) { - dev_err(&hw->adp->pdev->dev, "Invalid PIB Count (%u)\n", pib_cnt); - return 0; - } - - return pib_cnt; -} - -uint32_t crystalhd_link_get_addr_from_pib_Q(struct crystalhd_hw *hw) -{ - uint32_t Q_addr; - uint32_t addr_entry, r_offset, w_offset; - - Q_addr = hw->pib_del_Q_addr; - - /* Get the Read Pointer 0Th Location is Read Pointer */ - crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); - - /* Get the Write Pointer 1st Location is Write pointer */ - crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); - - /* Queue is empty */ - if (r_offset == w_offset) - return 0; - - if ((r_offset < MIN_PIB_Q_DEPTH) || (r_offset >= MAX_PIB_Q_DEPTH)) - return 0; - - /* Get the Actual Address of the PIB */ - crystalhd_link_mem_rd(hw, Q_addr + (r_offset * sizeof(uint32_t)), - 1, &addr_entry); - - /* Increment the Read Pointer */ - r_offset++; - - if (MAX_PIB_Q_DEPTH == r_offset) - r_offset = MIN_PIB_Q_DEPTH; - - /* Write back the read pointer to It's Location */ - crystalhd_link_mem_wr(hw, Q_addr, 1, &r_offset); - - return addr_entry; -} - -bool crystalhd_link_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel) -{ - uint32_t Q_addr; - uint32_t r_offset, w_offset, n_offset; - - Q_addr = hw->pib_rel_Q_addr; - - /* Get the Read Pointer */ - crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); - - /* Get the Write Pointer */ - crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); - - if ((r_offset < MIN_PIB_Q_DEPTH) || - (r_offset >= MAX_PIB_Q_DEPTH)) - return false; - - n_offset = w_offset + 1; - - if (MAX_PIB_Q_DEPTH == n_offset) - n_offset = MIN_PIB_Q_DEPTH; - - if (r_offset == n_offset) - return false; /* should never happen */ - - /* Write the DRAM ADDR to the Queue at Next Offset */ - crystalhd_link_mem_wr(hw, Q_addr + (w_offset * sizeof(uint32_t)), - 1, &addr_to_rel); - - /* Put the New value of the write pointer in Queue */ - crystalhd_link_mem_wr(hw, Q_addr + sizeof(uint32_t), 1, &n_offset); - - return true; -} - -void link_cpy_pib_to_app(C011_PIB *src_pib, BC_PIC_INFO_BLOCK *dst_pib) -{ - if (!src_pib || !dst_pib) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return; - } - - dst_pib->timeStamp = 0; - dst_pib->picture_number = src_pib->ppb.picture_number; - dst_pib->width = src_pib->ppb.width; - dst_pib->height = src_pib->ppb.height; - dst_pib->chroma_format = src_pib->ppb.chroma_format; - dst_pib->pulldown = src_pib->ppb.pulldown; - dst_pib->flags = src_pib->ppb.flags; - dst_pib->sess_num = src_pib->ptsStcOffset; - dst_pib->aspect_ratio = src_pib->ppb.aspect_ratio; - dst_pib->colour_primaries = src_pib->ppb.colour_primaries; - dst_pib->picture_meta_payload = src_pib->ppb.picture_meta_payload; - dst_pib->frame_rate = src_pib->resolution ; - return; -} - -void crystalhd_link_proc_pib(struct crystalhd_hw *hw) -{ - unsigned int cnt; - C011_PIB src_pib; - uint32_t pib_addr, pib_cnt; - BC_PIC_INFO_BLOCK *AppPib; - crystalhd_rx_dma_pkt *rx_pkt = NULL; - - pib_cnt = crystalhd_link_get_pib_avail_cnt(hw); - - if (!pib_cnt) - return; - - for (cnt = 0; cnt < pib_cnt; cnt++) { - pib_addr = crystalhd_link_get_addr_from_pib_Q(hw); - crystalhd_link_mem_rd(hw, pib_addr, sizeof(C011_PIB) / 4, - (uint32_t *)&src_pib); - - if (src_pib.bFormatChange) { - rx_pkt = (crystalhd_rx_dma_pkt *) - crystalhd_dioq_fetch(hw->rx_freeq); - if (!rx_pkt) - return; - - rx_pkt->flags = 0; - rx_pkt->flags |= COMP_FLAG_PIB_VALID | - COMP_FLAG_FMT_CHANGE; - AppPib = &rx_pkt->pib; - link_cpy_pib_to_app(&src_pib, AppPib); - - hw->PICHeight = rx_pkt->pib.height; - if (rx_pkt->pib.width > 1280) - hw->PICWidth = 1920; - else if (rx_pkt->pib.width > 720) - hw->PICWidth = 1280; - else - hw->PICWidth = 720; - - dev_info(&hw->adp->pdev->dev, - "[FMT CH] PIB:%x %x %x %x %x %x %x %x %x %x\n", - rx_pkt->pib.picture_number, - rx_pkt->pib.aspect_ratio, - rx_pkt->pib.chroma_format, - rx_pkt->pib.colour_primaries, - rx_pkt->pib.frame_rate, - rx_pkt->pib.height, - rx_pkt->pib.width, - rx_pkt->pib.n_drop, - rx_pkt->pib.pulldown, - rx_pkt->pib.ycom); - - crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, - true, rx_pkt->pkt_tag); - - } - - crystalhd_link_rel_addr_to_pib_Q(hw, pib_addr); - } -} - -void crystalhd_link_start_rx_dma_engine(struct crystalhd_hw *hw) -{ - uint32_t dma_cntrl; - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); - if (!(dma_cntrl & DMA_START_BIT)) { - dma_cntrl |= DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); - if (!(dma_cntrl & DMA_START_BIT)) { - dma_cntrl |= DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - - return; -} - -void crystalhd_link_stop_rx_dma_engine(struct crystalhd_hw *hw) -{ - struct device *dev = &hw->adp->pdev->dev; - uint32_t dma_cntrl = 0, count = 30; - uint32_t l0y = 1, l0uv = 1, l1y = 1, l1uv = 1; - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); - if ((dma_cntrl & DMA_START_BIT)) { - dma_cntrl &= ~DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); - if ((dma_cntrl & DMA_START_BIT)) { - dma_cntrl &= ~DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - - /* Poll for 3seconds (30 * 100ms) on both the lists..*/ - while ((l0y || l0uv || l1y || l1uv) && count) { - - if (l0y) { - l0y = hw->pfnReadFPGARegister(hw->adp, - MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0); - l0y &= DMA_START_BIT; - if (!l0y) - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - } - - if (l1y) { - l1y = hw->pfnReadFPGARegister(hw->adp, - MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1); - l1y &= DMA_START_BIT; - if (!l1y) - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - } - - if (l0uv) { - l0uv = hw->pfnReadFPGARegister(hw->adp, - MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0); - l0uv &= DMA_START_BIT; - if (!l0uv) - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - } - - if (l1uv) { - l1uv = hw->pfnReadFPGARegister(hw->adp, - MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1); - l1uv &= DMA_START_BIT; - if (!l1uv) - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - } - msleep_interruptible(100); - count--; - } - - hw->rx_list_post_index = 0; - - dev_dbg(dev, "Capture Stop: %d List0:Sts:%x List1:Sts:%x\n", - count, hw->rx_list_sts[0], hw->rx_list_sts[1]); -} - -BC_STATUS crystalhd_link_hw_prog_rxdma(struct crystalhd_hw *hw, - crystalhd_rx_dma_pkt *rx_pkt) -{ - struct device *dev; - uint32_t y_low_addr_reg, y_high_addr_reg; - uint32_t uv_low_addr_reg, uv_high_addr_reg; - addr_64 desc_addr; - unsigned long flags; - - if (!hw || !rx_pkt) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &hw->adp->pdev->dev; - - if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { - dev_err(dev, "List Out Of bounds %x\n", hw->rx_list_post_index); - return BC_STS_INV_ARG; - } - - spin_lock_irqsave(&hw->rx_lock, flags); - if (hw->rx_list_sts[hw->rx_list_post_index]) { - spin_unlock_irqrestore(&hw->rx_lock, flags); - return BC_STS_BUSY; - } - - if (!hw->rx_list_post_index) { - y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0; - y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0; - uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0; - uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0; - } else { - y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1; - y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1; - uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1; - uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1; - } - rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; - hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; - if (rx_pkt->uv_phy_addr) - hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; - hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; - - crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); - - crystalhd_link_start_rx_dma_engine(hw); - /* Program the Y descriptor */ - desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; - hw->pfnWriteFPGARegister(hw->adp, y_high_addr_reg, desc_addr.high_part); - hw->pfnWriteFPGARegister(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01); - - if (rx_pkt->uv_phy_addr) { - /* Program the UV descriptor */ - desc_addr.full_addr = rx_pkt->uv_phy_addr; - hw->pfnWriteFPGARegister(hw->adp, uv_high_addr_reg, desc_addr.high_part); - hw->pfnWriteFPGARegister(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01); - } - - spin_unlock_irqrestore(&hw->rx_lock, flags); - - return BC_STS_SUCCESS; -} - -BC_STATUS crystalhd_link_hw_post_cap_buff(struct crystalhd_hw *hw, - crystalhd_rx_dma_pkt *rx_pkt) -{ - BC_STATUS sts = crystalhd_link_hw_prog_rxdma(hw, rx_pkt); - - if (sts == BC_STS_BUSY) - crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, - false, rx_pkt->pkt_tag); - - return sts; -} - -void crystalhd_link_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, - uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) -{ - uint32_t y_dn_sz_reg, uv_dn_sz_reg; - - if (!list_index) { - y_dn_sz_reg = MISC1_Y_RX_LIST0_CUR_BYTE_CNT; - uv_dn_sz_reg = MISC1_UV_RX_LIST0_CUR_BYTE_CNT; - } else { - y_dn_sz_reg = MISC1_Y_RX_LIST1_CUR_BYTE_CNT; - uv_dn_sz_reg = MISC1_UV_RX_LIST1_CUR_BYTE_CNT; - } - - *y_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, y_dn_sz_reg); - *uv_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, uv_dn_sz_reg); -} - -/* - * This function should be called only after making sure that the two DMA - * lists are free. This function does not check if DMA's are active, before - * turning off the DMA. - */ -void crystalhd_link_hw_finalize_pause(struct crystalhd_hw *hw) -{ - uint32_t dma_cntrl; - - hw->stop_pending = 0; - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); - if (dma_cntrl & DMA_START_BIT) { - dma_cntrl &= ~DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - - dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); - if (dma_cntrl & DMA_START_BIT) { - dma_cntrl &= ~DMA_START_BIT; - hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, - dma_cntrl); - } - hw->rx_list_post_index = 0; - -// aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); -// aspm |= ASPM_L1_ENABLE; -// dev_info(&hw->adp->pdev->dev, "aspm on\n"); -// crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); -} - -bool crystalhd_link_rx_list0_handler(struct crystalhd_hw *hw, - uint32_t int_sts, - uint32_t y_err_sts, - uint32_t uv_err_sts) -{ - uint32_t tmp; - list_sts tmp_lsts; - - if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) - return false; - - tmp_lsts = hw->rx_list_sts[0]; - - /* Y0 - DMA */ - tmp = y_err_sts & GET_Y0_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[0] &= ~rx_waiting_y_intr; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; - } - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { - hw->rx_list_sts[0] &= ~rx_y_mask; - hw->rx_list_sts[0] |= rx_y_error; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[0] &= ~rx_y_mask; - hw->rx_list_sts[0] |= rx_y_error; - hw->rx_list_post_index = 0; - } - - /* UV0 - DMA */ - tmp = uv_err_sts & GET_UV0_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; - } - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { - hw->rx_list_sts[0] &= ~rx_uv_mask; - hw->rx_list_sts[0] |= rx_uv_error; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[0] &= ~rx_uv_mask; - hw->rx_list_sts[0] |= rx_uv_error; - hw->rx_list_post_index = 0; - } - - if (y_err_sts & GET_Y0_ERR_MSK) { - tmp = y_err_sts & GET_Y0_ERR_MSK; - hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); - } - - if (uv_err_sts & GET_UV0_ERR_MSK) { - tmp = uv_err_sts & GET_UV0_ERR_MSK; - hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); - } - - return (tmp_lsts != hw->rx_list_sts[0]); -} - -bool crystalhd_link_rx_list1_handler(struct crystalhd_hw *hw, - uint32_t int_sts, uint32_t y_err_sts, - uint32_t uv_err_sts) -{ - uint32_t tmp; - list_sts tmp_lsts; - - if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) - return false; - - tmp_lsts = hw->rx_list_sts[1]; - - /* Y1 - DMA */ - tmp = y_err_sts & GET_Y1_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[1] &= ~rx_waiting_y_intr; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; - } - - if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { - /* Add retry-support..*/ - hw->rx_list_sts[1] &= ~rx_y_mask; - hw->rx_list_sts[1] |= rx_y_error; - tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[1] &= ~rx_y_mask; - hw->rx_list_sts[1] |= rx_y_error; - hw->rx_list_post_index = 0; - } - - /* UV1 - DMA */ - tmp = uv_err_sts & GET_UV1_ERR_MSK; - if (int_sts & INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK) - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { - hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; - } - - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { - /* Add retry-support*/ - hw->rx_list_sts[1] &= ~rx_uv_mask; - hw->rx_list_sts[1] |= rx_uv_error; - tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; - } - - if (tmp) { - hw->rx_list_sts[1] &= ~rx_uv_mask; - hw->rx_list_sts[1] |= rx_uv_error; - hw->rx_list_post_index = 0; - } - - if (y_err_sts & GET_Y1_ERR_MSK) { - tmp = y_err_sts & GET_Y1_ERR_MSK; - hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); - } - - if (uv_err_sts & GET_UV1_ERR_MSK) { - tmp = uv_err_sts & GET_UV1_ERR_MSK; - hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); - } - - return (tmp_lsts != hw->rx_list_sts[1]); -} - -void crystalhd_link_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts) -{ - unsigned long flags; - uint32_t i, list_avail = 0; - BC_STATUS comp_sts = BC_STS_NO_DATA; - uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; - bool ret = 0; - - if (!hw) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return; - } - - if (!(intr_sts & GET_RX_INTR_MASK)) - return; - - y_err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS); - uv_err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS); - - for (i = 0; i < DMA_ENGINE_CNT; i++) { - /* Update States..*/ - spin_lock_irqsave(&hw->rx_lock, flags); - if (i == 0) - ret = crystalhd_link_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); - else - ret = crystalhd_link_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); - if (ret) { - switch (hw->rx_list_sts[i]) { - case sts_free: - comp_sts = BC_STS_SUCCESS; - list_avail = 1; - hw->stats.rx_success++; - break; - case rx_y_error: - case rx_uv_error: - case rx_sts_error: - /* We got error on both or Y or uv. */ - hw->stats.rx_errors++; - hw->pfnHWGetDoneSize(hw, i, &y_dn_sz, &uv_dn_sz); - dev_info(&hw->adp->pdev->dev, "list_index:%x " - "rx[%d] rxtot[%d] Y:%x UV:%x Int:%x YDnSz:%x " - "UVDnSz:%x\n", i, hw->stats.rx_errors, - hw->stats.rx_errors + hw->stats.rx_success, - y_err_sts, uv_err_sts, intr_sts, - y_dn_sz, uv_dn_sz); - hw->rx_list_sts[i] = sts_free; - comp_sts = BC_STS_ERROR; - break; - default: - /* Wait for completion..*/ - comp_sts = BC_STS_NO_DATA; - break; - } - } - spin_unlock_irqrestore(&hw->rx_lock, flags); - - /* handle completion...*/ - if (comp_sts != BC_STS_NO_DATA) { - crystalhd_rx_pkt_done(hw, i, comp_sts); - comp_sts = BC_STS_NO_DATA; - } - } - - if (list_avail) { - if (hw->stop_pending) { - if ((hw->rx_list_sts[0] == sts_free) && - (hw->rx_list_sts[1] == sts_free)) - crystalhd_link_hw_finalize_pause(hw); - } else { - if(!hw->hw_pause_issued) - crystalhd_hw_start_capture(hw); - } - } -} - -BC_STATUS crystalhd_link_hw_pause(struct crystalhd_hw *hw, bool state) -{ - uint32_t pause = 0; - BC_STATUS sts = BC_STS_SUCCESS; - - if(state) { - pause = 1; - hw->stats.pause_cnt++; - hw->stop_pending = 1; - hw->pfnWriteDevRegister(hw->adp, HW_PauseMbx, pause); - - if ((hw->rx_list_sts[0] == sts_free) && - (hw->rx_list_sts[1] == sts_free)) - crystalhd_link_hw_finalize_pause(hw); - } else { - pause = 0; - hw->stop_pending = 0; - sts = crystalhd_hw_start_capture(hw); - hw->pfnWriteDevRegister(hw->adp, HW_PauseMbx, pause); - } - return sts; -} - -BC_STATUS crystalhd_link_fw_cmd_post_proc(struct crystalhd_hw *hw, - BC_FW_CMD *fw_cmd) -{ - BC_STATUS sts = BC_STS_SUCCESS; - DecRspChannelStartVideo *st_rsp = NULL; - - switch (fw_cmd->cmd[0]) { - case eCMD_C011_DEC_CHAN_START_VIDEO: - st_rsp = (DecRspChannelStartVideo *)fw_cmd->rsp; - hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; - hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; - dev_dbg(&hw->adp->pdev->dev, "DelQAddr:%x RelQAddr:%x\n", - hw->pib_del_Q_addr, hw->pib_rel_Q_addr); - break; - case eCMD_C011_INIT: - if (!(crystalhd_link_load_firmware_config(hw))) { - dev_err(&hw->adp->pdev->dev, "Invalid Params\n"); - sts = BC_STS_FW_AUTH_FAILED; - } - break; - default: - break; - } - return sts; -} - -BC_STATUS crystalhd_link_put_ddr2sleep(struct crystalhd_hw *hw) -{ - uint32_t reg; - link_misc_perst_decoder_ctrl rst_cntrl_reg; - - /* Pulse reset pin of 7412 (MISC_PERST_DECODER_CTRL) */ - rst_cntrl_reg.whole_reg = hw->pfnReadDevRegister(hw->adp, MISC_PERST_DECODER_CTRL); - - rst_cntrl_reg.bcm_7412_rst = 1; - hw->pfnWriteDevRegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); - msleep_interruptible(50); - - rst_cntrl_reg.bcm_7412_rst = 0; - hw->pfnWriteDevRegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); - - /* Close all banks, put DDR in idle */ - hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); - - /* Set bit 25 (drop CKE pin of DDR) */ - reg = hw->pfnReadDevRegister(hw->adp, SDRAM_PARAM); - reg |= 0x02000000; - hw->pfnWriteDevRegister(hw->adp, SDRAM_PARAM, reg); - - /* Reset the audio block */ - hw->pfnWriteDevRegister(hw->adp, AUD_DSP_MISC_SOFT_RESET, 0x1); - - /* Power down Raptor PLL */ - reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllCCtl); - reg |= 0x00008000; - hw->pfnWriteDevRegister(hw->adp, DecHt_PllCCtl, reg); - - /* Power down all Audio PLL */ - hw->pfnWriteDevRegister(hw->adp, AIO_MISC_PLL_RESET, 0x1); - - /* Power down video clock (75MHz) */ - reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllECtl); - reg |= 0x00008000; - hw->pfnWriteDevRegister(hw->adp, DecHt_PllECtl, reg); - - /* Power down video clock (75MHz) */ - reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllDCtl); - reg |= 0x00008000; - hw->pfnWriteDevRegister(hw->adp, DecHt_PllDCtl, reg); - - /* Power down core clock (200MHz) */ - reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllACtl); - reg |= 0x00008000; - hw->pfnWriteDevRegister(hw->adp, DecHt_PllACtl, reg); - - /* Power down core clock (200MHz) */ - reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllBCtl); - reg |= 0x00008000; - hw->pfnWriteDevRegister(hw->adp, DecHt_PllBCtl, reg); - - return BC_STS_SUCCESS; -} - -/************************************************ -** -*************************************************/ - -BC_STATUS crystalhd_link_download_fw(struct crystalhd_hw *hw, - uint8_t *buffer, uint32_t sz) -{ - struct device *dev; - uint32_t reg_data, cnt, *temp_buff; - uint32_t fw_sig_len = 36; - uint32_t dram_offset = BC_FWIMG_ST_ADDR, sig_reg; - - if (!hw || !buffer || !sz) { - printk(KERN_ERR "%s: Invalid Params\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &hw->adp->pdev->dev; - - dev_dbg(dev, "%s entered\n", __func__); - - reg_data = hw->pfnReadFPGARegister(hw->adp, OTP_CMD); - if (!(reg_data & 0x02)) { - dev_err(dev, "Invalid hw config.. otp not programmed\n"); - return BC_STS_ERROR; - } - - reg_data = 0; - hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, 0); - reg_data |= BC_BIT(0); - hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); - - reg_data = 0; - cnt = 1000; - msleep_interruptible(10); - - while (reg_data != BC_BIT(4)) { - reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); - reg_data &= BC_BIT(4); - if (--cnt == 0) { - dev_err(dev, "Firmware Download RDY Timeout.\n"); - return BC_STS_TIMEOUT; - } - } - - msleep_interruptible(10); - /* Load the FW to the FW_ADDR field in the DCI_FIRMWARE_ADDR */ - hw->pfnWriteFPGARegister(hw->adp, DCI_FIRMWARE_ADDR, dram_offset); - temp_buff = (uint32_t *)buffer; - for (cnt = 0; cnt < (sz - fw_sig_len); cnt += 4) { - hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (dram_offset >> 19)); - hw->pfnWriteFPGARegister(hw->adp, DCI_FIRMWARE_DATA, *temp_buff); - dram_offset += 4; - temp_buff++; - } - msleep_interruptible(10); - - temp_buff++; - - sig_reg = (uint32_t)DCI_SIGNATURE_DATA_7; - for (cnt = 0; cnt < 8; cnt++) { - uint32_t swapped_data = *temp_buff; - swapped_data = bswap_32_1(swapped_data); - hw->pfnWriteFPGARegister(hw->adp, sig_reg, swapped_data); - sig_reg -= 4; - temp_buff++; - } - msleep_interruptible(10); - - reg_data = 0; - reg_data |= BC_BIT(1); - hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); - msleep_interruptible(10); - - reg_data = 0; - reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); - - if ((reg_data & BC_BIT(9)) == BC_BIT(9)) { - cnt = 1000; - while ((reg_data & BC_BIT(0)) != BC_BIT(0)) { - reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); - reg_data &= BC_BIT(0); - if (!(--cnt)) - break; - msleep_interruptible(10); - } - reg_data = 0; - reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_CMD); - reg_data |= BC_BIT(4); - hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); - - } else { - dev_err(dev, "F/w Signature mismatch\n"); - return BC_STS_FW_AUTH_FAILED; - } - - dev_dbg(dev, "Firmware Downloaded Successfully\n"); - - // Load command response addresses - hw->fwcmdPostAddr = TS_Host2CpuSnd; - hw->fwcmdPostMbox = Hst2CpuMbx1; - hw->fwcmdRespMbox = Cpu2HstMbx1; - - return BC_STS_SUCCESS;; -} - -BC_STATUS crystalhd_link_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) -{ - struct device *dev; - uint32_t cnt = 0, cmd_res_addr; - uint32_t *cmd_buff, *res_buff; - wait_queue_head_t fw_cmd_event; - int rc = 0; - BC_STATUS sts; - unsigned long flags; - - crystalhd_create_event(&fw_cmd_event); - - if (!hw || !fw_cmd) { - printk(KERN_ERR "%s: Invalid Arguments\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &hw->adp->pdev->dev; - - dev_dbg(dev, "%s entered\n", __func__); - - cmd_buff = fw_cmd->cmd; - res_buff = fw_cmd->rsp; - - if (!cmd_buff || !res_buff) { - dev_err(dev, "Invalid Parameters for F/W Command\n"); - return BC_STS_INV_ARG; - } - - hw->fwcmd_evt_sts = 0; - hw->pfw_cmd_event = &fw_cmd_event; - - spin_lock_irqsave(&hw->lock, flags); - - /*Write the command to the memory*/ - hw->pfnDevDRAMWrite(hw, hw->fwcmdPostAddr, FW_CMD_BUFF_SZ, cmd_buff); - - /*Memory Read for memory arbitrator flush*/ - hw->pfnDevDRAMRead(hw, hw->fwcmdPostAddr, 1, &cnt); - - /* Write the command address to mailbox */ - hw->pfnWriteDevRegister(hw->adp, hw->fwcmdPostMbox, hw->fwcmdPostAddr); - - spin_unlock_irqrestore(&hw->lock, flags); - - msleep_interruptible(50); - - // FW commands should complete even if we got a signal from the upper layer - crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, - 20000, rc, true); - - if (!rc) { - sts = BC_STS_SUCCESS; - } else if (rc == -EBUSY) { - dev_err(dev, "Firmware command T/O\n"); - sts = BC_STS_TIMEOUT; - } else if (rc == -EINTR) { - dev_err(dev, "FwCmd Wait Signal int - Should never happen\n"); - sts = BC_STS_IO_USER_ABORT; - } else { - dev_err(dev, "FwCmd IO Error.\n"); - sts = BC_STS_IO_ERROR; - } - - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "FwCmd Failed.\n"); - return sts; - } - - spin_lock_irqsave(&hw->lock, flags); - - /*Get the Responce Address*/ - cmd_res_addr = hw->pfnReadDevRegister(hw->adp, hw->fwcmdRespMbox); - - /*Read the Response*/ - hw->pfnDevDRAMRead(hw, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); - - spin_unlock_irqrestore(&hw->lock, flags); - - if (res_buff[2] != C011_RET_SUCCESS) { - dev_err(dev, "res_buff[2] != C011_RET_SUCCESS\n"); - return BC_STS_FW_CMD_ERR; - } - - sts = crystalhd_link_fw_cmd_post_proc(hw, fw_cmd); - if (sts != BC_STS_SUCCESS) - dev_err(dev, "crystalhd_fw_cmd_post_proc Failed.\n"); - - return sts; -} - -bool crystalhd_link_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw) -{ - uint32_t intr_sts = 0; - uint32_t deco_intr = 0; - bool rc = false; - - if (!adp || !hw->dev_started) - return rc; - - hw->stats.num_interrupts++; - - deco_intr = hw->pfnReadDevRegister(hw->adp, Stream2Host_Intr_Sts); - intr_sts = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_STATUS); - - if (intr_sts) { - /* let system know we processed interrupt..*/ - rc = true; - hw->stats.dev_interrupts++; - } - - if (deco_intr && (deco_intr != 0xdeaddead)) { - - if (deco_intr & 0x80000000) { - /*Set the Event and the status flag*/ - if (hw->pfw_cmd_event) { - hw->fwcmd_evt_sts = 1; - crystalhd_set_event(hw->pfw_cmd_event); - } - } - - if (deco_intr & BC_BIT(1)) - crystalhd_link_proc_pib(hw); - - hw->pfnWriteDevRegister(hw->adp, Stream2Host_Intr_Sts, deco_intr); - hw->pfnWriteDevRegister(hw->adp, Stream2Host_Intr_Sts, 0); - rc = 1; - } - - /* Rx interrupts */ - crystalhd_link_rx_isr(hw, intr_sts); - - /* Tx interrupts*/ - crystalhd_link_tx_isr(hw, intr_sts); - - /* Clear interrupts */ - if (rc) { - if (intr_sts) - hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_CLR_REG, intr_sts); - - hw->pfnWriteFPGARegister(hw->adp, INTR_EOI_CTRL, 1); - } - - return rc; -} - -// Dummy private function -void crystalhd_link_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext) -{ - return; -} - -bool crystalhd_link_notify_event(struct crystalhd_hw *hw, BRCM_EVENT EventCode) -{ - return true; -} diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_linkfuncs.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_linkfuncs.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_linkfuncs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_linkfuncs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,228 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_linkfuncs . h - * - * Description: - * BCM70012 Linux driver hardware layer. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#ifndef _CRYSTALHD_LINKFUNCS_H_ -#define _CRYSTALHD_LINKFUNCS_H_ - -#define ASPM_L1_ENABLE (BC_BIT(27)) - -/************************************************* - 7412 Decoder Registers. -**************************************************/ -#define FW_CMD_BUFF_SZ 64 -#define TS_Host2CpuSnd 0x00000100 -#define HW_PauseMbx 0x00000300 -#define Hst2CpuMbx1 0x00100F00 -#define Cpu2HstMbx1 0x00100F04 -#define MbxStat1 0x00100F08 -#define Stream2Host_Intr_Sts 0x00100F24 -#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ - -/* TS input status register */ -#define TS_StreamAFIFOStatus 0x0010044C -#define TS_StreamBFIFOStatus 0x0010084C - -/*UART Selection definitions*/ -#define UartSelectA 0x00100300 -#define UartSelectB 0x00100304 - -#define BSVS_UART_DEC_NONE 0x00 -#define BSVS_UART_DEC_OUTER 0x01 -#define BSVS_UART_DEC_INNER 0x02 -#define BSVS_UART_STREAM 0x03 - -/* Code-In fifo */ -#define REG_DecCA_RegCinCTL 0xa00 -#define REG_DecCA_RegCinBase 0xa0c -#define REG_DecCA_RegCinEnd 0xa10 -#define REG_DecCA_RegCinWrPtr 0xa04 -#define REG_DecCA_RegCinRdPtr 0xa08 - -#define REG_Dec_TsUser0Base 0x100864 -#define REG_Dec_TsUser0Rdptr 0x100868 -#define REG_Dec_TsUser0Wrptr 0x10086C -#define REG_Dec_TsUser0End 0x100874 - -/* ASF Case ...*/ -#define REG_Dec_TsAudCDB2Base 0x10036c -#define REG_Dec_TsAudCDB2Rdptr 0x100378 -#define REG_Dec_TsAudCDB2Wrptr 0x100374 -#define REG_Dec_TsAudCDB2End 0x100370 - -/* DRAM bringup Registers */ -#define SDRAM_PARAM 0x00040804 -#define SDRAM_PRECHARGE 0x000408B0 -#define SDRAM_EXT_MODE 0x000408A4 -#define SDRAM_MODE 0x000408A0 -#define SDRAM_REFRESH 0x00040890 -#define SDRAM_REF_PARAM 0x00040808 - -#define DecHt_PllACtl 0x34000C -#define DecHt_PllBCtl 0x340010 -#define DecHt_PllCCtl 0x340014 -#define DecHt_PllDCtl 0x340034 -#define DecHt_PllECtl 0x340038 -#define AUD_DSP_MISC_SOFT_RESET 0x00240104 -#define AIO_MISC_PLL_RESET 0x0026000C -#define PCIE_CLK_REQ_REG 0xDC -#define PCI_CLK_REQ_ENABLE (BC_BIT(8)) - -/************************************************* - F/W Copy engine definitions.. -**************************************************/ -#define BC_FWIMG_ST_ADDR 0x00000000 - -#define DecHt_HostSwReset 0x340000 -#define BC_DRAM_FW_CFG_ADDR 0x001c2000 - -typedef union _link_intr_mask_reg_ { - struct { - uint32_t mask_tx_done:1; - uint32_t mask_tx_err:1; - uint32_t mask_rx_done:1; - uint32_t mask_rx_err:1; - uint32_t mask_pcie_err:1; - uint32_t mask_pcie_rbusmast_err:1; - uint32_t mask_pcie_rgr_bridge:1; - uint32_t reserved:25; - }; - - uint32_t whole_reg; - -} intr_mask_reg; - -typedef union _link_misc_perst_deco_ctrl_ { - struct { - uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ - uint32_t reserved0:3; /* Reserved.No Effect*/ - uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ - uint32_t reserved1:27; /* Reseved. No Effect*/ - }; - - uint32_t whole_reg; - -} link_misc_perst_deco_ctrl; - -typedef union _link_misc_perst_clk_ctrl_ { - struct { - uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */ - uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */ - uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set - to select an alternate clock before setting this bit.*/ - uint32_t reserved0:5; /* Reserved */ - uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */ - uint32_t pll_div:4; /* This setting controls the divider for the PLL. */ - uint32_t reserved1:12; /* Reserved */ - }; - - uint32_t whole_reg; - -} link_misc_perst_clk_ctrl; - - -typedef union _link_misc_perst_decoder_ctrl_ { - struct { - uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ - uint32_t res0:3; /* Reserved.No Effect*/ - uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ - uint32_t res1:27; /* Reseved. No Effect */ - }; - - uint32_t whole_reg; - -} link_misc_perst_decoder_ctrl; - -/* DMA engine register BIT mask wrappers.. */ -#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK - -#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) - -uint32_t link_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); -void link_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); -uint32_t crystalhd_link_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); -void crystalhd_link_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); -uint32_t crystalhd_link_dram_rd(struct crystalhd_hw *hw, uint32_t mem_off); -void crystalhd_link_dram_wr(struct crystalhd_hw *hw, uint32_t mem_off, uint32_t val); -BC_STATUS crystalhd_link_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff); -BC_STATUS crystalhd_link_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff); -void crystalhd_link_enable_uarts(struct crystalhd_hw *hw); -void crystalhd_link_start_dram(struct crystalhd_hw *hw); -bool crystalhd_link_bring_out_of_rst(struct crystalhd_hw *hw); -bool crystalhd_link_put_in_reset(struct crystalhd_hw *hw); -void crystalhd_link_disable_interrupts(struct crystalhd_hw *hw); -void crystalhd_link_enable_interrupts(struct crystalhd_hw *hw); -void crystalhd_link_clear_errors(struct crystalhd_hw *hw); -void crystalhd_link_clear_interrupts(struct crystalhd_hw *hw); -void crystalhd_link_soft_rst(struct crystalhd_hw *hw); -bool crystalhd_link_load_firmware_config(struct crystalhd_hw *hw); -bool crystalhd_link_start_device(struct crystalhd_hw *hw); -bool crystalhd_link_stop_device(struct crystalhd_hw *hw); -uint32_t link_GetPicInfoLineNum(crystalhd_dio_req *dio, uint8_t *base); -uint32_t link_GetMode422Data(crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine, int type); -uint32_t link_GetMetaDataFromPib(crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine); -uint32_t link_GetHeightFromPib(crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine); -bool link_GetPictureInfo(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, crystalhd_dio_req *dio, - uint32_t *PicNumber, uint64_t *PicMetaData); -uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void *pRxDMAReq); -bool crystalhd_link_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth); -bool crystalhd_link_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, - bool b_188_byte_pkts, uint8_t *flags); -bool crystalhd_link_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts); -bool crystalhd_link_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts); -void crystalhd_link_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts); -void crystalhd_link_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr); -BC_STATUS crystalhd_link_stop_tx_dma_engine(struct crystalhd_hw *hw); -uint32_t crystalhd_link_get_pib_avail_cnt(struct crystalhd_hw *hw); -uint32_t crystalhd_link_get_addr_from_pib_Q(struct crystalhd_hw *hw); -bool crystalhd_link_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel); -void link_cpy_pib_to_app(C011_PIB *src_pib, BC_PIC_INFO_BLOCK *dst_pib); -void crystalhd_link_proc_pib(struct crystalhd_hw *hw); -void crystalhd_link_start_rx_dma_engine(struct crystalhd_hw *hw); -void crystalhd_link_stop_rx_dma_engine(struct crystalhd_hw *hw); -BC_STATUS crystalhd_link_hw_prog_rxdma(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt *rx_pkt); -BC_STATUS crystalhd_link_hw_post_cap_buff(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt *rx_pkt); -void crystalhd_link_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, - uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz); -void crystalhd_link_hw_finalize_pause(struct crystalhd_hw *hw); -bool crystalhd_link_rx_list0_handler(struct crystalhd_hw *hw,uint32_t int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); -bool crystalhd_link_rx_list1_handler(struct crystalhd_hw *hw,uint32_t int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); -void crystalhd_link_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts); -BC_STATUS crystalhd_link_hw_pause(struct crystalhd_hw *hw, bool state); -BC_STATUS crystalhd_link_fw_cmd_post_proc(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); -BC_STATUS crystalhd_link_put_ddr2sleep(struct crystalhd_hw *hw); -BC_STATUS crystalhd_link_download_fw(struct crystalhd_hw* hw, uint8_t* buffer, uint32_t sz); -BC_STATUS crystalhd_link_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); -bool crystalhd_link_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw); -void crystalhd_link_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext); -bool crystalhd_link_notify_event(struct crystalhd_hw *hw, BRCM_EVENT EventCode); -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_lnx.c crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_lnx.c --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_lnx.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_lnx.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,788 +0,0 @@ -/*************************************************************************** - BCM70010 Linux driver - Copyright (c) 2005-2009, Broadcom Corporation. - - This driver is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, version 2 of the License. - - This driver is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this driver. If not, see . -***************************************************************************/ - -#include - -#include "crystalhd_lnx.h" - -static struct class *crystalhd_class; - -static struct crystalhd_adp *g_adp_info; - -struct device *chddev(void) -{ - return &g_adp_info->pdev->dev; -} - -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18) -static irqreturn_t chd_dec_isr(int irq, void *arg) -#else -static irqreturn_t chd_dec_isr(int irq, void *arg, struct pt_regs *r) -#endif -{ - struct crystalhd_adp *adp = (struct crystalhd_adp *) arg; - int rc = 0; - if (adp) - rc = crystalhd_cmd_interrupt(&adp->cmds); - - return IRQ_RETVAL(rc); -} - -static int chd_dec_enable_int(struct crystalhd_adp *adp) -{ - int rc = 0; - - if (!adp || !adp->pdev) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return -EINVAL; - } - - rc = pci_enable_msi(adp->pdev); - if(rc != 0) - dev_err(&adp->pdev->dev, "MSI request failed..\n"); - else - adp->msi = 1; - - rc = request_irq(adp->pdev->irq, chd_dec_isr, IRQF_SHARED, - adp->name, (void *)adp); - - if (rc != 0) { - dev_err(&adp->pdev->dev, "Interrupt request failed..\n"); - if(adp->msi) { - pci_disable_msi(adp->pdev); - adp->msi = 0; - } - } - - return rc; -} - -static int chd_dec_disable_int(struct crystalhd_adp *adp) -{ - if (!adp || !adp->pdev) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return -EINVAL; - } - - free_irq(adp->pdev->irq, adp); - - if (adp->msi) { - pci_disable_msi(adp->pdev); - adp->msi = 0; - } - - return 0; -} - -crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr) -{ - unsigned long flags = 0; - crystalhd_ioctl_data *temp; - - if (!adp) - return NULL; - - spin_lock_irqsave(&adp->lock, flags); - - temp = adp->idata_free_head; - if (temp) { - adp->idata_free_head = adp->idata_free_head->next; - memset(temp, 0, sizeof(*temp)); - } - - spin_unlock_irqrestore(&adp->lock, flags); - return temp; -} - -void chd_dec_free_iodata(struct crystalhd_adp *adp, crystalhd_ioctl_data *iodata, - bool isr) -{ - unsigned long flags = 0; - - if (!adp || !iodata) - return; - - spin_lock_irqsave(&adp->lock, flags); - iodata->next = adp->idata_free_head; - adp->idata_free_head = iodata; - spin_unlock_irqrestore(&adp->lock, flags); -} - -static inline int crystalhd_user_data(unsigned long ud, void *dr, int size, int set) -{ - int rc; - - if (!ud || !dr) { - dev_err(chddev(), "%s: Invalid arg\n", __func__); - return -EINVAL; - } - - if (set) - rc = copy_to_user((void *)ud, dr, size); - else - rc = copy_from_user(dr, (void *)ud, size); - - if (rc) { - dev_err(chddev(), "Invalid args for command\n"); - rc = -EFAULT; - } - - return rc; -} - -static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, crystalhd_ioctl_data *io, - uint32_t m_sz, unsigned long ua) -{ - unsigned long ua_off; - int rc = 0; - - if (!adp || !io || !ua || !m_sz) { - dev_err(chddev(), "Invalid Arg!!\n"); - return -EINVAL; - } - - io->add_cdata = vmalloc(m_sz); - if (!io->add_cdata) { - dev_err(chddev(), "kalloc fail for sz:%x\n", m_sz); - return -ENOMEM; - } - - io->add_cdata_sz = m_sz; - ua_off = ua + sizeof(io->udata); - rc = crystalhd_user_data(ua_off, io->add_cdata, io->add_cdata_sz, 0); - if (rc) { - dev_err(chddev(), "failed to pull add_cdata sz:%x " - "ua_off:%x\n", io->add_cdata_sz, - (unsigned int)ua_off); - if (io->add_cdata) { - kfree(io->add_cdata); - io->add_cdata = NULL; - } - return -ENODATA; - } - - return rc; -} - -static int chd_dec_release_cdata(struct crystalhd_adp *adp, - crystalhd_ioctl_data *io, unsigned long ua) -{ - unsigned long ua_off; - int rc; - - if (!adp || !io || !ua) { - dev_err(chddev(), "Invalid Arg!!\n"); - return -EINVAL; - } - - if (io->cmd != BCM_IOC_FW_DOWNLOAD) { - ua_off = ua + sizeof(io->udata); - rc = crystalhd_user_data(ua_off, io->add_cdata, - io->add_cdata_sz, 1); - if (rc) { - dev_err(chddev(), "failed to push add_cdata sz:%x " - "ua_off:%x\n", io->add_cdata_sz, - (unsigned int)ua_off); - return -ENODATA; - } - } - - if (io->add_cdata) { - vfree(io->add_cdata); - io->add_cdata = NULL; - } - - return 0; -} - -static int chd_dec_proc_user_data(struct crystalhd_adp *adp, - crystalhd_ioctl_data *io, - unsigned long ua, int set) -{ - int rc; - uint32_t m_sz = 0; - - if (!adp || !io || !ua) { - dev_err(chddev(), "Invalid Arg!!\n"); - return -EINVAL; - } - - rc = crystalhd_user_data(ua, &io->udata, sizeof(io->udata), set); - if (rc) { - dev_err(chddev(), "failed to %s iodata\n", - (set ? "set" : "get")); - return rc; - } - - switch (io->cmd) { - case BCM_IOC_MEM_RD: - case BCM_IOC_MEM_WR: - case BCM_IOC_FW_DOWNLOAD: - m_sz = io->udata.u.devMem.NumDwords * 4; - if (set) - rc = chd_dec_release_cdata(adp, io, ua); - else - rc = chd_dec_fetch_cdata(adp, io, m_sz, ua); - break; - default: - break; - } - - return rc; -} - -static int chd_dec_api_cmd(struct crystalhd_adp *adp, unsigned long ua, - uint32_t uid, uint32_t cmd, crystalhd_cmd_proc func) -{ - int rc; - crystalhd_ioctl_data *temp; - BC_STATUS sts = BC_STS_SUCCESS; - - temp = chd_dec_alloc_iodata(adp, 0); - if (!temp) { - dev_err(chddev(), "Failed to get iodata..\n"); - return -EINVAL; - } - - temp->u_id = uid; - temp->cmd = cmd; - - rc = chd_dec_proc_user_data(adp, temp, ua, 0); - if (!rc) { - sts = func(&adp->cmds, temp); - if (sts == BC_STS_PENDING) - sts = BC_STS_NOT_IMPL; - temp->udata.RetSts = sts; - rc = chd_dec_proc_user_data(adp, temp, ua, 1); - } - - if (temp) { - chd_dec_free_iodata(adp, temp, 0); - temp = NULL; - } - - return rc; -} - -/* API interfaces */ -static int chd_dec_ioctl(struct inode *in, struct file *fd, - unsigned int cmd, unsigned long ua) -{ - struct crystalhd_adp *adp = chd_get_adp(); - crystalhd_cmd_proc cproc; - struct crystalhd_user *uc; - - if (!adp || !fd) { - dev_err(chddev(), "Invalid adp\n"); - return -EINVAL; - } - - uc = fd->private_data; - if (!uc) { - dev_err(chddev(), "Failed to get uc\n"); - return -ENODATA; - } - - cproc = crystalhd_get_cmd_proc(&adp->cmds, cmd, uc); - if (!cproc) { - dev_err(chddev(), "Unhandled command: %d\n", cmd); - return -EINVAL; - } - - return chd_dec_api_cmd(adp, ua, uc->uid, cmd, cproc); -} - -static int chd_dec_open(struct inode *in, struct file *fd) -{ - struct crystalhd_adp *adp = chd_get_adp(); - struct device *dev = &adp->pdev->dev; - int rc = 0; - BC_STATUS sts = BC_STS_SUCCESS; - struct crystalhd_user *uc = NULL; - - dev_dbg(dev, "Entering %s\n", __func__); - if (!adp) { - dev_err(dev, "Invalid adp\n"); - return -EINVAL; - } - - if (adp->cfg_users >= BC_LINK_MAX_OPENS) { - dev_info(dev, "Already in use.%d\n", adp->cfg_users); - return -EBUSY; - } - - sts = crystalhd_user_open(&adp->cmds, &uc); - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "cmd_user_open - %d\n", sts); - rc = -EBUSY; - } - else { - adp->cfg_users++; - fd->private_data = uc; - } - - return rc; -} - -static int chd_dec_close(struct inode *in, struct file *fd) -{ - struct crystalhd_adp *adp = chd_get_adp(); - struct device *dev = &adp->pdev->dev; - struct crystalhd_user *uc; - - dev_dbg(dev, "Entering %s\n", __func__); - if (!adp) { - dev_err(dev, "Invalid adp\n"); - return -EINVAL; - } - - uc = fd->private_data; - if (!uc) { - dev_err(dev, "Failed to get uc\n"); - return -ENODATA; - } - - crystalhd_user_close(&adp->cmds, uc); - - adp->cfg_users--; - - return 0; -} - -static const struct file_operations chd_dec_fops = { - .owner = THIS_MODULE, - .ioctl = chd_dec_ioctl, - .open = chd_dec_open, - .release = chd_dec_close, -}; - -static int __devinit chd_dec_init_chdev(struct crystalhd_adp *adp) -{ - struct device *xdev = &adp->pdev->dev; - struct device *dev; - crystalhd_ioctl_data *temp; - int rc = -ENODEV, i = 0; - - if (!adp) - goto fail; - - adp->chd_dec_major = register_chrdev(0, CRYSTALHD_API_NAME, - &chd_dec_fops); - if (adp->chd_dec_major < 0) { - dev_err(xdev, "Failed to create config dev\n"); - rc = adp->chd_dec_major; - goto fail; - } - - /* register crystalhd class */ - crystalhd_class = class_create(THIS_MODULE, "crystalhd"); - if (IS_ERR(crystalhd_class)) { - dev_err(xdev, "failed to create class\n"); - goto fail; - } - -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 25) - dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), - NULL, "crystalhd"); -#else - dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), - "crystalhd"); -#endif - if (IS_ERR(dev)) { - dev_err(xdev, "failed to create device\n"); - goto device_create_fail; - } - -// rc = crystalhd_create_elem_pool(adp, BC_LINK_ELEM_POOL_SZ); -// if (rc) { -// dev_err(xdev, "failed to create device\n"); -// goto elem_pool_fail; -// } - - /* Allocate general purpose ioctl pool. */ - for (i = 0; i < CHD_IODATA_POOL_SZ; i++) { - temp = kzalloc(sizeof(crystalhd_ioctl_data), GFP_KERNEL); - if (!temp) { - dev_err(xdev, "ioctl data pool kzalloc failed\n"); - rc = -ENOMEM; - goto kzalloc_fail; - } - /* Add to global pool.. */ - chd_dec_free_iodata(adp, temp, 0); - } - - return 0; - -kzalloc_fail: - //crystalhd_delete_elem_pool(adp); -//elem_pool_fail: - device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); -device_create_fail: - class_destroy(crystalhd_class); -fail: - return rc; -} - -static void __devexit chd_dec_release_chdev(struct crystalhd_adp *adp) -{ - crystalhd_ioctl_data *temp = NULL; - if (!adp) - return; - - if (adp->chd_dec_major > 0) { - /* unregister crystalhd class */ - device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); - unregister_chrdev(adp->chd_dec_major, CRYSTALHD_API_NAME); - dev_info(chddev(), "released api device - %d\n", - adp->chd_dec_major); - class_destroy(crystalhd_class); - } - adp->chd_dec_major = 0; - - /* Clear iodata pool.. */ - do { - temp = chd_dec_alloc_iodata(adp, 0); - if (temp) - kfree(temp); - } while (temp); - - //crystalhd_delete_elem_pool(adp); -} - -static int __devinit chd_pci_reserve_mem(struct crystalhd_adp *pinfo) -{ - struct device *dev = &pinfo->pdev->dev; - int rc; - - uint32_t bar0 = pci_resource_start(pinfo->pdev, 0); - uint32_t i2o_len = pci_resource_len(pinfo->pdev, 0); - - uint32_t bar2 = pci_resource_start(pinfo->pdev, 2); - uint32_t mem_len = pci_resource_len(pinfo->pdev, 2); - - dev_dbg(dev, "bar0:0x%x-0x%08x bar2:0x%x-0x%08x\n", - bar0, i2o_len, bar2, mem_len); - - /* bar-0 */ - rc = check_mem_region(bar0, i2o_len); - if (rc) { - printk(KERN_ERR "No valid mem region...\n"); - return -ENOMEM; - } - - pinfo->i2o_addr = ioremap_nocache(bar0, i2o_len); - if (!pinfo->i2o_addr) { - printk(KERN_ERR "Failed to remap i2o region...\n"); - return -ENOMEM; - } - - pinfo->pci_i2o_start = bar0; - pinfo->pci_i2o_len = i2o_len; - - /* bar-2 */ - rc = check_mem_region(bar2, mem_len); - if (rc) { - printk(KERN_ERR "No valid mem region...\n"); - return -ENOMEM; - } - - pinfo->mem_addr = ioremap_nocache(bar2, mem_len); - if (!pinfo->mem_addr) { - printk(KERN_ERR "Failed to remap mem region...\n"); - return -ENOMEM; - } - - pinfo->pci_mem_start = bar2; - pinfo->pci_mem_len = mem_len; - - /* pdev */ - rc = pci_request_regions(pinfo->pdev, pinfo->name); - if (rc < 0) { - printk(KERN_ERR "Region request failed: %d\n", rc); - return rc; - } - - dev_dbg(dev, "i2o_addr:0x%08lx Mapped addr:0x%08lx \n", - (unsigned long)pinfo->i2o_addr, (unsigned long)pinfo->mem_addr); - - return 0; -} - -static void __devexit chd_pci_release_mem(struct crystalhd_adp *pinfo) -{ - if (!pinfo) - return; - - if (pinfo->mem_addr) - iounmap(pinfo->mem_addr); - - if (pinfo->i2o_addr) - iounmap(pinfo->i2o_addr); - - pci_release_regions(pinfo->pdev); -} - - -static void __devexit chd_dec_pci_remove(struct pci_dev *pdev) -{ - struct crystalhd_adp *pinfo; - BC_STATUS sts = BC_STS_SUCCESS; - - dev_dbg(chddev(), "Entering %s\n", __func__); - - pinfo = (struct crystalhd_adp *) pci_get_drvdata(pdev); - if (!pinfo) { - dev_err(chddev(), "could not get adp\n"); - return; - } - - sts = crystalhd_delete_cmd_context(&pinfo->cmds); - if (sts != BC_STS_SUCCESS) - dev_err(chddev(), "cmd delete :%d\n", sts); - - chd_dec_release_chdev(pinfo); - - chd_dec_disable_int(pinfo); - - chd_pci_release_mem(pinfo); - pci_disable_device(pinfo->pdev); - - kfree(pinfo); - g_adp_info = NULL; -} - -static int __devinit chd_dec_pci_probe(struct pci_dev *pdev, - const struct pci_device_id *entry) -{ - struct device *dev = &pdev->dev; - struct crystalhd_adp *pinfo; - int rc; - BC_STATUS sts = BC_STS_SUCCESS; - - dev_info(dev, "Starting Device:0x%04x\n", pdev->device); - - pinfo = kzalloc(sizeof(struct crystalhd_adp), GFP_KERNEL); - if (!pinfo) { - dev_err(dev, "%s: Failed to allocate memory\n", __func__); - return -ENOMEM; - } - - pinfo->pdev = pdev; - - rc = pci_enable_device(pdev); - if (rc) { - dev_err(dev, "%s: Failed to enable PCI device\n", __func__); - return rc; - } - - snprintf(pinfo->name, 31, "crystalhd_pci_e:%d:%d:%d", - pdev->bus->number, PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn)); - - rc = chd_pci_reserve_mem(pinfo); - if (rc) { - dev_err(dev, "%s: Failed to set up memory regions.\n", - __func__); - pci_disable_device(pdev); - return -ENOMEM; - } - - pinfo->present = 1; - pinfo->drv_data = entry->driver_data; - - /* Setup adapter level lock.. */ - spin_lock_init(&pinfo->lock); - - /* setup api stuff.. */ - chd_dec_init_chdev(pinfo); - rc = chd_dec_enable_int(pinfo); - if (rc) { - dev_err(dev, "%s: _enable_int err:%d\n", __func__, rc); - pci_disable_device(pdev); - return -ENODEV; - } - - /* Set dma mask... */ - if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { - pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); - pinfo->dmabits = 64; - } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { - pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); - pinfo->dmabits = 32; - } else { - dev_err(dev, "%s: Unabled to setup DMA %d\n", __func__, rc); - pci_disable_device(pdev); - return -ENODEV; - } - - sts = crystalhd_setup_cmd_context(&pinfo->cmds, pinfo); - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "%s: cmd setup :%d\n", __func__, sts); - pci_disable_device(pdev); - return -ENODEV; - } - - pci_set_master(pdev); - - pci_set_drvdata(pdev, pinfo); - - g_adp_info = pinfo; - - return 0; -} - -#ifdef CONFIG_PM -int chd_dec_pci_suspend(struct pci_dev *pdev, pm_message_t state) -{ - struct crystalhd_adp *adp; - struct device *dev = &pdev->dev; - crystalhd_ioctl_data *temp; - BC_STATUS sts = BC_STS_SUCCESS; - - adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); - if (!adp) { - dev_err(dev, "%s: could not get adp\n", __func__); - return -ENODEV; - } - - temp = chd_dec_alloc_iodata(adp, false); - if (!temp) { - dev_err(dev, "could not get ioctl data\n"); - return -ENODEV; - } - - sts = crystalhd_suspend(&adp->cmds, temp); - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "Crystal HD Suspend %d\n", sts); - return -ENODEV; - } - - chd_dec_free_iodata(adp, temp, false); - chd_dec_disable_int(adp); - pci_save_state(pdev); - - /* Disable IO/bus master/irq router */ - pci_disable_device(pdev); - pci_set_power_state(pdev, pci_choose_state(pdev, state)); - return 0; -} - -int chd_dec_pci_resume(struct pci_dev *pdev) -{ - struct crystalhd_adp *adp; - struct device *dev = &pdev->dev; - BC_STATUS sts = BC_STS_SUCCESS; - int rc; - - adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); - if (!adp) { - dev_err(dev, "%s: could not get adp\n", __func__); - return -ENODEV; - } - - pci_set_power_state(pdev, PCI_D0); - pci_restore_state(pdev); - - /* device's irq possibly is changed, driver should take care */ - if (pci_enable_device(pdev)) { - dev_err(dev, "Failed to enable PCI device\n"); - return 1; - } - - pci_set_master(pdev); - - rc = chd_dec_enable_int(adp); - if (rc) { - dev_err(dev, "_enable_int err:%d\n", rc); - pci_disable_device(pdev); - return -ENODEV; - } - - sts = crystalhd_resume(&adp->cmds); - if (sts != BC_STS_SUCCESS) { - dev_err(dev, "Crystal HD Resume %d\n", sts); - pci_disable_device(pdev); - return -ENODEV; - } - - return 0; -} -#endif - -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24) -static DEFINE_PCI_DEVICE_TABLE(chd_dec_pci_id_table) = { - { PCI_VDEVICE(BROADCOM, 0x1612), 8 }, - { PCI_VDEVICE(BROADCOM, 0x1615), 8 }, - { 0, }, -}; -#else -static struct pci_device_id chd_dec_pci_id_table[] = { -/* vendor, device, subvendor, subdevice, class, classmask, driver_data */ - { 0x14e4, 0x1612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, - { 0x14e4, 0x1615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, - { 0, }, -}; -#endif -MODULE_DEVICE_TABLE(pci, chd_dec_pci_id_table); - -static struct pci_driver bc_chd_driver = { - .name = "crystalhd", - .probe = chd_dec_pci_probe, - .remove = __devexit_p(chd_dec_pci_remove), - .id_table = chd_dec_pci_id_table, -#ifdef CONFIG_PM - .suspend = chd_dec_pci_suspend, - .resume = chd_dec_pci_resume -#endif -}; - -struct crystalhd_adp *chd_get_adp(void) -{ - return g_adp_info; -} - -static int __init chd_dec_module_init(void) -{ - int rc; - - printk(KERN_DEBUG "Loading crystalhd v%d.%d.%d\n", - crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); - - rc = pci_register_driver(&bc_chd_driver); - - if (rc < 0) - printk(KERN_ERR "%s: Could not find any devices. err:%d\n", - __func__, rc); - - return rc; -} -module_init(chd_dec_module_init); - -static void __exit chd_dec_module_cleanup(void) -{ - printk(KERN_DEBUG "Unloading crystalhd %d.%d.%d\n", - crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); - - pci_unregister_driver(&bc_chd_driver); -} -module_exit(chd_dec_module_cleanup); - -MODULE_AUTHOR("Naren Sankar "); -MODULE_AUTHOR("Prasad Bolisetty "); -MODULE_DESCRIPTION(CRYSTAL_HD_NAME); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("crystalhd"); diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_lnx.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_lnx.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_lnx.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_lnx.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,95 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_lnx . c - * - * Description: - * BCM70012 Linux driver - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#ifndef _CRYSTALHD_LNX_H_ -#define _CRYSTALHD_LNX_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "crystalhd_cmds.h" - -#define CRYSTAL_HD_NAME "Broadcom Crystal HD Decoder Driver" - -/* OS specific PCI information structure and adapter information. */ -struct crystalhd_adp { - /* Hardware board/PCI specifics */ - char name[32]; - struct pci_dev *pdev; - - unsigned long pci_mem_start; - uint32_t pci_mem_len; - void *mem_addr; - - unsigned long pci_i2o_start; - uint32_t pci_i2o_len; - void *i2o_addr; - - unsigned int drv_data; - unsigned int dmabits; /* 32 | 64 */ - unsigned int registered; - unsigned int present; - unsigned int msi; - - spinlock_t lock; - - /* API Related */ - int chd_dec_major; - unsigned int cfg_users; - - crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */ - crystalhd_elem_t *elem_pool_head; /* Queue element pool */ - - struct crystalhd_cmd cmds; - - crystalhd_dio_req *ua_map_free_head; - struct pci_pool *fill_byte_pool; -}; - - -struct crystalhd_adp *chd_get_adp(void); -struct device *chddev(void); - -#endif - diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_misc.c crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_misc.c --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_misc.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_misc.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,946 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_misc . c - * - * Description: - * BCM70012 Linux driver misc routines. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#include -#include - -#include "crystalhd_lnx.h" -#include "crystalhd_misc.h" - -// Some HW specific code defines -extern uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void *); -extern uint32_t flea_GetRptDropParam(struct crystalhd_hw *hw, void *); - -static crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp) -{ - unsigned long flags = 0; - crystalhd_dio_req *temp = NULL; - - if (!adp) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return temp; - } - - spin_lock_irqsave(&adp->lock, flags); - temp = adp->ua_map_free_head; - if (temp) - adp->ua_map_free_head = adp->ua_map_free_head->next; - spin_unlock_irqrestore(&adp->lock, flags); - - return temp; -} - -static void crystalhd_free_dio(struct crystalhd_adp *adp, crystalhd_dio_req *dio) -{ - unsigned long flags = 0; - - if (!adp || !dio) - return; - spin_lock_irqsave(&adp->lock, flags); - dio->sig = crystalhd_dio_inv; - dio->page_cnt = 0; - dio->fb_size = 0; - memset(&dio->uinfo, 0, sizeof(dio->uinfo)); - dio->next = adp->ua_map_free_head; - adp->ua_map_free_head = dio; - spin_unlock_irqrestore(&adp->lock, flags); -} - -static crystalhd_elem_t *crystalhd_alloc_elem(struct crystalhd_adp *adp) -{ - unsigned long flags = 0; - crystalhd_elem_t *temp = NULL; - - if (!adp) - { - printk(KERN_ERR "%s: Invalid args\n", __func__); - return temp; - } - spin_lock_irqsave(&adp->lock, flags); - temp = adp->elem_pool_head; - if (temp) { - adp->elem_pool_head = adp->elem_pool_head->flink; - memset(temp, 0, sizeof(*temp)); - } - - spin_unlock_irqrestore(&adp->lock, flags); - - return temp; -} -static void crystalhd_free_elem(struct crystalhd_adp *adp, crystalhd_elem_t *elem) -{ - unsigned long flags = 0; - - if (!adp || !elem) - return; - spin_lock_irqsave(&adp->lock, flags); - elem->flink = adp->elem_pool_head; - adp->elem_pool_head = elem; - spin_unlock_irqrestore(&adp->lock, flags); -} - -static inline void crystalhd_set_sg(struct scatterlist *sg, struct page *page, - unsigned int len, unsigned int offset) -{ -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) - sg_set_page(sg, page, len, offset); -#else - sg->page = page; - sg->offset = offset; - sg->length = len; -#endif -#ifdef CONFIG_X86_64 - sg->dma_length = len; -#endif -} - -static inline void crystalhd_init_sg(struct scatterlist *sg, unsigned int entries) -{ - /* http://lkml.org/lkml/2007/11/27/68 */ -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) - sg_init_table(sg, entries); -#endif -} - -/*========================== Extern ========================================*/ -/** - * crystalhd_pci_cfg_rd - PCIe config read - * @adp: Adapter instance - * @off: PCI config space offset. - * @len: Size -- Byte, Word & dword. - * @val: Value read - * - * Return: - * Status. - * - * Get value from PCIe config space. - */ -BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off, - uint32_t len, uint32_t *val) -{ - BC_STATUS sts = BC_STS_SUCCESS; - int rc = 0; - - if (!adp || !val) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - switch (len) { - case 1: - rc = pci_read_config_byte(adp->pdev, off, (u8 *)val); - break; - case 2: - rc = pci_read_config_word(adp->pdev, off, (u16 *)val); - break; - case 4: - rc = pci_read_config_dword(adp->pdev, off, (u32 *)val); - break; - default: - rc = -EINVAL; - sts = BC_STS_INV_ARG; - dev_err(&adp->pdev->dev, "Invalid len:%d\n", len); - }; - - if (rc && (sts == BC_STS_SUCCESS)) - sts = BC_STS_ERROR; - - return sts; -} - -/** - * crystalhd_pci_cfg_wr - PCIe config write - * @adp: Adapter instance - * @off: PCI config space offset. - * @len: Size -- Byte, Word & dword. - * @val: Value to be written - * - * Return: - * Status. - * - * Set value to Link's PCIe config space. - */ -BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *adp, uint32_t off, - uint32_t len, uint32_t val) -{ - BC_STATUS sts = BC_STS_SUCCESS; - int rc = 0; - - if (!adp || !val) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - switch (len) { - case 1: - rc = pci_write_config_byte(adp->pdev, off, (u8)val); - break; - case 2: - rc = pci_write_config_word(adp->pdev, off, (u16)val); - break; - case 4: - rc = pci_write_config_dword(adp->pdev, off, val); - break; - default: - rc = -EINVAL; - sts = BC_STS_INV_ARG; - dev_err(&adp->pdev->dev, "Invalid len:%d\n", len); - }; - - if (rc && (sts == BC_STS_SUCCESS)) - sts = BC_STS_ERROR; - - return sts; -} - -/** - * bc_kern_dma_alloc - Allocate memory for Dma rings - * @adp: Adapter instance - * @sz: Size of the memory to allocate. - * @phy_addr: Physical address of the memory allocated. - * Typedef to system's dma_addr_t (u64) - * - * Return: - * Pointer to allocated memory.. - * - * Wrapper to Linux kernel interface. - * - */ -void *bc_kern_dma_alloc(struct crystalhd_adp *adp, uint32_t sz, - dma_addr_t *phy_addr) -{ - void *temp = NULL; - - if (!adp || !sz || !phy_addr) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return temp; - } - - temp = pci_alloc_consistent(adp->pdev, sz, phy_addr); - if (temp) - memset(temp, 0, sz); - - return temp; -} - -/** - * bc_kern_dma_free - Release Dma ring memory. - * @adp: Adapter instance - * @sz: Size of the memory to allocate. - * @ka: Kernel virtual address returned during _dio_alloc() - * @phy_addr: Physical address of the memory allocated. - * Typedef to system's dma_addr_t (u64) - * - * Return: - * none. - */ -void bc_kern_dma_free(struct crystalhd_adp *adp, uint32_t sz, void *ka, - dma_addr_t phy_addr) -{ - if (!adp || !ka || !sz || !phy_addr) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return; - } - - pci_free_consistent(adp->pdev, sz, ka, phy_addr); -} - -/** - * crystalhd_create_dioq - Create Generic DIO queue - * @adp: Adapter instance - * @dioq_hnd: Handle to the dio queue created - * @cb : Optional - Call back To free the element. - * @cbctx: Context to pass to callback. - * - * Return: - * status - * - * Initialize Generic DIO queue to hold any data. Callback - * will be used to free elements while deleting the queue. - */ -BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp, - crystalhd_dioq_t **dioq_hnd, - crystalhd_data_free_cb cb, void *cbctx) -{ - crystalhd_dioq_t *dioq = NULL; - - if (!adp || !dioq_hnd) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - dioq = kzalloc(sizeof(*dioq), GFP_KERNEL); - if (!dioq) - return BC_STS_INSUFF_RES; - - spin_lock_init(&dioq->lock); - dioq->sig = BC_LINK_DIOQ_SIG; - dioq->head = (crystalhd_elem_t *)&dioq->head; - dioq->tail = (crystalhd_elem_t *)&dioq->head; - crystalhd_create_event(&dioq->event); - dioq->adp = adp; - dioq->data_rel_cb = cb; - dioq->cb_context = cbctx; - *dioq_hnd = dioq; - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_delete_dioq - Delete Generic DIO queue - * @adp: Adapter instance - * @dioq: DIOQ instance.. - * - * Return: - * None. - * - * Release Generic DIO queue. This function will remove - * all the entries from the Queue and will release data - * by calling the call back provided during creation. - * - */ -void crystalhd_delete_dioq(struct crystalhd_adp *adp, crystalhd_dioq_t *dioq) -{ - void *temp; - - if (!dioq || (dioq->sig != BC_LINK_DIOQ_SIG)) - return; - - do { - temp = crystalhd_dioq_fetch(dioq); - if (temp && dioq->data_rel_cb) - dioq->data_rel_cb(dioq->cb_context, temp); - } while (temp); - dioq->sig = 0; - kfree(dioq); -} - -/** - * crystalhd_dioq_add - Add new DIO request element. - * @ioq: DIO queue instance - * @t: DIO request to be added. - * @wake: True - Wake up suspended process. - * @tag: Special tag to assign - For search and get. - * - * Return: - * Status. - * - * Insert new element to Q tail. - */ -BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data, - bool wake, uint32_t tag) -{ - unsigned long flags = 0; - crystalhd_elem_t *tmp; - - if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !data) { - dev_err(chddev(), "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - tmp = crystalhd_alloc_elem(ioq->adp); - if (!tmp) { - dev_err(chddev(), "%s: No free elements.\n", __func__); - return BC_STS_INSUFF_RES; - } - - tmp->data = data; - tmp->tag = tag; - spin_lock_irqsave(&ioq->lock, flags); - tmp->flink = (crystalhd_elem_t *)&ioq->head; - tmp->blink = ioq->tail; - tmp->flink->blink = tmp; - tmp->blink->flink = tmp; - ioq->count++; - spin_unlock_irqrestore(&ioq->lock, flags); - - if (wake) - crystalhd_set_event(&ioq->event); - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_dioq_fetch - Fetch element from head. - * @ioq: DIO queue instance - * - * Return: - * data element from the head.. - * - * Remove an element from Queue. - */ -void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq) -{ - unsigned long flags = 0; - crystalhd_elem_t *tmp; - crystalhd_elem_t *ret = NULL; - void *data = NULL; - - if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { - dev_err(chddev(), "%s: Invalid arg\n", __func__); - return data; - } - - spin_lock_irqsave(&ioq->lock, flags); - tmp = ioq->head; - if (tmp != (crystalhd_elem_t *)&ioq->head) { - ret = tmp; - tmp->flink->blink = tmp->blink; - tmp->blink->flink = tmp->flink; - ioq->count--; - } - spin_unlock_irqrestore(&ioq->lock, flags); - if (ret) { - data = ret->data; - crystalhd_free_elem(ioq->adp, ret); - } - - return data; -} -/** - * crystalhd_dioq_find_and_fetch - Search the tag and Fetch element - * @ioq: DIO queue instance - * @tag: Tag to search for. - * - * Return: - * element from the head.. - * - * Search TAG and remove the element. - */ -void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag) -{ - unsigned long flags = 0; - crystalhd_elem_t *tmp; - crystalhd_elem_t *ret = NULL; - void *data = NULL; - - if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { - dev_err(chddev(), "%s: Invalid arg\n", __func__); - return data; - } - - spin_lock_irqsave(&ioq->lock, flags); - tmp = ioq->head; - while (tmp != (crystalhd_elem_t *)&ioq->head) { - if (tmp->tag == tag) { - ret = tmp; - tmp->flink->blink = tmp->blink; - tmp->blink->flink = tmp->flink; - ioq->count--; - break; - } - tmp = tmp->flink; - } - spin_unlock_irqrestore(&ioq->lock, flags); - - if (ret) { - data = ret->data; - crystalhd_free_elem(ioq->adp, ret); - } - - return data; -} - -/** - * crystalhd_dioq_fetch_wait - Fetch element from Head. - * @ioq: DIO queue instance - * @to_secs: Wait timeout in seconds.. - * - * Return: - * element from the head.. - * - * Return element from head if Q is not empty. Wait for new element - * if Q is empty for Timeout seconds. - */ -void *crystalhd_dioq_fetch_wait(struct crystalhd_hw *hw, uint32_t to_secs, uint32_t *sig_pend) -{ - struct device *dev = chddev(); - unsigned long flags = 0; - int rc = 0; - - crystalhd_rx_dma_pkt *r_pkt = NULL; - crystalhd_dioq_t *ioq = hw->rx_rdyq; - uint32_t picYcomp = 0; - - unsigned long fetchTimeout = jiffies + msecs_to_jiffies(to_secs * 1000); - - if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !to_secs || !sig_pend) { - dev_err(dev, "%s: Invalid arg\n", __func__); - return r_pkt; - } - - spin_lock_irqsave(&ioq->lock, flags); - while (!time_after_eq(jiffies, fetchTimeout)) { - if(ioq->count == 0) { - spin_unlock_irqrestore(&ioq->lock, flags); - crystalhd_wait_on_event(&ioq->event, (ioq->count > 0), - 250, rc, false); - } - else - spin_unlock_irqrestore(&ioq->lock, flags); - if (rc == 0) { - // Found a packet. Check if it is a repeated picture or not - // Drop the picture if it is a repeated picture - // Lock against checks from get status calls - if(down_interruptible(&hw->fetch_sem)) - goto sem_error; - r_pkt = crystalhd_dioq_fetch(ioq); - // If format change packet, then return with out checking anything - if (r_pkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE)) - goto sem_rel_return; - if (hw->adp->pdev->device == BC_PCI_DEVID_LINK) { - picYcomp = link_GetRptDropParam(hw, hw->PICHeight, hw->PICWidth, (void *)r_pkt); - } - else { - // For Flea, we don't have the width and height handy since they - // come in the PIB in the picture, so this function will also - // populate the width and height - picYcomp = flea_GetRptDropParam(hw, (void *)r_pkt); - // For flea it is the above function that indicated format change - if(r_pkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE)) - goto sem_rel_return; - } - if(!picYcomp || (picYcomp == hw->LastPicNo) || - (picYcomp == hw->LastTwoPicNo)) { - //Discard picture - if(picYcomp != 0) { - hw->LastTwoPicNo = hw->LastPicNo; - hw->LastPicNo = picYcomp; - } - crystalhd_dioq_add(hw->rx_freeq, r_pkt, false, r_pkt->pkt_tag); - r_pkt = NULL; - up(&hw->fetch_sem); - } else { - if(hw->adp->pdev->device == BC_PCI_DEVID_LINK) { - if((picYcomp - hw->LastPicNo) > 1) { - dev_info(dev, "MISSING %u PICTURES\n", (picYcomp - hw->LastPicNo)); - } - } - hw->LastTwoPicNo = hw->LastPicNo; - hw->LastPicNo = picYcomp; - goto sem_rel_return; - } - } else if (rc == -EINTR) { - *sig_pend = 1; - return r_pkt; - } - spin_lock_irqsave(&ioq->lock, flags); - } - dev_info(dev, "FETCH TIMEOUT\n"); - spin_unlock_irqrestore(&ioq->lock, flags); - return r_pkt; -sem_error: - return NULL; -sem_rel_return: - up(&hw->fetch_sem); - return r_pkt; -} - -/** - * crystalhd_map_dio - Map user address for DMA - * @adp: Adapter instance - * @ubuff: User buffer to map. - * @ubuff_sz: User buffer size. - * @uv_offset: UV buffer offset. - * @en_422mode: TRUE:422 FALSE:420 Capture mode. - * @dir_tx: TRUE for Tx (To device from host) - * @dio_hnd: Handle to mapped DIO request. - * - * Return: - * Status. - * - * This routine maps user address and lock pages for DMA. - * - */ -BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, - uint32_t ubuff_sz, uint32_t uv_offset, - bool en_422mode, bool dir_tx, - crystalhd_dio_req **dio_hnd) -{ - struct device *dev; - crystalhd_dio_req *dio; - uint32_t start = 0, end = 0, count = 0; - uint32_t spsz = 0; - unsigned long uaddr = 0, uv_start = 0; - int i = 0, rw = 0, res = 0, nr_pages = 0, skip_fb_sg = 0; - - if (!adp || !ubuff || !ubuff_sz || !dio_hnd) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - dev = &adp->pdev->dev; - - /* Compute pages */ - uaddr = (unsigned long)ubuff; - count = ubuff_sz; - end = (uaddr + count + PAGE_SIZE - 1) >> PAGE_SHIFT; - start = uaddr >> PAGE_SHIFT; - nr_pages = end - start; - - if (!count || ((uaddr + count) < uaddr)) { - dev_err(dev, "User addr overflow!!\n"); - return BC_STS_INV_ARG; - } - - dio = crystalhd_alloc_dio(adp); - if (!dio) { - dev_err(dev, "dio pool empty..\n"); - return BC_STS_INSUFF_RES; - } - - if (dir_tx) { - rw = WRITE; - dio->direction = DMA_TO_DEVICE; - } else { - rw = READ; - dio->direction = DMA_FROM_DEVICE; - } - - if (nr_pages > dio->max_pages) { - dev_err(dev, "max_pages(%d) exceeded(%d)!!\n", - dio->max_pages, nr_pages); - crystalhd_unmap_dio(adp, dio); - return BC_STS_INSUFF_RES; - } - - if (uv_offset) { - uv_start = (uaddr + uv_offset) >> PAGE_SHIFT; - dio->uinfo.uv_sg_ix = uv_start - start; - dio->uinfo.uv_sg_off = ((uaddr + uv_offset) & ~PAGE_MASK); - } - - dio->fb_size = ubuff_sz & 0x03; - if (dio->fb_size) { - res = copy_from_user(dio->fb_va, - (void *)(uaddr + count - dio->fb_size), - dio->fb_size); - if (res) { - dev_err(dev, "failed %d to copy %u fill bytes from %p\n", - res, dio->fb_size, - (void *)(uaddr + count-dio->fb_size)); - crystalhd_unmap_dio(adp, dio); - return BC_STS_INSUFF_RES; - } - } - - down_read(¤t->mm->mmap_sem); - res = get_user_pages(current, current->mm, uaddr, nr_pages, rw == READ, - 0, dio->pages, NULL); - up_read(¤t->mm->mmap_sem); - - /* Save for release..*/ - dio->sig = crystalhd_dio_locked; - if (res < nr_pages) { - dev_err(dev, "get pages failed: %d-%d\n", nr_pages, res); - dio->page_cnt = res; - crystalhd_unmap_dio(adp, dio); - return BC_STS_ERROR; - } - - dio->page_cnt = nr_pages; - /* Get scatter/gather */ - crystalhd_init_sg(dio->sg, dio->page_cnt); - crystalhd_set_sg(&dio->sg[0], dio->pages[0], 0, uaddr & ~PAGE_MASK); - if (nr_pages > 1) { - dio->sg[0].length = PAGE_SIZE - dio->sg[0].offset; - -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) -#ifdef CONFIG_X86_64 - dio->sg[0].dma_length = dio->sg[0].length; -#endif -#endif - count -= dio->sg[0].length; - for (i = 1; i < nr_pages; i++) { - if (count < 4) { - spsz = count; - skip_fb_sg = 1; - } else { - spsz = (count < PAGE_SIZE) ? - (count & ~0x03) : PAGE_SIZE; - } - crystalhd_set_sg(&dio->sg[i], dio->pages[i], spsz, 0); - count -= spsz; - } - } else { - if (count < 4) { - dio->sg[0].length = count; - skip_fb_sg = 1; - } else { - dio->sg[0].length = count - dio->fb_size; - } -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) -#ifdef CONFIG_X86_64 - dio->sg[0].dma_length = dio->sg[0].length; -#endif -#endif - } - dio->sg_cnt = pci_map_sg(adp->pdev, dio->sg, - dio->page_cnt, dio->direction); - if (dio->sg_cnt <= 0) { - dev_err(dev, "sg map %d-%d\n", dio->sg_cnt, dio->page_cnt); - crystalhd_unmap_dio(adp, dio); - return BC_STS_ERROR; - } - if (dio->sg_cnt && skip_fb_sg) - dio->sg_cnt -= 1; - dio->sig = crystalhd_dio_sg_mapped; - /* Fill in User info.. */ - dio->uinfo.xfr_len = ubuff_sz; - dio->uinfo.xfr_buff = ubuff; - dio->uinfo.uv_offset = uv_offset; - dio->uinfo.b422mode = en_422mode; - dio->uinfo.dir_tx = dir_tx; - - *dio_hnd = dio; - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_unmap_sgl - Release mapped resources - * @adp: Adapter instance - * @dio: DIO request instance - * - * Return: - * Status. - * - * This routine is to unmap the user buffer pages. - */ -BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, crystalhd_dio_req *dio) -{ - struct page *page = NULL; - int j = 0; - - if (!adp || !dio) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return BC_STS_INV_ARG; - } - - if ((dio->page_cnt > 0) && (dio->sig != crystalhd_dio_inv)) { - for (j = 0; j < dio->page_cnt; j++) { - page = dio->pages[j]; - if (page) { - if (!PageReserved(page) && - (dio->direction == DMA_FROM_DEVICE)) - SetPageDirty(page); - page_cache_release(page); - } - } - } - if (dio->sig == crystalhd_dio_sg_mapped) - pci_unmap_sg(adp->pdev, dio->sg, dio->page_cnt, dio->direction); - - crystalhd_free_dio(adp, dio); - - return BC_STS_SUCCESS; -} - -/** - * crystalhd_create_dio_pool - Allocate mem pool for DIO management. - * @adp: Adapter instance - * @max_pages: Max pages for size calculation. - * - * Return: - * system error. - * - * This routine creates a memory pool to hold dio context for - * for HW Direct IO operation. - */ -int crystalhd_create_dio_pool(struct crystalhd_adp *adp, uint32_t max_pages) -{ - struct device *dev; - uint32_t asz = 0, i = 0; - uint8_t *temp; - crystalhd_dio_req *dio; - - if (!adp || !max_pages) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return -EINVAL; - } - - dev = &adp->pdev->dev; - - /* Get dma memory for fill byte handling..*/ - adp->fill_byte_pool = pci_pool_create("crystalhd_fbyte", - adp->pdev, 8, 8, 0); - if (!adp->fill_byte_pool) { - dev_err(dev, "failed to create fill byte pool\n"); - return -ENOMEM; - } - - /* Get the max size from user based on 420/422 modes */ - asz = (sizeof(*dio->pages) * max_pages) + - (sizeof(*dio->sg) * max_pages) + sizeof(*dio); - - dev_dbg(dev, "Initializing Dio pool %d %d %x %p\n", - BC_LINK_SG_POOL_SZ, max_pages, asz, adp->fill_byte_pool); - - for (i = 0; i < BC_LINK_SG_POOL_SZ; i++) { - temp = (uint8_t *)kzalloc(asz, GFP_KERNEL); - if ((temp) == NULL) { - dev_err(dev, "Failed to alloc %d mem\n", asz); - return -ENOMEM; - } - - dio = (crystalhd_dio_req *)temp; - temp += sizeof(*dio); - dio->pages = (struct page **)temp; - temp += (sizeof(*dio->pages) * max_pages); - dio->sg = (struct scatterlist *)temp; - dio->max_pages = max_pages; - dio->fb_va = pci_pool_alloc(adp->fill_byte_pool, GFP_KERNEL, - &dio->fb_pa); - if (!dio->fb_va) { - dev_err(dev, "fill byte alloc failed.\n"); - return -ENOMEM; - } - - crystalhd_free_dio(adp, dio); - } - - return 0; -} - -/** - * crystalhd_destroy_dio_pool - Release DIO mem pool. - * @adp: Adapter instance - * - * Return: - * none. - * - * This routine releases dio memory pool during close. - */ -void crystalhd_destroy_dio_pool(struct crystalhd_adp *adp) -{ - crystalhd_dio_req *dio; - int count = 0; - - if (!adp) { - printk(KERN_ERR "%s: Invalid arg\n", __func__); - return; - } - - do { - dio = crystalhd_alloc_dio(adp); - if (dio) { - if (dio->fb_va) - pci_pool_free(adp->fill_byte_pool, - dio->fb_va, dio->fb_pa); - count++; - kfree(dio); - } - } while (dio); - - if (adp->fill_byte_pool) { - pci_pool_destroy(adp->fill_byte_pool); - adp->fill_byte_pool = NULL; - } - - dev_dbg(&adp->pdev->dev, "Released dio pool %d\n", count); -} - -/** - * crystalhd_create_elem_pool - List element pool creation. - * @adp: Adapter instance - * @pool_size: Number of elements in the pool. - * - * Return: - * 0 - success, <0 error - * - * Create general purpose list element pool to hold pending, - * and active requests. - */ -int crystalhd_create_elem_pool(struct crystalhd_adp *adp, - uint32_t pool_size) -{ - uint32_t i; - crystalhd_elem_t *temp; - - if (!adp || !pool_size) - return -EINVAL; - - for (i = 0; i < pool_size; i++) { - temp = kzalloc(sizeof(*temp), GFP_KERNEL); - if (!temp) { - dev_err(&adp->pdev->dev, "kzalloc failed\n"); - return -ENOMEM; - } - crystalhd_free_elem(adp, temp); - } - dev_dbg(&adp->pdev->dev, "allocated %d elem\n", pool_size); - return 0; -} - -/** - * crystalhd_delete_elem_pool - List element pool deletion. - * @adp: Adapter instance - * - * Return: - * none - * - * Delete general purpose list element pool. - */ -void crystalhd_delete_elem_pool(struct crystalhd_adp *adp) -{ - crystalhd_elem_t *temp; - int dbg_cnt = 0; - - if (!adp) - return; - - do { - temp = crystalhd_alloc_elem(adp); - if (temp) { - kfree(temp); - dbg_cnt++; - } - } while (temp); - - dev_dbg(&adp->pdev->dev, "released %d elem\n", dbg_cnt); -} - -/*================ Debug support routines.. ================================*/ -void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount) -{ - struct device *dev = chddev(); - uint32_t i, k = 1; - - for (i = 0; i < dwcount; i++) { - if (k == 1) - dev_dbg(dev, "0x%08X : ", off); - - dev_dbg(dev, " 0x%08X ", *((uint32_t *)buff)); - - buff += sizeof(uint32_t); - off += sizeof(uint32_t); - k++; - if ((i == dwcount - 1) || (k > 4)) { - dev_dbg(dev, "\n"); - k = 1; - } - } -} diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_misc.h crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_misc.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/crystalhd_misc.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/crystalhd_misc.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,183 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_misc . h - * - * Description: - * BCM70012 Linux driver general purpose routines. - * Includes reg/mem read and write routines. - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -#ifndef _CRYSTALHD_MISC_H_ -#define _CRYSTALHD_MISC_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "bc_dts_glob_lnx.h" -#include "crystalhd_hw.h" - -// forward declare -struct crystalhd_hw; - -/* Global element pool for all Queue management. - * TX: Active = BC_TX_LIST_CNT, Free = BC_TX_LIST_CNT. - * RX: Free = BC_RX_LIST_CNT, Active = 2 - * FW-CMD: 4 - */ -#define BC_LINK_ELEM_POOL_SZ ((BC_TX_LIST_CNT * 2) + BC_RX_LIST_CNT + 2 + 4) - -/* Driver's IODATA pool count */ -#define CHD_IODATA_POOL_SZ (BC_IOCTL_DATA_POOL_SIZE * BC_LINK_MAX_OPENS) - -/* Scatter Gather memory pool size for Tx and Rx */ -#define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT) - -enum _crystalhd_dio_sig { - crystalhd_dio_inv = 0, - crystalhd_dio_locked, - crystalhd_dio_sg_mapped, -}; - -struct crystalhd_dio_user_info { - void *xfr_buff; - uint32_t xfr_len; - uint32_t uv_offset; - bool dir_tx; - - uint32_t uv_sg_ix; - uint32_t uv_sg_off; - int comp_sts; - int ev_sts; - uint32_t y_done_sz; - uint32_t uv_done_sz; - uint32_t comp_flags; - bool b422mode; -}; - -typedef struct _crystalhd_dio_req { - uint32_t sig; - uint32_t max_pages; - struct page **pages; - struct scatterlist *sg; - int sg_cnt; - int page_cnt; - int direction; - struct crystalhd_dio_user_info uinfo; - void *fb_va; - uint32_t fb_size; - dma_addr_t fb_pa; - void *pib_va; // pointer to temporary buffer to extract metadata - struct _crystalhd_dio_req *next; -} crystalhd_dio_req; - -#define BC_LINK_DIOQ_SIG (0x09223280) - -typedef struct _crystalhd_elem_s { - struct _crystalhd_elem_s *flink; - struct _crystalhd_elem_s *blink; - void *data; - uint32_t tag; -} crystalhd_elem_t; - -typedef void (*crystalhd_data_free_cb)(void *context, void *data); - -typedef struct _crystalhd_dioq_s { - uint32_t sig; - struct crystalhd_adp *adp; - crystalhd_elem_t *head; - crystalhd_elem_t *tail; - uint32_t count; - spinlock_t lock; - wait_queue_head_t event; - crystalhd_data_free_cb data_rel_cb; - void *cb_context; -} crystalhd_dioq_t; - -typedef void (*hw_comp_callback)(crystalhd_dio_req *, - wait_queue_head_t *event, BC_STATUS sts); - -/*========== PCIe Config access routines.================*/ -BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); -BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t); - -/*========= Linux Kernel Interface routines. ======================= */ -void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *); -void bc_kern_dma_free(struct crystalhd_adp *, uint32_t, - void *, dma_addr_t); -#define crystalhd_create_event(_ev) init_waitqueue_head(_ev) -#define crystalhd_set_event(_ev) wake_up_interruptible(_ev) -#define crystalhd_wait_on_event(ev, condition, timeout, ret, nosig) \ -do { \ - DECLARE_WAITQUEUE(entry, current); \ - unsigned long end = jiffies + msecs_to_jiffies(timeout); \ - ret = 0; \ - add_wait_queue(ev, &entry); \ - for (;;) { \ - set_current_state(TASK_INTERRUPTIBLE); \ - if (condition) { \ - break; \ - } \ - if (time_after_eq(jiffies, end)) { \ - ret = -EBUSY; \ - break; \ - } \ - schedule_timeout((HZ / 100 > 1) ? HZ / 100 : 1); \ - if (!nosig && signal_pending(current)) { \ - ret = -EINTR; \ - break; \ - } \ - } \ - set_current_state(TASK_RUNNING); \ - remove_wait_queue(ev, &entry); \ -} while (0) - -/*================ Direct IO mapping routines ==================*/ -extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t); -extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *); -extern BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t, - uint32_t, bool, bool, crystalhd_dio_req**); - -extern BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, crystalhd_dio_req*); -#define crystalhd_get_sgle_paddr(_dio, _ix) (cpu_to_le64(sg_dma_address(&_dio->sg[_ix]))) -#define crystalhd_get_sgle_len(_dio, _ix) (cpu_to_le32(sg_dma_len(&_dio->sg[_ix]))) - -/*================ General Purpose Queues ==================*/ -extern BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, crystalhd_dioq_t **, crystalhd_data_free_cb , void *); -extern void crystalhd_delete_dioq(struct crystalhd_adp *, crystalhd_dioq_t *); -extern BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data, bool wake, uint32_t tag); -extern void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq); -extern void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag); -extern void *crystalhd_dioq_fetch_wait(struct crystalhd_hw *hw, uint32_t to_secs, uint32_t *sig_pend); - -#define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0) - -extern int crystalhd_create_elem_pool(struct crystalhd_adp *, uint32_t); -extern void crystalhd_delete_elem_pool(struct crystalhd_adp *); - -/*================ Debug routines/macros .. ================================*/ -extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount); - -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/FleaDefs.h crystalhd-0.0~git20101029.6df10a0/driver/linux/FleaDefs.h --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/FleaDefs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/FleaDefs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,218 +0,0 @@ -#ifndef _FLEA_DEFS_ -#define _FLEA_DEFS_ - -/* -* Include a whole bunch of RDB files for register definitions -*/ -#include "bchp_misc1.h" -#include "bchp_misc2.h" -#include "bchp_misc3.h" -#include "bchp_scrub_ctrl.h" -#include "bchp_wrap_misc_intr2.h" -#include "bchp_armcr4_bridge.h" -#include "bchp_intr.h" -#include "bchp_pri_arb_control_regs.h" -#include "bchp_ddr23_ctl_regs_0.h" -#include "bchp_ddr23_phy_byte_lane_0.h" -#include "bchp_ddr23_phy_byte_lane_1.h" -#include "bchp_ddr23_phy_control_regs.h" -#include "bchp_clk.h" -#include "bchp_pcie_tl.h" -#include "bchp_sun_gisb_arb.h" -#include "bchp_misc_perst.h" -#include "bchp_decode_cpuregs_0.h" -#include "bchp_decode_cpuregs2_0.h" -#include "bchp_pcie_cfg.h" -#include "bchp_mfd.h" -#include "bchp_sun_top_ctrl.h" -#include "bchp_gio.h" -#include "bchp_pri_client_regs.h" - -// Assume we have 64MB DRam -#define FLEA_TOTAL_DRAM_SIZE 64*1024*1024 -#define FLEA_GISB_DIRECT_BASE 0x50 - -/*- These definition of the ADDRESS and DATA - - Registers are not there in RDB. - */ -#define FLEA_GISB_INDIRECT_ADDRESS 0xFFF8 -#define FLEA_GISB_INDIRECT_DATA 0xFFFC - -/* - * POLL count for Flea. - */ -#define FLEA_MAX_POLL_CNT 1000 - -/* - -- Flea Firmware Signature length (128 bit) - */ -#define FLEA_FW_SIG_LEN_IN_BYTES 16 -#define LENGTH_FIELD_SIZE 4 -#define FLEA_FW_SIG_LEN_IN_DWORD (FLEA_FW_SIG_LEN_IN_BYTES/4) -#define FW_DOWNLOAD_START_ADDR 0 - -/* - * Some macros to ease the bit specification from RDB - */ -#define SCRAM_KEY_DONE_INT_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT) -#define BOOT_VER_DONE_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT) -#define BOOT_VER_FAIL_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT) -#define SHARF_ERR_INTR BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT) -#define SCRUB_ENABLE_BIT BC_BIT(BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_SHIFT) -#define DRAM_SCRAM_ENABLE_BIT BC_BIT(BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_SHIFT) -#define ARM_RUN_REQ_BIT BC_BIT(BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_SHIFT) -#define GetScrubEndAddr(_Sz) ((FW_DOWNLOAD_START_ADDR + (_Sz - FLEA_FW_SIG_LEN_IN_BYTES -LENGTH_FIELD_SIZE-1))& (BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK)) - -/* --- Firmware Command Interface Definitions. --- We use BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 as host to FW mailbox. --- We use BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 as FW to Host mailbox. -*/ - -// Address where the command parameters are written. -#define DDRADDR_4_FWCMDS 0x100 - -// -// mailbox used for passing the FW Command address (DDR address) to -// firmware. -// -#define FW_CMD_POST_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 - -// Once we get a firmware command done interrupt, -// we will need to get the address of the response. -// This mailbox is written by FW before asserting the -// firmware command done interrupt. -#define FW_CMD_RES_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 - -/* --- RxDMA Picture QStatus Mailbox. --- RxDMA Picture Post Mailbox. < Write DDR address to this mailbox > - */ -#define RX_DMA_PIC_QSTS_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2 -#define RX_POST_MAILBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 -#define RX_POST_CONFIRM_SCRATCH BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5 -#define RX_START_SEQ_NUMBER 1 -#define INDICATE_TX_DONE_REG BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9 - -/* --- At the end of the picture frame there is the Link's Y0 data --- and there is Width data. The driver will copy this 32 bit data to Y[0] --- location. This makes the Flea PIB compatible with Link. --- Also note that Flea is capable of putting out the odd size picture widths --- so the PicWidth field is the actual picture width of the picture. In link --- We were only getting 1920,1280 or 720 as picture widths. -*/ -#define PIC_PIB_DATA_OFFSET_FROM_END 4 -#define PIC_PIB_DATA_SIZE_IN_BYTES 4 //The data that use to be in Y[0] component -#define PIC_WIDTH_OFFSET_FROM_END 8 //Width information for the driver. -#define PIC_WIDTH_DATA_SIZE_IN_BYTES 4 //Width information for the driver. - -/* --- The format change PIB comes in a dummy frame now. --- The Width field has the format change flag (bit-31) which --- the driver uses to detect the format change now. -*/ -#define PIB_FORMAT_CHANGE_BIT BC_BIT(31) -#define PIB_EOS_DETECTED_BIT BC_BIT(30) - -#define FLEA_DECODE_ERROR_FLAG 0x800 - -/* --- Interrupt Mask, Set and Clear registers are exactly --- same as the interrupt status register. We will --- Use the following union for all the registers. -*/ -typedef -union -_FLEA_INTR_BITS_COMMON_ -{ - struct - { - uint32_t L0TxDMADone:1; // Bit-0 - uint32_t L0TxDMAErr:1; // Bit-1 - uint32_t L0YRxDMADone:1; // Bit-2 - uint32_t L0YRxDMAErr:1; // Bit-3 - uint32_t L0UVRxDMADone:1; // Bit-4 - uint32_t L0UVRxDMAErr:1; // Bit-5 - uint32_t Reserved1:2; // Bit-6-7 - uint32_t L1TxDMADone:1; // Bit-8 - uint32_t L1TxDMAErr:1; // Bit-9 - uint32_t L1YRxDMADone:1; // Bit-10 - uint32_t L1YRxDMAErr:1; // Bit-11 - uint32_t L1UVRxDMADone:1; // Bit-12 - uint32_t L1UVRxDMAErr:1; // Bit-13 - uint32_t Reserved2:2; // Bit-14-15 - uint32_t ArmMbox0Int:1; // Bit-16 - uint32_t ArmMbox1Int:1; // Bit-17 - uint32_t ArmMbox2Int:1; // Bit-18 - uint32_t ArmMbox3Int:1; // Bit-19 - uint32_t Reserved3:4; // Bit-20-23 - uint32_t PcieTgtUrAttn:1; // Bit-24 - uint32_t PcieTgtCaAttn:1; // Bit-25 - uint32_t HaltIntr:1; // Bit-26 - uint32_t Reserved4:5; // Bit-27-31 - }; - - uint32_t WholeReg; -}FLEA_INTR_BITS_COMMON; - -typedef FLEA_INTR_BITS_COMMON FLEA_INTR_STS_REG; -typedef FLEA_INTR_BITS_COMMON FLEA_MASK_REG; - -/* -================================================================ --- Flea power state machine --- FLEA_PS_NONE --- Enter to this state when system boots up and device is not open. --- FLEA_PS_ACTIVE: --- 1. Set when the device is started and FW downloaded. --- 2. We come to this state from FLEA_PS_LP_COMPLETE when --- 2.a Free list length becomes greater than X. [Same As Internal Pause Sequence] --- 2.b There is a firmware command issued. --- 3. We come to this state from FLEA_PS_LP_PENDING when --- 3.a Free list length becomes greater than X. [Same As Internal Pause Sequence] --- 3.b There is a firmware command Issued. --- FLEA_PS_LP_PENDING --- 1. Enter to this state from FLEA_PS_ACTIVE --- 1.a FLL becomes greater less than Y[Same as Internal Resume]. --- FLEA_PS_LP_COMPLETE --- 1. Enter in to this state from FLEA_PS_LP_PENDING --- 1.a There are no Pending TX, RX, and FW Command. --- 2. Enter to This state when the handle is closed. --- 3. Enter to this state From ACTIVE --- 3.a FLL < Y. --- 3.b There is no TX,RX and FW pending. --- 4. Enter this state when RX is not running, either before it is started or after it is stopped. -================================================================= -*/ -typedef -enum -_FLEA_POWER_STATES_ -{ - FLEA_PS_NONE=0, - FLEA_PS_STOPPED, - FLEA_PS_ACTIVE, - FLEA_PS_LP_PENDING, - FLEA_PS_LP_COMPLETE -}FLEA_POWER_STATES; - -typedef enum _FLEA_STATE_CH_EVENT_ -{ - FLEA_EVT_NONE=0, - FLEA_EVT_START_DEVICE, - FLEA_EVT_STOP_DEVICE, - FLEA_EVT_FLL_CHANGE, - FLEA_EVT_FW_CMD_POST, - FLEA_EVT_CMD_COMP -}FLEA_STATE_CH_EVENT; - -#define TEST_BIT(_value_,_bit_number_) (_value_ & (0x00000001 << _bit_number_)) - -#define CLEAR_BIT(_value_,_bit_number_)\ -{_value_ = _value_ & (~(0x00000001 << _bit_number_));} - -#define SET_BIT(_value_,_bit_number_)\ -{_value_ |= (0x01 << _bit_number_);} - -#endif - diff -Nru crystalhd-0.0~git20101012.a3a83b8/driver/linux/Makefile.in crystalhd-0.0~git20101029.6df10a0/driver/linux/Makefile.in --- crystalhd-0.0~git20101012.a3a83b8/driver/linux/Makefile.in 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/driver/linux/Makefile.in 1970-01-01 00:00:00.000000000 +0000 @@ -1,48 +0,0 @@ -# -# Broadcom Crystal HD (BCM970012) controller Makefile. -# -# -KDIR = @KERN_DIR@ - - -INCLUDES = -I$(KDIR)/include -INCLUDES += -I$(src)/../../include -INCLUDES += -I$(src)/../../include/link -INCLUDES += -I$(src)/../../include/flea -INCLUDES += -I$(src)/../../include/flea/70015/magnum/basemodules/chp/70015/rdb/a0 - -EXTRA_CFLAGS = -D__KERNEL__ -DMODULE $(INCLUDES) $(INC) -EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -Werror -O2 - -OBJ := crystalhd_lnx.o \ - crystalhd_misc.o \ - crystalhd_cmds.o \ - crystalhd_hw.o \ - crystalhd_linkfuncs.o \ - crystalhd_fleafuncs.o \ - crystalhd_flea_ddr.o - -PWD = $(shell pwd) - -obj-m := crystalhd.o - crystalhd-objs := $(OBJ) - -all: - $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules - -install: - if [ -e "/lib/udev/rules.d" ] ; then cp -f 20-crystalhd.rules /lib/udev/rules.d/ ; fi - if [ -e "/etc/udev/rules.d" ] ; then cp -f 20-crystalhd.rules /etc/udev/rules.d/ ; fi - install -d /lib/modules/$(shell uname -r)/kernel/drivers/video/broadcom - install -m 0644 crystalhd.ko /lib/modules/$(shell uname -r)/kernel/drivers/video/broadcom - /sbin/depmod -a - -clean: - rm -f *.map *.list *.o *.ko crystalhd.mod.c $(OBJ) - -distclean: - rm -f *.map *.list *.o *.ko crystalhd.mod.c $(OBJ) - rm -f configure config.status config.log *~* - rm -rf autom4te.cache - rm -f Makefile - rm -f Module.symvers diff -Nru crystalhd-0.0~git20101012.a3a83b8/examples/hellobcm.cpp crystalhd-0.0~git20101029.6df10a0/examples/hellobcm.cpp --- crystalhd-0.0~git20101012.a3a83b8/examples/hellobcm.cpp 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/examples/hellobcm.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,271 +0,0 @@ -#include -#include -#include -#include -#include -#include "bc_dts_types.h" -#include "libcrystalhd_if.h" -#include -#include -#include - -#define TRY_CALL_1(func, p1, errmsg) \ - if (BC_STS_SUCCESS != func(p1)) \ - throw errmsg; - -#define TRY_CALL_2(func, p1, p2, errmsg) \ - if (BC_STS_SUCCESS != func(p1, p2)) \ - throw errmsg; - -#define TRY_CALL_5(func, p1, p2, p3, p4, p5, errmsg) \ - if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5)) \ - throw errmsg; - -#define TRY_CALL_6(func, p1, p2, p3, p4, p5, p6, errmsg) \ - if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5, p6)) \ - throw errmsg; - -#define OUTPUT_PROC_TIMEOUT 2000 - -int main() -{ - BC_STATUS ret; - HANDLE device = 0; - std::fstream inFile; - try - { - printf("starting up\n"); - // Initialize the Link and Decoder devices - uint32_t mode = DTS_PLAYBACK_MODE | DTS_LOAD_FILE_PLAY_FW | DTS_SKIP_TX_CHK_CPB | DTS_DFLT_RESOLUTION(vdecRESOLUTION_720p29_97); - ret = DtsDeviceOpen(&device, mode); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsDeviceOpen failed\n"); - throw "Failed to open device"; - } - ret = DtsOpenDecoder(device, BC_STREAM_TYPE_ES); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsOpenDecoder failed\n"); - throw "Failed to open decoder"; - } - ret = DtsSetVideoParams(device, BC_VID_ALGO_H264, FALSE, FALSE, TRUE, 0x80000000 | vdecFrameRate23_97); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsSetVideoParams failed\n"); - throw "Failed to set video params"; - } - ret = DtsSetColorSpace(device, MODE422_YUY2); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsSetColorSpace failed\n"); - throw "Failed to set colorspace mode"; - } - ret = DtsStartDecoder(device); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsStartDecoder failed\n"); - throw "Failed to start decoder"; - } - ret = DtsStartCapture(device); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsStartCapture failed\n"); - throw "Failed to start capture"; - } - printf("try calls done\n"); - - // Open the input stream - inFile.open("/tmp/test_video.264", std::ios::in | std::ios::binary); - if (!inFile.is_open()) - throw "Unable to open input file"; - else - printf("file opened successfully\n"); - - // Create a 4-byte aligned input buffer - uint8_t oddBytes = 0; - uint32_t inputLen = 32768; - uint8_t* input = (uint8_t*)malloc(inputLen+4); - printf("Input Buffer: %p\n", input); - if(((uintptr_t)input)%4) - oddBytes = 4 - ((uint8_t)((uintptr_t)input % 4)); - uint8_t* input_aligned = input + oddBytes; - printf("Aligned Input Buffer: %p, Offset = %d\n", input_aligned, oddBytes); - - // Create a 4-byte aligned output buffer - uint32_t ysize = 4147200; // 1920 x 1080 - uint32_t uvsize = 0; - uint8_t* rawBuf = (uint8_t*)malloc(ysize + uvsize + 4); - uint8_t* alignedBuf = rawBuf; - if(((uintptr_t)rawBuf)%4) - { - oddBytes = 4 - ((uint8_t)((uintptr_t)rawBuf % 4)); - alignedBuf = rawBuf + oddBytes; - printf("Aligned Buffer: %p, Offset = %d\n", alignedBuf, oddBytes); - } - - // If UV is in use, it's data immediately follows Y - uint8_t* ybuf = alignedBuf; - printf("Y Buffer: %p\n", ybuf); - uint8_t* uvbuf = NULL; - if (uvsize) - { - uvbuf = alignedBuf + ysize; - printf("UV Buffer: %p\n", ybuf); - } - - bool needData = true; - uint32_t bytesRead = 0; - bool formatChanged = false; - - // Open the output stream - //std::fstream outFile; - //outFile.open("/home/davilla/dozer/dump.yuv", std::ios::binary | std::ios::out); - uint32_t chunksSent = 0; - uint32_t bytesSent = 0; - uint32_t picsDecoded = 0; - uint32_t lastDecoded = 0xFF; - for (;;) - { - for (int i = 0; i < 6; i++) - { - // Read from input file if previously-read data was sent successfully - if (needData) - { - inFile.read((char*)input, inputLen); - if (inFile.fail()) - { - printf("Read %d pictures\n", picsDecoded); - throw "Unable to read input file"; - } - else if (inFile.eof()) - throw "Reached end of input file"; - - bytesRead += inputLen; - } - - // Push input data to driver - ret = DtsProcInput(device, input, inputLen, 0, 0); - if (ret == BC_STS_SUCCESS) - { - chunksSent++; - bytesSent += inputLen; - } - else - printf("DtsProcInput returned %d\n", ret); - usleep(1000); - needData = (ret == BC_STS_SUCCESS); // Only need more data if the send succeeded - } - - // Prepare output structure - BC_DTS_PROC_OUT output; - memset(&output, 0, sizeof(BC_DTS_PROC_OUT)); - output.PicInfo.width = 1920; - output.PicInfo.height = 1080; - output.Ybuff = ybuf; - output.YbuffSz = ysize/4; - output.UVbuff = uvbuf; - output.UVbuffSz = uvsize/4; - output.PoutFlags = BC_POUT_FLAGS_SIZE; - - // Request decoded data from the driver - ret = DtsProcOutput(device, OUTPUT_PROC_TIMEOUT, &output); - if (ret == BC_STS_SUCCESS) - { - if (!(output.PoutFlags & BC_POUT_FLAGS_PIB_VALID)) - { - printf("Invalid PIB received. Skipping picture. Flags: 0x%08x\n", output.PoutFlags); - continue; - } - picsDecoded++; - if (output.PicInfo.picture_number == lastDecoded) - { - /*BC_DTS_STATUS stat; - if (BC_STS_SUCCESS == DtsGetDriverStatus(device, &stat)) - { - printf("Driver Status\n-------------------\n", stat.ReadyListCount); - printf("ReadyListCount: %u\n", stat.ReadyListCount); - printf("FreeListCount: %u\n", stat.FreeListCount); - printf("FramesDropped: %u\n", stat.FramesDropped); - printf("FramesCaptured: %u\n", stat.FramesCaptured); - printf("FramesRepeated: %u\n", stat.FramesRepeated); - printf("InputCount: %u (ChunksSent: %u)\n", stat.ReadyListCount, chunksSent); - printf("InputTotalSize: %llu (BytesSent: %u)\n", stat.InputTotalSize, bytesSent); - printf("InputBusyCount: %u\n", stat.InputBusyCount); - printf("PIBMissCount: %u\n", stat.PIBMissCount); - }*/ - continue; - } - lastDecoded = output.PicInfo.picture_number; - printf("Received Output. Bytes In: %d, Y: %d, UV: %d, Number: %d, H: %d, W: %d, Flags: 0x%08x\n", bytesSent, output.YBuffDoneSz, output.UVBuffDoneSz, output.PicInfo.picture_number, output.PicInfo.height, output.PicInfo.width, output.PoutFlags); -/* - std::fstream picFile; - char picName[255]; - sprintf(picName, "/home/davilla/dozer/frames/picture_%d.yuv", picsDecoded); - picFile.open(picName, std::ios::binary | std::ios::out); - picFile.write((const char*)output.Ybuff, ysize); - output.PicInfo.picture_number -= 3; // Adjust for start-up pictures - picFile.close(); - //outFile.write((const char*)output.Ybuff, ysize); -*/ - } - else if (ret == BC_STS_FMT_CHANGE) - { - printf("Format Change Detected. Flags: 0x%08x\n", output.PoutFlags); - if ((output.PoutFlags & BC_POUT_FLAGS_PIB_VALID) && (output.PoutFlags & BC_POUT_FLAGS_FMT_CHANGE)) - { - // Read format data from driver - printf("New Format\n----------------------------------\n"); - printf("\tTimeStamp: %llu\n", output.PicInfo.timeStamp); - printf("\tPicture Number: %u\n", output.PicInfo.picture_number); - printf("\tWidth: %u\n", output.PicInfo.width); - printf("\tHeight: %u\n", output.PicInfo.height); - printf("\tChroma: 0x%03x\n", output.PicInfo.chroma_format); - printf("\tPulldown: %u\n", output.PicInfo.pulldown); - printf("\tFlags: 0x%08x\n", output.PicInfo.flags); - printf("\tFrame Rate/Res: %u\n", output.PicInfo.frame_rate); - printf("\tAspect Ratio: %u\n", output.PicInfo.aspect_ratio); - printf("\tColor Primaries: %u\n", output.PicInfo.colour_primaries); - printf("\tMetaData: %u\n", output.PicInfo.picture_meta_payload); - printf("\tSession Number: %u\n", output.PicInfo.sess_num); - printf("\tTimeStamp: %u\n", output.PicInfo.ycom); - printf("\tCustom Aspect: %u\n", output.PicInfo.custom_aspect_ratio_width_height); - printf("\tFrames to Drop: %u\n", output.PicInfo.n_drop); - printf("\tH264 Valid Fields: 0x%08x\n", output.PicInfo.other.h264.valid); - } - // TODO: Handle change - } - else if (ret == BC_STS_TIMEOUT) - { - printf("Timeout in DtsProcOutput. Accum Bytes: %d\n", bytesRead); - } - else if (ret == BC_STS_IO_XFR_ERROR) - { - printf("I/O Transfer Error.\n"); - } - else if (ret == BC_STS_IO_ERROR) - { - printf("I/O Error.\n"); - } - else if (ret == BC_STS_BUSY) - { - printf("Busy.\n"); - } - else - { - printf("DtsProcOutput return an unknown status: %d.\n", ret); - return 0; - } - } - } - catch(const char* msg) - { - printf("%s\n", msg); - } - catch (...) - { - printf("An unknown exception was thrown\n"); - } - - inFile.close(); - DtsStopDecoder(device); - DtsCloseDecoder(device); - DtsDeviceClose(device); - return 0; -} - - diff -Nru crystalhd-0.0~git20101012.a3a83b8/examples/Makefile crystalhd-0.0~git20101029.6df10a0/examples/Makefile --- crystalhd-0.0~git20101012.a3a83b8/examples/Makefile 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/examples/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,12 +0,0 @@ -CPP := g++ -CPPFLAGS += -D__LINUX_USER__ -LDFLAGS += -lcrystalhd -lpthread -INCLUDES += -I../include/ -I../linux_lib/libcrystalhd/ - -% : %.cpp - $(CPP) $(INCLUDES) $(CPPFLAGS) $(LDFLAGS) -o $@ $< - -all: hellobcm mpeg2test - -clean: - rm hellobcm mpeg2test diff -Nru crystalhd-0.0~git20101012.a3a83b8/examples/mpeg2test.cpp crystalhd-0.0~git20101029.6df10a0/examples/mpeg2test.cpp --- crystalhd-0.0~git20101012.a3a83b8/examples/mpeg2test.cpp 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/examples/mpeg2test.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,277 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define TRY_CALL_1(func, p1, errmsg) \ - if (BC_STS_SUCCESS != func(p1)) \ - throw errmsg; - -#define TRY_CALL_2(func, p1, p2, errmsg) \ - if (BC_STS_SUCCESS != func(p1, p2)) \ - throw errmsg; - -#define TRY_CALL_5(func, p1, p2, p3, p4, p5, errmsg) \ - if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5)) \ - throw errmsg; - -#define TRY_CALL_6(func, p1, p2, p3, p4, p5, p6, errmsg) \ - if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5, p6)) \ - throw errmsg; - -#define OUTPUT_PROC_TIMEOUT 2000 - -int main() -{ - BC_STATUS ret; - HANDLE device = 0; - std::fstream inFile; - try - { - printf("starting up\n"); - // Initialize the Link and Decoder devices - uint32_t mode = DTS_PLAYBACK_MODE | - DTS_LOAD_FILE_PLAY_FW | - DTS_SKIP_TX_CHK_CPB | - DTS_DFLT_RESOLUTION(vdecRESOLUTION_1080i29_97); - - ret = DtsDeviceOpen(&device, mode); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsDeviceOpen failed\n"); - throw "Failed to open device"; - } - ret = DtsOpenDecoder(device, BC_STREAM_TYPE_PES); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsOpenDecoder failed\n"); - throw "Failed to open decoder"; - } - ret = DtsSetVideoParams(device, BC_VID_ALGO_MPEG2, FALSE, FALSE, TRUE, 0); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsSetVideoParams failed\n"); - throw "Failed to set video params"; - } - ret = DtsSetColorSpace(device, MODE422_YUY2); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsSetColorSpace failed\n"); - throw "Failed to set colorspace mode"; - } - ret = DtsStartDecoder(device); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsStartDecoder failed\n"); - throw "Failed to start decoder"; - } - ret = DtsStartCapture(device); - if (ret != BC_STS_SUCCESS) { - printf("crap, DtsStartCapture failed\n"); - throw "Failed to start capture"; - } - printf("try calls done\n"); - - // Open the input stream - inFile.open("/tmp/test.mpeg2", std::ios::in | std::ios::binary); - if (!inFile.is_open()) - throw "Unable to open input file"; - else - printf("file opened successfully\n"); - - // Create a 4-byte aligned input buffer - uint8_t oddBytes = 0; - uint32_t inputLen = 32768; - uint8_t* input = (uint8_t*)malloc(inputLen+4); - printf("Input Buffer: %p\n", input); - if(((uintptr_t)input)%4) - oddBytes = 4 - ((uint8_t)((uintptr_t)input % 4)); - uint8_t* input_aligned = input + oddBytes; - printf("Aligned Input Buffer: %p, Offset = %d\n", input_aligned, oddBytes); - - // Create a 4-byte aligned output buffer - uint32_t ysize = 4147200; // 1920 x 1080 - uint32_t uvsize = 0; - uint8_t* rawBuf = (uint8_t*)malloc(ysize + uvsize + 4); - uint8_t* alignedBuf = rawBuf; - if(((uintptr_t)rawBuf)%4) - { - oddBytes = 4 - ((uint8_t)((uintptr_t)rawBuf % 4)); - alignedBuf = rawBuf + oddBytes; - printf("Aligned Buffer: %p, Offset = %d\n", alignedBuf, oddBytes); - } - - // If UV is in use, it's data immediately follows Y - uint8_t* ybuf = alignedBuf; - printf("Y Buffer: %p\n", ybuf); - uint8_t* uvbuf = NULL; - if (uvsize) - { - uvbuf = alignedBuf + ysize; - printf("UV Buffer: %p\n", ybuf); - } - - bool needData = true; - uint32_t bytesRead = 0; - bool formatChanged = false; - - // Open the output stream - //std::fstream outFile; - //outFile.open("/home/davilla/dozer/dump.yuv", std::ios::binary | std::ios::out); - uint32_t chunksSent = 0; - uint32_t bytesSent = 0; - uint32_t picsDecoded = 0; - uint32_t lastDecoded = 0xFF; - for (;;) - { - for (int i = 0; i < 2; i++) - { - // Read from input file if previously-read data was sent successfully - if (needData) - { - inFile.read((char*)input, inputLen); - if (inFile.fail()) - { - printf("Read %d pictures\n", picsDecoded); - throw "Unable to read input file"; - } - else if (inFile.eof()) - throw "Reached end of input file"; - - bytesRead += inputLen; - } - - // Push input data to driver - ret = DtsProcInput(device, input, inputLen, 0, 0); - if (ret == BC_STS_SUCCESS) - { - chunksSent++; - bytesSent += inputLen; - } - else - printf("DtsProcInput returned %d\n", ret); - usleep(1000); - needData = (ret == BC_STS_SUCCESS); // Only need more data if the send succeeded - } - - // Prepare output structure - BC_DTS_PROC_OUT output; - memset(&output, 0, sizeof(BC_DTS_PROC_OUT)); - output.PicInfo.width = 1920; - output.PicInfo.height = 1080; - output.Ybuff = ybuf; - output.YbuffSz = ysize/4; - output.UVbuff = uvbuf; - output.UVbuffSz = uvsize/4; - output.PoutFlags = BC_POUT_FLAGS_SIZE; - - // Request decoded data from the driver - ret = DtsProcOutput(device, OUTPUT_PROC_TIMEOUT, &output); - if (ret == BC_STS_SUCCESS) - { - if (!(output.PoutFlags & BC_POUT_FLAGS_PIB_VALID)) - { - printf("Invalid PIB received. Skipping picture. Flags: 0x%08x\n", output.PoutFlags); - continue; - } - picsDecoded++; - if (output.PicInfo.picture_number == lastDecoded) - { - /*BC_DTS_STATUS stat; - if (BC_STS_SUCCESS == DtsGetDriverStatus(device, &stat)) - { - printf("Driver Status\n-------------------\n", stat.ReadyListCount); - printf("ReadyListCount: %u\n", stat.ReadyListCount); - printf("FreeListCount: %u\n", stat.FreeListCount); - printf("FramesDropped: %u\n", stat.FramesDropped); - printf("FramesCaptured: %u\n", stat.FramesCaptured); - printf("FramesRepeated: %u\n", stat.FramesRepeated); - printf("InputCount: %u (ChunksSent: %u)\n", stat.ReadyListCount, chunksSent); - printf("InputTotalSize: %llu (BytesSent: %u)\n", stat.InputTotalSize, bytesSent); - printf("InputBusyCount: %u\n", stat.InputBusyCount); - printf("PIBMissCount: %u\n", stat.PIBMissCount); - }*/ - continue; - } - lastDecoded = output.PicInfo.picture_number; - printf("Received Output. Bytes In: %d, Y: %d, UV: %d, Number: %d, H: %d, W: %d, Flags: 0x%08x\n", bytesSent, output.YBuffDoneSz, output.UVBuffDoneSz, output.PicInfo.picture_number, output.PicInfo.height, output.PicInfo.width, output.PoutFlags); -/* - std::fstream picFile; - char picName[255]; - sprintf(picName, "/home/davilla/dozer/frames/picture_%d.yuv", picsDecoded); - picFile.open(picName, std::ios::binary | std::ios::out); - picFile.write((const char*)output.Ybuff, ysize); - output.PicInfo.picture_number -= 3; // Adjust for start-up pictures - picFile.close(); - //outFile.write((const char*)output.Ybuff, ysize); -*/ - } - else if (ret == BC_STS_FMT_CHANGE) - { - printf("Format Change Detected. Flags: 0x%08x\n", output.PoutFlags); - if ((output.PoutFlags & BC_POUT_FLAGS_PIB_VALID) && (output.PoutFlags & BC_POUT_FLAGS_FMT_CHANGE)) - { - // Read format data from driver - printf("New Format\n----------------------------------\n"); - printf("\tTimeStamp: %llu\n", output.PicInfo.timeStamp); - printf("\tPicture Number: %u\n", output.PicInfo.picture_number); - printf("\tWidth: %u\n", output.PicInfo.width); - printf("\tHeight: %u\n", output.PicInfo.height); - printf("\tChroma: 0x%03x\n", output.PicInfo.chroma_format); - printf("\tPulldown: %u\n", output.PicInfo.pulldown); - printf("\tFlags: 0x%08x\n", output.PicInfo.flags); - printf("\tFrame Rate/Res: %u\n", output.PicInfo.frame_rate); - printf("\tAspect Ratio: %u\n", output.PicInfo.aspect_ratio); - printf("\tColor Primaries: %u\n", output.PicInfo.colour_primaries); - printf("\tMetaData: %u\n", output.PicInfo.picture_meta_payload); - printf("\tSession Number: %u\n", output.PicInfo.sess_num); - printf("\tTimeStamp: %u\n", output.PicInfo.ycom); - printf("\tCustom Aspect: %u\n", output.PicInfo.custom_aspect_ratio_width_height); - printf("\tFrames to Drop: %u\n", output.PicInfo.n_drop); - printf("\tH264 Valid Fields: 0x%08x\n", output.PicInfo.other.h264.valid); - } - // TODO: Handle change - } - else if (ret == BC_STS_TIMEOUT) - { - printf("Timeout in DtsProcOutput. Accum Bytes: %d\n", bytesRead); - } - else if (ret == BC_STS_IO_XFR_ERROR) - { - printf("I/O Transfer Error.\n"); - } - else if (ret == BC_STS_IO_ERROR) - { - printf("I/O Error.\n"); - } - else if (ret == BC_STS_BUSY) - { - printf("Busy.\n"); - } - else - { - printf("DtsProcOutput return an unknown status: %d.\n", ret); - return 0; - } - } - } - catch(const char* msg) - { - printf("%s\n", msg); - } - catch (...) - { - printf("An unknown exception was thrown\n"); - } - - inFile.close(); - DtsStopDecoder(device); - DtsCloseDecoder(device); - DtsDeviceClose(device); - return 0; -} - - diff -Nru crystalhd-0.0~git20101012.a3a83b8/export-driver-for-staging.sh crystalhd-0.0~git20101029.6df10a0/export-driver-for-staging.sh --- crystalhd-0.0~git20101012.a3a83b8/export-driver-for-staging.sh 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/export-driver-for-staging.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,40 +0,0 @@ -#!/bin/bash -# -# Crude script to export kernel driver bits to a kernel git tree, -# under drivers/staging/crystalhd/ -# You still need to edit drivers/staging/{Kconfig,Makefile} by hand -# - -if [ -z "$1" ]; then - echo "You need to specify a path to a kernel tree" - exit 1 -fi - -kernelsrc=$1 -dest=$kernelsrc/drivers/staging/crystalhd -me=$PWD - -if [ ! -e $dest ]; then - mkdir $dest -fi - -# Copy files into place in kernel git tree -cp -a $me/driver/linux/*.c $dest/ -cp -a $me/driver/linux/*.h $dest/ -cp -a $me/include/*.h $dest/ -cp -a $me/include/link/bcm_70012_regs.h $dest/ -# except these -rm -f $dest/vdec_info.h $dest/7411d.h, $dest/libcrystalhd_version.h - -# Now run unifdef over the source to strip out legacy compat -pushd $dest -perl -pi -e 's|KERNEL_VERSION.*|1|g' *.c *.h -for f in *.c *.h -do - cp $f tmp-$f - unifdef -DLINUX_VERSION_CODE=2 tmp-$f > $f - rm -f tmp-$f -done - -# Now show diff and diffstat -git diff -p --stat diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/aclocal.m4 crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/aclocal.m4 --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/aclocal.m4 2010-10-12 20:47:17.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/aclocal.m4 1970-01-01 00:00:00.000000000 +0000 @@ -1,9129 +0,0 @@ -# generated automatically by aclocal 1.11.1 -*- Autoconf -*- - -# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, -# 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. -# This file is free software; the Free Software Foundation -# gives unlimited permission to copy and/or distribute it, -# with or without modifications, as long as this notice is preserved. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY, to the extent permitted by law; without -# even the implied warranty of MERCHANTABILITY or FITNESS FOR A -# PARTICULAR PURPOSE. - -m4_ifndef([AC_AUTOCONF_VERSION], - [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl -m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.67],, -[m4_warning([this file was generated for autoconf 2.67. -You have another version of autoconf. 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-esac - -# Try without a prefix underscore, then with it. -for ac_symprfx in "" "_"; do - - # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol. - symxfrm="\\1 $ac_symprfx\\2 \\2" - - # Write the raw and C identifiers. - if test "$lt_cv_nm_interface" = "MS dumpbin"; then - # Fake it for dumpbin and say T for any non-static function - # and D for any global variable. - # Also find C++ and __fastcall symbols from MSVC++, - # which start with @ or ?. - lt_cv_sys_global_symbol_pipe="$AWK ['"\ -" {last_section=section; section=\$ 3};"\ -" /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\ -" \$ 0!~/External *\|/{next};"\ -" / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\ -" {if(hide[section]) next};"\ -" {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\ -" {split(\$ 0, a, /\||\r/); split(a[2], s)};"\ -" s[1]~/^[@?]/{print s[1], s[1]; next};"\ -" s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\ -" ' prfx=^$ac_symprfx]" - else - lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[[ ]]\($symcode$symcode*\)[[ ]][[ ]]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'" - fi - - # Check to see that the pipe works correctly. - pipe_works=no - - rm -f conftest* - cat > conftest.$ac_ext <<_LT_EOF -#ifdef __cplusplus -extern "C" { -#endif -char nm_test_var; -void nm_test_func(void); -void nm_test_func(void){} -#ifdef __cplusplus -} -#endif -int main(){nm_test_var='a';nm_test_func();return(0);} -_LT_EOF - - if AC_TRY_EVAL(ac_compile); then - # Now try to grab the symbols. - nlist=conftest.nm - if AC_TRY_EVAL(NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist) && test -s "$nlist"; then - # Try sorting and uniquifying the output. - if sort "$nlist" | uniq > "$nlist"T; then - mv -f "$nlist"T "$nlist" - else - rm -f "$nlist"T - fi - - # Make sure that we snagged all the symbols we need. - if $GREP ' nm_test_var$' "$nlist" >/dev/null; then - if $GREP ' nm_test_func$' "$nlist" >/dev/null; then - cat <<_LT_EOF > conftest.$ac_ext -#ifdef __cplusplus -extern "C" { -#endif - -_LT_EOF - # Now generate the symbol file. - eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext' - - cat <<_LT_EOF >> conftest.$ac_ext - -/* The mapping between symbol names and symbols. */ -const struct { - const char *name; - void *address; -} -lt__PROGRAM__LTX_preloaded_symbols[[]] = -{ - { "@PROGRAM@", (void *) 0 }, -_LT_EOF - $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/ {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext - cat <<\_LT_EOF >> conftest.$ac_ext - {0, (void *) 0} -}; - -/* This works around a problem in FreeBSD linker */ -#ifdef FREEBSD_WORKAROUND -static const void *lt_preloaded_setup() { - return lt__PROGRAM__LTX_preloaded_symbols; -} -#endif - -#ifdef __cplusplus -} -#endif -_LT_EOF - # Now try linking the two files. - mv conftest.$ac_objext conftstm.$ac_objext - lt_save_LIBS="$LIBS" - lt_save_CFLAGS="$CFLAGS" - LIBS="conftstm.$ac_objext" - CFLAGS="$CFLAGS$_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)" - if AC_TRY_EVAL(ac_link) && test -s conftest${ac_exeext}; then - pipe_works=yes - fi - LIBS="$lt_save_LIBS" - CFLAGS="$lt_save_CFLAGS" - else - echo "cannot find nm_test_func in $nlist" >&AS_MESSAGE_LOG_FD - fi - else - echo "cannot find nm_test_var in $nlist" >&AS_MESSAGE_LOG_FD - fi - else - echo "cannot run $lt_cv_sys_global_symbol_pipe" >&AS_MESSAGE_LOG_FD - fi - else - echo "$progname: failed program was:" >&AS_MESSAGE_LOG_FD - cat conftest.$ac_ext >&5 - fi - rm -rf conftest* conftst* - - # Do not use the global_symbol_pipe unless it works. - if test "$pipe_works" = yes; then - break - else - lt_cv_sys_global_symbol_pipe= - fi -done -]) -if test -z "$lt_cv_sys_global_symbol_pipe"; then - lt_cv_sys_global_symbol_to_cdecl= -fi -if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then - AC_MSG_RESULT(failed) -else - AC_MSG_RESULT(ok) -fi - -_LT_DECL([global_symbol_pipe], [lt_cv_sys_global_symbol_pipe], [1], - [Take the output of nm and produce a listing of raw symbols and C names]) -_LT_DECL([global_symbol_to_cdecl], [lt_cv_sys_global_symbol_to_cdecl], [1], - [Transform the output of nm in a proper C declaration]) -_LT_DECL([global_symbol_to_c_name_address], - [lt_cv_sys_global_symbol_to_c_name_address], [1], - [Transform the output of nm in a C name address pair]) -_LT_DECL([global_symbol_to_c_name_address_lib_prefix], - [lt_cv_sys_global_symbol_to_c_name_address_lib_prefix], [1], - [Transform the output of nm in a C name address pair when lib prefix is needed]) -]) # _LT_CMD_GLOBAL_SYMBOLS - - -# _LT_COMPILER_PIC([TAGNAME]) -# --------------------------- -m4_defun([_LT_COMPILER_PIC], -[m4_require([_LT_TAG_COMPILER])dnl -_LT_TAGVAR(lt_prog_compiler_wl, $1)= -_LT_TAGVAR(lt_prog_compiler_pic, $1)= -_LT_TAGVAR(lt_prog_compiler_static, $1)= - -AC_MSG_CHECKING([for $compiler option to produce PIC]) -m4_if([$1], [CXX], [ - # C++ specific cases for pic, static, wl, etc. - if test "$GXX" = yes; then - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' - - case $host_os in - aix*) - # All AIX code is PIC. - if test "$host_cpu" = ia64; then - # AIX 5 now supports IA64 processor - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - fi - ;; - - amigaos*) - case $host_cpu in - powerpc) - # see comment about AmigaOS4 .so support - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - ;; - m68k) - # FIXME: we need at least 68020 code to build shared libraries, but - # adding the `-m68020' flag to GCC prevents building anything better, - # like `-m68040'. - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-m68020 -resident32 -malways-restore-a4' - ;; - esac - ;; - - beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) - # PIC is the default for these OSes. - ;; - mingw* | cygwin* | os2* | pw32* | cegcc*) - # This hack is so that the source file can tell whether it is being - # built for inclusion in a dll (and should export symbols for example). - # Although the cygwin gcc ignores -fPIC, still need this for old-style - # (--disable-auto-import) libraries - m4_if([$1], [GCJ], [], - [_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT']) - ;; - darwin* | rhapsody*) - # PIC is the default on this platform - # Common symbols not allowed in MH_DYLIB files - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fno-common' - ;; - *djgpp*) - # DJGPP does not support shared libraries at all - _LT_TAGVAR(lt_prog_compiler_pic, $1)= - ;; - interix[[3-9]]*) - # Interix 3.x gcc -fpic/-fPIC options generate broken code. - # Instead, we relocate shared libraries at runtime. - ;; - sysv4*MP*) - if test -d /usr/nec; then - _LT_TAGVAR(lt_prog_compiler_pic, $1)=-Kconform_pic - fi - ;; - hpux*) - # PIC is the default for 64-bit PA HP-UX, but not for 32-bit - # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag - # sets the default TLS model and affects inlining. - case $host_cpu in - hppa*64*) - ;; - *) - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - ;; - esac - ;; - *qnx* | *nto*) - # QNX uses GNU C++, but need to define -shared option too, otherwise - # it will coredump. - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared' - ;; - *) - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - ;; - esac - else - case $host_os in - aix[[4-9]]*) - # All AIX code is PIC. - if test "$host_cpu" = ia64; then - # AIX 5 now supports IA64 processor - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - else - _LT_TAGVAR(lt_prog_compiler_static, $1)='-bnso -bI:/lib/syscalls.exp' - fi - ;; - chorus*) - case $cc_basename in - cxch68*) - # Green Hills C++ Compiler - # _LT_TAGVAR(lt_prog_compiler_static, $1)="--no_auto_instantiation -u __main -u __premain -u _abort -r $COOL_DIR/lib/libOrb.a $MVME_DIR/lib/CC/libC.a $MVME_DIR/lib/classix/libcx.s.a" - ;; - esac - ;; - dgux*) - case $cc_basename in - ec++*) - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' - ;; - ghcx*) - # Green Hills C++ Compiler - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' - ;; - *) - ;; - esac - ;; - freebsd* | dragonfly*) - # FreeBSD uses GNU C++ - ;; - hpux9* | hpux10* | hpux11*) - case $cc_basename in - CC*) - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive' - if test "$host_cpu" != ia64; then - _LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z' - fi - ;; - aCC*) - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive' - case $host_cpu in - hppa*64*|ia64*) - # +Z the default - ;; - *) - _LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z' - ;; - esac - ;; - *) - ;; - esac - ;; - interix*) - # This is c89, which is MS Visual C++ (no shared libs) - # Anyone wants to do a port? - ;; - irix5* | irix6* | nonstopux*) - case $cc_basename in - CC*) - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' - # CC pic flag -KPIC is the default. - ;; - *) - ;; - esac - ;; - linux* | k*bsd*-gnu | kopensolaris*-gnu) - case $cc_basename in - KCC*) - # KAI C++ Compiler - _LT_TAGVAR(lt_prog_compiler_wl, $1)='--backend -Wl,' - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - ;; - ecpc* ) - # old Intel C++ for x86_64 which still supported -KPIC. - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' - ;; - icpc* ) - # Intel C++, used to be incompatible with GCC. - # ICC 10 doesn't accept -KPIC any more. - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' - ;; - pgCC* | pgcpp*) - # Portland Group C++ compiler - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fpic' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - ;; - cxx*) - # Compaq C++ - # Make sure the PIC flag is empty. It appears that all Alpha - # Linux and Compaq Tru64 Unix objects are PIC. - _LT_TAGVAR(lt_prog_compiler_pic, $1)= - _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' - ;; - xlc* | xlC*) - # IBM XL 8.0 on PPC - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-qpic' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-qstaticlink' - ;; - *) - case `$CC -V 2>&1 | sed 5q` in - *Sun\ C*) - # Sun C++ 5.9 - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ' - ;; - esac - ;; - esac - ;; - lynxos*) - ;; - m88k*) - ;; - mvs*) - case $cc_basename in - cxx*) - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-W c,exportall' - ;; - *) - ;; - esac - ;; - netbsd* | netbsdelf*-gnu) - ;; - *qnx* | *nto*) - # QNX uses GNU C++, but need to define -shared option too, otherwise - # it will coredump. - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared' - ;; - osf3* | osf4* | osf5*) - case $cc_basename in - KCC*) - _LT_TAGVAR(lt_prog_compiler_wl, $1)='--backend -Wl,' - ;; - RCC*) - # Rational C++ 2.4.1 - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' - ;; - cxx*) - # Digital/Compaq C++ - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - # Make sure the PIC flag is empty. It appears that all Alpha - # Linux and Compaq Tru64 Unix objects are PIC. - _LT_TAGVAR(lt_prog_compiler_pic, $1)= - _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' - ;; - *) - ;; - esac - ;; - psos*) - ;; - solaris*) - case $cc_basename in - CC*) - # Sun C++ 4.2, 5.x and Centerline C++ - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ' - ;; - gcx*) - # Green Hills C++ Compiler - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-PIC' - ;; - *) - ;; - esac - ;; - sunos4*) - case $cc_basename in - CC*) - # Sun C++ 4.x - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - ;; - lcc*) - # Lucid - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' - ;; - *) - ;; - esac - ;; - sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) - case $cc_basename in - CC*) - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - ;; - esac - ;; - tandem*) - case $cc_basename in - NCC*) - # NonStop-UX NCC 3.20 - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' - ;; - *) - ;; - esac - ;; - vxworks*) - ;; - *) - _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no - ;; - esac - fi -], -[ - if test "$GCC" = yes; then - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' - - case $host_os in - aix*) - # All AIX code is PIC. - if test "$host_cpu" = ia64; then - # AIX 5 now supports IA64 processor - _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' - fi - ;; - - amigaos*) - case $host_cpu in - powerpc) - # see comment about AmigaOS4 .so support - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - ;; - m68k) - # FIXME: we need at least 68020 code to build shared libraries, but - # adding the `-m68020' flag to GCC prevents building anything better, - # like `-m68040'. - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-m68020 -resident32 -malways-restore-a4' - ;; - esac - ;; - - beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) - # PIC is the default for these OSes. - ;; - - mingw* | cygwin* | pw32* | os2* | cegcc*) - # This hack is so that the source file can tell whether it is being - # built for inclusion in a dll (and should export symbols for example). - # Although the cygwin gcc ignores -fPIC, still need this for old-style - # (--disable-auto-import) libraries - m4_if([$1], [GCJ], [], - [_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT']) - ;; - - darwin* | rhapsody*) - # PIC is the default on this platform - # Common symbols not allowed in MH_DYLIB files - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fno-common' - ;; - - hpux*) - # PIC is the default for 64-bit PA HP-UX, but not for 32-bit - # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag - # sets the default TLS model and affects inlining. - case $host_cpu in - hppa*64*) - # +Z the default - ;; - *) - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - ;; - esac - ;; - - interix[[3-9]]*) - # Interix 3.x gcc -fpic/-fPIC options generate broken code. - # Instead, we relocate shared libraries at runtime. - ;; - - msdosdjgpp*) - # Just because we use GCC doesn't mean we suddenly get shared libraries - # on systems that don't support them. - _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no - enable_shared=no - ;; - - *nto* | *qnx*) - # QNX uses GNU C++, but need to define -shared option too, otherwise - # it will coredump. - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared' - ;; - - sysv4*MP*) - if test -d /usr/nec; then - _LT_TAGVAR(lt_prog_compiler_pic, $1)=-Kconform_pic - fi - ;; - - *) - _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' - ;; - esac - else - # PORTME Check for flag to pass linker flags through the system compiler. - case $host_os in - aix*) - _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' - if test "$host_cpu" = ia64; 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See the - * GNU Lesser General Public License for more details. - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - *******************************************************************/ diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/autogen.sh crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/autogen.sh --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/autogen.sh 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/autogen.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,98 +0,0 @@ -#!/bin/sh -# you can either set the environment variables AUTOCONF and AUTOMAKE -# to the right versions, or leave them unset and get the RedHat 7.3 defaults - -DIE=0 -package=gst-plugin -srcfile=src/main.c - -# autogen.sh helper functions (copied from GStreamer's common/ CVS module) -if test ! -f ./gst-autogen.sh; -then - echo There is something wrong with your source tree. - echo You are either missing ./gst-autogen.sh or not - echo running autogen.sh from the top-level source - echo directory. - exit 1 -fi -. ./gst-autogen.sh - -CONFIGURE_DEF_OPT='--enable-maintainer-mode --enable-debug' - -autogen_options $@ - -echo -n "+ check for build tools" -if test ! -z "$NOCHECK"; then echo " skipped"; else echo; fi -version_check "autoconf" "$AUTOCONF autoconf autoconf259 autoconf257 autoconf-2.54 autoconf-2.53 autoconf-2.52" \ - "ftp://ftp.gnu.org/pub/gnu/autoconf/" 2 52 || DIE=1 -version_check "automake" "$AUTOMAKE automake automake-1.9 automake19 automake-1.7 automake-1.6 automake-1.5" \ - "ftp://ftp.gnu.org/pub/gnu/automake/" 1 7 || DIE=1 -###version_check "autopoint" "autopoint" \ -### "ftp://ftp.gnu.org/pub/gnu/gettext/" 0 11 5 || DIE=1 -version_check "libtoolize" "$LIBTOOLIZE libtoolize glibtoolize" \ - "ftp://ftp.gnu.org/pub/gnu/libtool/" 1 5 0 || DIE=1 -version_check "pkg-config" "" \ - "http://www.freedesktop.org/software/pkgconfig" 0 8 0 || DIE=1 - -die_check $DIE - -autoconf_2_52d_check || DIE=1 -aclocal_check || DIE=1 -autoheader_check || DIE=1 - -die_check $DIE - -# if no arguments specified then this will be printed -if test -z "$*"; then - echo "+ checking for autogen.sh options" - echo " This autogen script will automatically run ./configure as:" - echo " ./configure $CONFIGURE_DEF_OPT" - echo " To pass any additional options, please specify them on the $0" - echo " command line." -fi - -tool_run "$aclocal" "-I m4/ $ACLOCAL_FLAGS" -tool_run "$libtoolize" "--copy --force" -tool_run "$autoheader" -tool_run "$autoconf" -tool_run "$automake" "-a -c" - -if test ! -f /usr/include/libcrystalhd/libcrystalhd_if.h; -then - echo libcrystalhd is not installed - echo install it from source or a binary package and re-run this script - exit 1 -fi - -# if enable exists, add an -enable option for each of the lines in that file -if test -f enable; then - for a in `cat enable`; do - CONFIGURE_FILE_OPT="--enable-$a" - done -fi - -# if disable exists, add an -disable option for each of the lines in that file -if test -f disable; then - for a in `cat disable`; do - CONFIGURE_FILE_OPT="$CONFIGURE_FILE_OPT --disable-$a" - done -fi - -test -n "$NOCONFIGURE" && { - echo "+ skipping configure stage for package $package, as requested." - echo "+ autogen.sh done." - exit 0 -} - -echo "+ running configure ... " -test ! -z "$CONFIGURE_DEF_OPT" && echo " ./configure default flags: $CONFIGURE_DEF_OPT" -test ! -z "$CONFIGURE_EXT_OPT" && echo " ./configure external flags: $CONFIGURE_EXT_OPT" -test ! -z "$CONFIGURE_FILE_OPT" && echo " ./configure enable/disable flags: $CONFIGURE_FILE_OPT" -echo - -./configure $CONFIGURE_DEF_OPT $CONFIGURE_EXT_OPT $CONFIGURE_FILE_OPT || { - echo " configure failed" - exit 1 -} - -echo "Now type 'make' to compile $package." diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/autoregen.sh crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/autoregen.sh --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/autoregen.sh 2010-10-12 20:47:16.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/autoregen.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,2 +0,0 @@ -#!/bin/sh -./autogen.sh $@ diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/ChangeLog crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/ChangeLog --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/ChangeLog 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/ChangeLog 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -Please refer to the release notes. \ No newline at end of file diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/config.guess crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/config.guess --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/config.guess 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/config.guess 1970-01-01 00:00:00.000000000 +0000 @@ -1,1526 +0,0 @@ -#! /bin/sh -# Attempt to guess a canonical system name. -# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 -# Free Software Foundation, Inc. - -timestamp='2008-01-23' - -# This file is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. -# -# As a special exception to the GNU General Public License, if you -# distribute this file as part of a program that contains a -# configuration script generated by Autoconf, you may include it under -# the same distribution terms that you use for the rest of that program. - - -# Originally written by Per Bothner . -# Please send patches to . Submit a context -# diff and a properly formatted ChangeLog entry. -# -# This script attempts to guess a canonical system name similar to -# config.sub. If it succeeds, it prints the system name on stdout, and -# exits with 0. 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then - echo rs6000-ibm-aix3.2.4 - else - echo rs6000-ibm-aix3.2 - fi - exit ;; - *:AIX:*:[456]) - IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` - if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then - IBM_ARCH=rs6000 - else - IBM_ARCH=powerpc - fi - if [ -x /usr/bin/oslevel ] ; then - IBM_REV=`/usr/bin/oslevel` - else - IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} - fi - echo ${IBM_ARCH}-ibm-aix${IBM_REV} - exit ;; - *:AIX:*:*) - echo rs6000-ibm-aix - exit ;; - ibmrt:4.4BSD:*|romp-ibm:BSD:*) - echo romp-ibm-bsd4.4 - exit ;; - ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and - echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to - exit ;; # report: romp-ibm BSD 4.3 - *:BOSX:*:*) - echo rs6000-bull-bosx - exit ;; - DPX/2?00:B.O.S.:*:*) - echo m68k-bull-sysv3 - exit ;; - 9000/[34]??:4.3bsd:1.*:*) - echo m68k-hp-bsd - exit ;; - hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) - echo m68k-hp-bsd4.4 - exit ;; - 9000/[34678]??:HP-UX:*:*) - HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` - case "${UNAME_MACHINE}" in - 9000/31? ) HP_ARCH=m68000 ;; - 9000/[34]?? ) HP_ARCH=m68k ;; - 9000/[678][0-9][0-9]) - if [ -x /usr/bin/getconf ]; then - sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` - sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` - case "${sc_cpu_version}" in - 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 - 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 - 532) # CPU_PA_RISC2_0 - case "${sc_kernel_bits}" in - 32) HP_ARCH="hppa2.0n" ;; - 64) HP_ARCH="hppa2.0w" ;; - '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 - esac ;; - esac - fi - if [ "${HP_ARCH}" = "" ]; then - eval $set_cc_for_build - sed 's/^ //' << EOF >$dummy.c - - #define _HPUX_SOURCE - #include - #include - - int main () - { - #if defined(_SC_KERNEL_BITS) - long bits = sysconf(_SC_KERNEL_BITS); - #endif - long cpu = sysconf (_SC_CPU_VERSION); - - switch (cpu) - { - case CPU_PA_RISC1_0: puts ("hppa1.0"); break; - case CPU_PA_RISC1_1: puts ("hppa1.1"); break; - case CPU_PA_RISC2_0: - #if defined(_SC_KERNEL_BITS) - switch (bits) - { - case 64: puts ("hppa2.0w"); break; - case 32: puts ("hppa2.0n"); break; - default: puts ("hppa2.0"); break; - } break; - #else /* !defined(_SC_KERNEL_BITS) */ - puts ("hppa2.0"); break; - #endif - default: puts ("hppa1.0"); break; - } - exit (0); - } -EOF - (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` - test -z "$HP_ARCH" && HP_ARCH=hppa - fi ;; - esac - if [ ${HP_ARCH} = "hppa2.0w" ] - then - eval $set_cc_for_build - - # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating - # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler - # generating 64-bit code. GNU and HP use different nomenclature: - # - # $ CC_FOR_BUILD=cc ./config.guess - # => hppa2.0w-hp-hpux11.23 - # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess - # => hppa64-hp-hpux11.23 - - if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | - grep __LP64__ >/dev/null - then - HP_ARCH="hppa2.0w" - else - HP_ARCH="hppa64" - fi - fi - echo ${HP_ARCH}-hp-hpux${HPUX_REV} - exit ;; - ia64:HP-UX:*:*) - HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` - echo ia64-hp-hpux${HPUX_REV} - exit ;; - 3050*:HI-UX:*:*) - eval $set_cc_for_build - sed 's/^ //' << EOF >$dummy.c - #include - int - main () - { - long cpu = sysconf (_SC_CPU_VERSION); - /* The order matters, because CPU_IS_HP_MC68K erroneously returns - true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct - results, however. */ - if (CPU_IS_PA_RISC (cpu)) - { - switch (cpu) - { - case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; - case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; - case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; - default: puts ("hppa-hitachi-hiuxwe2"); break; - } - } - else if (CPU_IS_HP_MC68K (cpu)) - puts ("m68k-hitachi-hiuxwe2"); - else puts ("unknown-hitachi-hiuxwe2"); - exit (0); - } -EOF - $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && - { echo "$SYSTEM_NAME"; exit; } - echo unknown-hitachi-hiuxwe2 - exit ;; - 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) - echo hppa1.1-hp-bsd - exit ;; - 9000/8??:4.3bsd:*:*) - echo hppa1.0-hp-bsd - exit ;; - *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) - echo hppa1.0-hp-mpeix - exit ;; - hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) - echo hppa1.1-hp-osf - exit ;; - hp8??:OSF1:*:*) - echo hppa1.0-hp-osf - exit ;; - i*86:OSF1:*:*) - if [ -x /usr/sbin/sysversion ] ; then - echo ${UNAME_MACHINE}-unknown-osf1mk - else - echo ${UNAME_MACHINE}-unknown-osf1 - fi - exit ;; - parisc*:Lites*:*:*) - echo hppa1.1-hp-lites - exit ;; - C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) - echo c1-convex-bsd - exit ;; - C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) - if getsysinfo -f scalar_acc - then echo c32-convex-bsd - else echo c2-convex-bsd - fi - exit ;; - C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) - echo c34-convex-bsd - exit ;; - C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) - echo c38-convex-bsd - exit ;; - C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) - echo c4-convex-bsd - exit ;; - CRAY*Y-MP:*:*:*) - echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit ;; - CRAY*[A-Z]90:*:*:*) - echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ - | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ - -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ - -e 's/\.[^.]*$/.X/' - exit ;; - CRAY*TS:*:*:*) - echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit ;; - CRAY*T3E:*:*:*) - echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit ;; - CRAY*SV1:*:*:*) - echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit ;; - *:UNICOS/mp:*:*) - echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit ;; - F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) - FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` - FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` - FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` - echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" - exit ;; - 5000:UNIX_System_V:4.*:*) - FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` - FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` - echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" - exit ;; - i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) - echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} - exit ;; - sparc*:BSD/OS:*:*) - echo sparc-unknown-bsdi${UNAME_RELEASE} - exit ;; - *:BSD/OS:*:*) - echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} - exit ;; - *:FreeBSD:*:*) - case ${UNAME_MACHINE} in - pc98) - echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - amd64) - echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - *) - echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - esac - exit ;; - i*:CYGWIN*:*) - echo ${UNAME_MACHINE}-pc-cygwin - exit ;; - *:MINGW*:*) - echo ${UNAME_MACHINE}-pc-mingw32 - exit ;; - i*:windows32*:*) - # uname -m includes "-pc" on this system. - echo ${UNAME_MACHINE}-mingw32 - exit ;; - i*:PW*:*) - echo ${UNAME_MACHINE}-pc-pw32 - exit ;; - *:Interix*:[3456]*) - case ${UNAME_MACHINE} in - x86) - echo i586-pc-interix${UNAME_RELEASE} - exit ;; - EM64T | authenticamd) - echo x86_64-unknown-interix${UNAME_RELEASE} - exit ;; - IA64) - echo ia64-unknown-interix${UNAME_RELEASE} - exit ;; - esac ;; - [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) - echo i${UNAME_MACHINE}-pc-mks - exit ;; - i*:Windows_NT*:* | Pentium*:Windows_NT*:*) - # How do we know it's Interix rather than the generic POSIX subsystem? - # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we - # UNAME_MACHINE based on the output of uname instead of i386? - echo i586-pc-interix - exit ;; - i*:UWIN*:*) - echo ${UNAME_MACHINE}-pc-uwin - exit ;; - amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*) - echo x86_64-unknown-cygwin - exit ;; - p*:CYGWIN*:*) - echo powerpcle-unknown-cygwin - exit ;; - prep*:SunOS:5.*:*) - echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit ;; - *:GNU:*:*) - # the GNU system - echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` - exit ;; - *:GNU/*:*:*) - # other systems with GNU libc and userland - echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu - exit ;; - i*86:Minix:*:*) - echo ${UNAME_MACHINE}-pc-minix - exit ;; - arm*:Linux:*:*) - eval $set_cc_for_build - if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ - | grep -q __ARM_EABI__ - then - echo ${UNAME_MACHINE}-unknown-linux-gnu - else - echo ${UNAME_MACHINE}-unknown-linux-gnueabi - fi - exit ;; - avr32*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; - cris:Linux:*:*) - echo cris-axis-linux-gnu - exit ;; - crisv32:Linux:*:*) - echo crisv32-axis-linux-gnu - exit ;; - frv:Linux:*:*) - echo frv-unknown-linux-gnu - exit ;; - ia64:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; - m32r*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; - m68*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; - mips:Linux:*:*) - eval $set_cc_for_build - sed 's/^ //' << EOF >$dummy.c - #undef CPU - #undef mips - #undef mipsel - #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) - CPU=mipsel - #else - #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) - CPU=mips - #else - CPU= - #endif - #endif -EOF - eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' - /^CPU/{ - s: ::g - p - }'`" - test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } - ;; - mips64:Linux:*:*) - eval $set_cc_for_build - sed 's/^ //' << EOF >$dummy.c - #undef CPU - #undef mips64 - #undef mips64el - #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) - CPU=mips64el - #else - #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) - CPU=mips64 - #else - CPU= - #endif - #endif -EOF - eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' - /^CPU/{ - s: ::g - p - }'`" - test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } - ;; - or32:Linux:*:*) - echo or32-unknown-linux-gnu - exit ;; - ppc:Linux:*:*) - echo powerpc-unknown-linux-gnu - exit ;; - ppc64:Linux:*:*) - echo powerpc64-unknown-linux-gnu - exit ;; - alpha:Linux:*:*) - case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in - EV5) UNAME_MACHINE=alphaev5 ;; - EV56) UNAME_MACHINE=alphaev56 ;; - PCA56) UNAME_MACHINE=alphapca56 ;; - PCA57) UNAME_MACHINE=alphapca56 ;; - EV6) UNAME_MACHINE=alphaev6 ;; - EV67) UNAME_MACHINE=alphaev67 ;; - EV68*) UNAME_MACHINE=alphaev68 ;; - esac - objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null - if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi - echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} - exit ;; - parisc:Linux:*:* | hppa:Linux:*:*) - # Look for CPU level - case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in - PA7*) echo hppa1.1-unknown-linux-gnu ;; - PA8*) echo hppa2.0-unknown-linux-gnu ;; - *) echo hppa-unknown-linux-gnu ;; - esac - exit ;; - parisc64:Linux:*:* | hppa64:Linux:*:*) - echo hppa64-unknown-linux-gnu - exit ;; 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exit; } - ;; - i*86:DYNIX/ptx:4*:*) - # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. - # earlier versions are messed up and put the nodename in both - # sysname and nodename. - echo i386-sequent-sysv4 - exit ;; - i*86:UNIX_SV:4.2MP:2.*) - # Unixware is an offshoot of SVR4, but it has its own version - # number series starting with 2... - # I am not positive that other SVR4 systems won't match this, - # I just have to hope. -- rms. - # Use sysv4.2uw... so that sysv4* matches it. - echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} - exit ;; - i*86:OS/2:*:*) - # If we were able to find `uname', then EMX Unix compatibility - # is probably installed. - echo ${UNAME_MACHINE}-pc-os2-emx - exit ;; - i*86:XTS-300:*:STOP) - echo ${UNAME_MACHINE}-unknown-stop - exit ;; - i*86:atheos:*:*) - echo ${UNAME_MACHINE}-unknown-atheos - exit ;; - i*86:syllable:*:*) - echo ${UNAME_MACHINE}-pc-syllable - exit ;; - i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) - echo i386-unknown-lynxos${UNAME_RELEASE} - exit ;; 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- PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort - # says - echo i586-unisys-sysv4 - exit ;; - *:UNIX_System_V:4*:FTX*) - # From Gerald Hewes . - # How about differentiating between stratus architectures? -djm - echo hppa1.1-stratus-sysv4 - exit ;; - *:*:*:FTX*) - # From seanf@swdc.stratus.com. - echo i860-stratus-sysv4 - exit ;; - i*86:VOS:*:*) - # From Paul.Green@stratus.com. - echo ${UNAME_MACHINE}-stratus-vos - exit ;; - *:VOS:*:*) - # From Paul.Green@stratus.com. - echo hppa1.1-stratus-vos - exit ;; - mc68*:A/UX:*:*) - echo m68k-apple-aux${UNAME_RELEASE} - exit ;; - news*:NEWS-OS:6*:*) - echo mips-sony-newsos6 - exit ;; - R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) - if [ -d /usr/nec ]; then - echo mips-nec-sysv${UNAME_RELEASE} - else - echo mips-unknown-sysv${UNAME_RELEASE} - fi - exit ;; - BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. - echo powerpc-be-beos - exit ;; - BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. - echo powerpc-apple-beos - exit ;; - BePC:BeOS:*:*) # BeOS running on Intel PC compatible. - echo i586-pc-beos - exit ;; - SX-4:SUPER-UX:*:*) - echo sx4-nec-superux${UNAME_RELEASE} - exit ;; - SX-5:SUPER-UX:*:*) - echo sx5-nec-superux${UNAME_RELEASE} - exit ;; - SX-6:SUPER-UX:*:*) - echo sx6-nec-superux${UNAME_RELEASE} - exit ;; - SX-7:SUPER-UX:*:*) - echo sx7-nec-superux${UNAME_RELEASE} - exit ;; - SX-8:SUPER-UX:*:*) - echo sx8-nec-superux${UNAME_RELEASE} - exit ;; - SX-8R:SUPER-UX:*:*) - echo sx8r-nec-superux${UNAME_RELEASE} - exit ;; - Power*:Rhapsody:*:*) - echo powerpc-apple-rhapsody${UNAME_RELEASE} - exit ;; - *:Rhapsody:*:*) - echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} - exit ;; - *:Darwin:*:*) - UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown - case $UNAME_PROCESSOR in - unknown) UNAME_PROCESSOR=powerpc ;; - esac - echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} - exit ;; - *:procnto*:*:* | *:QNX:[0123456789]*:*) - UNAME_PROCESSOR=`uname -p` - if test "$UNAME_PROCESSOR" = "x86"; then - UNAME_PROCESSOR=i386 - UNAME_MACHINE=pc - fi - echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} - exit ;; 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- *:ITS:*:*) - echo pdp10-unknown-its - exit ;; - SEI:*:*:SEIUX) - echo mips-sei-seiux${UNAME_RELEASE} - exit ;; - *:DragonFly:*:*) - echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` - exit ;; - *:*VMS:*:*) - UNAME_MACHINE=`(uname -p) 2>/dev/null` - case "${UNAME_MACHINE}" in - A*) echo alpha-dec-vms ; exit ;; - I*) echo ia64-dec-vms ; exit ;; - V*) echo vax-dec-vms ; exit ;; - esac ;; - *:XENIX:*:SysV) - echo i386-pc-xenix - exit ;; - i*86:skyos:*:*) - echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' - exit ;; - i*86:rdos:*:*) - echo ${UNAME_MACHINE}-pc-rdos - exit ;; -esac - -#echo '(No uname command or uname output not recognized.)' 1>&2 -#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 - -eval $set_cc_for_build -cat >$dummy.c < -# include -#endif -main () -{ -#if defined (sony) -#if defined (MIPSEB) - /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, - I don't know.... */ - printf ("mips-sony-bsd\n"); exit (0); -#else -#include - printf ("m68k-sony-newsos%s\n", -#ifdef NEWSOS4 - "4" -#else - "" -#endif - ); exit (0); -#endif -#endif - -#if defined (__arm) && defined (__acorn) && defined (__unix) - printf ("arm-acorn-riscix\n"); exit (0); -#endif - -#if defined (hp300) && !defined (hpux) - printf ("m68k-hp-bsd\n"); exit (0); -#endif - -#if defined (NeXT) -#if !defined (__ARCHITECTURE__) -#define __ARCHITECTURE__ "m68k" -#endif - int version; - version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; - if (version < 4) - printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); - else - printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); - exit (0); -#endif - -#if defined (MULTIMAX) || defined (n16) -#if defined (UMAXV) - printf ("ns32k-encore-sysv\n"); exit (0); -#else -#if defined (CMU) - printf ("ns32k-encore-mach\n"); exit (0); -#else - printf ("ns32k-encore-bsd\n"); exit (0); -#endif -#endif -#endif - -#if defined (__386BSD__) - printf ("i386-pc-bsd\n"); exit (0); -#endif - -#if defined (sequent) -#if defined (i386) - printf ("i386-sequent-dynix\n"); exit (0); -#endif -#if defined (ns32000) - printf ("ns32k-sequent-dynix\n"); exit (0); -#endif -#endif - -#if defined (_SEQUENT_) - struct utsname un; - - uname(&un); - - if (strncmp(un.version, "V2", 2) == 0) { - printf ("i386-sequent-ptx2\n"); exit (0); - } - if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ - printf ("i386-sequent-ptx1\n"); exit (0); - } - printf ("i386-sequent-ptx\n"); exit (0); - -#endif - -#if defined (vax) -# if !defined (ultrix) -# include -# if defined (BSD) -# if BSD == 43 - printf ("vax-dec-bsd4.3\n"); exit (0); -# else -# if BSD == 199006 - printf ("vax-dec-bsd4.3reno\n"); exit (0); -# else - printf ("vax-dec-bsd\n"); exit (0); -# endif -# endif -# else - printf ("vax-dec-bsd\n"); exit (0); -# endif -# else - printf ("vax-dec-ultrix\n"); exit (0); -# endif -#endif - -#if defined (alliant) && defined (i860) - printf ("i860-alliant-bsd\n"); exit (0); -#endif - - exit (1); -} -EOF - -$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && - { echo "$SYSTEM_NAME"; exit; } - -# Apollos put the system type in the environment. - -test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } - -# Convex versions that predate uname can use getsysinfo(1) - -if [ -x /usr/convex/getsysinfo ] -then - case `getsysinfo -f cpu_type` in - c1*) - echo c1-convex-bsd - exit ;; - c2*) - if getsysinfo -f scalar_acc - then echo c32-convex-bsd - else echo c2-convex-bsd - fi - exit ;; - c34*) - echo c34-convex-bsd - exit ;; - c38*) - echo c38-convex-bsd - exit ;; - c4*) - echo c4-convex-bsd - exit ;; - esac -fi - -cat >&2 < in order to provide the needed -information to handle your system. - -config.guess timestamp = $timestamp - -uname -m = `(uname -m) 2>/dev/null || echo unknown` -uname -r = `(uname -r) 2>/dev/null || echo unknown` -uname -s = `(uname -s) 2>/dev/null || echo unknown` -uname -v = `(uname -v) 2>/dev/null || echo unknown` - -/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` -/bin/uname -X = `(/bin/uname -X) 2>/dev/null` - -hostinfo = `(hostinfo) 2>/dev/null` -/bin/universe = `(/bin/universe) 2>/dev/null` -/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` -/bin/arch = `(/bin/arch) 2>/dev/null` -/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` -/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` - -UNAME_MACHINE = ${UNAME_MACHINE} -UNAME_RELEASE = ${UNAME_RELEASE} -UNAME_SYSTEM = ${UNAME_SYSTEM} -UNAME_VERSION = ${UNAME_VERSION} -EOF - -exit 1 - -# Local variables: -# eval: (add-hook 'write-file-hooks 'time-stamp) -# time-stamp-start: "timestamp='" -# time-stamp-format: "%:y-%02m-%02d" -# time-stamp-end: "'" -# End: diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/config.h.in crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/config.h.in --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/config.h.in 2010-10-12 20:47:18.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/config.h.in 1970-01-01 00:00:00.000000000 +0000 @@ -1,68 +0,0 @@ -/* config.h.in. Generated from configure.ac by autoheader. */ - -/* Define the version */ -#undef GST_PLUGIN_VERSION - -/* Define the release version */ -#undef GST_PLUGIN_VERSION_RELEASE - -/* Define to 1 if you have the header file. */ -#undef HAVE_DLFCN_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_INTTYPES_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_MEMORY_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_STDINT_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_STDLIB_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_STRINGS_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_STRING_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_SYS_STAT_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_SYS_TYPES_H - -/* Define to 1 if you have the header file. */ -#undef HAVE_UNISTD_H - -/* Define to the sub-directory in which libtool stores uninstalled libraries. - */ -#undef LT_OBJDIR - -/* Name of package */ -#undef PACKAGE - -/* Define to the address where bug reports for this package should be sent. */ -#undef PACKAGE_BUGREPORT - -/* Define to the full name of this package. */ -#undef PACKAGE_NAME - -/* Define to the full name and version of this package. */ -#undef PACKAGE_STRING - -/* Define to the one symbol short name of this package. */ -#undef PACKAGE_TARNAME - -/* Define to the home page for this package. */ -#undef PACKAGE_URL - -/* Define to the version of this package. */ -#undef PACKAGE_VERSION - -/* Define to 1 if you have the ANSI C header files. */ -#undef STDC_HEADERS - -/* Version number of package */ -#undef VERSION diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/config.sub crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/config.sub --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/config.sub 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/config.sub 1970-01-01 00:00:00.000000000 +0000 @@ -1,1658 +0,0 @@ -#! /bin/sh -# Configuration validation subroutine script. -# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 -# Free Software Foundation, Inc. - -timestamp='2008-01-16' - -# This file is (in principle) common to ALL GNU software. -# The presence of a machine in this file suggests that SOME GNU software -# can handle that machine. It does not imply ALL GNU software can. -# -# This file is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. -# -# As a special exception to the GNU General Public License, if you -# distribute this file as part of a program that contains a -# configuration script generated by Autoconf, you may include it under -# the same distribution terms that you use for the rest of that program. - - -# Please send patches to . Submit a context -# diff and a properly formatted ChangeLog entry. -# -# Configuration subroutine to validate and canonicalize a configuration type. -# Supply the specified configuration type as an argument. -# If it is invalid, we print an error message on stderr and exit with code 1. -# Otherwise, we print the canonical config type on stdout and succeed. - -# This file is supposed to be the same for all GNU packages -# and recognize all the CPU types, system types and aliases -# that are meaningful with *any* GNU software. -# Each package is responsible for reporting which valid configurations -# it does not support. The user should be able to distinguish -# a failure to support a valid configuration from a meaningless -# configuration. - -# The goal of this file is to map all the various variations of a given -# machine specification into a single specification in the form: -# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM -# or in some cases, the newer four-part form: -# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM -# It is wrong to echo any other type of specification. - -me=`echo "$0" | sed -e 's,.*/,,'` - -usage="\ -Usage: $0 [OPTION] CPU-MFR-OPSYS - $0 [OPTION] ALIAS - -Canonicalize a configuration name. - -Operation modes: - -h, --help print this help, then exit - -t, --time-stamp print date of last modification, then exit - -v, --version print version number, then exit - -Report bugs and patches to ." - -version="\ -GNU config.sub ($timestamp) - -Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. - -This is free software; see the source for copying conditions. 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We also -### recognize some manufacturers as not being operating systems, so we -### can provide default operating systems below. -case $os in - -sun*os*) - # Prevent following clause from handling this invalid input. - ;; - -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ - -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ - -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ - -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ - -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ - -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ - -apple | -axis | -knuth | -cray) - os= - basic_machine=$1 - ;; - -sim | -cisco | -oki | -wec | -winbond) - os= - basic_machine=$1 - ;; - -scout) - ;; - -wrs) - os=-vxworks - basic_machine=$1 - ;; - -chorusos*) - os=-chorusos - basic_machine=$1 - ;; - -chorusrdb) - os=-chorusrdb - basic_machine=$1 - ;; - -hiux*) - os=-hiuxwe2 - ;; - -sco6) - os=-sco5v6 - basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` - ;; 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- -psos*) - os=-psos - ;; - -mint | -mint[0-9]*) - basic_machine=m68k-atari - os=-mint - ;; -esac - -# Decode aliases for certain CPU-COMPANY combinations. -case $basic_machine in - # Recognize the basic CPU types without company name. - # Some are omitted here because they have special meanings below. - 1750a | 580 \ - | a29k \ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ - | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ - | bfin \ - | c4x | clipper \ - | d10v | d30v | dlx | dsp16xx \ - | fido | fr30 | frv \ - | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ - | i370 | i860 | i960 | ia64 \ - | ip2k | iq2000 \ - | m32c | m32r | m32rle | m68000 | m68k | m88k \ - | maxq | mb | microblaze | mcore | mep \ - | mips | mipsbe | mipseb | mipsel | mipsle \ - | mips16 \ - | mips64 | mips64el \ - | mips64vr | mips64vrel \ - | mips64orion | mips64orionel \ - | mips64vr4100 | mips64vr4100el \ - | mips64vr4300 | mips64vr4300el \ - | mips64vr5000 | mips64vr5000el \ - | mips64vr5900 | mips64vr5900el \ - | mipsisa32 | mipsisa32el \ - | mipsisa32r2 | mipsisa32r2el \ - | mipsisa64 | mipsisa64el \ - | mipsisa64r2 | mipsisa64r2el \ - | mipsisa64sb1 | mipsisa64sb1el \ - | mipsisa64sr71k | mipsisa64sr71kel \ - | mipstx39 | mipstx39el \ - | mn10200 | mn10300 \ - | mt \ - | msp430 \ - | nios | nios2 \ - | ns16k | ns32k \ - | or32 \ - | pdp10 | pdp11 | pj | pjl \ - | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ - | pyramid \ - | score \ - | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ - | sh64 | sh64le \ - | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ - | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ - | spu | strongarm \ - | tahoe | thumb | tic4x | tic80 | tron \ - | v850 | v850e \ - | we32k \ - | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ - | z8k) - basic_machine=$basic_machine-unknown - ;; - m6811 | m68hc11 | m6812 | m68hc12) - # Motorola 68HC11/12. - basic_machine=$basic_machine-unknown - os=-none - ;; - m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) - ;; - ms1) - basic_machine=mt-unknown - ;; - - # We use `pc' rather than `unknown' - # because (1) that's what they normally are, and - # (2) the word "unknown" tends to confuse beginning users. - i*86 | x86_64) - basic_machine=$basic_machine-pc - ;; - # Object if more than one company name word. - *-*-*) - echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 - exit 1 - ;; - # Recognize the basic CPU types with company name. - 580-* \ - | a29k-* \ - | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ - | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ - | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ - | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ - | avr-* | avr32-* \ - | bfin-* | bs2000-* \ - | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ - | clipper-* | craynv-* | cydra-* \ - | d10v-* | d30v-* | dlx-* \ - | elxsi-* \ - | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ - | h8300-* | h8500-* \ - | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ - | i*86-* | i860-* | i960-* | ia64-* \ - | ip2k-* | iq2000-* \ - | m32c-* | m32r-* | m32rle-* \ - | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ - | m88110-* | m88k-* | maxq-* | mcore-* \ - | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ - | mips16-* \ - | mips64-* | mips64el-* \ - | mips64vr-* | mips64vrel-* \ - | mips64orion-* | mips64orionel-* \ - | mips64vr4100-* | mips64vr4100el-* \ - | mips64vr4300-* | mips64vr4300el-* \ - | mips64vr5000-* | mips64vr5000el-* \ - | mips64vr5900-* | mips64vr5900el-* \ - | mipsisa32-* | mipsisa32el-* \ - | mipsisa32r2-* | mipsisa32r2el-* \ - | mipsisa64-* | mipsisa64el-* \ - | mipsisa64r2-* | mipsisa64r2el-* \ - | mipsisa64sb1-* | mipsisa64sb1el-* \ - | mipsisa64sr71k-* | mipsisa64sr71kel-* \ - | mipstx39-* | mipstx39el-* \ - | mmix-* \ - | mt-* \ - | msp430-* \ - | nios-* | nios2-* \ - | none-* | np1-* | ns16k-* | ns32k-* \ - | orion-* \ - | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ - | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ - | pyramid-* \ - | romp-* | rs6000-* \ - | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ - | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ - | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ - | sparclite-* \ - | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \ - | tahoe-* | thumb-* \ - | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ - | tron-* \ - | v850-* | v850e-* | vax-* \ - | we32k-* \ - | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ - | xstormy16-* | xtensa*-* \ - | ymp-* \ - | z8k-*) - ;; - # Recognize the basic CPU types without company name, with glob match. - xtensa*) - basic_machine=$basic_machine-unknown - ;; - # Recognize the various machine names and aliases which stand - # for a CPU type and a company and sometimes even an OS. - 386bsd) - basic_machine=i386-unknown - os=-bsd - ;; - 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) - basic_machine=m68000-att - ;; - 3b*) - basic_machine=we32k-att - ;; - a29khif) - basic_machine=a29k-amd - os=-udi - ;; - abacus) - basic_machine=abacus-unknown - ;; - adobe68k) - basic_machine=m68010-adobe - os=-scout - ;; - alliant | fx80) - basic_machine=fx80-alliant - ;; - altos | altos3068) - basic_machine=m68k-altos - ;; - am29k) - basic_machine=a29k-none - os=-bsd - ;; - amd64) - basic_machine=x86_64-pc - ;; - amd64-*) - basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - amdahl) - basic_machine=580-amdahl - os=-sysv - ;; - amiga | amiga-*) - basic_machine=m68k-unknown - ;; - amigaos | amigados) - basic_machine=m68k-unknown - os=-amigaos - ;; - amigaunix | amix) - basic_machine=m68k-unknown - os=-sysv4 - ;; - apollo68) - basic_machine=m68k-apollo - os=-sysv - ;; - apollo68bsd) - basic_machine=m68k-apollo - os=-bsd - ;; - aux) - basic_machine=m68k-apple - os=-aux - ;; - balance) - basic_machine=ns32k-sequent - os=-dynix - ;; - blackfin) - basic_machine=bfin-unknown - os=-linux - ;; - blackfin-*) - basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'` - os=-linux - ;; - c90) - basic_machine=c90-cray - os=-unicos - ;; - convex-c1) - basic_machine=c1-convex - os=-bsd - ;; - convex-c2) - basic_machine=c2-convex - os=-bsd - ;; - convex-c32) - basic_machine=c32-convex - os=-bsd - ;; - convex-c34) - basic_machine=c34-convex - os=-bsd - ;; - convex-c38) - basic_machine=c38-convex - os=-bsd - ;; - cray | j90) - basic_machine=j90-cray - os=-unicos - ;; - craynv) - basic_machine=craynv-cray - os=-unicosmp - ;; - cr16) - basic_machine=cr16-unknown - os=-elf - ;; - crds | unos) - basic_machine=m68k-crds - ;; - crisv32 | crisv32-* | etraxfs*) - basic_machine=crisv32-axis - ;; - cris | cris-* | etrax*) - basic_machine=cris-axis - ;; - crx) - basic_machine=crx-unknown - os=-elf - ;; - da30 | da30-*) - basic_machine=m68k-da30 - ;; - decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) - basic_machine=mips-dec - ;; - decsystem10* | dec10*) - basic_machine=pdp10-dec - os=-tops10 - ;; - decsystem20* | dec20*) - basic_machine=pdp10-dec - os=-tops20 - ;; - delta | 3300 | motorola-3300 | motorola-delta \ - | 3300-motorola | delta-motorola) - basic_machine=m68k-motorola - ;; - delta88) - basic_machine=m88k-motorola - os=-sysv3 - ;; - djgpp) - basic_machine=i586-pc - os=-msdosdjgpp - ;; - dpx20 | dpx20-*) - basic_machine=rs6000-bull - os=-bosx - ;; - dpx2* | dpx2*-bull) - basic_machine=m68k-bull - os=-sysv3 - ;; - ebmon29k) - basic_machine=a29k-amd - os=-ebmon - ;; - elxsi) - basic_machine=elxsi-elxsi - os=-bsd - ;; - encore | umax | mmax) - basic_machine=ns32k-encore - ;; - es1800 | OSE68k | ose68k | ose | OSE) - basic_machine=m68k-ericsson - os=-ose - ;; - fx2800) - basic_machine=i860-alliant - ;; - genix) - basic_machine=ns32k-ns - ;; - gmicro) - basic_machine=tron-gmicro - os=-sysv - ;; - go32) - basic_machine=i386-pc - os=-go32 - ;; - h3050r* | hiux*) - basic_machine=hppa1.1-hitachi - os=-hiuxwe2 - ;; - h8300hms) - basic_machine=h8300-hitachi - os=-hms - ;; - h8300xray) - basic_machine=h8300-hitachi - os=-xray - ;; - h8500hms) - basic_machine=h8500-hitachi - os=-hms - ;; - harris) - basic_machine=m88k-harris - os=-sysv3 - ;; - hp300-*) - basic_machine=m68k-hp - ;; - hp300bsd) - basic_machine=m68k-hp - os=-bsd - ;; - hp300hpux) - basic_machine=m68k-hp - os=-hpux - ;; - hp3k9[0-9][0-9] | hp9[0-9][0-9]) - basic_machine=hppa1.0-hp - ;; - hp9k2[0-9][0-9] | hp9k31[0-9]) - basic_machine=m68000-hp - ;; - hp9k3[2-9][0-9]) - basic_machine=m68k-hp - ;; - hp9k6[0-9][0-9] | hp6[0-9][0-9]) - basic_machine=hppa1.0-hp - ;; - hp9k7[0-79][0-9] | hp7[0-79][0-9]) - basic_machine=hppa1.1-hp - ;; - hp9k78[0-9] | hp78[0-9]) - # FIXME: really hppa2.0-hp - basic_machine=hppa1.1-hp - ;; - hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) - # FIXME: really hppa2.0-hp - basic_machine=hppa1.1-hp - ;; - hp9k8[0-9][13679] | hp8[0-9][13679]) - basic_machine=hppa1.1-hp - ;; - hp9k8[0-9][0-9] | hp8[0-9][0-9]) - basic_machine=hppa1.0-hp - ;; - hppa-next) - os=-nextstep3 - ;; - hppaosf) - basic_machine=hppa1.1-hp - os=-osf - ;; - hppro) - basic_machine=hppa1.1-hp - os=-proelf - ;; - i370-ibm* | ibm*) - basic_machine=i370-ibm - ;; -# I'm not sure what "Sysv32" means. Should this be sysv3.2? - i*86v32) - basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` - os=-sysv32 - ;; - i*86v4*) - basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` - os=-sysv4 - ;; - i*86v) - basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` - os=-sysv - ;; - i*86sol2) - basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` - os=-solaris2 - ;; - i386mach) - basic_machine=i386-mach - os=-mach - ;; - i386-vsta | vsta) - basic_machine=i386-unknown - os=-vsta - ;; - iris | iris4d) - basic_machine=mips-sgi - case $os in - -irix*) - ;; - *) - os=-irix4 - ;; - esac - ;; - isi68 | isi) - basic_machine=m68k-isi - os=-sysv - ;; - m68knommu) - basic_machine=m68k-unknown - os=-linux - ;; - m68knommu-*) - basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'` - os=-linux - ;; - m88k-omron*) - basic_machine=m88k-omron - ;; - magnum | m3230) - basic_machine=mips-mips - os=-sysv - ;; - merlin) - basic_machine=ns32k-utek - os=-sysv - ;; - mingw32) - basic_machine=i386-pc - os=-mingw32 - ;; - mingw32ce) - basic_machine=arm-unknown - os=-mingw32ce - ;; - miniframe) - basic_machine=m68000-convergent - ;; - *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) - basic_machine=m68k-atari - os=-mint - ;; - mips3*-*) - basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` - ;; - mips3*) - basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown - ;; - monitor) - basic_machine=m68k-rom68k - os=-coff - ;; - morphos) - basic_machine=powerpc-unknown - os=-morphos - ;; - msdos) - basic_machine=i386-pc - os=-msdos - ;; - ms1-*) - basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` - ;; - mvs) - basic_machine=i370-ibm - os=-mvs - ;; - ncr3000) - basic_machine=i486-ncr - os=-sysv4 - ;; - netbsd386) - basic_machine=i386-unknown - os=-netbsd - ;; - netwinder) - basic_machine=armv4l-rebel - os=-linux - ;; - news | news700 | news800 | news900) - basic_machine=m68k-sony - os=-newsos - ;; - news1000) - basic_machine=m68030-sony - os=-newsos - ;; - news-3600 | risc-news) - basic_machine=mips-sony - os=-newsos - ;; - necv70) - basic_machine=v70-nec - os=-sysv - ;; - next | m*-next ) - basic_machine=m68k-next - case $os in - -nextstep* ) - ;; - -ns2*) - os=-nextstep2 - ;; - *) - os=-nextstep3 - ;; - esac - ;; - nh3000) - basic_machine=m68k-harris - os=-cxux - ;; - nh[45]000) - basic_machine=m88k-harris - os=-cxux - ;; - nindy960) - basic_machine=i960-intel - os=-nindy - ;; - mon960) - basic_machine=i960-intel - os=-mon960 - ;; - nonstopux) - basic_machine=mips-compaq - os=-nonstopux - ;; - np1) - basic_machine=np1-gould - ;; - nsr-tandem) - basic_machine=nsr-tandem - ;; - op50n-* | op60c-*) - basic_machine=hppa1.1-oki - os=-proelf - ;; - openrisc | openrisc-*) - basic_machine=or32-unknown - ;; - os400) - basic_machine=powerpc-ibm - os=-os400 - ;; - OSE68000 | ose68000) - basic_machine=m68000-ericsson - os=-ose - ;; - os68k) - basic_machine=m68k-none - os=-os68k - ;; - pa-hitachi) - basic_machine=hppa1.1-hitachi - os=-hiuxwe2 - ;; - paragon) - basic_machine=i860-intel - os=-osf - ;; - parisc) - basic_machine=hppa-unknown - os=-linux - ;; - parisc-*) - basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'` - os=-linux - ;; - pbd) - basic_machine=sparc-tti - ;; - pbb) - basic_machine=m68k-tti - ;; - pc532 | pc532-*) - basic_machine=ns32k-pc532 - ;; - pc98) - basic_machine=i386-pc - ;; - pc98-*) - basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - pentium | p5 | k5 | k6 | nexgen | viac3) - basic_machine=i586-pc - ;; - pentiumpro | p6 | 6x86 | athlon | athlon_*) - basic_machine=i686-pc - ;; - pentiumii | pentium2 | pentiumiii | pentium3) - basic_machine=i686-pc - ;; - pentium4) - basic_machine=i786-pc - ;; - pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) - basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - pentiumpro-* | p6-* | 6x86-* | athlon-*) - basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) - basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - pentium4-*) - basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - pn) - basic_machine=pn-gould - ;; - power) basic_machine=power-ibm - ;; - ppc) basic_machine=powerpc-unknown - ;; - ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - ppcle | powerpclittle | ppc-le | powerpc-little) - basic_machine=powerpcle-unknown - ;; - ppcle-* | powerpclittle-*) - basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - ppc64) basic_machine=powerpc64-unknown - ;; - ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - ppc64le | powerpc64little | ppc64-le | powerpc64-little) - basic_machine=powerpc64le-unknown - ;; - ppc64le-* | powerpc64little-*) - basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - ps2) - basic_machine=i386-ibm - ;; - pw32) - basic_machine=i586-unknown - os=-pw32 - ;; - rdos) - basic_machine=i386-pc - os=-rdos - ;; - rom68k) - basic_machine=m68k-rom68k - os=-coff - ;; - rm[46]00) - basic_machine=mips-siemens - ;; - rtpc | rtpc-*) - basic_machine=romp-ibm - ;; - s390 | s390-*) - basic_machine=s390-ibm - ;; - s390x | s390x-*) - basic_machine=s390x-ibm - ;; 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"write failure creating $CONFIG_STATUS" "$LINENO" 5 - - -# configure is writing to config.log, and then calls config.status. -# config.status does its own redirection, appending to config.log. -# Unfortunately, on DOS this fails, as config.log is still kept open -# by configure, so config.status won't be able to write to it; its -# output is simply discarded. So we exec the FD to /dev/null, -# effectively closing config.log, so it can be properly (re)opened and -# appended to by config.status. When coming back to configure, we -# need to make the FD available again. -if test "$no_create" != yes; then - ac_cs_success=: - ac_config_status_args= - test "$silent" = yes && - ac_config_status_args="$ac_config_status_args --quiet" - exec 5>/dev/null - $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false - exec 5>>config.log - # Use ||, not &&, to avoid exiting from the if with $? = 1, which - # would make configure fail if this is the last instruction. - $ac_cs_success || as_fn_exit 1 -fi -if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 -$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} -fi - - diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/configure.ac crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/configure.ac --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/configure.ac 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/configure.ac 1970-01-01 00:00:00.000000000 +0000 @@ -1,133 +0,0 @@ -AC_INIT - -dnl versions of gstreamer and plugins-base -GST_MAJORMINOR=0.10 -GST_REQUIRED=0.10.0 -GSTPB_REQUIRED=0.10.0 - -dnl fill in your package name and version here -dnl the fourth (nano) number should be 0 for a release, 1 for CVS, -dnl and 2... for a prerelease - -dnl when going to/from release please set the nano correctly ! -dnl releases only do Wall, cvs and prerelease does Werror too -AS_VERSION(gst-bcmdec, GST_PLUGIN_VERSION, 0, 10, 0, 37, - GST_PLUGIN_CVS="no", GST_PLUGIN_CVS="yes") - -dnl AM_MAINTAINER_MODE provides the option to enable maintainer mode -AM_MAINTAINER_MODE - -AM_INIT_AUTOMAKE($PACKAGE, $VERSION) - -AC_PREFIX_DEFAULT(/usr) - -dnl make aclocal work in maintainer mode -AC_SUBST(ACLOCAL_AMFLAGS, "-I m4") - -AM_CONFIG_HEADER(config.h) - -dnl check for tools -AC_PROG_CC -AC_PROG_LIBTOOL - - -dnl decide on error flags -AS_COMPILER_FLAG(-Wall, GST_WALL="yes", GST_WALL="no") - -if test "x$GST_WALL" = "xyes"; then - GST_ERROR="$GST_ERROR -Wall" - - if test "x$GST_PLUGIN_CVS" = "xyes"; then - AS_COMPILER_FLAG(-Werror,GST_ERROR="$GST_ERROR -Werror",GST_ERROR="$GST_ERROR") - fi -fi - -dnl Check for pkgconfig first -AC_CHECK_PROG(HAVE_PKGCONFIG, pkg-config, yes, no) - -dnl Give error and exit if we don't have pkgconfig -if test "x$HAVE_PKGCONFIG" = "xno"; then - AC_MSG_ERROR(you need to have pkgconfig installed !) -fi - -dnl Now we're ready to ask for gstreamer libs and cflags -dnl And we can also ask for the right version of gstreamer - - -PKG_CHECK_MODULES(GST, \ - gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED, - HAVE_GST=yes,HAVE_GST=no) - -dnl Give error and exit if we don't have gstreamer -if test "x$HAVE_GST" = "xno"; then - AC_MSG_ERROR(you need gstreamer development packages installed !) -fi - -dnl append GST_ERROR cflags to GST_CFLAGS -GST_CFLAGS="$GST_CFLAGS $GST_ERROR" - -dnl make GST_CFLAGS and GST_LIBS available -AC_SUBST(GST_CFLAGS) -AC_SUBST(GST_LIBS) - -dnl make GST_MAJORMINOR available in Makefile.am -AC_SUBST(GST_MAJORMINOR) - -dnl If we need them, we can also use the base class libraries -PKG_CHECK_MODULES(GST_BASE, gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED, - HAVE_GST_BASE=yes, HAVE_GST_BASE=no) - -dnl Give a warning if we don't have gstreamer libs -dnl you can turn this into an error if you need them -if test "x$HAVE_GST_BASE" = "xno"; then - AC_MSG_NOTICE(no GStreamer base class libraries found (gstreamer-base-$GST_MAJORMINOR)) -fi - -dnl make _CFLAGS and _LIBS available -AC_SUBST(GST_BASE_CFLAGS) -AC_SUBST(GST_BASE_LIBS) - -dnl If we need them, we can also use the gstreamer-plugins-base libraries -PKG_CHECK_MODULES(GSTPB_BASE, - gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED, - HAVE_GSTPB_BASE=yes, HAVE_GSTPB_BASE=no) - -dnl Give a warning if we don't have gstreamer libs -dnl you can turn this into an error if you need them -if test "x$HAVE_GSTPB_BASE" = "xno"; then - AC_MSG_NOTICE(no GStreamer Plugins Base libraries found (gstreamer-plugins-base-$GST_MAJORMINOR)) -fi - -dnl make _CFLAGS and _LIBS available -AC_SUBST(GSTPB_BASE_CFLAGS) -AC_SUBST(GSTPB_BASE_LIBS) - -dnl If we need them, we can also use the gstreamer-controller libraries -PKG_CHECK_MODULES(GSTCTRL, - gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED, - HAVE_GSTCTRL=yes, HAVE_GSTCTRL=no) - -dnl Give a warning if we don't have gstreamer-controller -dnl you can turn this into an error if you need them -if test "x$HAVE_GSTCTRL" = "xno"; then - AC_MSG_NOTICE(no GStreamer Controller libraries found (gstreamer-controller-$GST_MAJORMINOR)) -fi - -dnl make _CFLAGS and _LIBS available -AC_SUBST(GSTCTRL_CFLAGS) -AC_SUBST(GSTCTRL_LIBS) - -dnl set the plugindir where plugins should be installed -if test "x${prefix}" = "x$HOME"; then - plugindir="$HOME/.gstreamer-$GST_MAJORMINOR/plugins" -else - plugindir="\$(libdir)/gstreamer-$GST_MAJORMINOR" -fi -AC_SUBST(plugindir) - -dnl set proper LDFLAGS for plugins -GST_PLUGIN_LDFLAGS='-module -avoid-version -export-symbols-regex [_]*\(gst_\|Gst\|GST_\).*' -AC_SUBST(GST_PLUGIN_LDFLAGS) - -AC_OUTPUT(Makefile m4/Makefile src/Makefile) - diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/COPYING crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/COPYING --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/COPYING 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/COPYING 1970-01-01 00:00:00.000000000 +0000 @@ -1,504 +0,0 @@ - GNU LESSER GENERAL PUBLIC LICENSE - Version 2.1, February 1999 - - Copyright (C) 1991, 1999 Free Software Foundation, Inc. - 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - -[This is the first released version of the Lesser GPL. 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See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -# 02110-1301, USA. - -# As a special exception to the GNU General Public License, if you -# distribute this file as part of a program that contains a -# configuration script generated by Autoconf, you may include it under -# the same distribution terms that you use for the rest of that program. - -# Originally written by Alexandre Oliva . - -case $1 in - '') - echo "$0: No command. Try \`$0 --help' for more information." 1>&2 - exit 1; - ;; - -h | --h*) - cat <<\EOF -Usage: depcomp [--help] [--version] PROGRAM [ARGS] - -Run PROGRAMS ARGS to compile a file, generating dependencies -as side-effects. - -Environment variables: - depmode Dependency tracking mode. - source Source file read by `PROGRAMS ARGS'. - object Object file output by `PROGRAMS ARGS'. - DEPDIR directory where to store dependencies. - depfile Dependency file to output. - tmpdepfile Temporary file to use when outputing dependencies. - libtool Whether libtool is used (yes/no). - -Report bugs to . -EOF - exit $? - ;; - -v | --v*) - echo "depcomp $scriptversion" - exit $? - ;; -esac - -if test -z "$depmode" || test -z "$source" || test -z "$object"; then - echo "depcomp: Variables source, object and depmode must be set" 1>&2 - exit 1 -fi - -# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. -depfile=${depfile-`echo "$object" | - sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} -tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} - -rm -f "$tmpdepfile" - -# Some modes work just like other modes, but use different flags. We -# parameterize here, but still list the modes in the big case below, -# to make depend.m4 easier to write. Note that we *cannot* use a case -# here, because this file can only contain one case statement. -if test "$depmode" = hp; then - # HP compiler uses -M and no extra arg. - gccflag=-M - depmode=gcc -fi - -if test "$depmode" = dashXmstdout; then - # This is just like dashmstdout with a different argument. - dashmflag=-xM - depmode=dashmstdout -fi - -case "$depmode" in -gcc3) -## gcc 3 implements dependency tracking that does exactly what -## we want. Yay! Note: for some reason libtool 1.4 doesn't like -## it if -MD -MP comes after the -MF stuff. Hmm. -## Unfortunately, FreeBSD c89 acceptance of flags depends upon -## the command line argument order; so add the flags where they -## appear in depend2.am. Note that the slowdown incurred here -## affects only configure: in makefiles, %FASTDEP% shortcuts this. - for arg - do - case $arg in - -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;; - *) set fnord "$@" "$arg" ;; - esac - shift # fnord - shift # $arg - done - "$@" - stat=$? - if test $stat -eq 0; then : - else - rm -f "$tmpdepfile" - exit $stat - fi - mv "$tmpdepfile" "$depfile" - ;; - -gcc) -## There are various ways to get dependency output from gcc. Here's -## why we pick this rather obscure method: -## - Don't want to use -MD because we'd like the dependencies to end -## up in a subdir. Having to rename by hand is ugly. -## (We might end up doing this anyway to support other compilers.) -## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like -## -MM, not -M (despite what the docs say). -## - Using -M directly means running the compiler twice (even worse -## than renaming). - if test -z "$gccflag"; then - gccflag=-MD, - fi - "$@" -Wp,"$gccflag$tmpdepfile" - stat=$? - if test $stat -eq 0; then : - else - rm -f "$tmpdepfile" - exit $stat - fi - rm -f "$depfile" - echo "$object : \\" > "$depfile" - alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz -## The second -e expression handles DOS-style file names with drive letters. - sed -e 's/^[^:]*: / /' \ - -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile" -## This next piece of magic avoids the `deleted header file' problem. -## The problem is that when a header file which appears in a .P file -## is deleted, the dependency causes make to die (because there is -## typically no way to rebuild the header). We avoid this by adding -## dummy dependencies for each header file. Too bad gcc doesn't do -## this for us directly. - tr ' ' ' -' < "$tmpdepfile" | -## Some versions of gcc put a space before the `:'. On the theory -## that the space means something, we add a space to the output as -## well. -## Some versions of the HPUX 10.20 sed can't process this invocation -## correctly. Breaking it into two sed invocations is a workaround. - sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" - rm -f "$tmpdepfile" - ;; - -hp) - # This case exists only to let depend.m4 do its work. It works by - # looking at the text of this script. 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However on - # icc -MD -MF foo.d -c -o sub/foo.o sub/foo.c - # ICC 7.0 will fill foo.d with something like - # foo.o: sub/foo.c - # foo.o: sub/foo.h - # which is wrong. We want: - # sub/foo.o: sub/foo.c - # sub/foo.o: sub/foo.h - # sub/foo.c: - # sub/foo.h: - # ICC 7.1 will output - # foo.o: sub/foo.c sub/foo.h - # and will wrap long lines using \ : - # foo.o: sub/foo.c ... \ - # sub/foo.h ... \ - # ... - - "$@" -MD -MF "$tmpdepfile" - stat=$? - if test $stat -eq 0; then : - else - rm -f "$tmpdepfile" - exit $stat - fi - rm -f "$depfile" - # Each line is of the form `foo.o: dependent.h', - # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'. - # Do two passes, one to just change these to - # `$object: dependent.h' and one to simply `dependent.h:'. - sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile" - # Some versions of the HPUX 10.20 sed can't process this invocation - # correctly. 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The following -more-detailed instructions are generic; see the `README' file for -instructions specific to this package. - - The `configure' shell script attempts to guess correct values for -various system-dependent variables used during compilation. It uses -those values to create a `Makefile' in each directory of the package. -It may also create one or more `.h' files containing system-dependent -definitions. Finally, it creates a shell script `config.status' that -you can run in the future to recreate the current configuration, and a -file `config.log' containing compiler output (useful mainly for -debugging `configure'). - - It can also use an optional file (typically called `config.cache' -and enabled with `--cache-file=config.cache' or simply `-C') that saves -the results of its tests to speed up reconfiguring. Caching is -disabled by default to prevent problems with accidental use of stale -cache files. - - If you need to do unusual things to compile the package, please try -to figure out how `configure' could check whether to do them, and mail -diffs or instructions to the address given in the `README' so they can -be considered for the next release. If you are using the cache, and at -some point `config.cache' contains results you don't want to keep, you -may remove or edit it. - - The file `configure.ac' (or `configure.in') is used to create -`configure' by a program called `autoconf'. You need `configure.ac' if -you want to change it or regenerate `configure' using a newer version -of `autoconf'. - -The simplest way to compile this package is: - - 1. `cd' to the directory containing the package's source code and type - `./configure' to configure the package for your system. - - Running `configure' might take a while. While running, it prints - some messages telling which features it is checking for. - - 2. Type `make' to compile the package. - - 3. Optionally, type `make check' to run any self-tests that come with - the package. - - 4. Type `make install' to install the programs and any data files and - documentation. - - 5. You can remove the program binaries and object files from the - source code directory by typing `make clean'. To also remove the - files that `configure' created (so you can compile the package for - a different kind of computer), type `make distclean'. There is - also a `make maintainer-clean' target, but that is intended mainly - for the package's developers. If you use it, you may have to get - all sorts of other programs in order to regenerate files that came - with the distribution. - - 6. Often, you can also type `make uninstall' to remove the installed - files again. - -Compilers and Options -===================== - -Some systems require unusual options for compilation or linking that the -`configure' script does not know about. Run `./configure --help' for -details on some of the pertinent environment variables. - - You can give `configure' initial values for configuration parameters -by setting variables in the command line or in the environment. Here -is an example: - - ./configure CC=c99 CFLAGS=-g LIBS=-lposix - - *Note Defining Variables::, for more details. - -Compiling For Multiple Architectures -==================================== - -You can compile the package for more than one kind of computer at the -same time, by placing the object files for each architecture in their -own directory. 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Or, you can set the -`CONFIG_SITE' environment variable to the location of the site script. -A warning: not all `configure' scripts look for a site script. - -Defining Variables -================== - -Variables not defined in a site shell script can be set in the -environment passed to `configure'. However, some packages may run -configure again during the build, and the customized values of these -variables may be lost. In order to avoid this problem, you should set -them in the `configure' command line, using `VAR=value'. For example: - - ./configure CC=/usr/local2/bin/gcc - -causes the specified `gcc' to be used as the C compiler (unless it is -overridden in the site shell script). - -Unfortunately, this technique does not work for `CONFIG_SHELL' due to -an Autoconf bug. Until the bug is fixed you can use this workaround: - - CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash - -`configure' Invocation -====================== - -`configure' recognizes the following options to control how it operates. - -`--help' -`-h' - Print a summary of the options to `configure', and exit. - -`--version' -`-V' - Print the version of Autoconf used to generate the `configure' - script, and exit. - -`--cache-file=FILE' - Enable the cache: use and save the results of the tests in FILE, - traditionally `config.cache'. FILE defaults to `/dev/null' to - disable caching. - -`--config-cache' -`-C' - Alias for `--cache-file=config.cache'. - -`--quiet' -`--silent' -`-q' - Do not print messages saying which checks are being made. To - suppress all normal output, redirect it to `/dev/null' (any error - messages will still be shown). - -`--srcdir=DIR' - Look for the package's source code in directory DIR. Usually - `configure' can determine that directory automatically. - -`configure' also accepts some other, not widely useful, options. Run -`configure --help' for more details. - diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/install-sh crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/install-sh --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/install-sh 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/install-sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,519 +0,0 @@ -#!/bin/sh -# install - install a program, script, or datafile - -scriptversion=2006-12-25.00 - -# This originates from X11R5 (mit/util/scripts/install.sh), which was -# later released in X11R6 (xc/config/util/install.sh) with the -# following copyright and license. -# -# Copyright (C) 1994 X Consortium -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to -# deal in the Software without restriction, including without limitation the -# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -# sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 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This is $PACKAGE $VERSION, but the -$progname: definition of this LT_INIT comes from an older release. -$progname: You should recreate aclocal.m4 with macros from $PACKAGE $VERSION -$progname: and run autoconf again. -_LT_EOF - else - cat >&2 <<_LT_EOF -$progname: Version mismatch error. This is $PACKAGE $VERSION, but the -$progname: definition of this LT_INIT comes from $PACKAGE $macro_version. -$progname: You should recreate aclocal.m4 with macros from $PACKAGE $VERSION -$progname: and run autoconf again. -_LT_EOF - fi - else - cat >&2 <<_LT_EOF -$progname: Version mismatch error. This is $PACKAGE $VERSION, revision $package_revision, -$progname: but the definition of this LT_INIT comes from revision $macro_revision. -$progname: You should recreate aclocal.m4 with macros from revision $package_revision -$progname: of $PACKAGE $VERSION and run autoconf again. -_LT_EOF - fi - - exit $EXIT_MISMATCH - fi -} - - -## ----------- ## -## Main. ## -## ----------- ## - -$opt_help || { - # Sanity checks first: - func_check_version_match - - if test "$build_libtool_libs" != yes && test "$build_old_libs" != yes; then - func_fatal_configuration "not configured to build any kind of library" - fi - - test -z "$mode" && func_fatal_error "error: you must specify a MODE." - - - # Darwin sucks - eval std_shrext=\"$shrext_cmds\" - - - # Only execute mode is allowed to have -dlopen flags. - if test -n "$execute_dlfiles" && test "$mode" != execute; then - func_error "unrecognized option \`-dlopen'" - $ECHO "$help" 1>&2 - exit $EXIT_FAILURE - fi - - # Change the help message to a mode-specific one. - generic_help="$help" - help="Try \`$progname --help --mode=$mode' for more information." -} - - -# func_lalib_p file -# True iff FILE is a libtool `.la' library or `.lo' object file. -# This function is only a basic sanity check; it will hardly flush out -# determined imposters. -func_lalib_p () -{ - test -f "$1" && - $SED -e 4q "$1" 2>/dev/null \ - | $GREP "^# Generated by .*$PACKAGE" > /dev/null 2>&1 -} - -# func_lalib_unsafe_p file -# True iff FILE is a libtool `.la' library or `.lo' object file. -# This function implements the same check as func_lalib_p without -# resorting to external programs. To this end, it redirects stdin and -# closes it afterwards, without saving the original file descriptor. -# As a safety measure, use it only where a negative result would be -# fatal anyway. Works if `file' does not exist. -func_lalib_unsafe_p () -{ - lalib_p=no - if test -f "$1" && test -r "$1" && exec 5<&0 <"$1"; then - for lalib_p_l in 1 2 3 4 - do - read lalib_p_line - case "$lalib_p_line" in - \#\ Generated\ by\ *$PACKAGE* ) lalib_p=yes; break;; - esac - done - exec 0<&5 5<&- - fi - test "$lalib_p" = yes -} - -# func_ltwrapper_script_p file -# True iff FILE is a libtool wrapper script -# This function is only a basic sanity check; it will hardly flush out -# determined imposters. -func_ltwrapper_script_p () -{ - func_lalib_p "$1" -} - -# func_ltwrapper_executable_p file -# True iff FILE is a libtool wrapper executable -# This function is only a basic sanity check; it will hardly flush out -# determined imposters. -func_ltwrapper_executable_p () -{ - func_ltwrapper_exec_suffix= - case $1 in - *.exe) ;; - *) func_ltwrapper_exec_suffix=.exe ;; - esac - $GREP "$magic_exe" "$1$func_ltwrapper_exec_suffix" >/dev/null 2>&1 -} - -# func_ltwrapper_scriptname file -# Assumes file is an ltwrapper_executable -# uses $file to determine the appropriate filename for a -# temporary ltwrapper_script. -func_ltwrapper_scriptname () -{ - func_ltwrapper_scriptname_result="" - if func_ltwrapper_executable_p "$1"; then - func_dirname_and_basename "$1" "" "." - func_stripname '' '.exe' "$func_basename_result" - func_ltwrapper_scriptname_result="$func_dirname_result/$objdir/${func_stripname_result}_ltshwrapper" - fi -} - -# func_ltwrapper_p file -# True iff FILE is a libtool wrapper script or wrapper executable -# This function is only a basic sanity check; it will hardly flush out -# determined imposters. -func_ltwrapper_p () -{ - func_ltwrapper_script_p "$1" || func_ltwrapper_executable_p "$1" -} - - -# func_execute_cmds commands fail_cmd -# Execute tilde-delimited COMMANDS. -# If FAIL_CMD is given, eval that upon failure. -# FAIL_CMD may read-access the current command in variable CMD! -func_execute_cmds () -{ - $opt_debug - save_ifs=$IFS; IFS='~' - for cmd in $1; do - IFS=$save_ifs - eval cmd=\"$cmd\" - func_show_eval "$cmd" "${2-:}" - done - IFS=$save_ifs -} - - -# func_source file -# Source FILE, adding directory component if necessary. -# Note that it is not necessary on cygwin/mingw to append a dot to -# FILE even if both FILE and FILE.exe exist: automatic-append-.exe -# behavior happens only for exec(3), not for open(2)! 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"./$1" ;; - esac -} - - -# func_infer_tag arg -# Infer tagged configuration to use if any are available and -# if one wasn't chosen via the "--tag" command line option. -# Only attempt this if the compiler in the base compile -# command doesn't match the default compiler. -# arg is usually of the form 'gcc ...' -func_infer_tag () -{ - $opt_debug - if test -n "$available_tags" && test -z "$tagname"; then - CC_quoted= - for arg in $CC; do - func_quote_for_eval "$arg" - CC_quoted="$CC_quoted $func_quote_for_eval_result" - done - case $@ in - # Blanks in the command may have been stripped by the calling shell, - # but not from the CC environment variable when configure was run. - " $CC "* | "$CC "* | " `$ECHO $CC` "* | "`$ECHO $CC` "* | " $CC_quoted"* | "$CC_quoted "* | " `$ECHO $CC_quoted` "* | "`$ECHO $CC_quoted` "*) ;; - # Blanks at the start of $base_compile will cause this to fail - # if we don't check for them as well. - *) - for z in $available_tags; do - if $GREP "^# ### BEGIN LIBTOOL TAG CONFIG: $z$" < "$progpath" > /dev/null; then - # Evaluate the configuration. - eval "`${SED} -n -e '/^# ### BEGIN LIBTOOL TAG CONFIG: '$z'$/,/^# ### END LIBTOOL TAG CONFIG: '$z'$/p' < $progpath`" - CC_quoted= - for arg in $CC; do - # Double-quote args containing other shell metacharacters. - func_quote_for_eval "$arg" - CC_quoted="$CC_quoted $func_quote_for_eval_result" - done - case "$@ " in - " $CC "* | "$CC "* | " `$ECHO $CC` "* | "`$ECHO $CC` "* | " $CC_quoted"* | "$CC_quoted "* | " `$ECHO $CC_quoted` "* | "`$ECHO $CC_quoted` "*) - # The compiler in the base compile command matches - # the one in the tagged configuration. - # Assume this is the tagged configuration we want. - tagname=$z - break - ;; - esac - fi - done - # If $tagname still isn't set, then no tagged configuration - # was found and let the user know that the "--tag" command - # line option must be used. - if test -z "$tagname"; then - func_echo "unable to infer tagged configuration" - func_fatal_error "specify a tag with \`--tag'" -# else -# func_verbose "using $tagname tagged configuration" - fi - ;; - esac - fi -} - - - -# func_write_libtool_object output_name pic_name nonpic_name -# Create a libtool object file (analogous to a ".la" file), -# but don't create it if we're doing a dry run. -func_write_libtool_object () -{ - write_libobj=${1} - if test "$build_libtool_libs" = yes; then - write_lobj=\'${2}\' - else - write_lobj=none - fi - - if test "$build_old_libs" = yes; then - write_oldobj=\'${3}\' - else - write_oldobj=none - fi - - $opt_dry_run || { - cat >${write_libobj}T <?"'"'"' &()|`$[]' \ - && func_warning "libobj name \`$libobj' may not contain shell special characters." - func_dirname_and_basename "$obj" "/" "" - objname="$func_basename_result" - xdir="$func_dirname_result" - lobj=${xdir}$objdir/$objname - - test -z "$base_compile" && \ - func_fatal_help "you must specify a compilation command" - - # Delete any leftover library objects. - if test "$build_old_libs" = yes; then - removelist="$obj $lobj $libobj ${libobj}T" - else - removelist="$lobj $libobj ${libobj}T" - fi - - # On Cygwin there's no "real" PIC flag so we must build both object types - case $host_os in - cygwin* | mingw* | pw32* | os2* | cegcc*) - pic_mode=default - ;; - esac - if test "$pic_mode" = no && test "$deplibs_check_method" != pass_all; then - # non-PIC code in shared libraries is not supported - pic_mode=default - fi - - # Calculate the filename of the output object if compiler does - # not support -o with -c - if test "$compiler_c_o" = no; then - output_obj=`$ECHO "X$srcfile" | $Xsed -e 's%^.*/%%' -e 's%\.[^.]*$%%'`.${objext} - lockfile="$output_obj.lock" - else - output_obj= - need_locks=no - lockfile= - fi - - # Lock this critical section if it is needed - # We use this script file to make the link, it avoids creating a new file - if test "$need_locks" = yes; then - until $opt_dry_run || ln "$progpath" "$lockfile" 2>/dev/null; do - func_echo "Waiting for $lockfile to be removed" - sleep 2 - done - elif test "$need_locks" = warn; then - if test -f "$lockfile"; then - $ECHO "\ -*** ERROR, $lockfile exists and contains: -`cat $lockfile 2>/dev/null` - -This indicates that another process is trying to use the same -temporary object file, and libtool could not work around it because -your compiler does not support \`-c' and \`-o' together. If you -repeat this compilation, it may succeed, by chance, but you had better -avoid parallel builds (make -j) in this platform, or get a better -compiler." - - $opt_dry_run || $RM $removelist - exit $EXIT_FAILURE - fi - removelist="$removelist $output_obj" - $ECHO "$srcfile" > "$lockfile" - fi - - $opt_dry_run || $RM $removelist - removelist="$removelist $lockfile" - trap '$opt_dry_run || $RM $removelist; exit $EXIT_FAILURE' 1 2 15 - - if test -n "$fix_srcfile_path"; then - eval srcfile=\"$fix_srcfile_path\" - fi - func_quote_for_eval "$srcfile" - qsrcfile=$func_quote_for_eval_result - - # Only build a PIC object if we are building libtool libraries. - if test "$build_libtool_libs" = yes; then - # Without this assignment, base_compile gets emptied. - fbsd_hideous_sh_bug=$base_compile - - if test "$pic_mode" != no; then - command="$base_compile $qsrcfile $pic_flag" - else - # Don't build PIC code - command="$base_compile $qsrcfile" - fi - - func_mkdir_p "$xdir$objdir" - - if test -z "$output_obj"; then - # Place PIC objects in $objdir - command="$command -o $lobj" - fi - - func_show_eval_locale "$command" \ - 'test -n "$output_obj" && $RM $removelist; exit $EXIT_FAILURE' - - if test "$need_locks" = warn && - test "X`cat $lockfile 2>/dev/null`" != "X$srcfile"; then - $ECHO "\ -*** ERROR, $lockfile contains: -`cat $lockfile 2>/dev/null` - -but it should contain: -$srcfile - -This indicates that another process is trying to use the same -temporary object file, and libtool could not work around it because -your compiler does not support \`-c' and \`-o' together. If you -repeat this compilation, it may succeed, by chance, but you had better -avoid parallel builds (make -j) in this platform, or get a better -compiler." - - $opt_dry_run || $RM $removelist - exit $EXIT_FAILURE - fi - - # Just move the object if needed, then go on to compile the next one - if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then - func_show_eval '$MV "$output_obj" "$lobj"' \ - 'error=$?; $opt_dry_run || $RM $removelist; exit $error' - fi - - # Allow error messages only from the first compilation. - if test "$suppress_opt" = yes; then - suppress_output=' >/dev/null 2>&1' - fi - fi - - # Only build a position-dependent object if we build old libraries. - if test "$build_old_libs" = yes; then - if test "$pic_mode" != yes; then - # Don't build PIC code - command="$base_compile $qsrcfile$pie_flag" - else - command="$base_compile $qsrcfile $pic_flag" - fi - if test "$compiler_c_o" = yes; then - command="$command -o $obj" - fi - - # Suppress compiler output if we already did a PIC compilation. - command="$command$suppress_output" - func_show_eval_locale "$command" \ - '$opt_dry_run || $RM $removelist; exit $EXIT_FAILURE' - - if test "$need_locks" = warn && - test "X`cat $lockfile 2>/dev/null`" != "X$srcfile"; then - $ECHO "\ -*** ERROR, $lockfile contains: -`cat $lockfile 2>/dev/null` - -but it should contain: -$srcfile - -This indicates that another process is trying to use the same -temporary object file, and libtool could not work around it because -your compiler does not support \`-c' and \`-o' together. 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- *.exe:*) - destfile=$destfile.exe - ;; - *:*.exe) - func_stripname '' '.exe' "$destfile" - destfile=$func_stripname_result - ;; - esac - ;; - esac - func_show_eval "$install_prog\$stripme \$file \$destfile" 'exit $?' - $opt_dry_run || if test -n "$outputname"; then - ${RM}r "$tmpdir" - fi - ;; - esac - done - - for file in $staticlibs; do - func_basename "$file" - name="$func_basename_result" - - # Set up the ranlib parameters. - oldlib="$destdir/$name" - - func_show_eval "$install_prog \$file \$oldlib" 'exit $?' - - if test -n "$stripme" && test -n "$old_striplib"; then - func_show_eval "$old_striplib $oldlib" 'exit $?' - fi - - # Do each command in the postinstall commands. - func_execute_cmds "$old_postinstall_cmds" 'exit $?' - done - - test -n "$future_libdirs" && \ - func_warning "remember to run \`$progname --finish$future_libdirs'" - - if test -n "$current_libdirs"; then - # Maybe just do a dry run. - $opt_dry_run && current_libdirs=" -n$current_libdirs" - exec_cmd='$SHELL $progpath $preserve_args --finish$current_libdirs' - else - exit $EXIT_SUCCESS - fi -} - -test "$mode" = install && func_mode_install ${1+"$@"} - - -# func_generate_dlsyms outputname originator pic_p -# Extract symbols from dlprefiles and create ${outputname}S.o with -# a dlpreopen symbol table. -func_generate_dlsyms () -{ - $opt_debug - my_outputname="$1" - my_originator="$2" - my_pic_p="${3-no}" - my_prefix=`$ECHO "$my_originator" | sed 's%[^a-zA-Z0-9]%_%g'` - my_dlsyms= - - if test -n "$dlfiles$dlprefiles" || test "$dlself" != no; then - if test -n "$NM" && test -n "$global_symbol_pipe"; then - my_dlsyms="${my_outputname}S.c" - else - func_error "not configured to extract global symbols from dlpreopened files" - fi - fi - - if test -n "$my_dlsyms"; then - case $my_dlsyms in - "") ;; - *.c) - # Discover the nlist of each of the dlfiles. - nlist="$output_objdir/${my_outputname}.nm" - - func_show_eval "$RM $nlist ${nlist}S ${nlist}T" - - # Parse the name list into a source file. - func_verbose "creating $output_objdir/$my_dlsyms" - - $opt_dry_run || $ECHO > "$output_objdir/$my_dlsyms" "\ -/* $my_dlsyms - symbol resolution table for \`$my_outputname' dlsym emulation. */ -/* Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION */ - -#ifdef __cplusplus -extern \"C\" { -#endif - -/* External symbol declarations for the compiler. */\ -" - - if test "$dlself" = yes; then - func_verbose "generating symbol list for \`$output'" - - $opt_dry_run || echo ': @PROGRAM@ ' > "$nlist" - - # Add our own program objects to the symbol list. - progfiles=`$ECHO "X$objs$old_deplibs" | $SP2NL | $Xsed -e "$lo2o" | $NL2SP` - for progfile in $progfiles; do - func_verbose "extracting global C symbols from \`$progfile'" - $opt_dry_run || eval "$NM $progfile | $global_symbol_pipe >> '$nlist'" - done - - if test -n "$exclude_expsyms"; then - $opt_dry_run || { - eval '$EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T' - eval '$MV "$nlist"T "$nlist"' - } - fi - - if test -n "$export_symbols_regex"; then - $opt_dry_run || { - eval '$EGREP -e "$export_symbols_regex" "$nlist" > "$nlist"T' - eval '$MV "$nlist"T "$nlist"' - } - fi - - # Prepare the list of exported symbols - if test -z "$export_symbols"; then - export_symbols="$output_objdir/$outputname.exp" - $opt_dry_run || { - $RM $export_symbols - eval "${SED} -n -e '/^: @PROGRAM@ $/d' -e 's/^.* \(.*\)$/\1/p' "'< "$nlist" > "$export_symbols"' - case $host in - *cygwin* | *mingw* | *cegcc* ) - eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' - eval 'cat "$export_symbols" >> "$output_objdir/$outputname.def"' - ;; - esac - } - else - $opt_dry_run || { - eval "${SED} -e 's/\([].[*^$]\)/\\\\\1/g' -e 's/^/ /' -e 's/$/$/'"' < "$export_symbols" > "$output_objdir/$outputname.exp"' - eval '$GREP -f "$output_objdir/$outputname.exp" < "$nlist" > "$nlist"T' - eval '$MV "$nlist"T "$nlist"' - case $host in - *cygwin | *mingw* | *cegcc* ) - eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' - eval 'cat "$nlist" >> "$output_objdir/$outputname.def"' - ;; - esac - } - fi - fi - - for dlprefile in $dlprefiles; do - func_verbose "extracting global C symbols from \`$dlprefile'" - func_basename "$dlprefile" - name="$func_basename_result" - $opt_dry_run || { - eval '$ECHO ": $name " >> "$nlist"' - eval "$NM $dlprefile 2>/dev/null | $global_symbol_pipe >> '$nlist'" - } - done - - $opt_dry_run || { - # Make sure we have at least an empty file. - test -f "$nlist" || : > "$nlist" - - if test -n "$exclude_expsyms"; then - $EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T - $MV "$nlist"T "$nlist" - fi - - # Try sorting and uniquifying the output. - if $GREP -v "^: " < "$nlist" | - if sort -k 3 /dev/null 2>&1; then - sort -k 3 - else - sort +2 - fi | - uniq > "$nlist"S; then - : - else - $GREP -v "^: " < "$nlist" > "$nlist"S - fi - - if test -f "$nlist"S; then - eval "$global_symbol_to_cdecl"' < "$nlist"S >> "$output_objdir/$my_dlsyms"' - else - $ECHO '/* NONE */' >> "$output_objdir/$my_dlsyms" - fi - - $ECHO >> "$output_objdir/$my_dlsyms" "\ - -/* The mapping between symbol names and symbols. */ -typedef struct { - const char *name; - void *address; -} lt_dlsymlist; -" - case $host in - *cygwin* | *mingw* | *cegcc* ) - $ECHO >> "$output_objdir/$my_dlsyms" "\ -/* DATA imports from DLLs on WIN32 con't be const, because - runtime relocations are performed -- see ld's documentation - on pseudo-relocs. */" - lt_dlsym_const= ;; - *osf5*) - echo >> "$output_objdir/$my_dlsyms" "\ -/* This system does not cope well with relocations in const data */" - lt_dlsym_const= ;; - *) - lt_dlsym_const=const ;; - esac - - $ECHO >> "$output_objdir/$my_dlsyms" "\ -extern $lt_dlsym_const lt_dlsymlist -lt_${my_prefix}_LTX_preloaded_symbols[]; -$lt_dlsym_const lt_dlsymlist -lt_${my_prefix}_LTX_preloaded_symbols[] = -{\ - { \"$my_originator\", (void *) 0 }," - - case $need_lib_prefix in - no) - eval "$global_symbol_to_c_name_address" < "$nlist" >> "$output_objdir/$my_dlsyms" - ;; - *) - eval "$global_symbol_to_c_name_address_lib_prefix" < "$nlist" >> "$output_objdir/$my_dlsyms" - ;; - esac - $ECHO >> "$output_objdir/$my_dlsyms" "\ - {0, (void *) 0} -}; - -/* This works around a problem in FreeBSD linker */ -#ifdef FREEBSD_WORKAROUND -static const void *lt_preloaded_setup() { - return lt_${my_prefix}_LTX_preloaded_symbols; -} -#endif - -#ifdef __cplusplus -} -#endif\ -" - } # !$opt_dry_run - - pic_flag_for_symtable= - case "$compile_command " in - *" -static "*) ;; - *) - case $host in - # compiling the symbol table file with pic_flag works around - # a FreeBSD bug that causes programs to crash when -lm is - # linked before any other PIC object. But we must not use - # pic_flag when linking with -static. The problem exists in - # FreeBSD 2.2.6 and is fixed in FreeBSD 3.1. - *-*-freebsd2*|*-*-freebsd3.0*|*-*-freebsdelf3.0*) - pic_flag_for_symtable=" $pic_flag -DFREEBSD_WORKAROUND" ;; - *-*-hpux*) - pic_flag_for_symtable=" $pic_flag" ;; - *) - if test "X$my_pic_p" != Xno; then - pic_flag_for_symtable=" $pic_flag" - fi - ;; - esac - ;; - esac - symtab_cflags= - for arg in $LTCFLAGS; do - case $arg in - -pie | -fpie | -fPIE) ;; - *) symtab_cflags="$symtab_cflags $arg" ;; - esac - done - - # Now compile the dynamic symbol file. - func_show_eval '(cd $output_objdir && $LTCC$symtab_cflags -c$no_builtin_flag$pic_flag_for_symtable "$my_dlsyms")' 'exit $?' - - # Clean up the generated files. - func_show_eval '$RM "$output_objdir/$my_dlsyms" "$nlist" "${nlist}S" "${nlist}T"' - - # Transform the symbol file into the correct name. - symfileobj="$output_objdir/${my_outputname}S.$objext" - case $host in - *cygwin* | *mingw* | *cegcc* ) - if test -f "$output_objdir/$my_outputname.def"; then - compile_command=`$ECHO "X$compile_command" | $Xsed -e "s%@SYMFILE@%$output_objdir/$my_outputname.def $symfileobj%"` - finalize_command=`$ECHO "X$finalize_command" | $Xsed -e "s%@SYMFILE@%$output_objdir/$my_outputname.def $symfileobj%"` - else - compile_command=`$ECHO "X$compile_command" | $Xsed -e "s%@SYMFILE@%$symfileobj%"` - finalize_command=`$ECHO "X$finalize_command" | $Xsed -e "s%@SYMFILE@%$symfileobj%"` - fi - ;; - *) - compile_command=`$ECHO "X$compile_command" | $Xsed -e "s%@SYMFILE@%$symfileobj%"` - finalize_command=`$ECHO "X$finalize_command" | $Xsed -e "s%@SYMFILE@%$symfileobj%"` - ;; - esac - ;; - *) - func_fatal_error "unknown suffix for \`$my_dlsyms'" - ;; - esac - else - # We keep going just in case the user didn't refer to - # lt_preloaded_symbols. The linker will fail if global_symbol_pipe - # really was required. - - # Nullify the symbol file. - compile_command=`$ECHO "X$compile_command" | $Xsed -e "s% @SYMFILE@%%"` - finalize_command=`$ECHO "X$finalize_command" | $Xsed -e "s% @SYMFILE@%%"` - fi -} - -# func_win32_libid arg -# return the library type of file 'arg' -# -# Need a lot of goo to handle *both* DLLs and import libs -# Has to be a shell function in order to 'eat' the argument -# that is supplied when $file_magic_command is called. -func_win32_libid () -{ - $opt_debug - win32_libid_type="unknown" - win32_fileres=`file -L $1 2>/dev/null` - case $win32_fileres in - *ar\ archive\ import\ library*) # definitely import - win32_libid_type="x86 archive import" - ;; - *ar\ archive*) # could be an import, or static - if eval $OBJDUMP -f $1 | $SED -e '10q' 2>/dev/null | - $EGREP 'file format pe-i386(.*architecture: i386)?' >/dev/null ; then - win32_nmres=`eval $NM -f posix -A $1 | - $SED -n -e ' - 1,100{ - / I /{ - s,.*,import, - p - q - } - }'` - case $win32_nmres in - import*) win32_libid_type="x86 archive import";; - *) win32_libid_type="x86 archive static";; - esac - fi - ;; - *DLL*) - win32_libid_type="x86 DLL" - ;; - *executable*) # but shell scripts are "executable" too... - case $win32_fileres in - *MS\ Windows\ PE\ Intel*) - win32_libid_type="x86 DLL" - ;; - esac - ;; - esac - $ECHO "$win32_libid_type" -} - - - -# func_extract_an_archive dir oldlib -func_extract_an_archive () -{ - $opt_debug - f_ex_an_ar_dir="$1"; shift - f_ex_an_ar_oldlib="$1" - func_show_eval "(cd \$f_ex_an_ar_dir && $AR x \"\$f_ex_an_ar_oldlib\")" 'exit $?' - if ($AR t "$f_ex_an_ar_oldlib" | sort | sort -uc >/dev/null 2>&1); then - : - else - func_fatal_error "object name conflicts in archive: $f_ex_an_ar_dir/$f_ex_an_ar_oldlib" - fi -} - - -# func_extract_archives gentop oldlib ... -func_extract_archives () -{ - $opt_debug - my_gentop="$1"; shift - my_oldlibs=${1+"$@"} - my_oldobjs="" - my_xlib="" - my_xabs="" - my_xdir="" - - for my_xlib in $my_oldlibs; do - # Extract the objects. - case $my_xlib in - [\\/]* | [A-Za-z]:[\\/]*) my_xabs="$my_xlib" ;; - *) my_xabs=`pwd`"/$my_xlib" ;; - esac - func_basename "$my_xlib" - my_xlib="$func_basename_result" - my_xlib_u=$my_xlib - while :; do - case " $extracted_archives " in - *" $my_xlib_u "*) - func_arith $extracted_serial + 1 - extracted_serial=$func_arith_result - my_xlib_u=lt$extracted_serial-$my_xlib ;; - *) break ;; - esac - done - extracted_archives="$extracted_archives $my_xlib_u" - my_xdir="$my_gentop/$my_xlib_u" - - func_mkdir_p "$my_xdir" - - case $host in - *-darwin*) - func_verbose "Extracting $my_xabs" - # Do not bother doing anything if just a dry run - $opt_dry_run || { - darwin_orig_dir=`pwd` - cd $my_xdir || exit $? - darwin_archive=$my_xabs - darwin_curdir=`pwd` - darwin_base_archive=`basename "$darwin_archive"` - darwin_arches=`$LIPO -info "$darwin_archive" 2>/dev/null | $GREP Architectures 2>/dev/null || true` - if test -n "$darwin_arches"; then - darwin_arches=`$ECHO "$darwin_arches" | $SED -e 's/.*are://'` - darwin_arch= - func_verbose "$darwin_base_archive has multiple architectures $darwin_arches" - for darwin_arch in $darwin_arches ; do - func_mkdir_p "unfat-$$/${darwin_base_archive}-${darwin_arch}" - $LIPO -thin $darwin_arch -output "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" "${darwin_archive}" - cd "unfat-$$/${darwin_base_archive}-${darwin_arch}" - func_extract_an_archive "`pwd`" "${darwin_base_archive}" - cd "$darwin_curdir" - $RM "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" - done # $darwin_arches - ## Okay now we've a bunch of thin objects, gotta fatten them up :) - darwin_filelist=`find unfat-$$ -type f -name \*.o -print -o -name \*.lo -print | $SED -e "$basename" | sort -u` - darwin_file= - darwin_files= - for darwin_file in $darwin_filelist; do - darwin_files=`find unfat-$$ -name $darwin_file -print | $NL2SP` - $LIPO -create -output "$darwin_file" $darwin_files - done # $darwin_filelist - $RM -rf unfat-$$ - cd "$darwin_orig_dir" - else - cd $darwin_orig_dir - func_extract_an_archive "$my_xdir" "$my_xabs" - fi # $darwin_arches - } # !$opt_dry_run - ;; - *) - func_extract_an_archive "$my_xdir" "$my_xabs" - ;; - esac - my_oldobjs="$my_oldobjs "`find $my_xdir -name \*.$objext -print -o -name \*.lo -print | $NL2SP` - done - - func_extract_archives_result="$my_oldobjs" -} - - - -# func_emit_wrapper_part1 [arg=no] -# -# Emit the first part of a libtool wrapper script on stdout. -# For more information, see the description associated with -# func_emit_wrapper(), below. -func_emit_wrapper_part1 () -{ - func_emit_wrapper_part1_arg1=no - if test -n "$1" ; then - func_emit_wrapper_part1_arg1=$1 - fi - - $ECHO "\ -#! $SHELL - -# $output - temporary wrapper script for $objdir/$outputname -# Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION -# -# The $output program cannot be directly executed until all the libtool -# libraries that it depends on are installed. -# -# This wrapper script should never be moved out of the build directory. -# If it is, it will not operate correctly. - -# Sed substitution that helps us do robust quoting. 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Disable this feature. - alias -g '\${1+\"\$@\"}'='\"\$@\"' - setopt NO_GLOB_SUBST -else - case \`(set -o) 2>/dev/null\` in *posix*) set -o posix;; esac -fi -BIN_SH=xpg4; export BIN_SH # for Tru64 -DUALCASE=1; export DUALCASE # for MKS sh - -# The HP-UX ksh and POSIX shell print the target directory to stdout -# if CDPATH is set. -(unset CDPATH) >/dev/null 2>&1 && unset CDPATH - -relink_command=\"$relink_command\" - -# This environment variable determines our operation mode. -if test \"\$libtool_install_magic\" = \"$magic\"; then - # install mode needs the following variables: - generated_by_libtool_version='$macro_version' - notinst_deplibs='$notinst_deplibs' -else - # When we are sourced in execute mode, \$file and \$ECHO are already set. - if test \"\$libtool_execute_magic\" != \"$magic\"; then - ECHO=\"$qecho\" - file=\"\$0\" - # Make sure echo works. - if test \"X\$1\" = X--no-reexec; then - # Discard the --no-reexec flag, and continue. - shift - elif test \"X\`{ \$ECHO '\t'; } 2>/dev/null\`\" = 'X\t'; then - # Yippee, \$ECHO works! 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Calling this function does no harm for other -# $host/$build combinations not listed above. -# -# ARG is the path (on $build) that should be converted to -# the proper representation for $host. The result is stored -# in $func_to_host_path_result. -func_to_host_path () -{ - func_to_host_path_result="$1" - if test -n "$1" ; then - case $host in - *mingw* ) - lt_sed_naive_backslashify='s|\\\\*|\\|g;s|/|\\|g;s|\\|\\\\|g' - case $build in - *mingw* ) # actually, msys - # awkward: cmd appends spaces to result - lt_sed_strip_trailing_spaces="s/[ ]*\$//" - func_to_host_path_tmp1=`( cmd //c echo "$1" |\ - $SED -e "$lt_sed_strip_trailing_spaces" ) 2>/dev/null || echo ""` - func_to_host_path_result=`echo "$func_to_host_path_tmp1" |\ - $SED -e "$lt_sed_naive_backslashify"` - ;; - *cygwin* ) - func_to_host_path_tmp1=`cygpath -w "$1"` - func_to_host_path_result=`echo "$func_to_host_path_tmp1" |\ - $SED -e "$lt_sed_naive_backslashify"` - ;; - * ) - # Unfortunately, winepath does not exit with a non-zero - # error code, so we are forced to check the contents of - # stdout. On the other hand, if the command is not - # found, the shell will set an exit code of 127 and print - # *an error message* to stdout. So we must check for both - # error code of zero AND non-empty stdout, which explains - # the odd construction: - func_to_host_path_tmp1=`winepath -w "$1" 2>/dev/null` - if test "$?" -eq 0 && test -n "${func_to_host_path_tmp1}"; then - func_to_host_path_result=`echo "$func_to_host_path_tmp1" |\ - $SED -e "$lt_sed_naive_backslashify"` - else - # Allow warning below. - func_to_host_path_result="" - fi - ;; - esac - if test -z "$func_to_host_path_result" ; then - func_error "Could not determine host path corresponding to" - func_error " '$1'" - func_error "Continuing, but uninstalled executables may not work." - # Fallback: - func_to_host_path_result="$1" - fi - ;; - esac - fi -} -# end: func_to_host_path - -# func_to_host_pathlist arg -# -# Convert pathlists to host format when used with build tools. -# See func_to_host_path(), above. This function supports the -# following $build/$host combinations (but does no harm for -# combinations not listed here): -# $build $host -# mingw (msys) mingw [e.g. native] -# cygwin mingw -# *nix + wine mingw -# -# Path separators are also converted from $build format to -# $host format. If ARG begins or ends with a path separator -# character, it is preserved (but converted to $host format) -# on output. -# -# ARG is a pathlist (on $build) that should be converted to -# the proper representation on $host. The result is stored -# in $func_to_host_pathlist_result. -func_to_host_pathlist () -{ - func_to_host_pathlist_result="$1" - if test -n "$1" ; then - case $host in - *mingw* ) - lt_sed_naive_backslashify='s|\\\\*|\\|g;s|/|\\|g;s|\\|\\\\|g' - # Remove leading and trailing path separator characters from - # ARG. msys behavior is inconsistent here, cygpath turns them - # into '.;' and ';.', and winepath ignores them completely. - func_to_host_pathlist_tmp2="$1" - # Once set for this call, this variable should not be - # reassigned. It is used in tha fallback case. - func_to_host_pathlist_tmp1=`echo "$func_to_host_pathlist_tmp2" |\ - $SED -e 's|^:*||' -e 's|:*$||'` - case $build in - *mingw* ) # Actually, msys. - # Awkward: cmd appends spaces to result. - lt_sed_strip_trailing_spaces="s/[ ]*\$//" - func_to_host_pathlist_tmp2=`( cmd //c echo "$func_to_host_pathlist_tmp1" |\ - $SED -e "$lt_sed_strip_trailing_spaces" ) 2>/dev/null || echo ""` - func_to_host_pathlist_result=`echo "$func_to_host_pathlist_tmp2" |\ - $SED -e "$lt_sed_naive_backslashify"` - ;; - *cygwin* ) - func_to_host_pathlist_tmp2=`cygpath -w -p "$func_to_host_pathlist_tmp1"` - func_to_host_pathlist_result=`echo "$func_to_host_pathlist_tmp2" |\ - $SED -e "$lt_sed_naive_backslashify"` - ;; - * ) - # unfortunately, winepath doesn't convert pathlists - func_to_host_pathlist_result="" - func_to_host_pathlist_oldIFS=$IFS - IFS=: - for func_to_host_pathlist_f in $func_to_host_pathlist_tmp1 ; do - IFS=$func_to_host_pathlist_oldIFS - if test -n "$func_to_host_pathlist_f" ; then - func_to_host_path "$func_to_host_pathlist_f" - if test -n "$func_to_host_path_result" ; then - if test -z "$func_to_host_pathlist_result" ; then - func_to_host_pathlist_result="$func_to_host_path_result" - else - func_to_host_pathlist_result="$func_to_host_pathlist_result;$func_to_host_path_result" - fi - fi - fi - IFS=: - done - IFS=$func_to_host_pathlist_oldIFS - ;; - esac - if test -z "$func_to_host_pathlist_result" ; then - func_error "Could not determine the host path(s) corresponding to" - func_error " '$1'" - func_error "Continuing, but uninstalled executables may not work." - # Fallback. This may break if $1 contains DOS-style drive - # specifications. The fix is not to complicate the expression - # below, but for the user to provide a working wine installation - # with winepath so that path translation in the cross-to-mingw - # case works properly. - lt_replace_pathsep_nix_to_dos="s|:|;|g" - func_to_host_pathlist_result=`echo "$func_to_host_pathlist_tmp1" |\ - $SED -e "$lt_replace_pathsep_nix_to_dos"` - fi - # Now, add the leading and trailing path separators back - case "$1" in - :* ) func_to_host_pathlist_result=";$func_to_host_pathlist_result" - ;; - esac - case "$1" in - *: ) func_to_host_pathlist_result="$func_to_host_pathlist_result;" - ;; - esac - ;; - esac - fi -} -# end: func_to_host_pathlist - -# func_emit_cwrapperexe_src -# emit the source code for a wrapper executable on stdout -# Must ONLY be called from within func_mode_link because -# it depends on a number of variable set therein. -func_emit_cwrapperexe_src () -{ - cat < -#include -#ifdef _MSC_VER -# include -# include -# include -# define setmode _setmode -#else -# include -# include -# ifdef __CYGWIN__ -# include -# define HAVE_SETENV -# ifdef __STRICT_ANSI__ -char *realpath (const char *, char *); -int putenv (char *); -int setenv (const char *, const char *, int); -# endif -# endif -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(PATH_MAX) -# define LT_PATHMAX PATH_MAX -#elif defined(MAXPATHLEN) -# define LT_PATHMAX MAXPATHLEN -#else -# define LT_PATHMAX 1024 -#endif - -#ifndef S_IXOTH -# define S_IXOTH 0 -#endif -#ifndef S_IXGRP -# define S_IXGRP 0 -#endif - -#ifdef _MSC_VER -# define S_IXUSR _S_IEXEC -# define stat _stat -# ifndef _INTPTR_T_DEFINED -# define intptr_t int -# endif -#endif - -#ifndef DIR_SEPARATOR -# define DIR_SEPARATOR '/' -# define PATH_SEPARATOR ':' -#endif - -#if defined (_WIN32) || defined (__MSDOS__) || defined (__DJGPP__) || \ - defined (__OS2__) -# define HAVE_DOS_BASED_FILE_SYSTEM -# define FOPEN_WB "wb" -# ifndef DIR_SEPARATOR_2 -# define DIR_SEPARATOR_2 '\\' -# endif -# ifndef PATH_SEPARATOR_2 -# define PATH_SEPARATOR_2 ';' -# endif -#endif - -#ifndef DIR_SEPARATOR_2 -# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) -#else /* DIR_SEPARATOR_2 */ -# define IS_DIR_SEPARATOR(ch) \ - (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) -#endif /* DIR_SEPARATOR_2 */ - -#ifndef PATH_SEPARATOR_2 -# define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR) -#else /* PATH_SEPARATOR_2 */ -# define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR_2) -#endif /* PATH_SEPARATOR_2 */ - -#ifdef __CYGWIN__ -# define FOPEN_WB "wb" -#endif - -#ifndef FOPEN_WB -# define FOPEN_WB "w" -#endif -#ifndef _O_BINARY -# define _O_BINARY 0 -#endif - -#define XMALLOC(type, num) ((type *) xmalloc ((num) * sizeof(type))) -#define XFREE(stale) do { \ - if (stale) { free ((void *) stale); stale = 0; } \ -} while (0) - -#undef LTWRAPPER_DEBUGPRINTF -#if defined DEBUGWRAPPER -# define LTWRAPPER_DEBUGPRINTF(args) ltwrapper_debugprintf args -static void -ltwrapper_debugprintf (const char *fmt, ...) -{ - va_list args; - va_start (args, fmt); - (void) vfprintf (stderr, fmt, args); - va_end (args); -} -#else -# define LTWRAPPER_DEBUGPRINTF(args) -#endif - -const char *program_name = NULL; - -void *xmalloc (size_t num); -char *xstrdup (const char *string); -const char *base_name (const char *name); -char *find_executable (const char *wrapper); -char *chase_symlinks (const char *pathspec); -int make_executable (const char *path); -int check_executable (const char *path); -char *strendzap (char *str, const char *pat); -void lt_fatal (const char *message, ...); -void lt_setenv (const char *name, const char *value); -char *lt_extend_str (const char *orig_value, const char *add, int to_end); -void lt_opt_process_env_set (const char *arg); -void lt_opt_process_env_prepend (const char *arg); -void lt_opt_process_env_append (const char *arg); -int lt_split_name_value (const char *arg, char** name, char** value); -void lt_update_exe_path (const char *name, const char *value); -void lt_update_lib_path (const char *name, const char *value); - -static const char *script_text_part1 = -EOF - - func_emit_wrapper_part1 yes | - $SED -e 's/\([\\"]\)/\\\1/g' \ - -e 's/^/ "/' -e 's/$/\\n"/' - echo ";" - cat <"))); - for (i = 0; i < newargc; i++) - { - LTWRAPPER_DEBUGPRINTF (("(main) newargz[%d] : %s\n", i, (newargz[i] ? newargz[i] : ""))); - } - -EOF - - case $host_os in - mingw*) - cat <<"EOF" - /* execv doesn't actually work on mingw as expected on unix */ - rval = _spawnv (_P_WAIT, lt_argv_zero, (const char * const *) newargz); - if (rval == -1) - { - /* failed to start process */ - LTWRAPPER_DEBUGPRINTF (("(main) failed to launch target \"%s\": errno = %d\n", lt_argv_zero, errno)); - return 127; - } - return rval; -EOF - ;; - *) - cat <<"EOF" - execv (lt_argv_zero, newargz); - return rval; /* =127, but avoids unused variable warning */ -EOF - ;; - esac - - cat <<"EOF" -} - -void * -xmalloc (size_t num) -{ - void *p = (void *) malloc (num); - if (!p) - lt_fatal ("Memory exhausted"); - - return p; -} - -char * -xstrdup (const char *string) -{ - return string ? strcpy ((char *) xmalloc (strlen (string) + 1), - string) : NULL; -} - -const char * -base_name (const char *name) -{ - const char *base; - -#if defined (HAVE_DOS_BASED_FILE_SYSTEM) - /* Skip over the disk name in MSDOS pathnames. */ - if (isalpha ((unsigned char) name[0]) && name[1] == ':') - name += 2; -#endif - - for (base = name; *name; name++) - if (IS_DIR_SEPARATOR (*name)) - base = name + 1; - return base; -} - -int -check_executable (const char *path) -{ - struct stat st; - - LTWRAPPER_DEBUGPRINTF (("(check_executable) : %s\n", - path ? (*path ? path : "EMPTY!") : "NULL!")); - if ((!path) || (!*path)) - return 0; - - if ((stat (path, &st) >= 0) - && (st.st_mode & (S_IXUSR | S_IXGRP | S_IXOTH))) - return 1; - else - return 0; -} - -int -make_executable (const char *path) -{ - int rval = 0; - struct stat st; - - LTWRAPPER_DEBUGPRINTF (("(make_executable) : %s\n", - path ? (*path ? path : "EMPTY!") : "NULL!")); - if ((!path) || (!*path)) - return 0; - - if (stat (path, &st) >= 0) - { - rval = chmod (path, st.st_mode | S_IXOTH | S_IXGRP | S_IXUSR); - } - return rval; -} - -/* Searches for the full path of the wrapper. Returns - newly allocated full path name if found, NULL otherwise - Does not chase symlinks, even on platforms that support them. -*/ -char * -find_executable (const char *wrapper) -{ - int has_slash = 0; - const char *p; - const char *p_next; - /* static buffer for getcwd */ - char tmp[LT_PATHMAX + 1]; - int tmp_len; - char *concat_name; - - LTWRAPPER_DEBUGPRINTF (("(find_executable) : %s\n", - wrapper ? (*wrapper ? wrapper : "EMPTY!") : "NULL!")); - - if ((wrapper == NULL) || (*wrapper == '\0')) - return NULL; - - /* Absolute path? */ -#if defined (HAVE_DOS_BASED_FILE_SYSTEM) - if (isalpha ((unsigned char) wrapper[0]) && wrapper[1] == ':') - { - concat_name = xstrdup (wrapper); - if (check_executable (concat_name)) - return concat_name; - XFREE (concat_name); - } - else - { -#endif - if (IS_DIR_SEPARATOR (wrapper[0])) - { - concat_name = xstrdup (wrapper); - if (check_executable (concat_name)) - return concat_name; - XFREE (concat_name); - } -#if defined (HAVE_DOS_BASED_FILE_SYSTEM) - } -#endif - - for (p = wrapper; *p; p++) - if (*p == '/') - { - has_slash = 1; - break; - } - if (!has_slash) - { - /* no slashes; search PATH */ - const char *path = getenv ("PATH"); - if (path != NULL) - { - for (p = path; *p; p = p_next) - { - const char *q; - size_t p_len; - for (q = p; *q; q++) - if (IS_PATH_SEPARATOR (*q)) - break; - p_len = q - p; - p_next = (*q == '\0' ? q : q + 1); - if (p_len == 0) - { - /* empty path: current directory */ - if (getcwd (tmp, LT_PATHMAX) == NULL) - lt_fatal ("getcwd failed"); - tmp_len = strlen (tmp); - concat_name = - XMALLOC (char, tmp_len + 1 + strlen (wrapper) + 1); - memcpy (concat_name, tmp, tmp_len); - concat_name[tmp_len] = '/'; - strcpy (concat_name + tmp_len + 1, wrapper); - } - else - { - concat_name = - XMALLOC (char, p_len + 1 + strlen (wrapper) + 1); - memcpy (concat_name, p, p_len); - concat_name[p_len] = '/'; - strcpy (concat_name + p_len + 1, wrapper); - } - if (check_executable (concat_name)) - return concat_name; - XFREE (concat_name); - } - } - /* not found in PATH; assume curdir */ - } - /* Relative path | not found in path: prepend cwd */ - if (getcwd (tmp, LT_PATHMAX) == NULL) - lt_fatal ("getcwd failed"); - tmp_len = strlen (tmp); - concat_name = XMALLOC (char, tmp_len + 1 + strlen (wrapper) + 1); - memcpy (concat_name, tmp, tmp_len); - concat_name[tmp_len] = '/'; - strcpy (concat_name + tmp_len + 1, wrapper); - - if (check_executable (concat_name)) - return concat_name; - XFREE (concat_name); - return NULL; -} - -char * -chase_symlinks (const char *pathspec) -{ -#ifndef S_ISLNK - return xstrdup (pathspec); -#else - char buf[LT_PATHMAX]; - struct stat s; - char *tmp_pathspec = xstrdup (pathspec); - char *p; - int has_symlinks = 0; - while (strlen (tmp_pathspec) && !has_symlinks) - { - LTWRAPPER_DEBUGPRINTF (("checking path component for symlinks: %s\n", - tmp_pathspec)); - if (lstat (tmp_pathspec, &s) == 0) - { - if (S_ISLNK (s.st_mode) != 0) - { - has_symlinks = 1; - break; - } - - /* search backwards for last DIR_SEPARATOR */ - p = tmp_pathspec + strlen (tmp_pathspec) - 1; - while ((p > tmp_pathspec) && (!IS_DIR_SEPARATOR (*p))) - p--; - if ((p == tmp_pathspec) && (!IS_DIR_SEPARATOR (*p))) - { - /* no more DIR_SEPARATORS left */ - break; - } - *p = '\0'; - } - else - { - char *errstr = strerror (errno); - lt_fatal ("Error accessing file %s (%s)", tmp_pathspec, errstr); - } - } - XFREE (tmp_pathspec); - - if (!has_symlinks) - { - return xstrdup (pathspec); - } - - tmp_pathspec = realpath (pathspec, buf); - if (tmp_pathspec == 0) - { - lt_fatal ("Could not follow symlinks for %s", pathspec); - } - return xstrdup (tmp_pathspec); -#endif -} - -char * -strendzap (char *str, const char *pat) -{ - size_t len, patlen; - - assert (str != NULL); - assert (pat != NULL); - - len = strlen (str); - patlen = strlen (pat); - - if (patlen <= len) - { - str += len - patlen; - if (strcmp (str, pat) == 0) - *str = '\0'; - } - return str; -} - -static void -lt_error_core (int exit_status, const char *mode, - const char *message, va_list ap) -{ - fprintf (stderr, "%s: %s: ", program_name, mode); - vfprintf (stderr, message, ap); - fprintf (stderr, ".\n"); - - if (exit_status >= 0) - exit (exit_status); -} - -void -lt_fatal (const char *message, ...) -{ - va_list ap; - va_start (ap, message); - lt_error_core (EXIT_FAILURE, "FATAL", message, ap); - va_end (ap); -} - -void -lt_setenv (const char *name, const char *value) -{ - LTWRAPPER_DEBUGPRINTF (("(lt_setenv) setting '%s' to '%s'\n", - (name ? name : ""), - (value ? value : ""))); - { -#ifdef HAVE_SETENV - /* always make a copy, for consistency with !HAVE_SETENV */ - char *str = xstrdup (value); - setenv (name, str, 1); -#else - int len = strlen (name) + 1 + strlen (value) + 1; - char *str = XMALLOC (char, len); - sprintf (str, "%s=%s", name, value); - if (putenv (str) != EXIT_SUCCESS) - { - XFREE (str); - } -#endif - } -} - -char * -lt_extend_str (const char *orig_value, const char *add, int to_end) -{ - char *new_value; - if (orig_value && *orig_value) - { - int orig_value_len = strlen (orig_value); - int add_len = strlen (add); - new_value = XMALLOC (char, add_len + orig_value_len + 1); - if (to_end) - { - strcpy (new_value, orig_value); - strcpy (new_value + orig_value_len, add); - } - else - { - strcpy (new_value, add); - strcpy (new_value + add_len, orig_value); - } - } - else - { - new_value = xstrdup (add); - } - return new_value; -} - -int -lt_split_name_value (const char *arg, char** name, char** value) -{ - const char *p; - int len; - if (!arg || !*arg) - return 1; - - p = strchr (arg, (int)'='); - - if (!p) - return 1; - - *value = xstrdup (++p); - - len = strlen (arg) - strlen (*value); - *name = XMALLOC (char, len); - strncpy (*name, arg, len-1); - (*name)[len - 1] = '\0'; - - return 0; -} - -void -lt_opt_process_env_set (const char *arg) -{ - char *name = NULL; - char *value = NULL; - - if (lt_split_name_value (arg, &name, &value) != 0) - { - XFREE (name); - XFREE (value); - lt_fatal ("bad argument for %s: '%s'", env_set_opt, arg); - } - - lt_setenv (name, value); - XFREE (name); - XFREE (value); -} - -void -lt_opt_process_env_prepend (const char *arg) -{ - char *name = NULL; - char *value = NULL; - char *new_value = NULL; - - if (lt_split_name_value (arg, &name, &value) != 0) - { - XFREE (name); - XFREE (value); - lt_fatal ("bad argument for %s: '%s'", env_prepend_opt, arg); - } - - new_value = lt_extend_str (getenv (name), value, 0); - lt_setenv (name, new_value); - XFREE (new_value); - XFREE (name); - XFREE (value); -} - -void -lt_opt_process_env_append (const char *arg) -{ - char *name = NULL; - char *value = NULL; - char *new_value = NULL; - - if (lt_split_name_value (arg, &name, &value) != 0) - { - XFREE (name); - XFREE (value); - lt_fatal ("bad argument for %s: '%s'", env_append_opt, arg); - } - - new_value = lt_extend_str (getenv (name), value, 1); - lt_setenv (name, new_value); - XFREE (new_value); - XFREE (name); - XFREE (value); -} - -void -lt_update_exe_path (const char *name, const char *value) -{ - LTWRAPPER_DEBUGPRINTF (("(lt_update_exe_path) modifying '%s' by prepending '%s'\n", - (name ? name : ""), - (value ? value : ""))); - - if (name && *name && value && *value) - { - char *new_value = lt_extend_str (getenv (name), value, 0); - /* some systems can't cope with a ':'-terminated path #' */ - int len = strlen (new_value); - while (((len = strlen (new_value)) > 0) && IS_PATH_SEPARATOR (new_value[len-1])) - { - new_value[len-1] = '\0'; - } - lt_setenv (name, new_value); - XFREE (new_value); - } -} - -void -lt_update_lib_path (const char *name, const char *value) -{ - LTWRAPPER_DEBUGPRINTF (("(lt_update_lib_path) modifying '%s' by prepending '%s'\n", - (name ? name : ""), - (value ? value : ""))); - - if (name && *name && value && *value) - { - char *new_value = lt_extend_str (getenv (name), value, 0); - lt_setenv (name, new_value); - XFREE (new_value); - } -} - - -EOF -} -# end: func_emit_cwrapperexe_src - -# func_mode_link arg... -func_mode_link () -{ - $opt_debug - case $host in - *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-cegcc*) - # It is impossible to link a dll without this setting, and - # we shouldn't force the makefile maintainer to figure out - # which system we are compiling for in order to pass an extra - # flag for every libtool invocation. - # allow_undefined=no - - # FIXME: Unfortunately, there are problems with the above when trying - # to make a dll which has undefined symbols, in which case not - # even a static library is built. For now, we need to specify - # -no-undefined on the libtool link line when we can be certain - # that all symbols are satisfied, otherwise we get a static library. - allow_undefined=yes - ;; - *) - allow_undefined=yes - ;; - esac - libtool_args=$nonopt - base_compile="$nonopt $@" - compile_command=$nonopt - finalize_command=$nonopt - - compile_rpath= - finalize_rpath= - compile_shlibpath= - finalize_shlibpath= - convenience= - old_convenience= - deplibs= - old_deplibs= - compiler_flags= - linker_flags= - dllsearchpath= - lib_search_path=`pwd` - inst_prefix_dir= - new_inherited_linker_flags= - - avoid_version=no - dlfiles= - dlprefiles= - dlself=no - export_dynamic=no - export_symbols= - export_symbols_regex= - generated= - libobjs= - ltlibs= - module=no - no_install=no - objs= - non_pic_objects= - precious_files_regex= - prefer_static_libs=no - preload=no - prev= - prevarg= - release= - rpath= - xrpath= - perm_rpath= - temp_rpath= - thread_safe=no - vinfo= - vinfo_number=no - weak_libs= - single_module="${wl}-single_module" - func_infer_tag $base_compile - - # We need to know -static, to get the right output filenames. - for arg - do - case $arg in - -shared) - test "$build_libtool_libs" != yes && \ - func_fatal_configuration "can not build a shared library" - build_old_libs=no - break - ;; - -all-static | -static | -static-libtool-libs) - case $arg in - -all-static) - if test "$build_libtool_libs" = yes && test -z "$link_static_flag"; then - func_warning "complete static linking is impossible in this configuration" - fi - if test -n "$link_static_flag"; then - dlopen_self=$dlopen_self_static - fi - prefer_static_libs=yes - ;; - -static) - if test -z "$pic_flag" && test -n "$link_static_flag"; then - dlopen_self=$dlopen_self_static - fi - prefer_static_libs=built - ;; - -static-libtool-libs) - if test -z "$pic_flag" && test -n "$link_static_flag"; then - dlopen_self=$dlopen_self_static - fi - prefer_static_libs=yes - ;; - esac - build_libtool_libs=no - build_old_libs=yes - break - ;; - esac - done - - # See if our shared archives depend on static archives. - test -n "$old_archive_from_new_cmds" && build_old_libs=yes - - # Go through the arguments, transforming them on the way. - while test "$#" -gt 0; do - arg="$1" - shift - func_quote_for_eval "$arg" - qarg=$func_quote_for_eval_unquoted_result - func_append libtool_args " $func_quote_for_eval_result" - - # If the previous option needs an argument, assign it. - if test -n "$prev"; then - case $prev in - output) - func_append compile_command " @OUTPUT@" - func_append finalize_command " @OUTPUT@" - ;; - esac - - case $prev in - dlfiles|dlprefiles) - if test "$preload" = no; then - # Add the symbol object into the linking commands. - func_append compile_command " @SYMFILE@" - func_append finalize_command " @SYMFILE@" - preload=yes - fi - case $arg in - *.la | *.lo) ;; # We handle these cases below. - force) - if test "$dlself" = no; then - dlself=needless - export_dynamic=yes - fi - prev= - continue - ;; - self) - if test "$prev" = dlprefiles; then - dlself=yes - elif test "$prev" = dlfiles && test "$dlopen_self" != yes; then - dlself=yes - else - dlself=needless - export_dynamic=yes - fi - prev= - continue - ;; - *) - if test "$prev" = dlfiles; then - dlfiles="$dlfiles $arg" - else - dlprefiles="$dlprefiles $arg" - fi - prev= - continue - ;; - esac - ;; - expsyms) - export_symbols="$arg" - test -f "$arg" \ - || func_fatal_error "symbol file \`$arg' does not exist" - prev= - continue - ;; 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do - if $opt_duplicate_deps ; then - case "$libs " in - *" $deplib "*) specialdeplibs="$specialdeplibs $deplib" ;; - esac - fi - libs="$libs $deplib" - done - - if test "$linkmode" = lib; then - libs="$predeps $libs $compiler_lib_search_path $postdeps" - - # Compute libraries that are listed more than once in $predeps - # $postdeps and mark them as special (i.e., whose duplicates are - # not to be eliminated). - pre_post_deps= - if $opt_duplicate_compiler_generated_deps; then - for pre_post_dep in $predeps $postdeps; do - case "$pre_post_deps " in - *" $pre_post_dep "*) specialdeplibs="$specialdeplibs $pre_post_deps" ;; - esac - pre_post_deps="$pre_post_deps $pre_post_dep" - done - fi - pre_post_deps= - fi - - deplibs= - newdependency_libs= - newlib_search_path= - need_relink=no # whether we're linking any uninstalled libtool libraries - notinst_deplibs= # not-installed libtool libraries - notinst_path= # paths that contain not-installed libtool libraries - - case $linkmode in - lib) - passes="conv dlpreopen link" - for file in $dlfiles $dlprefiles; do - case $file in - *.la) ;; - *) - func_fatal_help "libraries can \`-dlopen' only libtool libraries: $file" - ;; - esac - done - ;; - prog) - compile_deplibs= - finalize_deplibs= - alldeplibs=no - newdlfiles= - newdlprefiles= - passes="conv scan dlopen dlpreopen link" - ;; - *) passes="conv" - ;; - esac - - for pass in $passes; do - # The preopen pass in lib mode reverses $deplibs; put it back here - # so that -L comes before libs that need it for instance... - if test "$linkmode,$pass" = "lib,link"; then - ## FIXME: Find the place where the list is rebuilt in the wrong - ## order, and fix it there properly - tmp_deplibs= - for deplib in $deplibs; do - tmp_deplibs="$deplib $tmp_deplibs" - done - deplibs="$tmp_deplibs" - fi - - if test "$linkmode,$pass" = "lib,link" || - test "$linkmode,$pass" = "prog,scan"; then - libs="$deplibs" - deplibs= - fi - if test "$linkmode" = prog; then - case $pass in - dlopen) libs="$dlfiles" ;; - dlpreopen) libs="$dlprefiles" ;; - link) - libs="$deplibs %DEPLIBS%" - test "X$link_all_deplibs" != Xno && libs="$libs $dependency_libs" - ;; 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then - case "$new_inherited_linker_flags " in - *" $deplib "*) ;; - * ) new_inherited_linker_flags="$new_inherited_linker_flags $deplib" ;; - esac - fi - fi - continue - ;; - -l*) - if test "$linkmode" != lib && test "$linkmode" != prog; then - func_warning "\`-l' is ignored for archives/objects" - continue - fi - func_stripname '-l' '' "$deplib" - name=$func_stripname_result - if test "$linkmode" = lib; then - searchdirs="$newlib_search_path $lib_search_path $compiler_lib_search_dirs $sys_lib_search_path $shlib_search_path" - else - searchdirs="$newlib_search_path $lib_search_path $sys_lib_search_path $shlib_search_path" - fi - for searchdir in $searchdirs; do - for search_ext in .la $std_shrext .so .a; do - # Search the libtool library - lib="$searchdir/lib${name}${search_ext}" - if test -f "$lib"; then - if test "$search_ext" = ".la"; then - found=yes - else - found=no - fi - break 2 - fi - done - done - if test "$found" != yes; then - # deplib doesn't seem to be a libtool library - if test "$linkmode,$pass" = "prog,link"; then - compile_deplibs="$deplib $compile_deplibs" - finalize_deplibs="$deplib $finalize_deplibs" - else - deplibs="$deplib $deplibs" - test "$linkmode" = lib && newdependency_libs="$deplib $newdependency_libs" - fi - continue - else # deplib is a libtool library - # If $allow_libtool_libs_with_static_runtimes && $deplib is a stdlib, - # We need to do some special things here, and not later. - if test "X$allow_libtool_libs_with_static_runtimes" = "Xyes" ; then - case " $predeps $postdeps " in - *" $deplib "*) - if func_lalib_p "$lib"; then - library_names= - old_library= - func_source "$lib" - for l in $old_library $library_names; do - ll="$l" - done - if test "X$ll" = "X$old_library" ; then # only static version available - found=no - func_dirname "$lib" "" "." - ladir="$func_dirname_result" - lib=$ladir/$old_library - if test "$linkmode,$pass" = "prog,link"; then - compile_deplibs="$deplib $compile_deplibs" - finalize_deplibs="$deplib $finalize_deplibs" - else - deplibs="$deplib $deplibs" - test "$linkmode" = lib && newdependency_libs="$deplib $newdependency_libs" - fi - continue - fi - fi - ;; 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then - $ECHO - $ECHO "*** And there doesn't seem to be a static archive available" - $ECHO "*** The link will probably fail, sorry" - else - add="$dir/$old_library" - fi - elif test -n "$old_library"; then - add="$dir/$old_library" - fi - fi - esac - elif test "$hardcode_minus_L" = no; then - case $host in - *-*-sunos*) add_shlibpath="$dir" ;; - esac - add_dir="-L$dir" - add="-l$name" - elif test "$hardcode_shlibpath_var" = no; then - add_shlibpath="$dir" - add="-l$name" - else - lib_linked=no - fi - ;; - relink) - if test "$hardcode_direct" = yes && - test "$hardcode_direct_absolute" = no; then - add="$dir/$linklib" - elif test "$hardcode_minus_L" = yes; then - add_dir="-L$dir" - # Try looking first in the location we're being installed to. - if test -n "$inst_prefix_dir"; then - case $libdir in - [\\/]*) - add_dir="$add_dir -L$inst_prefix_dir$libdir" - ;; - esac - fi - add="-l$name" - elif test "$hardcode_shlibpath_var" = yes; then - add_shlibpath="$dir" - add="-l$name" - else - lib_linked=no - fi - ;; - *) lib_linked=no ;; - esac - - if test "$lib_linked" != yes; then - func_fatal_configuration "unsupported hardcode properties" - fi - - if test -n "$add_shlibpath"; then - case :$compile_shlibpath: in - *":$add_shlibpath:"*) ;; - *) compile_shlibpath="$compile_shlibpath$add_shlibpath:" ;; - esac - fi - if test "$linkmode" = prog; then - test -n "$add_dir" && compile_deplibs="$add_dir $compile_deplibs" - test -n "$add" && compile_deplibs="$add $compile_deplibs" - else - test -n "$add_dir" && deplibs="$add_dir $deplibs" - test -n "$add" && deplibs="$add $deplibs" - if test "$hardcode_direct" != yes && - test "$hardcode_minus_L" != yes && - test "$hardcode_shlibpath_var" = yes; then - case :$finalize_shlibpath: in - *":$libdir:"*) ;; - *) finalize_shlibpath="$finalize_shlibpath$libdir:" ;; - esac - fi - fi - fi - - if test "$linkmode" = prog || test "$mode" = relink; then - add_shlibpath= - add_dir= - add= - # Finalize command for both is simple: just hardcode it. - if test "$hardcode_direct" = yes && - test "$hardcode_direct_absolute" = no; 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then - rmfiles="$rmfiles $objdir/lt-$name" - fi - if test "X$noexename" != "X$name" ; then - rmfiles="$rmfiles $objdir/lt-${noexename}.c" - fi - fi - fi - ;; - esac - func_show_eval "$RM $rmfiles" 'exit_status=1' - done - objdir="$origobjdir" - - # Try to remove the ${objdir}s in the directories where we deleted files - for dir in $rmdirs; do - if test -d "$dir"; then - func_show_eval "rmdir $dir >/dev/null 2>&1" - fi - done - - exit $exit_status -} - -{ test "$mode" = uninstall || test "$mode" = clean; } && - func_mode_uninstall ${1+"$@"} - -test -z "$mode" && { - help="$generic_help" - func_fatal_help "you must specify a MODE" -} - -test -z "$exec_cmd" && \ - func_fatal_help "invalid operation mode \`$mode'" - -if test -n "$exec_cmd"; then - eval exec "$exec_cmd" - exit $EXIT_FAILURE -fi - -exit $exit_status - - -# The TAGs below are defined such that we never get into a situation -# in which we disable both kinds of libraries. Given conflicting -# choices, we go for a static library, that is the most portable, -# since we can't tell whether shared libraries were disabled because -# the user asked for that or because the platform doesn't support -# them. This is particularly important on AIX, because we don't -# support having both static and shared libraries enabled at the same -# time on that platform, so we default to a shared-only configuration. -# If a disable-shared tag is given, we'll fallback to a static-only -# configuration. But we'll never go from static-only to shared-only. - -# ### BEGIN LIBTOOL TAG CONFIG: disable-shared -build_libtool_libs=no -build_old_libs=yes -# ### END LIBTOOL TAG CONFIG: disable-shared - -# ### BEGIN LIBTOOL TAG CONFIG: disable-static -build_old_libs=`case $build_libtool_libs in yes) echo no;; *) echo yes;; esac` -# ### END LIBTOOL TAG CONFIG: disable-static - -# Local Variables: -# mode:shell-script -# sh-indentation:2 -# End: -# vi:sw=2 - diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/as-compiler-flag.m4 crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/as-compiler-flag.m4 --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/as-compiler-flag.m4 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/as-compiler-flag.m4 1970-01-01 00:00:00.000000000 +0000 @@ -1,25 +0,0 @@ -dnl as-compiler-flag.m4 0.0.1 -dnl autostars m4 macro for detection of compiler flags -dnl -dnl ds@schleef.org - -AC_DEFUN([AS_COMPILER_FLAG], -[ - AC_MSG_CHECKING([to see if compiler understands $1]) - - save_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS $1" - - AC_TRY_COMPILE([ ], [], [flag_ok=yes], [flag_ok=no]) - CFLAGS="$save_CFLAGS" - - if test "X$flag_ok" = Xyes ; then - $2 - true - else - $3 - true - fi - AC_MSG_RESULT([$flag_ok]) -]) - diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/as-version.m4 crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/as-version.m4 --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/as-version.m4 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/as-version.m4 1970-01-01 00:00:00.000000000 +0000 @@ -1,66 +0,0 @@ -dnl as-version.m4 0.1.0 - -dnl autostars m4 macro for versioning - -dnl Thomas Vander Stichele - -dnl $Id: as-version.m4,v 1.2 2004-09-17 22:18:03 leroutier Exp $ - -dnl AS_VERSION(PACKAGE, PREFIX, MAJOR, MINOR, MICRO, NANO, -dnl ACTION-IF-NO-NANO, [ACTION-IF-NANO]) - -dnl example -dnl AS_VERSION(gstreamer, GST_VERSION, 0, 3, 2,) -dnl for a 0.3.2 release version - -dnl this macro -dnl - defines [$PREFIX]_MAJOR, MINOR and MICRO -dnl - if NANO is empty, then we're in release mode, else in cvs/dev mode -dnl - defines [$PREFIX], VERSION, and [$PREFIX]_RELEASE -dnl - executes the relevant action -dnl - AC_SUBST's PACKAGE, VERSION, [$PREFIX] and [$PREFIX]_RELEASE -dnl as well as the little ones -dnl - doesn't call AM_INIT_AUTOMAKE anymore because it prevents -dnl maintainer mode from running ok -dnl -dnl don't forget to put #undef [$2] and [$2]_RELEASE in acconfig.h -dnl if you use acconfig.h - -AC_DEFUN([AS_VERSION], -[ - PACKAGE=[$1] - [$2]_MAJOR=[$3] - [$2]_MINOR=[$4] - [$2]_MICRO=[$5] - NANO=[$6] - [$2]_NANO=$NANO - if test "x$NANO" = "x" || test "x$NANO" = "x0"; - then - AC_MSG_NOTICE(configuring [$1] for release) - VERSION=[$3].[$4].[$5] - [$2]_RELEASE=1 - dnl execute action - ifelse([$7], , :, [$7]) - else - AC_MSG_NOTICE(configuring [$1] for development with nano $NANO) - VERSION=[$3].[$4].[$5].$NANO - [$2]_RELEASE=0.`date +%Y%m%d.%H%M%S` - dnl execute action - ifelse([$8], , :, [$8]) - fi - - [$2]=$VERSION - AC_DEFINE_UNQUOTED([$2], "$[$2]", [Define the version]) - AC_SUBST([$2]) - AC_DEFINE_UNQUOTED([$2]_RELEASE, "$[$2]_RELEASE", [Define the release version]) - AC_SUBST([$2]_RELEASE) - - AC_SUBST([$2]_MAJOR) - AC_SUBST([$2]_MINOR) - AC_SUBST([$2]_MICRO) - AC_SUBST([$2]_NANO) - AC_DEFINE_UNQUOTED(PACKAGE, "$PACKAGE", [Define the package name]) - AC_SUBST(PACKAGE) - AC_DEFINE_UNQUOTED(VERSION, "$VERSION", [Define the version]) - AC_SUBST(VERSION) -]) diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/Makefile.am crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/Makefile.am --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/Makefile.am 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/Makefile.am 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -EXTRA_DIST = as-version.m4 as-compiler-flag.m4 diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/Makefile.in crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/Makefile.in --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/m4/Makefile.in 2010-10-12 20:47:19.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/m4/Makefile.in 1970-01-01 00:00:00.000000000 +0000 @@ -1,372 +0,0 @@ -# Makefile.in generated by automake 1.11.1 from Makefile.am. -# @configure_input@ - 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You may need the \`Bison' package - in order for those modifications to take effect. You can get - \`Bison' from any GNU archive site." - rm -f y.tab.c y.tab.h - if test $# -ne 1; then - eval LASTARG="\${$#}" - case $LASTARG in - *.y) - SRCFILE=`echo "$LASTARG" | sed 's/y$/c/'` - if test -f "$SRCFILE"; then - cp "$SRCFILE" y.tab.c - fi - SRCFILE=`echo "$LASTARG" | sed 's/y$/h/'` - if test -f "$SRCFILE"; then - cp "$SRCFILE" y.tab.h - fi - ;; - esac - fi - if test ! -f y.tab.h; then - echo >y.tab.h - fi - if test ! -f y.tab.c; then - echo 'main() { return 0; }' >y.tab.c - fi - ;; - - lex|flex) - echo 1>&2 "\ -WARNING: \`$1' is $msg. You should only need it if - you modified a \`.l' file. You may need the \`Flex' package - in order for those modifications to take effect. You can get - \`Flex' from any GNU archive site." - rm -f lex.yy.c - if test $# -ne 1; then - eval LASTARG="\${$#}" - case $LASTARG in - *.l) - SRCFILE=`echo "$LASTARG" | sed 's/l$/c/'` - if test -f "$SRCFILE"; then - cp "$SRCFILE" lex.yy.c - fi - ;; - esac - fi - if test ! -f lex.yy.c; then - echo 'main() { return 0; }' >lex.yy.c - fi - ;; - - help2man) - echo 1>&2 "\ -WARNING: \`$1' is $msg. You should only need it if - you modified a dependency of a manual page. You may need the - \`Help2man' package in order for those modifications to take - effect. You can get \`Help2man' from any GNU archive site." - - file=`echo "$*" | sed -n "$sed_output"` - test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"` - if test -f "$file"; then - touch $file - else - test -z "$file" || exec >$file - echo ".ab help2man is required to generate this page" - exit 1 - fi - ;; - - makeinfo) - echo 1>&2 "\ -WARNING: \`$1' is $msg. You should only need it if - you modified a \`.texi' or \`.texinfo' file, or any other file - indirectly affecting the aspect of the manual. The spurious - call might also be the consequence of using a buggy \`make' (AIX, - DU, IRIX). You might want to install the \`Texinfo' package or - the \`GNU make' package. Grab either from any GNU archive site." - # The file to touch is that specified with -o ... - file=`echo "$*" | sed -n "$sed_output"` - test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"` - if test -z "$file"; then - # ... or it is the one specified with @setfilename ... - infile=`echo "$*" | sed 's/.* \([^ ]*\) *$/\1/'` - file=`sed -n ' - /^@setfilename/{ - s/.* \([^ ]*\) *$/\1/ - p - q - }' $infile` - # ... or it is derived from the source name (dir/f.texi becomes f.info) - test -z "$file" && file=`echo "$infile" | sed 's,.*/,,;s,.[^.]*$,,'`.info - fi - # If the file does not exist, the user really needs makeinfo; - # let's fail without touching anything. - test -f $file || exit 1 - touch $file - ;; - - tar) - shift - - # We have already tried tar in the generic part. - # Look for gnutar/gtar before invocation to avoid ugly error - # messages. - if (gnutar --version > /dev/null 2>&1); then - gnutar "$@" && exit 0 - fi - if (gtar --version > /dev/null 2>&1); then - gtar "$@" && exit 0 - fi - firstarg="$1" - if shift; then - case $firstarg in - *o*) - firstarg=`echo "$firstarg" | sed s/o//` - tar "$firstarg" "$@" && exit 0 - ;; - esac - case $firstarg in - *h*) - firstarg=`echo "$firstarg" | sed s/h//` - tar "$firstarg" "$@" && exit 0 - ;; - esac - fi - - echo 1>&2 "\ -WARNING: I can't seem to be able to run \`tar' with the given arguments. - You may want to install GNU tar or Free paxutils, or check the - command line arguments." - exit 1 - ;; - - *) - echo 1>&2 "\ -WARNING: \`$1' is needed, and is $msg. - You might have modified some files without having the - proper tools for further handling them. Check the \`README' file, - it often tells you about the needed prerequisites for installing - this package. You may also peek at any GNU archive site, in case - some other package would contain this missing \`$1' program." - exit 1 - ;; -esac - -exit 0 - -# Local variables: -# eval: (add-hook 'write-file-hooks 'time-stamp) -# time-stamp-start: "scriptversion=" -# time-stamp-format: "%:y-%02m-%02d.%02H" -# time-stamp-end: "$" -# End: diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/NEWS crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/NEWS --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/NEWS 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/NEWS 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -Please refer to the release notes for all comments and instructions. \ No newline at end of file diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/README crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/README --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/README 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/README 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -Please refer to the release notes for all comments and instructions. \ No newline at end of file diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/decif.c crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/decif.c --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/decif.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/decif.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,207 +0,0 @@ -/******************************************************************** - * Copyright(c) 2008 Broadcom Corporation. - * - * Name: decif.cpp - * - * Description: Device Interface API. - * - * AU - * - * HISTORY: - * - ******************************************************************* - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published - * by the Free Software Foundation, either version 2.1 of the License. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - *******************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "decif.h" - -BC_STATUS decif_getcaps(BcmDecIF *decif, BC_HW_CAPS *hwCaps) -{ - BC_STATUS sts = BC_STS_SUCCESS; - if(decif != NULL) - sts = DtsGetCapabilities(decif->hdev, hwCaps); - else - sts = DtsGetCapabilities(NULL, hwCaps); - return sts; -} - -BC_STATUS decif_open(BcmDecIF *decif) -{ - BC_STATUS sts = BC_STS_SUCCESS; - guint32 mode = DTS_PLAYBACK_MODE | DTS_LOAD_FILE_PLAY_FW | DTS_SKIP_TX_CHK_CPB | - DTS_DFLT_RESOLUTION(vdecRESOLUTION_720p29_97); - sts = DtsDeviceOpen(&decif->hdev,mode); - if (sts != BC_STS_SUCCESS) - decif->hdev = NULL; - - return sts; -} - -BC_STATUS decif_close(BcmDecIF *decif) -{ - BC_STATUS sts = BC_STS_SUCCESS; - if (decif->hdev) { - sts = DtsDeviceClose(decif->hdev); - decif->hdev = NULL; - } - - return sts; -} - -BC_STATUS decif_prepare_play(BcmDecIF *decif) -{ - BC_STATUS sts = BC_STS_SUCCESS; - uint32_t stream_type = BC_STREAM_TYPE_ES; - - sts = DtsOpenDecoder(decif->hdev, stream_type); - return sts; - -} - -BC_STATUS decif_start_play(BcmDecIF *decif) -{ - BC_STATUS sts = DtsStartDecoder(decif->hdev); - - if (sts != BC_STS_SUCCESS) - return sts; - - sts = DtsStartCapture(decif->hdev); - - return sts; -} - -BC_STATUS decif_pause(BcmDecIF *decif, gboolean pause) -{ - BC_STATUS sts; - - if (pause) - sts = DtsPauseDecoder(decif->hdev); - else - sts = DtsResumeDecoder(decif->hdev); - - return sts; -} - -BC_STATUS decif_stop(BcmDecIF *decif) -{ - BC_STATUS sts = DtsStopDecoder(decif->hdev); - - if (sts != BC_STS_SUCCESS) - return sts; - - sts = DtsCloseDecoder(decif->hdev); - - return sts; -} - -BC_STATUS decif_flush_dec(BcmDecIF *decif, gint8 flush_type) -{ - return DtsFlushInput(decif->hdev, flush_type); -} - -BC_STATUS decif_flush_rxbuf(BcmDecIF *decif, gboolean discard_only) -{ - return DtsFlushRxCapture(decif->hdev, discard_only); -} - -BC_STATUS decif_setcolorspace(BcmDecIF *decif, BC_OUTPUT_FORMAT mode) -{ - return DtsSetColorSpace(decif->hdev,mode); -} - -BC_STATUS decif_send_buffer(BcmDecIF *decif, guint8 *buffer, guint32 size, - GstClockTime time_stamp, guint8 flags) -{ - BC_STATUS sts = BC_STS_SUCCESS; -// guint8 odd_bytes = 0; -// guint8 *psend_buff = decif->aligned_buf; -// -// while(((uintptr_t)psend_buff) & 0x03) -// psend_buff++; -// -// if (((uintptr_t)buffer) % 4) odd_bytes = 4 - ((guint8)((uintptr_t)buffer % 4)); -// -// if (odd_bytes) { -// memcpy(psend_buff, buffer, odd_bytes); -// sts = DtsProcInput(decif->hdev, psend_buff, odd_bytes, time_stamp, flags); -// time_stamp = 0; -// if (sts != BC_STS_SUCCESS) -// return sts; -// buffer += odd_bytes; -// size -= odd_bytes; -// if (!size) -// return BC_STS_SUCCESS; -// } - - sts = DtsProcInput(decif->hdev, buffer, size, time_stamp, flags); - - return sts; -} - -BC_STATUS decif_get_drv_status(BcmDecIF *decif, gboolean *suspended, guint32 *rll, guint32 *picNumFlags) -{ - BC_DTS_STATUS drv_status; - BC_STATUS sts = DtsGetDriverStatus(decif->hdev, &drv_status); - if (sts == BC_STS_SUCCESS) { - if (drv_status.PowerStateChange) - *suspended = TRUE; - else - *suspended = FALSE; - *rll = drv_status.ReadyListCount; - *picNumFlags = drv_status.picNumFlags; - } - - return sts; -} - -BC_STATUS decif_get_eos(BcmDecIF *decif, gboolean *bEOS) -{ - return DtsIsEndOfStream(decif->hdev, (uint8_t *)bEOS); -} - -BC_STATUS decif_decode_catchup(BcmDecIF *decif, gboolean catchup) -{ - BC_STATUS sts; - - return sts=BC_STS_SUCCESS; // Temporarily disable Catchup - - if (catchup) - sts = DtsSetFFRate(decif->hdev, 2); - else - sts = DtsSetFFRate(decif->hdev, 1); - - return sts; -} - -BC_STATUS decif_setinputformat(BcmDecIF *decif, BC_INPUT_FORMAT bcInputFormat) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - sts = DtsSetInputFormat(decif->hdev, &bcInputFormat); - - return sts; -} \ No newline at end of file diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/decif.h crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/decif.h --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/decif.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/decif.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,88 +0,0 @@ -/******************************************************************** - * Copyright(c) 2008 Broadcom Corporation. - * - * Name: decif.h - * - * Description: Devic Interface API. - * - * AU - * - * HISTORY: - * - ******************************************************************* - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published - * by the Free Software Foundation, either version 2.1 of the License. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - *******************************************************************/ -#ifndef __BCMDECIF_H__ -#define __BCMDECIF_H__ - -#include "bc_dts_defs.h" -#include "libcrystalhd_if.h" - -#define PROC_TIMEOUT 3000 -#define ALIGN_BUF_SIZE (512*1024) - -struct _DecIf -{ - HANDLE hdev; -}; -typedef struct _DecIf BcmDecIF; - -BC_STATUS decif_getcaps(BcmDecIF *decif, BC_HW_CAPS *hwCaps); - -BC_STATUS -decif_open(BcmDecIF * decif); - -BC_STATUS -decif_close(BcmDecIF * decif); - -BC_STATUS -decif_prepare_play(BcmDecIF* decif); - -BC_STATUS -decif_start_play(BcmDecIF * decif); - -BC_STATUS -decif_pause(BcmDecIF * decif,gboolean pause); - -BC_STATUS -decif_stop(BcmDecIF * decif); - -BC_STATUS -decif_flush_dec(BcmDecIF * decif,gint8 flush_type); - -BC_STATUS -decif_flush_rxbuf(BcmDecIF * decif,gboolean discard_only); - -BC_STATUS -decif_send_buffer(BcmDecIF * decif,guint8* buffer,guint32 size,GstClockTime time_stamp,guint8 flags); - -BC_STATUS -decif_setcolorspace(BcmDecIF * decif, BC_OUTPUT_FORMAT mode); - -BC_STATUS -decif_get_drv_status(BcmDecIF * decif, gboolean* suspended, guint32 *rll, guint32 *picNumFlags); - -BC_STATUS -decif_get_eos(BcmDecIF *decif, gboolean *bEOS); - -BC_STATUS -decif_decode_catchup(BcmDecIF * decif, gboolean catchup); - -BC_STATUS -decif_setinputformat(BcmDecIF *decif, BC_INPUT_FORMAT bcInputFormat); - -#endif - - - diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/gstbcmdec.c crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/gstbcmdec.c --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/gstbcmdec.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/gstbcmdec.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,2772 +0,0 @@ -/******************************************************************** - * Copyright(c) 2008 Broadcom Corporation. - * - * Name: gstbcmdec.c - * - * Description: Broadcom 70012 decoder plugin - * - * AU - * - * HISTORY: - * - ******************************************************************* - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published - * by the Free Software Foundation, either version 2.1 of the License. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - *******************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef HAVE_CONFIG_H -#include -#endif - -#include - -#include "decif.h" -#include "parse.h" -#include "gstbcmdec.h" - -GST_DEBUG_CATEGORY_STATIC (gst_bcmdec_debug); -#define GST_CAT_DEFAULT gst_bcmdec_debug - -//#define YV12__ - -//#define FILE_DUMP__ 1 - -static GstFlowReturn bcmdec_send_buff_detect_error(GstBcmDec *bcmdec, GstBuffer *buf, - guint8* pbuffer, guint32 size, - guint32 offset, GstClockTime tCurrent, - guint8 flags) -{ - BC_STATUS sts, suspend_sts = BC_STS_SUCCESS; - gboolean suspended = FALSE; - guint32 rll=0; - guint32 nextPicNumFlags = 0; - - sts = decif_send_buffer(&bcmdec->decif, pbuffer, size, tCurrent, flags); - - if (sts != BC_STS_SUCCESS) { - GST_ERROR_OBJECT(bcmdec, "proc input failed sts = %d", sts); - GST_ERROR_OBJECT(bcmdec, "Chain: timeStamp = %llu size = %d data = %p", - GST_BUFFER_TIMESTAMP(buf), GST_BUFFER_SIZE(buf), - GST_BUFFER_DATA (buf)); - if ((sts == BC_STS_IO_USER_ABORT) || (sts == BC_STS_ERROR)) { - suspend_sts = decif_get_drv_status(&bcmdec->decif,&suspended, &rll, &nextPicNumFlags); - if (suspend_sts == BC_STS_SUCCESS) { - if (suspended) { - GST_DEBUG_OBJECT(bcmdec, "suspend status recv"); - if (!bcmdec->suspend_mode) { - bcmdec_suspend_callback(bcmdec); - bcmdec->suspend_mode = TRUE; - GST_DEBUG_OBJECT(bcmdec, "suspend done", sts); - } - if (bcmdec_resume_callback(bcmdec) == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "resume done", sts); - bcmdec->suspend_mode = FALSE; - sts = decif_send_buffer(&bcmdec->decif, pbuffer, size, tCurrent, flags); - GST_ERROR_OBJECT(bcmdec, "proc input..2 sts = %d", sts); - } else { - GST_DEBUG_OBJECT(bcmdec, "resume failed", sts); - } - } - else if (sts == BC_STS_ERROR) { - GST_DEBUG_OBJECT(bcmdec, "device is not suspended"); - //gst_buffer_unref (buf); - return GST_FLOW_ERROR; - } - } else { - GST_DEBUG_OBJECT(bcmdec, "decif_get_drv_status -- failed %d", sts); - } - } - } - - return GST_FLOW_OK; -} - -/* bcmdec signals and args */ -enum { - /* FILL ME */ - LAST_SIGNAL -}; - -enum { - PROP_0, - PROP_SILENT -}; - - -GLB_INST_STS *g_inst_sts = NULL; - -/* - * the capabilities of the inputs and outputs. - * - * describe the real formats here. - */ -static GstStaticPadTemplate sink_factory_bcm70015 = GST_STATIC_PAD_TEMPLATE("sink", GST_PAD_SINK, GST_PAD_ALWAYS, - GST_STATIC_CAPS("video/mpeg, " "mpegversion = (int) {2, 4}," "systemstream =(boolean) false; " - "video/x-h264;" "video/x-vc1;" "video/x-wmv, " "wmvversion = (int) {3};" - "video/x-msmpeg, " "msmpegversion = (int) {43};" - "video/x-divx, " "divxversion = (int) {3, 4, 5};" "video/x-xvid;")); - -static GstStaticPadTemplate sink_factory_bcm70012 = GST_STATIC_PAD_TEMPLATE("sink", GST_PAD_SINK, GST_PAD_ALWAYS, - GST_STATIC_CAPS("video/mpeg, " "mpegversion = (int) {2}," "systemstream =(boolean) false; " - "video/x-h264;" "video/x-vc1;" "video/x-wmv, " "wmvversion = (int) {3};")); - -#ifdef YV12__ -static GstStaticPadTemplate src_factory = GST_STATIC_PAD_TEMPLATE("src", GST_PAD_SRC, GST_PAD_ALWAYS, - GST_STATIC_CAPS("video/x-raw-yuv, " "format = (fourcc) { YV12 }, " "width = (int) [ 1, MAX ], " - "height = (int) [ 1, MAX ], " "framerate = (fraction) [ 0/1, 2147483647/1 ]")); -#define BUF_MULT (12 / 8) -#define BUF_MODE MODE420 -#else -static GstStaticPadTemplate src_factory = GST_STATIC_PAD_TEMPLATE("src", GST_PAD_SRC, GST_PAD_ALWAYS, - GST_STATIC_CAPS("video/x-raw-yuv, " "format = (fourcc) { YUY2 } , " "framerate = (fraction) [0,MAX], " - "width = (int) [1,MAX], " "height = (int) [1,MAX]; " "video/x-raw-yuv, " - "format = (fourcc) { UYVY } , " "framerate = (fraction) [0,MAX], " "width = (int) [1,MAX], " - "height = (int) [1,MAX]; ")); -#define BUF_MULT (16 / 8) -#define BUF_MODE MODE422_YUY2 -#endif - -GST_BOILERPLATE(GstBcmDec, gst_bcmdec, GstElement, GST_TYPE_ELEMENT); - -/* GObject vmethod implementations */ - -static void gst_bcmdec_base_init(gpointer gclass) -{ - static GstElementDetails element_details; - BC_HW_CAPS hwCaps; - - element_details.klass = (gchar *)"Codec/Decoder/Video"; - element_details.longname = (gchar *)"Generic Video Decoder"; - element_details.description = (gchar *)"Decodes various Video Formats using CrystalHD Decoders"; - element_details.author = (gchar *)"BRCM"; - - GstElementClass *element_class = GST_ELEMENT_CLASS(gclass); - - hwCaps.DecCaps = 0; - decif_getcaps(NULL, &hwCaps); - - gst_element_class_add_pad_template(element_class, gst_static_pad_template_get (&src_factory)); - if(hwCaps.DecCaps & BC_DEC_FLAGS_M4P2) - gst_element_class_add_pad_template(element_class, gst_static_pad_template_get (&sink_factory_bcm70015)); - else - gst_element_class_add_pad_template(element_class, gst_static_pad_template_get (&sink_factory_bcm70012)); - gst_element_class_set_details(element_class, &element_details); -} - -/* initialize the bcmdec's class */ -static void gst_bcmdec_class_init(GstBcmDecClass *klass) -{ - GObjectClass *gobject_class; - GstElementClass *gstelement_class; - - gobject_class = (GObjectClass *)klass; - gstelement_class = (GstElementClass *)klass; - - gstelement_class->change_state = gst_bcmdec_change_state; - - gobject_class->set_property = gst_bcmdec_set_property; - gobject_class->get_property = gst_bcmdec_get_property; - gobject_class->finalize = gst_bcmdec_finalize; - - g_object_class_install_property(gobject_class, PROP_SILENT, - g_param_spec_boolean("silent", "Silent", - "Produce verbose output ?", - FALSE, (GParamFlags)G_PARAM_READWRITE)); -} - -/* - * initialize the new element - * instantiate pads and add them to element - * set pad calback functions - * initialize instance structure - */ -static void gst_bcmdec_init(GstBcmDec *bcmdec, GstBcmDecClass *gclass) -{ - pid_t pid; - BC_STATUS sts = BC_STS_SUCCESS; - int shmid = 0; - BC_HW_CAPS hwCaps; - - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_init"); - - bcmdec_reset(bcmdec); - - hwCaps.DecCaps = 0; - sts = decif_getcaps(&bcmdec->decif, &hwCaps); - if(hwCaps.DecCaps & BC_DEC_FLAGS_M4P2) { - bcmdec->sinkpad = gst_pad_new_from_static_template(&sink_factory_bcm70015, "sink"); - } - else - bcmdec->sinkpad = gst_pad_new_from_static_template(&sink_factory_bcm70012, "sink"); - - gst_pad_set_event_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_sink_event)); - - gst_pad_set_setcaps_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_sink_set_caps)); - gst_pad_set_getcaps_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_getcaps)); - gst_pad_set_chain_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_chain)); - - bcmdec->srcpad = gst_pad_new_from_static_template (&src_factory, "src"); - - gst_pad_set_getcaps_function(bcmdec->srcpad, GST_DEBUG_FUNCPTR(gst_bcmdec_getcaps)); - - gst_pad_set_event_function(bcmdec->srcpad, GST_DEBUG_FUNCPTR(gst_bcmdec_src_event)); - - gst_pad_use_fixed_caps(bcmdec->srcpad); - bcmdec_negotiate_format(bcmdec); - - gst_element_add_pad(GST_ELEMENT(bcmdec), bcmdec->sinkpad); - gst_element_add_pad(GST_ELEMENT(bcmdec), bcmdec->srcpad); - bcmdec->silent = FALSE; - pid = getpid(); - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_init _-- PID = %x",pid); - - sts = bcmdec_create_shmem(bcmdec, &shmid); - - GST_DEBUG_OBJECT(bcmdec, "bcmdec_create_shmem _-- Sts = %x",sts); -} - -/* plugin close function*/ -static void gst_bcmdec_finalize(GObject *object) -{ - GstBcmDec *bcmdec = GST_BCMDEC(object); - - bcmdec_del_shmem(bcmdec); - /*gst_bcmdec_cleanup(bcmdec);*/ - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_finalize"); - G_OBJECT_CLASS(parent_class)->finalize(object); -} - -static void gst_bcmdec_set_property(GObject *object, guint prop_id, - const GValue *value, GParamSpec *pspec) -{ - GstBcmDec *bcmdec = GST_BCMDEC(object); - - switch (prop_id) { - case PROP_SILENT: - bcmdec->silent = g_value_get_boolean (value); - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_set_property PROP_SILENT"); - break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID(object, prop_id, pspec); - break; - } - - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_set_property"); -} - -static void gst_bcmdec_get_property(GObject *object, guint prop_id, - GValue *value, GParamSpec *pspec) -{ - GstBcmDec *bcmdec = GST_BCMDEC(object); - - switch (prop_id) { - case PROP_SILENT: - g_value_set_boolean (value, bcmdec->silent); - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_get_property PROP_SILENT"); - break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; - } - - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_get_property"); -} - -/* GstElement vmethod implementations */ -static gboolean gst_bcmdec_sink_event(GstPad* pad, GstEvent* event) -{ - GstBcmDec *bcmdec; - BC_STATUS sts = BC_STS_SUCCESS; - bcmdec = GST_BCMDEC(gst_pad_get_parent(pad)); - - gboolean result = TRUE; - - switch (GST_EVENT_TYPE(event)) { - case GST_EVENT_NEWSEGMENT: - GstFormat newsegment_format; - gint64 newsegment_start; - - gst_event_parse_new_segment(event, NULL, NULL, &newsegment_format, - &newsegment_start, NULL, NULL); - - bcmdec->base_clock_time = newsegment_start; - bcmdec->cur_stream_time = 0; - - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "new segment"); - - bcmdec->codec_params.inside_buffer = TRUE; - bcmdec->codec_params.consumed_offset = 0; - bcmdec->codec_params.strtcode_offset = 0; - bcmdec->codec_params.nal_sz = 0; - bcmdec->insert_pps = TRUE; - bcmdec->base_time = 0; - - bcmdec->spes_frame_cnt = 0; - bcmdec->catchup_on = FALSE; - bcmdec->last_output_spes_time = 0; - bcmdec->last_spes_time = 0; - - result = gst_pad_push_event(bcmdec->srcpad, event); - break; - - case GST_EVENT_FLUSH_START: - GST_DEBUG_OBJECT(bcmdec, "Flush Start"); - -#if 0 - pthread_mutex_lock(&bcmdec->fn_lock); - if (!g_inst_sts->waiting) /*in case of playback process waiting*/ - bcmdec_process_flush_start(bcmdec); - pthread_mutex_unlock(&bcmdec->fn_lock); -#endif - bcmdec_process_flush_start(bcmdec); - result = gst_pad_push_event(bcmdec->srcpad, event); - break; - - case GST_EVENT_FLUSH_STOP: - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "Flush Stop"); - //if (!g_inst_sts->waiting) - // bcmdec_process_flush_stop(bcmdec); - bcmdec_process_flush_stop(bcmdec); - result = gst_pad_push_event(bcmdec->srcpad, event); - break; - - case GST_EVENT_EOS: - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "EOS on sink pad"); - sts = decif_flush_dec(&bcmdec->decif, 0); - GST_DEBUG_OBJECT(bcmdec, "dec_flush ret = %d", sts); - bcmdec->ev_eos = event; - gst_event_ref(bcmdec->ev_eos); - break; - - default: - result = gst_pad_push_event(bcmdec->srcpad, event); - GST_DEBUG_OBJECT(bcmdec, "unhandled event on sink pad"); - break; - } - - gst_object_unref(bcmdec); - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_sink_event %u", GST_EVENT_TYPE(event)); - return result; -} - -static GstCaps *gst_bcmdec_getcaps (GstPad * pad) -{ - GstBcmDec *bcmdec; - GstCaps *caps; - bcmdec = GST_BCMDEC(gst_pad_get_parent(pad)); - - caps = gst_caps_copy (gst_pad_get_pad_template_caps (pad)); - - return caps; -} - -/* this function handles the link with other elements */ -static gboolean gst_bcmdec_sink_set_caps(GstPad *pad, GstCaps *caps) -{ - GstBcmDec *bcmdec; - bcmdec = GST_BCMDEC(gst_pad_get_parent(pad)); - GstStructure *structure; - GstCaps *intersection; - const gchar *mime; - guint num = 0; - guint den = 0; - const GValue *g_value; - int version = 0; - GstBuffer *buffer; - guint8 *data; - guint size; - guint index; - - GST_DEBUG_OBJECT (pad, "setcaps called"); - - intersection = gst_caps_intersect(gst_pad_get_pad_template_caps(pad), caps); - GST_DEBUG_OBJECT(bcmdec, "Intersection return %", GST_PTR_FORMAT, intersection); - if (gst_caps_is_empty(intersection)) { - GST_ERROR_OBJECT(bcmdec, "setscaps:caps empty"); - gst_object_unref(bcmdec); - return FALSE; - } - gst_caps_unref(intersection); - structure = gst_caps_get_structure(caps, 0); - mime = gst_structure_get_name(structure); - if (!strcmp("video/x-h264", mime)) { - bcmdec->input_format = BC_MSUBTYPE_AVC1; // GStreamer uses the bit-stream format so have to add start codes - // We might override this later down below if the codec_data indicates otherwise - // So don't print codec type yet GST_DEBUG_OBJECT(bcmdec, "InFmt H.264"); - } else if (!strcmp("video/mpeg", mime)) { - gst_structure_get_int(structure, "mpegversion", &version); - if (version == 2) { - bcmdec->input_format = BC_MSUBTYPE_MPEG2VIDEO; - GST_DEBUG_OBJECT(bcmdec, "InFmt MPEG2"); - } else if (version == 4) { - bcmdec->input_format = BC_MSUBTYPE_DIVX; - GST_DEBUG_OBJECT(bcmdec, "InFmt MPEG4"); - } else { - gst_object_unref(bcmdec); - return FALSE; - } - } else if (!strcmp("video/x-vc1", mime)) { - bcmdec->input_format = BC_MSUBTYPE_VC1; - GST_DEBUG_OBJECT(bcmdec, "InFmt VC1"); - } else if (!strcmp("video/x-divx", mime)) { - gst_structure_get_int(structure, "divxversion", &version); - if(version == 3) { - bcmdec->input_format = BC_MSUBTYPE_DIVX311; - GST_DEBUG_OBJECT(bcmdec, "InFmt DIVX3"); - } else { - bcmdec->input_format = BC_MSUBTYPE_DIVX; - GST_DEBUG_OBJECT(bcmdec, "InFmt DIVX%d", version); - } - } else if (!strcmp("video/x-xvid", mime)) { - bcmdec->input_format = BC_MSUBTYPE_DIVX; - GST_DEBUG_OBJECT(bcmdec, "InFmt XVID"); - } else if (!strcmp("video/x-msmpeg", mime)) { - bcmdec->input_format = BC_MSUBTYPE_DIVX311; - GST_DEBUG_OBJECT(bcmdec, "InFmt MPMPEGv43"); - } else if (!strcmp("video/x-wmv", mime)) { - gst_structure_get_int(structure, "wmvversion", &version); - if(version == 3) { - bcmdec->input_format = BC_MSUBTYPE_WMV3; - GST_DEBUG_OBJECT(bcmdec, "InFmt WMV9"); - } else { - gst_object_unref(bcmdec); - return FALSE; - } - } else { - GST_DEBUG_OBJECT(bcmdec, "unknown mime %s", mime); - gst_object_unref(bcmdec); - return FALSE; - } - - g_value = gst_structure_get_value(structure, "framerate"); - if (g_value != NULL) { - num = gst_value_get_fraction_numerator(g_value); - den = gst_value_get_fraction_denominator(g_value); - - bcmdec->input_framerate = (double)num / den; - GST_LOG_OBJECT(bcmdec, "demux frame rate = %f ", bcmdec->input_framerate); - } else { - GST_DEBUG_OBJECT(bcmdec, "no demux framerate_value"); - } - - g_value = gst_structure_get_value(structure, "pixel-aspect-ratio"); - if (g_value) { - bcmdec->input_par_x = gst_value_get_fraction_numerator(g_value); - bcmdec->input_par_y = gst_value_get_fraction_denominator(g_value); - GST_DEBUG_OBJECT(bcmdec, "sink caps have pixel-aspect-ratio of %d:%d", - bcmdec->input_par_x, bcmdec->input_par_y); - if (bcmdec->input_par_x > 5 * bcmdec->input_par_y) { - bcmdec->input_par_x = 1; - bcmdec->input_par_y = 1; - GST_DEBUG_OBJECT(bcmdec, "demux par reset"); - } - - } else { - GST_DEBUG_OBJECT (bcmdec, "no par from demux"); - } - - gst_structure_get_int(structure, "width", &bcmdec->frame_width); - gst_structure_get_int(structure, "height", &bcmdec->frame_height); - - // Check Codec Data for various codecs - // Determine if this is bitstream video (AVC1 or no start codes) or Byte stream video (H264) - // Determine if this is VC-1 AP or SP/MP for VC-1 - if ((g_value = gst_structure_get_value (structure, "codec_data"))) { - if (G_VALUE_TYPE(g_value) == GST_TYPE_BUFFER) { - if (!strcmp("video/x-h264", mime)) { - GST_DEBUG_OBJECT (bcmdec, "Don't have start codes'"); - bcmdec->input_format = BC_MSUBTYPE_AVC1; - GST_DEBUG_OBJECT(bcmdec, "InFmt H.264 (AVC1)"); - - buffer = gst_value_get_buffer(g_value); - data = GST_BUFFER_DATA(buffer); - size = GST_BUFFER_SIZE(buffer); - - GST_DEBUG_OBJECT(bcmdec, "codec_data size = %d", size); - - /* parse the avcC data */ - if (size < 7) { - GST_ERROR_OBJECT(bcmdec, "avcC size %u < 7", size); - goto avcc_error; - } - /* parse the version, this must be 1 */ - if (data[0] != 1) - goto wrong_version; - - if (bcmdec->codec_params.sps_pps_buf == NULL) - bcmdec->codec_params.sps_pps_buf = (guint8 *)malloc(size * 2); - if (bcmdec_insert_sps_pps(bcmdec, buffer) != BC_STS_SUCCESS) { - bcmdec->codec_params.pps_size = 0; - } - } else if (!strcmp("video/x-wmv", mime)) { - buffer = gst_value_get_buffer(g_value); - data = GST_BUFFER_DATA(buffer); - size = GST_BUFFER_SIZE(buffer); - - GST_DEBUG_OBJECT(bcmdec, "codec_data size = %d", size); - if (size == 4) { - // Simple or Main Profile - bcmdec->input_format = BC_MSUBTYPE_WMV3; - GST_DEBUG_OBJECT(bcmdec, "InFmt VC-1 (SP/MP)"); - if (bcmdec->codec_params.sps_pps_buf == NULL) - bcmdec->codec_params.sps_pps_buf = (guint8 *)malloc(4); - memcpy(bcmdec->codec_params.sps_pps_buf, data, 4); - bcmdec->codec_params.pps_size = 4; - } else { - bcmdec->input_format = BC_MSUBTYPE_VC1; - GST_DEBUG_OBJECT(bcmdec, "InFmt VC-1 (AP)"); - for (index = 0; index < size; index++) { - data += index; - if (((size - index) >= 4) && (*data == 0x00) && (*(data + 1) == 0x00) && - (*(data + 2) == 0x01) && (*(data + 3) == 0x0f)) { - GST_DEBUG_OBJECT(bcmdec, "VC1 Sequence Header Found for Adv Profile"); - - if ((size - index + 1) > MAX_ADV_PROF_SEQ_HDR_SZ) - bcmdec->codec_params.pps_size = MAX_ADV_PROF_SEQ_HDR_SZ; - else - bcmdec->codec_params.pps_size = size - index + 1; - memcpy(bcmdec->codec_params.sps_pps_buf, data, bcmdec->codec_params.pps_size); - break; - } - } - } - } - } - } else { - if (!strcmp("video/x-h264", mime)) { - GST_DEBUG_OBJECT (bcmdec, "Have start codes'"); - bcmdec->input_format = BC_MSUBTYPE_H264; - GST_DEBUG_OBJECT(bcmdec, "InFmt H.264 (H264)");; - bcmdec->codec_params.nal_size_bytes = 4; // 4 sync bytes used - } else { - // No Codec data. So try with FourCC for VC1/WMV9 - if (!strcmp("video/x-wmv", mime)) { - guint32 fourcc; - if (gst_structure_get_fourcc (structure, "format", &fourcc)) { - if ((fourcc == GST_MAKE_FOURCC ('W', 'V', 'C', '1')) || - (fourcc == GST_MAKE_FOURCC ('W', 'M', 'V', 'A'))) { - bcmdec->input_format = BC_MSUBTYPE_VC1; - GST_DEBUG_OBJECT(bcmdec, "InFmt VC-1 (AP)"); - } else { - GST_DEBUG_OBJECT(bcmdec, "no codec_data. Don't know how to handle"); - gst_object_unref(bcmdec); - return FALSE; - } - } - } else { - GST_DEBUG_OBJECT(bcmdec, "no codec_data. Don't know how to handle"); - gst_object_unref(bcmdec); - return FALSE; - } - } - } - - if (bcmdec->play_pending) { - bcmdec->play_pending = FALSE; - bcmdec_process_play(bcmdec); - } - - gst_object_unref(bcmdec); - - return TRUE; - - /* ERRORS */ -avcc_error: - { - gst_object_unref(bcmdec); - return FALSE; - } - -wrong_version: - { - GST_ERROR_OBJECT(bcmdec, "wrong avcC version"); - gst_object_unref(bcmdec); - return FALSE; - } -} - -void bcmdec_msleep(gint msec) -{ - gint cnt = msec; - - while (cnt) { - usleep(1000); - cnt--; - } -} - -/* - * chain function - * this function does the actual processing - */ -static GstFlowReturn gst_bcmdec_chain(GstPad *pad, GstBuffer *buf) -{ - GstBcmDec *bcmdec; -// BC_STATUS sts = BC_STS_SUCCESS; - guint32 buf_sz = 0; - guint32 offset = 0; - GstClockTime tCurrent = 0; - guint8 *pbuffer; - guint32 size = 0; -// guint32 vc1_buff_sz = 0; - - -#ifdef FILE_DUMP__ - guint32 bytes_written =0; -#endif - bcmdec = GST_BCMDEC (GST_OBJECT_PARENT (pad)); - -#ifdef FILE_DUMP__ - if (bcmdec->fhnd == NULL) - bcmdec->fhnd = fopen("dump2.264", "a+"); -#endif - - if (bcmdec->flushing) { - GST_DEBUG_OBJECT(bcmdec, "input while flushing"); - gst_buffer_unref(buf); - return GST_FLOW_OK; - } - - if (GST_CLOCK_TIME_NONE != GST_BUFFER_TIMESTAMP(buf)) { - if (bcmdec->base_time == 0) { - bcmdec->base_time = GST_BUFFER_TIMESTAMP(buf); - GST_DEBUG_OBJECT(bcmdec, "base time is set to %llu", bcmdec->base_time / 1000000); - } - tCurrent = GST_BUFFER_TIMESTAMP(buf); - } - buf_sz = GST_BUFFER_SIZE(buf); - - if (bcmdec->play_pending) { - bcmdec->play_pending = FALSE; - bcmdec_process_play(bcmdec); - } else if (!bcmdec->streaming) { - GST_DEBUG_OBJECT(bcmdec, "input while streaming is false"); - gst_buffer_unref(buf); - return GST_FLOW_WRONG_STATE; - } - - pbuffer = GST_BUFFER_DATA (buf); - size = GST_BUFFER_SIZE(buf); - - if (GST_FLOW_OK != bcmdec_send_buff_detect_error(bcmdec, buf, pbuffer, size, offset, tCurrent, bcmdec->proc_in_flags)) { - gst_buffer_unref(buf); - return GST_FLOW_ERROR; - } - -#ifdef FILE_DUMP__ - bytes_written = fwrite(GST_BUFFER_DATA(buf), sizeof(unsigned char), GST_BUFFER_SIZE(buf), bcmdec->fhnd); -#endif - - gst_buffer_unref(buf); - return GST_FLOW_OK; -} - -static gboolean gst_bcmdec_src_event(GstPad *pad, GstEvent *event) -{ - gboolean result; - GstBcmDec *bcmdec; - - bcmdec = GST_BCMDEC(GST_OBJECT_PARENT(pad)); - - result = gst_pad_push_event(bcmdec->sinkpad, event); - - return result; -} - -static gboolean bcmdec_negotiate_format(GstBcmDec *bcmdec) -{ - GstCaps *caps; - guint32 fourcc; - gboolean result; - guint num = (guint)(bcmdec->output_params.framerate * 1000); - guint den = 1000; - GstStructure *s1; - const GValue *framerate_value; - GstVideoFormat vidFmt; - -#ifdef YV12__ - fourcc = GST_STR_FOURCC("YV12"); - vidFmt = GST_VIDEO_FORMAT_YV12; -#else - fourcc = GST_STR_FOURCC("YUY2"); - vidFmt = GST_VIDEO_FORMAT_YUY2; -#endif - GST_DEBUG_OBJECT(bcmdec, "framerate = %f", bcmdec->output_params.framerate); - - if(bcmdec->interlace) { - caps = gst_video_format_new_caps_interlaced(vidFmt, bcmdec->output_params.width, - bcmdec->output_params.height, num, den, - bcmdec->output_params.aspectratio_x, - bcmdec->output_params.aspectratio_y, - TRUE); - } else { - caps = gst_video_format_new_caps(vidFmt, bcmdec->output_params.width, - bcmdec->output_params.height, num, den, - bcmdec->output_params.aspectratio_x, - bcmdec->output_params.aspectratio_y); - } - - result = gst_pad_set_caps(bcmdec->srcpad, caps); - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_negotiate_format %d", result); - - if (bcmdec->output_params.clr_space == MODE422_YUY2) { - bcmdec->output_params.y_size = bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT; - if (bcmdec->interlace) { - GST_DEBUG_OBJECT(bcmdec, "bcmdec_negotiate_format Interlaced"); - bcmdec->output_params.y_size /= 2; - } - bcmdec->output_params.uv_size = 0; - GST_DEBUG_OBJECT(bcmdec, "YUY2 set on caps"); - } else if (bcmdec->output_params.clr_space == MODE420) { - bcmdec->output_params.y_size = bcmdec->output_params.width * bcmdec->output_params.height; - bcmdec->output_params.uv_size = bcmdec->output_params.width * bcmdec->output_params.height / 2; -#ifdef YV12__ - if (bcmdec->interlace) { - GST_DEBUG_OBJECT(bcmdec, "bcmdec_negotiate_format Interlaced"); - bcmdec->output_params.y_size = bcmdec->output_params.width * bcmdec->output_params.height / 2; - bcmdec->output_params.uv_size = bcmdec->output_params.y_size / 2; - } -#endif - GST_DEBUG_OBJECT(bcmdec, "420 set on caps"); - } - - s1 = gst_caps_get_structure(caps, 0); - - framerate_value = gst_structure_get_value(s1, "framerate"); - if (framerate_value != NULL) { - num = gst_value_get_fraction_numerator(framerate_value); - den = gst_value_get_fraction_denominator(framerate_value); - GST_DEBUG_OBJECT(bcmdec, "framerate = %f rate_num %d rate_den %d", bcmdec->output_params.framerate, num, den); - } else { - GST_DEBUG_OBJECT(bcmdec, "failed to get framerate_value"); - } - - framerate_value = gst_structure_get_value (s1, "pixel-aspect-ratio"); - if (framerate_value) { - num = gst_value_get_fraction_numerator(framerate_value); - den = gst_value_get_fraction_denominator(framerate_value); - GST_DEBUG_OBJECT(bcmdec, "pixel-aspect-ratio_x = %d y %d ", num, den); - } else { - GST_DEBUG_OBJECT(bcmdec, "failed to get par"); - } - - gst_caps_unref(caps); - - return result; -} - -static gboolean bcmdec_process_play(GstBcmDec *bcmdec) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - BC_INPUT_FORMAT bcInputFormat; - - GST_DEBUG_OBJECT(bcmdec, "Starting Process Play"); - - bcInputFormat.OptFlags = 0; // NAREN - FIXME - Should we enable BD mode and max frame rate mode for LINK? - bcInputFormat.FGTEnable = FALSE; - bcInputFormat.MetaDataEnable = FALSE; - bcInputFormat.Progressive = !(bcmdec->interlace); - bcInputFormat.mSubtype= bcmdec->input_format; - - //Use Demux Image Size for VC-1 Simple/Main - if(bcInputFormat.mSubtype == BC_MSUBTYPE_WMV3) - { - //VC-1 Simple/Main - bcInputFormat.width = bcmdec->frame_width; - bcInputFormat.height = bcmdec->frame_height; - } - else - { - bcInputFormat.width = bcmdec->output_params.width; - bcInputFormat.height = bcmdec->output_params.height; - } - - bcInputFormat.startCodeSz = bcmdec->codec_params.nal_size_bytes; - bcInputFormat.pMetaData = bcmdec->codec_params.sps_pps_buf; - bcInputFormat.metaDataSz = bcmdec->codec_params.pps_size; - bcInputFormat.OptFlags = 0x80000000 | vdecFrameRate23_97; - - // ENABLE the Following lines if HW Scaling is desired - bcInputFormat.bEnableScaling = false; -// bcInputFormat.ScalingParams.sWidth = 800; - - sts = decif_setinputformat(&bcmdec->decif, bcInputFormat); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "set input format success"); - } else { - GST_ERROR_OBJECT(bcmdec, "set input format failed"); - bcmdec->streaming = FALSE; - return FALSE; - } - - sts = decif_prepare_play(&bcmdec->decif); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "prepare play success"); - } else { - GST_ERROR_OBJECT(bcmdec, "prepare play failed"); - bcmdec->streaming = FALSE; - return FALSE; - } - - GST_DEBUG_OBJECT(bcmdec, "Setting color space %d", BUF_MODE); - - decif_setcolorspace(&bcmdec->decif, BUF_MODE); - - sts = decif_start_play(&bcmdec->decif); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "start play success"); - bcmdec->streaming = TRUE; - } else { - GST_ERROR_OBJECT(bcmdec, "start play failed"); - bcmdec->streaming = FALSE; - return FALSE; - } - - if (sem_post(&bcmdec->play_event) == -1) - GST_ERROR_OBJECT(bcmdec, "sem_post failed"); - - if (sem_post(&bcmdec->push_start_event) == -1) - GST_ERROR_OBJECT(bcmdec, "push_start post failed"); - - return TRUE; -} - -static GstStateChangeReturn gst_bcmdec_change_state(GstElement *element, GstStateChange transition) -{ - GstStateChangeReturn result = GST_STATE_CHANGE_SUCCESS; - GstBcmDec *bcmdec = GST_BCMDEC(element); - BC_STATUS sts = BC_STS_SUCCESS; - GstClockTime clock_time; - GstClockTime base_clock_time; - int ret = 0; - - switch (transition) { - case GST_STATE_CHANGE_NULL_TO_READY: - GST_DEBUG_OBJECT(bcmdec, "State change from NULL_TO_READY"); - if (bcmdec_mul_inst_cor(bcmdec)) { - sts = decif_open(&bcmdec->decif); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "dev open success"); - parse_init(&bcmdec->parse); - } else { - GST_ERROR_OBJECT(bcmdec, "dev open failed %d",sts); - GST_ERROR_OBJECT(bcmdec, "dev open failed...ret GST_STATE_CHANGE_FAILURE"); - return GST_STATE_CHANGE_FAILURE; - } - } else { - GST_ERROR_OBJECT(bcmdec, "dev open failed...ret GST_STATE_CHANGE_FAILURE"); - return GST_STATE_CHANGE_FAILURE; - } - - break; - - case GST_STATE_CHANGE_READY_TO_PAUSED: - if (!bcmdec_start_recv_thread(bcmdec)) { - GST_ERROR_OBJECT(bcmdec, "GST_STATE_CHANGE_NULL_TO_READY -failed"); - return GST_STATE_CHANGE_FAILURE; - } - if (!bcmdec_start_push_thread(bcmdec)) { - GST_ERROR_OBJECT(bcmdec, "GST_STATE_CHANGE_READY_TO_THREAD -failed"); - return GST_STATE_CHANGE_FAILURE; - } - if (!bcmdec_start_get_rbuf_thread(bcmdec)) { - GST_ERROR_OBJECT(bcmdec, "GST_STATE_CHANGE_THREAD_TO_RBUF -failed"); - return GST_STATE_CHANGE_FAILURE; - } - - bcmdec->play_pending = TRUE; - GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_READY_TO_PAUSED"); - break; - case GST_STATE_CHANGE_PAUSED_TO_PLAYING: - GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_PAUSED_TO_PLAYING"); - bcmdec->gst_clock = gst_element_get_clock(element); - if (bcmdec->gst_clock) { - //printf("clock available %p\n",bcmdec->gst_clock); - base_clock_time = gst_element_get_base_time(element); - //printf("base clock time %lld\n",base_clock_time); - clock_time = gst_clock_get_time(bcmdec->gst_clock); - //printf(" clock time %lld\n",clock_time); - } - break; - - case GST_STATE_CHANGE_PAUSED_TO_READY: - GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_PAUSED_TO_READY"); - bcmdec->streaming = FALSE; - GST_DEBUG_OBJECT(bcmdec, "Flushing\n"); - sts = decif_flush_dec(&bcmdec->decif, 2); - if (sts != BC_STS_SUCCESS) - GST_ERROR_OBJECT(bcmdec, "Dec flush failed %d",sts); - if (!bcmdec->play_pending) { - GST_DEBUG_OBJECT(bcmdec, "Stopping\n"); - sts = decif_stop(&bcmdec->decif); - if (sts == BC_STS_SUCCESS) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "stop play success"); - g_inst_sts->cur_decode = UNKNOWN; - g_inst_sts->rendered_frames = 0; - GST_DEBUG_OBJECT(bcmdec, "cur_dec set to UNKNOWN"); - - } else { - GST_ERROR_OBJECT(bcmdec, "stop play failed %d", sts); - } - } - GST_DEBUG_OBJECT(bcmdec, "Stopping threads\n"); - if (bcmdec->get_rbuf_thread) { - GST_DEBUG_OBJECT(bcmdec, "rbuf stop event"); - if (sem_post(&bcmdec->rbuf_stop_event) == -1) - GST_ERROR_OBJECT(bcmdec, "sem_post failed"); - GST_DEBUG_OBJECT(bcmdec, "waiting for get_rbuf_thread exit"); - ret = pthread_join(bcmdec->get_rbuf_thread, NULL); - GST_DEBUG_OBJECT(bcmdec, "get_rbuf_thread exit - %d errno = %d", ret, errno); - bcmdec->get_rbuf_thread = 0; - } - - if (bcmdec->recv_thread) { - GST_DEBUG_OBJECT(bcmdec, "quit event"); - if (sem_post(&bcmdec->quit_event) == -1) - GST_ERROR_OBJECT(bcmdec, "sem_post failed"); - GST_DEBUG_OBJECT(bcmdec, "waiting for rec_thread exit"); - ret = pthread_join(bcmdec->recv_thread, NULL); - GST_DEBUG_OBJECT(bcmdec, "thread exit - %d errno = %d", ret, errno); - bcmdec->recv_thread = 0; - } - - if (bcmdec->push_thread) { - GST_DEBUG_OBJECT(bcmdec, "waiting for push_thread exit"); - ret = pthread_join(bcmdec->push_thread, NULL); - GST_DEBUG_OBJECT(bcmdec, "push_thread exit - %d errno = %d", ret, errno); - bcmdec->push_thread = 0; - } - - break; - - case GST_STATE_CHANGE_PLAYING_TO_PAUSED: - GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_PLAYING_TO_PAUSED"); - break; - - default: - GST_DEBUG_OBJECT(bcmdec, "default %d", transition); - break; - } - result = GST_ELEMENT_CLASS(parent_class)->change_state(element, transition); - if (result == GST_STATE_CHANGE_FAILURE) { - GST_ERROR_OBJECT(bcmdec, "parent class state change failed"); - return result; - } - - if(transition == GST_STATE_CHANGE_READY_TO_NULL) { - GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_READY_TO_NULL"); - sts = gst_bcmdec_cleanup(bcmdec); - if (sts == BC_STS_SUCCESS) - GST_DEBUG_OBJECT(bcmdec, "dev close success"); - else - GST_ERROR_OBJECT(bcmdec, "dev close failed %d", sts); - } - - return result; -} - - -GstClockTime gst_get_current_timex (void) -{ - GTimeVal tv; - - g_get_current_time(&tv); - return GST_TIMEVAL_TO_TIME(tv); -} - -clock_t bcm_get_tick_count() -{ - tms tm; - return times(&tm); -} - -static gboolean bcmdec_get_buffer(GstBcmDec *bcmdec, GstBuffer **obuf) -{ - GstFlowReturn ret; - GST_DEBUG_OBJECT(bcmdec, "gst_pad_alloc_buffer_and_set_caps "); - - ret = gst_pad_alloc_buffer_and_set_caps(bcmdec->srcpad, - GST_BUFFER_OFFSET_NONE, - bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT, - GST_PAD_CAPS (bcmdec->srcpad), obuf); - if (ret != GST_FLOW_OK) { - GST_ERROR_OBJECT(bcmdec, "gst_pad_alloc_buffer_and_set_caps failed %d ",ret); - return FALSE; - } - - if (((uintptr_t)GST_BUFFER_DATA(*obuf)) % 4) - GST_DEBUG_OBJECT(bcmdec, "buf is not aligned"); - - return TRUE; -} - - -static void bcmdec_init_procout(GstBcmDec *bcmdec,BC_DTS_PROC_OUT* pout, guint8* buf) -{ - // GSTREAMER only supports Interleaved mode for Interlaced content - //if (bcmdec->format_reset) - { - memset(pout,0,sizeof(BC_DTS_PROC_OUT)); - pout->PicInfo.width = bcmdec->output_params.width ; - pout->PicInfo.height = bcmdec->output_params.height; - pout->YbuffSz = bcmdec->output_params.y_size / 4; - pout->UVbuffSz = bcmdec->output_params.uv_size / 4; - - pout->PoutFlags = BC_POUT_FLAGS_SIZE ; -#ifdef YV12__ - pout->PoutFlags |= BC_POUT_FLAGS_YV12; -#endif - if (bcmdec->interlace) - pout->PoutFlags |= BC_POUT_FLAGS_INTERLACED; - - if ((bcmdec->output_params.stride) || (bcmdec->interlace)) { - pout->PoutFlags |= BC_POUT_FLAGS_STRIDE ; - if (bcmdec->interlace) - pout->StrideSz = bcmdec->output_params.width + 2 * bcmdec->output_params.stride; - else - pout->StrideSz = bcmdec->output_params.stride; - } -// bcmdec->format_reset = FALSE; - } - pout->PoutFlags = pout->PoutFlags & 0xff; - pout->Ybuff = (uint8_t*)buf; - - if (pout->UVbuffSz) { - if (bcmdec->interlace) { - pout->UVbuff = buf + bcmdec->output_params.y_size * 2; - if (bcmdec->sec_field) { - pout->Ybuff += bcmdec->output_params.width; - pout->UVbuff += bcmdec->output_params.width / 2; - } - } else { - pout->UVbuff = buf + bcmdec->output_params.y_size; - } - } else { - pout->UVbuff = NULL; - if (bcmdec->interlace) { - if (bcmdec->sec_field) - pout->Ybuff += bcmdec->output_params.width * 2; - } - } - - return; -} - -static void bcmdec_set_framerate(GstBcmDec * bcmdec,guint32 nFrameRate) -{ - gdouble framerate; - -// bcmdec->interlace = FALSE; - framerate = (gdouble)nFrameRate / 1000; - - if((framerate) && (bcmdec->output_params.framerate != framerate)) - { - bcmdec->output_params.framerate = framerate; - bcmdec->frame_time = (GstClockTime)(UNITS / bcmdec->output_params.framerate); - - //if (bcmdec->interlace) - // bcmdec->output_params.framerate /= 2; - - GST_DEBUG_OBJECT(bcmdec, "framerate = %x", framerate); - } -} - -static void bcmdec_set_aspect_ratio(GstBcmDec *bcmdec, BC_PIC_INFO_BLOCK *pic_info) -{ - switch (pic_info->aspect_ratio) { - case vdecAspectRatioSquare: - bcmdec->output_params.aspectratio_x = 1; - bcmdec->output_params.aspectratio_y = 1; - break; - case vdecAspectRatio12_11: - bcmdec->output_params.aspectratio_x = 12; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio10_11: - bcmdec->output_params.aspectratio_x = 10; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio16_11: - bcmdec->output_params.aspectratio_x = 16; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio40_33: - bcmdec->output_params.aspectratio_x = 40; - bcmdec->output_params.aspectratio_y = 33; - break; - case vdecAspectRatio24_11: - bcmdec->output_params.aspectratio_x = 24; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio20_11: - bcmdec->output_params.aspectratio_x = 20; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio32_11: - bcmdec->output_params.aspectratio_x = 32; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio80_33: - bcmdec->output_params.aspectratio_x = 80; - bcmdec->output_params.aspectratio_y = 33; - break; - case vdecAspectRatio18_11: - bcmdec->output_params.aspectratio_x = 18; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio15_11: - bcmdec->output_params.aspectratio_x = 15; - bcmdec->output_params.aspectratio_y = 11; - break; - case vdecAspectRatio64_33: - bcmdec->output_params.aspectratio_x = 64; - bcmdec->output_params.aspectratio_y = 33; - break; - case vdecAspectRatio160_99: - bcmdec->output_params.aspectratio_x = 160; - bcmdec->output_params.aspectratio_y = 99; - break; - case vdecAspectRatio4_3: - bcmdec->output_params.aspectratio_x = 4; - bcmdec->output_params.aspectratio_y = 3; - break; - case vdecAspectRatio16_9: - bcmdec->output_params.aspectratio_x = 16; - bcmdec->output_params.aspectratio_y = 9; - break; - case vdecAspectRatio221_1: - bcmdec->output_params.aspectratio_x = 221; - bcmdec->output_params.aspectratio_y = 1; - break; - case vdecAspectRatioOther: - bcmdec->output_params.aspectratio_x = pic_info->custom_aspect_ratio_width_height & 0x0000ffff; - bcmdec->output_params.aspectratio_y = pic_info->custom_aspect_ratio_width_height >> 16; - break; - case vdecAspectRatioUnknown: - default: - bcmdec->output_params.aspectratio_x = 0; - bcmdec->output_params.aspectratio_y = 0; - break; - } - - // Use Demux Aspect ratio first before falling back to HW ratio - if(bcmdec->input_par_x != 0) { - bcmdec->output_params.aspectratio_x = bcmdec->input_par_x; - bcmdec->output_params.aspectratio_y = bcmdec->input_par_y; - } else if (bcmdec->output_params.aspectratio_x == 0) { - bcmdec->output_params.aspectratio_x = 1; - bcmdec->output_params.aspectratio_y = 1; - } - - GST_DEBUG_OBJECT(bcmdec, "dec_par x = %d", bcmdec->output_params.aspectratio_x); - GST_DEBUG_OBJECT(bcmdec, "dec_par y = %d", bcmdec->output_params.aspectratio_y); -} - -static gboolean bcmdec_format_change(GstBcmDec *bcmdec, BC_PIC_INFO_BLOCK *pic_info) -{ - GST_DEBUG_OBJECT(bcmdec, "Got format Change to %dx%d", pic_info->width, pic_info->height); - gboolean result = FALSE; - - if (pic_info->height == 1088) - pic_info->height = 1080; - - bcmdec->output_params.width = pic_info->width; - bcmdec->output_params.height = pic_info->height; - - bcmdec_set_aspect_ratio(bcmdec,pic_info); - - // Interlaced - if((pic_info->flags & VDEC_FLAG_INTERLACED_SRC) == VDEC_FLAG_INTERLACED_SRC) - bcmdec->interlace = true; - else - bcmdec->interlace = false; - - if( (bcmdec->input_format == BC_MSUBTYPE_AVC1) || (bcmdec->input_format == BC_MSUBTYPE_H264)) { - if (!bcmdec->interlace && - (pic_info->pulldown == vdecFrame_X1) && - (pic_info->flags & VDEC_FLAG_FIELDPAIR) && - (pic_info->flags & VDEC_FLAG_INTERLACED_SRC)) - bcmdec->interlace = true; - } - - result = bcmdec_negotiate_format(bcmdec); - if (!bcmdec->silent) { - if (result) - GST_DEBUG_OBJECT(bcmdec, "negotiate_format success"); - else - GST_ERROR_OBJECT(bcmdec, "negotiate_format failed"); - } - //bcmdec->format_reset = TRUE; - return result; -} - -static int bcmdec_wait_for_event(GstBcmDec *bcmdec) -{ - int ret = 0, i = 0; - sem_t *event_list[] = { &bcmdec->play_event, &bcmdec->quit_event }; - - GST_DEBUG_OBJECT(bcmdec, "Waiting for event\n"); - - while (1) { - for (i = 0; i < 2; i++) { - - ret = sem_trywait(event_list[i]); - if (ret == 0) { - GST_DEBUG_OBJECT(bcmdec, "event wait over in Rx thread ret = %d",i); - return i; - } else if (errno == EINTR) { - break; - } - if (bcmdec->streaming) - break; - } - usleep(10); - } -} - -static void bcmdec_flush_gstbuf_queue(GstBcmDec *bcmdec) -{ - GSTBUF_LIST *gst_queue_element; - int sval; - - do { - gst_queue_element = bcmdec_rem_buf(bcmdec); - if (gst_queue_element) { - if (gst_queue_element->gstbuf) { - gst_buffer_unref (gst_queue_element->gstbuf); - bcmdec_put_que_mem_buf(bcmdec,gst_queue_element); - } - } else { - GST_DEBUG_OBJECT(bcmdec, "no gst_queue_element"); - } - } while (gst_queue_element && gst_queue_element->gstbuf); - - // Re-initialize the buf_event semaphone since we have just flushed the entire queued - sem_destroy(&bcmdec->buf_event); - sem_init(&bcmdec->buf_event, 0, 0); - sem_getvalue(&bcmdec->buf_event, &sval); - GST_DEBUG_OBJECT(bcmdec, "sem value after flush is %d", sval); -} - -static void * bcmdec_process_push(void *ctx) -{ - GstBcmDec *bcmdec = (GstBcmDec *)ctx; - GSTBUF_LIST *gst_queue_element = NULL; - gboolean result = FALSE, done = FALSE; - struct timespec ts; - gint ret; - - ts.tv_sec = time(NULL); - ts.tv_nsec = 30 * 1000000; - - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "process push starting "); - - while (1) { - - if (!bcmdec->recv_thread && !bcmdec->streaming) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "process push exiting.."); - break; - } - - ret = sem_timedwait(&bcmdec->push_start_event, &ts); - if (ret < 0) { - if (errno == ETIMEDOUT) - continue; - else if (errno == EINTR) - break; - } else { - GST_DEBUG_OBJECT(bcmdec, "push_start wait over"); - done = FALSE; - } - - ts.tv_sec = time(NULL) + 1; - ts.tv_nsec = 0; - - while (bcmdec->streaming && !done) { - ret = sem_timedwait(&bcmdec->buf_event, &ts); - if (ret < 0) { - switch (errno) { - case ETIMEDOUT: - if (bcmdec->streaming) { - continue; - } else { - done = TRUE; - GST_DEBUG_OBJECT(bcmdec, "TOB "); - break; - } - case EINTR: - GST_DEBUG_OBJECT(bcmdec, "Sig interrupt "); - done = TRUE; - break; - - default: - GST_ERROR_OBJECT(bcmdec, "sem wait failed %d ", errno); - done = TRUE; - break; - } - } - if (ret == 0) { - GST_DEBUG_OBJECT(bcmdec, "Starting to PUSH "); - gst_queue_element = bcmdec_rem_buf(bcmdec); - if (gst_queue_element) { - if (gst_queue_element->gstbuf) { - GST_DEBUG_OBJECT(bcmdec, "Trying to PUSH "); - result = gst_pad_push(bcmdec->srcpad, gst_queue_element->gstbuf); - if (result != GST_FLOW_OK) { - GST_DEBUG_OBJECT(bcmdec, "exiting, failed to push sts = %d", result); - gst_buffer_unref(gst_queue_element->gstbuf); - done = TRUE; - } else { - GST_DEBUG_OBJECT(bcmdec, "PUSHED, Qcnt:%d, Rcnt:%d", bcmdec->gst_que_cnt, bcmdec->gst_padbuf_que_cnt); - if ((g_inst_sts->rendered_frames++ > THUMBNAIL_FRAMES) && (g_inst_sts->cur_decode != PLAYBACK)) { - g_inst_sts->cur_decode = PLAYBACK; - GST_DEBUG_OBJECT(bcmdec, "cur_dec set to PLAYBACK"); - } - } - } else { - /*exit */ /* NULL value of gstbuf indicates EOS */ - gst_pad_push_event(bcmdec->srcpad, bcmdec->ev_eos); - gst_event_unref(bcmdec->ev_eos); - done = TRUE; - bcmdec->streaming = FALSE; - GST_DEBUG_OBJECT(bcmdec, "eos sent, cnt:%d", bcmdec->gst_que_cnt); - } - bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); - } else - GST_DEBUG_OBJECT(bcmdec, "NO BUFFER FOUND"); - } - if (bcmdec->flushing && bcmdec->push_exit) { - GST_DEBUG_OBJECT(bcmdec, "push -flush exit"); - break; - } - } - if (bcmdec->flushing) { - GST_DEBUG_OBJECT(bcmdec, "flushing gstbuf queue"); - bcmdec_flush_gstbuf_queue(bcmdec); - if (sem_post(&bcmdec->push_stop_event) == -1) - GST_ERROR_OBJECT(bcmdec, "push_stop sem_post failed"); - g_inst_sts->rendered_frames = 0; - } - } - bcmdec_flush_gstbuf_queue(bcmdec); - GST_DEBUG_OBJECT(bcmdec, "process push exiting.. "); - pthread_exit((void*)&result); -} - -static void * bcmdec_process_output(void *ctx) -{ - BC_DTS_PROC_OUT pout; - BC_STATUS sts = BC_STS_SUCCESS; - GstBcmDec *bcmdec = (GstBcmDec *)ctx; - GstBuffer *gstbuf = NULL; - gboolean rx_flush = FALSE, bEOS = FALSE; - const guint first_picture = 3; - guint32 pic_number = 0; - GstClockTime clock_time = 0; - gboolean first_frame_after_seek = FALSE; - GstClockTime cur_stream_time_diff = 0; - int wait_cnt = 0; - guint32 nextPicNumFlags = 0; - - gboolean is_paused = FALSE; - - GSTBUF_LIST *gst_queue_element = NULL; - - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "Rx thread started"); - - while (1) { - if (1 == bcmdec_wait_for_event(bcmdec)) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "quit event set, exit"); - break; - } - - GST_DEBUG_OBJECT(bcmdec, "wait over streaming = %d", bcmdec->streaming); - while (bcmdec->streaming && !bcmdec->last_picture_set) { - GST_DEBUG_OBJECT(bcmdec, "Getting Status\n"); - // NAREN FIXME - This is HARDCODED right now till we get HW PAUSE and RESUME working from the driver - uint32_t rll; - gboolean tmp; - decif_get_drv_status(&(bcmdec->decif), &tmp, &rll, &nextPicNumFlags); - if(rll >= 12 && !is_paused) { - GST_DEBUG_OBJECT(bcmdec, "HW PAUSE with RLL %u", rll); - decif_pause(&(bcmdec->decif), TRUE); - is_paused = TRUE; - } - else if (rll < 12 && is_paused) { - GST_DEBUG_OBJECT(bcmdec, "HW RESUME with RLL %u", rll); - decif_pause(&(bcmdec->decif), false); - is_paused = FALSE; - } - - if(rll == 0) { - usleep(3 * 1000); - continue; - } - - guint8* data_ptr; - if (gstbuf == NULL) { - if (!bcmdec->rbuf_thread_running) { - if (!bcmdec_get_buffer(bcmdec, &gstbuf)) { - usleep(30 * 1000); - continue; - } - GST_DEBUG_OBJECT(bcmdec, "got default buffer, going to proc output"); - } else { - if (gst_queue_element) { - if (gst_queue_element->gstbuf) - gst_buffer_unref(gst_queue_element->gstbuf); - bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); - gst_queue_element = NULL; - } - - gst_queue_element = bcmdec_rem_padbuf(bcmdec); - if (!gst_queue_element) { - GST_DEBUG_OBJECT(bcmdec, "rbuf queue empty"); - usleep(10 * 1000); - continue; - } - - gstbuf = gst_queue_element->gstbuf; - if (!gstbuf) { - bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); - gst_queue_element = NULL; - usleep(10 * 1000); - continue; - } - GST_DEBUG_OBJECT(bcmdec, "got rbuf, going to proc output"); - } - } - else - GST_DEBUG_OBJECT(bcmdec, "re-using rbuf, going to proc output"); - - data_ptr = GST_BUFFER_DATA(gstbuf); - - bcmdec_init_procout(bcmdec, &pout, data_ptr); - rx_flush = TRUE; - pout.PicInfo.picture_number = 0; - // For interlaced content, if I am holding a buffer but the next buffer is not from the same picture - // i.e. the second field, then assume that this is a case of one field per picture and deliver this field - // Don't deliver the one with picture number of 0 - if(bcmdec->sec_field) { - if(((nextPicNumFlags & 0x0FFFFFFF) - first_picture) != pic_number) { - if(pic_number == 0) - gst_buffer_unref(gstbuf); - else if (gst_queue_element) { - GST_BUFFER_FLAG_SET(gstbuf, GST_VIDEO_BUFFER_ONEFIELD); - gst_queue_element->gstbuf = gstbuf; - bcmdec_ins_buf(bcmdec, gst_queue_element); - bcmdec->prev_pic = pic_number; - gst_queue_element = NULL; - } else { - GST_DEBUG_OBJECT(bcmdec, "SOMETHING BAD HAPPENED\n"); - gst_buffer_unref(gstbuf); - } - gstbuf = NULL; - bcmdec->sec_field = FALSE;; - continue; - } - } - sts = DtsProcOutput(bcmdec->decif.hdev, PROC_TIMEOUT, &pout); - GST_DEBUG_OBJECT(bcmdec, "procoutput status %d", sts); - switch (sts) { - case BC_STS_FMT_CHANGE: - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "procout ret FMT"); - if ((pout.PoutFlags & BC_POUT_FLAGS_PIB_VALID) && - (pout.PoutFlags & BC_POUT_FLAGS_FMT_CHANGE)) { - if (bcmdec_format_change(bcmdec, &pout.PicInfo)) { - GST_DEBUG_OBJECT(bcmdec, "format change success"); - //bcmdec->frame_time = (GstClockTime)(UNITS / bcmdec->output_params.framerate); - bcmdec->last_spes_time = 0; - bcmdec->prev_clock_time = 0; - cur_stream_time_diff = 0; - first_frame_after_seek = TRUE; - } else { - GST_DEBUG_OBJECT(bcmdec, "format change failed"); - } - } - gst_buffer_unref(gstbuf); - gstbuf = NULL; - bcmdec->sec_field = FALSE; - - if (sem_post(&bcmdec->rbuf_start_event) == -1) - GST_ERROR_OBJECT(bcmdec, "rbuf sem_post failed"); - - //should modify to wait event - wait_cnt = 0; - while (!bcmdec->rbuf_thread_running && (wait_cnt < 5000)) { - usleep(1000); - wait_cnt++; - } - GST_DEBUG_OBJECT(bcmdec, "format change wait for rbuf thread start wait_cnt:%d", wait_cnt); - - break; - case BC_STS_SUCCESS: - if (!(pout.PoutFlags & BC_POUT_FLAGS_PIB_VALID)) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "procout ret PIB miss %d", pout.PicInfo.picture_number - 3); - continue; - } - - bcmdec_set_framerate(bcmdec, pout.PicInfo.frame_rate); - pic_number = pout.PicInfo.picture_number - first_picture; - - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "pic_number from HW is %u", pout.PicInfo.picture_number); - - if (bcmdec->flushing) { - GST_DEBUG_OBJECT(bcmdec, "flushing discard, pic = %d", pic_number); - continue; - } - - if (bcmdec->prev_pic + 1 < pic_number) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "LOST PICTURE pic_no = %d, prev = %d", pic_number, bcmdec->prev_pic); - } - -/* if ((bcmdec->prev_pic == pic_number) && (bcmdec->ses_nbr == pout.PicInfo.sess_num) && !bcmdec->interlace) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "rp"); - - if (!(pout.PicInfo.flags & VDEC_FLAG_LAST_PICTURE)) - continue; - }*/ - - if (!bcmdec->interlace || bcmdec->sec_field) { - GST_DEBUG_OBJECT(bcmdec, "Progressive or Second Field"); - GST_BUFFER_OFFSET(gstbuf) = 0; - GST_BUFFER_TIMESTAMP(gstbuf) = bcmdec_get_time_stamp(bcmdec, pic_number, pout.PicInfo.timeStamp); - GST_BUFFER_DURATION(gstbuf) = bcmdec->frame_time; - if (bcmdec->gst_clock) { - clock_time = gst_clock_get_time(bcmdec->gst_clock); - if (first_frame_after_seek) { - bcmdec->prev_clock_time = clock_time; - first_frame_after_seek = FALSE; - cur_stream_time_diff = 0; - } - if (bcmdec->prev_clock_time > clock_time) - bcmdec->prev_clock_time = 0; - cur_stream_time_diff += clock_time - bcmdec->prev_clock_time; - bcmdec->cur_stream_time = cur_stream_time_diff + bcmdec->base_clock_time; - bcmdec->prev_clock_time = clock_time; - if ((bcmdec->last_spes_time < bcmdec->cur_stream_time) && - (!bcmdec->catchup_on) && (pout.PicInfo.timeStamp)) { - bcmdec->catchup_on = TRUE; - decif_decode_catchup(&bcmdec->decif, TRUE); - } else if (bcmdec->catchup_on) { - decif_decode_catchup(&bcmdec->decif, FALSE); - bcmdec->catchup_on = FALSE; - } - } - } - - GST_BUFFER_SIZE(gstbuf) = bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT; - - if (!bcmdec->interlace || bcmdec->sec_field) { - if (gst_queue_element) { - // If interlaced, set the GST_VIDEO_BUFFER_TFF flags - if(bcmdec->sec_field) - GST_BUFFER_FLAG_SET(gstbuf, GST_VIDEO_BUFFER_TFF); - gst_queue_element->gstbuf = gstbuf; - bcmdec_ins_buf(bcmdec, gst_queue_element); - bcmdec->prev_pic = pic_number; - } else { - GST_ERROR_OBJECT(bcmdec, "This CANNOT HAPPEN");//pending error recovery - } - gstbuf = NULL; - bcmdec->sec_field = FALSE; - gst_queue_element = NULL; - } else { - GST_DEBUG_OBJECT(bcmdec, "Wait for second field"); - bcmdec->sec_field = TRUE; - } - break; - - case BC_STS_TIMEOUT: - GST_DEBUG_OBJECT(bcmdec, "procout timeout QCnt:%d, RCnt:%d, Paused:%d", - bcmdec->gst_que_cnt, bcmdec->gst_padbuf_que_cnt, bcmdec->paused); - break; - case BC_STS_IO_XFR_ERROR: - GST_DEBUG_OBJECT(bcmdec, "procout xfer error"); - break; - case BC_STS_IO_USER_ABORT: - case BC_STS_IO_ERROR: - bcmdec->streaming = FALSE; - GST_DEBUG_OBJECT(bcmdec, "ABORT sts = %d", sts); - if (gstbuf) { - gst_buffer_unref(gstbuf); - gstbuf = NULL; - } - break; - case BC_STS_NO_DATA: - GST_DEBUG_OBJECT(bcmdec, "procout no data"); - // Check for EOS - decif_get_eos(&bcmdec->decif, &bEOS); - if (bEOS) { - if (gstbuf) { - gst_buffer_unref(gstbuf); - gstbuf = NULL; - } - if (gst_queue_element) { - gst_queue_element->gstbuf = NULL; - bcmdec_ins_buf(bcmdec, gst_queue_element); - gst_queue_element = NULL; - } else { - GST_DEBUG_OBJECT(bcmdec, "queue element failed"); - } - GST_DEBUG_OBJECT(bcmdec, "last picture set "); - bcmdec->last_picture_set = TRUE; - } - break; - default: - GST_DEBUG_OBJECT(bcmdec, "unhandled status from Procout sts %d",sts); - if (gstbuf) { - gst_buffer_unref(gstbuf); - gstbuf = NULL; - } - break; - } - } - if (gstbuf) { - gst_buffer_unref(gstbuf); - gstbuf = NULL; - } - if (gst_queue_element) { - bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); - gst_queue_element = NULL; - } - if (rx_flush) { - if (!bcmdec->flushing) { -// GST_DEBUG_OBJECT(bcmdec, "DtsFlushRxCapture called"); -// sts = decif_flush_rxbuf(&bcmdec->decif, FALSE); -// if (sts != BC_STS_SUCCESS) -// GST_DEBUG_OBJECT(bcmdec, "DtsFlushRxCapture failed"); - } - rx_flush = FALSE; - if (bcmdec->flushing) { - if (sem_post(&bcmdec->recv_stop_event) == -1) - GST_ERROR_OBJECT(bcmdec, "recv_stop sem_post failed"); - } - GST_DEBUG_OBJECT(bcmdec, "DtsFlushRxCapture Done"); - } - } - GST_DEBUG_OBJECT(bcmdec, "Rx thread exiting .."); - pthread_exit((void*)&sts); -} - -static gboolean bcmdec_start_push_thread(GstBcmDec *bcmdec) -{ - gboolean result = TRUE; - pthread_attr_t thread_attr; - gint ret = 0; - - pthread_attr_init(&thread_attr); - pthread_attr_setdetachstate(&thread_attr, PTHREAD_CREATE_JOINABLE); - pthread_create(&bcmdec->push_thread, &thread_attr, bcmdec_process_push, bcmdec); - pthread_attr_destroy(&thread_attr); - - if (!bcmdec->push_thread) { - GST_ERROR_OBJECT(bcmdec, "Failed to create PushThread"); - result = FALSE; - } else { - GST_DEBUG_OBJECT(bcmdec, "Success to create PushThread"); - } - - ret = sem_init(&bcmdec->buf_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "play event init failed"); - result = FALSE; - } - - ret = sem_init(&bcmdec->push_start_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "play event init failed"); - result = FALSE; - } - - ret = sem_init(&bcmdec->push_stop_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "push_stop event init failed"); - result = FALSE; - } - - return result; -} - -static gboolean bcmdec_start_recv_thread(GstBcmDec *bcmdec) -{ - gboolean result = TRUE; - gint ret = 0; - pthread_attr_t thread_attr; - - if (!bcmdec_alloc_mem_buf_que_pool(bcmdec)) - GST_ERROR_OBJECT(bcmdec, "pool alloc failed/n"); - - ret = sem_init(&bcmdec->play_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "play event init failed"); - result = FALSE; - } - - ret = sem_init(&bcmdec->quit_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "play event init failed"); - result = FALSE; - } - - ret = sem_init(&bcmdec->recv_stop_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "recv_stop event init failed"); - result = FALSE; - } - - pthread_attr_init(&thread_attr); - pthread_attr_setdetachstate(&thread_attr, PTHREAD_CREATE_JOINABLE); - pthread_create(&bcmdec->recv_thread, &thread_attr, bcmdec_process_output, bcmdec); - pthread_attr_destroy(&thread_attr); - - if (!bcmdec->recv_thread) { - GST_ERROR_OBJECT(bcmdec, "Failed to create RxThread"); - result = FALSE; - } else { - GST_DEBUG_OBJECT(bcmdec, "Success to create RxThread"); - } - - return result; -} - -static GstClockTime bcmdec_get_time_stamp(GstBcmDec *bcmdec, guint32 pic_no, GstClockTime spes_time) -{ - GstClockTime time_stamp = 0; - GstClockTime frame_time = (GstClockTime)(UNITS / bcmdec->output_params.framerate); - - if (bcmdec->enable_spes) { - if (spes_time) { - time_stamp = spes_time ; - if (bcmdec->spes_frame_cnt && bcmdec->last_output_spes_time) { - bcmdec->frame_time = (time_stamp - bcmdec->last_output_spes_time) / bcmdec->spes_frame_cnt; - bcmdec->spes_frame_cnt = 0; - } - if (bcmdec->frame_time > 0) - frame_time = bcmdec->frame_time; - bcmdec->spes_frame_cnt++; - bcmdec->last_output_spes_time = bcmdec->last_spes_time = time_stamp; - } else { - if (bcmdec->frame_time > 0) - frame_time = bcmdec->frame_time; - bcmdec->last_spes_time += frame_time; - time_stamp = bcmdec->last_spes_time; - bcmdec->spes_frame_cnt++; - } - } else { - time_stamp = (GstClockTime)(bcmdec->base_time + frame_time * pic_no); - } - - if (!bcmdec->enable_spes) { - if (bcmdec->interlace) { - if (bcmdec->prev_pic == pic_no) - bcmdec->rpt_pic_cnt++; - time_stamp += bcmdec->rpt_pic_cnt * frame_time; - } - } - - return time_stamp; -} - -static void bcmdec_process_flush_stop(GstBcmDec *bcmdec) -{ - bcmdec->ses_change = TRUE; - bcmdec->base_time = 0; - bcmdec->flushing = FALSE; - bcmdec->streaming = TRUE; - bcmdec->rpt_pic_cnt = 0; - - GST_DEBUG_OBJECT(bcmdec, "flush stop started"); - - if (sem_post(&bcmdec->play_event) == -1) - GST_ERROR_OBJECT(bcmdec, "sem_post failed"); - - bcmdec->push_exit = FALSE; - - if (sem_post(&bcmdec->push_start_event) == -1) - GST_ERROR_OBJECT(bcmdec, "push_start post failed"); - - GST_DEBUG_OBJECT(bcmdec, "flush stop complete"); - -} - -static void bcmdec_process_flush_start(GstBcmDec *bcmdec) -{ - gint ret = 1; - BC_STATUS sts = BC_STS_SUCCESS; - struct timespec ts; - - ts.tv_sec=time(NULL) + 5; - ts.tv_nsec = 0; - - bcmdec->flushing = TRUE; - bcmdec->streaming = FALSE; - - ret = sem_timedwait(&bcmdec->recv_stop_event, &ts); - if (ret < 0) { - switch (errno) { - case ETIMEDOUT: - GST_DEBUG_OBJECT(bcmdec, "recv_stop_event sig timed out "); - break; - case EINTR: - GST_DEBUG_OBJECT(bcmdec, "Sig interrupt "); - break; - default: - GST_ERROR_OBJECT(bcmdec, "sem wait failed %d ",errno); - break; - } - } - - bcmdec->push_exit = TRUE; - - ret = sem_timedwait(&bcmdec->push_stop_event, &ts); - if (ret < 0) { - switch (errno) { - case ETIMEDOUT: - GST_DEBUG_OBJECT(bcmdec, "push_stop_event sig timed out "); - break; - case EINTR: - GST_DEBUG_OBJECT(bcmdec, "Sig interrupt "); - break; - default: - GST_ERROR_OBJECT(bcmdec, "sem wait failed %d ",errno); - break; - } - } - sts = decif_flush_dec(&bcmdec->decif, 2); - if (sts != BC_STS_SUCCESS) - GST_ERROR_OBJECT(bcmdec, "flush_dec failed sts %d", sts); -} - -static BC_STATUS gst_bcmdec_cleanup(GstBcmDec *bcmdec) -{ - BC_STATUS sts = BC_STS_SUCCESS; - - GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_cleanup - enter"); - bcmdec->streaming = FALSE; - - bcmdec_release_mem_buf_que_pool(bcmdec); -// bcmdec_release_mem_rbuf_que_pool(bcmdec); - - if (bcmdec->decif.hdev) - sts = decif_close(&bcmdec->decif); - - sem_destroy(&bcmdec->quit_event); - sem_destroy(&bcmdec->play_event); - sem_destroy(&bcmdec->push_start_event); - sem_destroy(&bcmdec->buf_event); - sem_destroy(&bcmdec->rbuf_start_event); - sem_destroy(&bcmdec->rbuf_stop_event); - sem_destroy(&bcmdec->rbuf_ins_event); - sem_destroy(&bcmdec->push_stop_event); - sem_destroy(&bcmdec->recv_stop_event); - - pthread_mutex_destroy(&bcmdec->gst_buf_que_lock); - pthread_mutex_destroy(&bcmdec->gst_padbuf_que_lock); - //pthread_mutex_destroy(&bcmdec->fn_lock); - if (bcmdec->codec_params.sps_pps_buf) { - free(bcmdec->codec_params.sps_pps_buf); - bcmdec->codec_params.sps_pps_buf = NULL; - } - - if (bcmdec->dest_buf) { - free(bcmdec->dest_buf); - bcmdec->dest_buf = NULL; - } - -// if (bcmdec->vc1_dest_buffer) { -// free(bcmdec->vc1_dest_buffer); -// bcmdec->vc1_dest_buffer = NULL; -// } - - if (bcmdec->gst_clock) { - gst_object_unref(bcmdec->gst_clock); - bcmdec->gst_clock = NULL; - } - - if (sem_post(&g_inst_sts->inst_ctrl_event) == -1) - GST_ERROR_OBJECT(bcmdec, "inst_ctrl_event post failed"); - else - GST_DEBUG_OBJECT(bcmdec, "inst_ctrl_event posted"); - - return sts; -} - -static void bcmdec_reset(GstBcmDec * bcmdec) -{ - bcmdec->dec_ready = FALSE; - bcmdec->streaming = FALSE; - bcmdec->format_reset = TRUE; - bcmdec->interlace = FALSE; - - bcmdec->output_params.width = 720; - bcmdec->output_params.height = 480; - bcmdec->output_params.framerate = 29; - bcmdec->output_params.aspectratio_x = 16; - bcmdec->output_params.aspectratio_y = 9; - bcmdec->output_params.clr_space = BUF_MODE; - if (bcmdec->output_params.clr_space == MODE420) { /* MODE420 */ - bcmdec->output_params.y_size = 720 * 480; - bcmdec->output_params.uv_size = 720 * 480 / 2; - } else { /* MODE422_YUV */ - bcmdec->output_params.y_size = 720 * 480 * 2; - bcmdec->output_params.uv_size = 0; - } - - bcmdec->output_params.stride = 0; - - bcmdec->base_time = 0; - bcmdec->fhnd = NULL; - - bcmdec->play_pending = FALSE; - - bcmdec->gst_buf_que_hd = NULL; - bcmdec->gst_buf_que_tl = NULL; - bcmdec->gst_que_cnt = 0; - bcmdec->last_picture_set = FALSE; - bcmdec->gst_buf_que_sz = GST_BUF_LIST_POOL_SZ; - bcmdec->gst_padbuf_que_sz = GST_RENDERER_BUF_POOL_SZ; - bcmdec->rbuf_thread_running = FALSE; - - bcmdec->insert_start_code = FALSE; - bcmdec->codec_params.sps_pps_buf = NULL; - - bcmdec->input_framerate = 0; - bcmdec->input_par_x = 0; - bcmdec->input_par_y = 0; - bcmdec->prev_pic = -1; - - bcmdec->codec_params.inside_buffer = TRUE; - bcmdec->codec_params.consumed_offset = 0; - bcmdec->codec_params.strtcode_offset = 0; - bcmdec->codec_params.nal_sz = 0; - bcmdec->codec_params.pps_size = 0; - bcmdec->codec_params.nal_size_bytes = 4; - - bcmdec->paused = FALSE; - - bcmdec->flushing = FALSE; - bcmdec->ses_nbr = 0; - bcmdec->insert_pps = TRUE; - bcmdec->ses_change = FALSE; - - bcmdec->push_exit = FALSE; - - bcmdec->suspend_mode = FALSE; - bcmdec->gst_clock = NULL; - bcmdec->rpt_pic_cnt = 0; - - //bcmdec->enable_spes = FALSE; - bcmdec->enable_spes = TRUE; - bcmdec->dest_buf = NULL; - bcmdec->catchup_on = FALSE; - bcmdec->last_output_spes_time = 0; - - pthread_mutex_init(&bcmdec->gst_buf_que_lock, NULL); - pthread_mutex_init(&bcmdec->gst_padbuf_que_lock, NULL); - //pthread_mutex_init(&bcmdec->fn_lock,NULL); -} - -static void bcmdec_put_que_mem_buf(GstBcmDec *bcmdec, GSTBUF_LIST *gst_queue_element) -{ - pthread_mutex_lock(&bcmdec->gst_buf_que_lock); - - gst_queue_element->next = bcmdec->gst_mem_buf_que_hd; - bcmdec->gst_mem_buf_que_hd = gst_queue_element; - - bcmdec->gst_que_cnt++; - GST_DEBUG_OBJECT(bcmdec, "mem pool inc is %u", bcmdec->gst_que_cnt); - - pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); -} - -static GSTBUF_LIST * bcmdec_get_que_mem_buf(GstBcmDec *bcmdec) -{ - GSTBUF_LIST *gst_queue_element = NULL; - - pthread_mutex_lock(&bcmdec->gst_buf_que_lock); - - gst_queue_element = bcmdec->gst_mem_buf_que_hd; - if (gst_queue_element) { - bcmdec->gst_mem_buf_que_hd = bcmdec->gst_mem_buf_que_hd->next; - bcmdec->gst_que_cnt--; - - GST_DEBUG_OBJECT(bcmdec, "mem pool dec is %u", bcmdec->gst_que_cnt); - } - - pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); - - return gst_queue_element; -} - -static gboolean bcmdec_alloc_mem_buf_que_pool(GstBcmDec *bcmdec) -{ - GSTBUF_LIST *gst_queue_element = NULL; - guint i = 0; - - bcmdec->gst_mem_buf_que_hd = NULL; - while (i++gst_buf_que_sz) { - if (!(gst_queue_element = (GSTBUF_LIST *)malloc(sizeof(GSTBUF_LIST)))) { - GST_ERROR_OBJECT(bcmdec, "mempool malloc failed "); - return FALSE; - } - memset(gst_queue_element, 0, sizeof(GSTBUF_LIST)); - bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); - } - return TRUE; -} - -static gboolean bcmdec_release_mem_buf_que_pool(GstBcmDec *bcmdec) -{ - GSTBUF_LIST *gst_queue_element; - guint i = 0; - - do { - gst_queue_element = bcmdec_get_que_mem_buf(bcmdec); - if (gst_queue_element) { - free(gst_queue_element); - i++; - } - } while (gst_queue_element); - - bcmdec->gst_mem_buf_que_hd = NULL; - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "mem_buf_que_pool released... %d", i); - - return TRUE; -} - -static void bcmdec_ins_buf(GstBcmDec *bcmdec,GSTBUF_LIST *gst_queue_element) -{ - pthread_mutex_lock(&bcmdec->gst_buf_que_lock); - - if (!bcmdec->gst_buf_que_hd) { - bcmdec->gst_buf_que_hd = bcmdec->gst_buf_que_tl = gst_queue_element; - } else { - bcmdec->gst_buf_que_tl->next = gst_queue_element; - bcmdec->gst_buf_que_tl = gst_queue_element; - gst_queue_element->next = NULL; - } - - if (sem_post(&bcmdec->buf_event) == -1) - GST_ERROR_OBJECT(bcmdec, "buf sem_post failed"); - else - GST_DEBUG_OBJECT(bcmdec, "buffer inserted and buf_event signalled"); - - pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); -} - -static GSTBUF_LIST * bcmdec_rem_buf(GstBcmDec *bcmdec) -{ - GSTBUF_LIST *temp; - - pthread_mutex_lock(&bcmdec->gst_buf_que_lock); - - if (bcmdec->gst_buf_que_hd == bcmdec->gst_buf_que_tl) { - temp = bcmdec->gst_buf_que_hd; - bcmdec->gst_buf_que_hd = bcmdec->gst_buf_que_tl = NULL; - } else { - temp = bcmdec->gst_buf_que_hd; - bcmdec->gst_buf_que_hd = temp->next; - } - - pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); - - return temp; -} - -static BC_STATUS bcmdec_insert_sps_pps(GstBcmDec *bcmdec, GstBuffer* gstbuf) -{ - BC_STATUS sts = BC_STS_SUCCESS; - guint8 *data = GST_BUFFER_DATA(gstbuf); - guint32 data_size = GST_BUFFER_SIZE(gstbuf); - gint profile; - guint nal_size; - guint num_sps, num_pps, i; - - bcmdec->codec_params.pps_size = 0; - - profile = (data[1] << 16) | (data[2] << 8) | data[3]; - GST_DEBUG_OBJECT(bcmdec, "profile %06x",profile); - - bcmdec->codec_params.nal_size_bytes = (data[4] & 0x03) + 1; - - GST_DEBUG_OBJECT(bcmdec, "nal size %d",bcmdec->codec_params.nal_size_bytes); - - num_sps = data[5] & 0x1f; - GST_DEBUG_OBJECT(bcmdec, "num sps %d",num_sps); - - data += 6; - data_size -= 6; - - for (i = 0; i < num_sps; i++) { - - if (data_size < 2) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "too small 2"); - return BC_STS_ERROR; - } - - nal_size = (data[0] << 8) | data[1]; - data += 2; - data_size -= 2; - - if (data_size < nal_size) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "too small 3"); - return BC_STS_ERROR; - } - - bcmdec->codec_params.sps_pps_buf[0] = 0; - bcmdec->codec_params.sps_pps_buf[1] = 0; - bcmdec->codec_params.sps_pps_buf[2] = 0; - bcmdec->codec_params.sps_pps_buf[3] = 1; - - bcmdec->codec_params.pps_size += 4; - - memcpy(bcmdec->codec_params.sps_pps_buf + bcmdec->codec_params.pps_size, data, nal_size); - bcmdec->codec_params.pps_size += nal_size; - - data += nal_size; - data_size -= nal_size; - } - - if (data_size < 1) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "too small 4"); - return BC_STS_ERROR; - } - - num_pps = data[0]; - data += 1; - data_size -= 1; - - for (i = 0; i < num_pps; i++) { - - if (data_size < 2) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "too small 5"); - return BC_STS_ERROR; - } - - nal_size = (data[0] << 8) | data[1]; - data += 2; - data_size -= 2; - - if (data_size < nal_size) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "too small 6"); - return BC_STS_ERROR; - } - - bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+0] = 0; - bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+1] = 0; - bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+2] = 0; - bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+3] = 1; - - bcmdec->codec_params.pps_size += 4; - - memcpy(bcmdec->codec_params.sps_pps_buf + bcmdec->codec_params.pps_size, data, nal_size); - bcmdec->codec_params.pps_size += nal_size; - - data += nal_size; - data_size -= nal_size; - } - - GST_DEBUG_OBJECT(bcmdec, "data size at end = %d ",data_size); - - return sts; -} - -static BC_STATUS bcmdec_suspend_callback(GstBcmDec *bcmdec) -{ - BC_STATUS sts = BC_STS_SUCCESS; - bcmdec_flush_gstbuf_queue(bcmdec); - - bcmdec->base_time = 0; - if (bcmdec->decif.hdev) - sts = decif_close(&bcmdec->decif); - bcmdec->codec_params.inside_buffer = TRUE; - bcmdec->codec_params.consumed_offset = 0; - bcmdec->codec_params.strtcode_offset = 0; - bcmdec->codec_params.nal_sz = 0; - bcmdec->insert_pps = TRUE; - - return sts; -} - -static BC_STATUS bcmdec_resume_callback(GstBcmDec *bcmdec) -{ - BC_STATUS sts = BC_STS_SUCCESS; - BC_INPUT_FORMAT bcInputFormat; - - sts = decif_open(&bcmdec->decif); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "dev open success"); - } else { - GST_ERROR_OBJECT(bcmdec, "dev open failed %d", sts); - return sts; - } - - bcInputFormat.OptFlags = 0; // NAREN - FIXME - Should we enable BD mode and max frame rate mode for LINK? - bcInputFormat.FGTEnable = FALSE; - bcInputFormat.MetaDataEnable = FALSE; - bcInputFormat.Progressive = !(bcmdec->interlace); - bcInputFormat.mSubtype= bcmdec->input_format; - - //Use Demux Image Size for VC-1 Simple/Main - if(bcInputFormat.mSubtype == BC_MSUBTYPE_WMV3) - { - //VC-1 Simple/Main - bcInputFormat.width = bcmdec->frame_width; - bcInputFormat.height = bcmdec->frame_height; - } - else - { - bcInputFormat.width = bcmdec->output_params.width; - bcInputFormat.height = bcmdec->output_params.height; - } - - bcInputFormat.startCodeSz = bcmdec->codec_params.nal_size_bytes; - bcInputFormat.pMetaData = bcmdec->codec_params.sps_pps_buf; - bcInputFormat.metaDataSz = bcmdec->codec_params.pps_size; - bcInputFormat.OptFlags = 0x80000000 | vdecFrameRate23_97; - - sts = decif_setinputformat(&bcmdec->decif, bcInputFormat); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "set input format success"); - } else { - GST_ERROR_OBJECT(bcmdec, "set input format failed"); - bcmdec->streaming = FALSE; - return sts; - } - - sts = decif_prepare_play(&bcmdec->decif); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "prepare play success"); - } else { - GST_ERROR_OBJECT(bcmdec, "prepare play failed %d", sts); - bcmdec->streaming = FALSE; - return sts; - } - - decif_setcolorspace(&bcmdec->decif, BUF_MODE); - - sts = decif_start_play(&bcmdec->decif); - if (sts == BC_STS_SUCCESS) { - GST_DEBUG_OBJECT(bcmdec, "start play success"); - bcmdec->streaming = TRUE; - } else { - GST_ERROR_OBJECT(bcmdec, "start play failed %d", sts); - bcmdec->streaming = FALSE; - return sts; - } - - if (sem_post(&bcmdec->play_event) == -1) - GST_ERROR_OBJECT(bcmdec, "sem_post failed"); - - if (sem_post(&bcmdec->push_start_event) == -1) - GST_ERROR_OBJECT(bcmdec, "push_start post failed"); - - return sts; -} - -static gboolean bcmdec_mul_inst_cor(GstBcmDec *bcmdec) -{ - struct timespec ts; - gint ret = 0; - int i = 0; - - if ((intptr_t)g_inst_sts == -1) { - GST_ERROR_OBJECT(bcmdec, "mul_inst_cor :shmem ptr invalid"); - return FALSE; - } - - if (g_inst_sts->cur_decode == PLAYBACK) { - GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor : ret false %d", g_inst_sts->cur_decode); - return FALSE; - } - - for (i = 0; i < 15; i++) { - ts.tv_sec = time(NULL) + 3; - ts.tv_nsec = 0; - ret = sem_timedwait(&g_inst_sts->inst_ctrl_event, &ts); - if (ret < 0) { - if (errno == ETIMEDOUT) { - if (g_inst_sts->cur_decode == PLAYBACK) { - GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor :playback is set , exit"); - return FALSE; - } else { - GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor :wait for thumb nail decode finish"); - continue; - } - } else if (errno == EINTR) { - return FALSE; - } - } else { - GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor :ctrl_event is given"); - return TRUE; - } - } - GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor : ret false cur_dec = %d wait = %d", g_inst_sts->cur_decode, g_inst_sts->waiting); - - return FALSE; -} - -static BC_STATUS bcmdec_create_shmem(GstBcmDec *bcmdec, int *shmem_id) -{ - int shmid = -1; - key_t shmkey = BCM_GST_SHMEM_KEY; - shmid_ds buf; - - if (shmem_id == NULL) { - GST_ERROR_OBJECT(bcmdec, "Invalid argument ..."); - return BC_STS_INSUFF_RES; - } - - *shmem_id = shmid; - - //First Try to create it. - shmid = shmget(shmkey, 1024, 0644 | IPC_CREAT | IPC_EXCL); - if (shmid == -1) { - if (errno == EEXIST) { - GST_DEBUG_OBJECT(bcmdec, "bcmdec_create_shmem:shmem already exists :%d", errno); - shmid = shmget(shmkey, 1024, 0644); - if (shmid == -1) { - GST_ERROR_OBJECT(bcmdec, "bcmdec_create_shmem:unable to get shmid :%d", errno); - return BC_STS_INSUFF_RES; - } - - //we got the shmid, see if any process is alreday attached to it - if (shmctl(shmid,IPC_STAT,&buf) == -1) { - GST_ERROR_OBJECT(bcmdec, "bcmdec_create_shmem:shmctl failed ..."); - return BC_STS_ERROR; - } - - if (buf.shm_nattch == 0) { - sem_destroy(&g_inst_sts->inst_ctrl_event); - //No process is currently attached to the shmem seg. go ahead and delete it as its contents are stale. - if (shmctl(shmid, IPC_RMID, NULL) != -1) - GST_DEBUG_OBJECT(bcmdec, "bcmdec_create_shmem:deleted shmem segment and creating a new one ..."); - //create a new shmem - shmid = shmget(shmkey, 1024, 0644 | IPC_CREAT | IPC_EXCL); - if (shmid == -1) { - GST_ERROR_OBJECT(bcmdec, "bcmdec_create_shmem:unable to get shmid :%d", errno); - return BC_STS_INSUFF_RES; - } - //attach to it - bcmdec_get_shmem(bcmdec, shmid, TRUE); - - } else { - //attach to it - bcmdec_get_shmem(bcmdec, shmid, FALSE); - } - - } else { - GST_ERROR_OBJECT(bcmdec, "shmcreate failed with err %d",errno); - return BC_STS_ERROR; - } - } else { - //we created just attach to it - bcmdec_get_shmem(bcmdec, shmid, TRUE); - } - - *shmem_id = shmid; - - return BC_STS_SUCCESS; -} - -static BC_STATUS bcmdec_get_shmem(GstBcmDec *bcmdec, int shmid, gboolean newmem) -{ - gint ret = 0; - g_inst_sts = (GLB_INST_STS *)shmat(shmid, (void *)0, 0); - if ((intptr_t)g_inst_sts == -1) { - GST_ERROR_OBJECT(bcmdec, "Unable to open shared memory ...errno = %d", errno); - return BC_STS_ERROR; - } - - if (newmem) { - ret = sem_init(&g_inst_sts->inst_ctrl_event, 5, 1); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "inst_ctrl_event failed"); - return BC_STS_ERROR; - } - } - - return BC_STS_SUCCESS; -} - -static BC_STATUS bcmdec_del_shmem(GstBcmDec *bcmdec) -{ - int shmid = 0; - shmid_ds buf; - - //First dettach the shared mem segment - if (shmdt(g_inst_sts) == -1) - GST_ERROR_OBJECT(bcmdec, "Unable to detach shared memory ..."); - - //delete the shared mem segment if there are no other attachments - shmid = shmget((key_t)BCM_GST_SHMEM_KEY, 0, 0); - if (shmid == -1) { - GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:Unable get shmid ..."); - return BC_STS_ERROR; - } - - if (shmctl(shmid, IPC_STAT, &buf) == -1) { - GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:shmctl failed ..."); - return BC_STS_ERROR; - } - - if (buf.shm_nattch == 0) { - sem_destroy(&g_inst_sts->inst_ctrl_event); - //No process is currently attached to the shmem seg. go ahead and delete it - if (shmctl(shmid, IPC_RMID, NULL) != -1) { - GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:deleted shmem segment ..."); - return BC_STS_ERROR; - } else { - GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:unable to delete shmem segment ..."); - } - } - - return BC_STS_SUCCESS; -} - -// For renderer buffer -static void bcmdec_flush_gstrbuf_queue(GstBcmDec *bcmdec) -{ - GSTBUF_LIST *gst_queue_element = NULL; - - while (1) { - gst_queue_element = bcmdec_rem_padbuf(bcmdec); - if (gst_queue_element) { - if (gst_queue_element->gstbuf) { - gst_buffer_unref (gst_queue_element->gstbuf); - bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); - } else { - break; - } - } - else { - GST_DEBUG_OBJECT(bcmdec, "no gst_queue_element"); - break; - } - } -} - -static void * bcmdec_process_get_rbuf(void *ctx) -{ - GstBcmDec *bcmdec = (GstBcmDec *)ctx; - GstFlowReturn ret = GST_FLOW_ERROR; - GSTBUF_LIST *gst_queue_element = NULL; - gboolean result = FALSE, done = FALSE; - GstBuffer *gstbuf = NULL; - guint bufSz = 0; - gboolean get_buf_start = FALSE; - int revent = -1; - - while (1) { - revent = sem_trywait(&bcmdec->rbuf_start_event); - if (revent == 0) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "got start get buf event "); - get_buf_start = TRUE; - bcmdec->rbuf_thread_running = TRUE; - } - - revent = sem_trywait(&bcmdec->rbuf_stop_event); - if (revent == 0) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "quit event set, exit"); - break; - } - - if (!bcmdec->streaming || !get_buf_start) { - GST_DEBUG_OBJECT(bcmdec, "SLEEPING in get bufs"); - usleep(100 * 1000); - } - - while (bcmdec->streaming && get_buf_start) - { - //GST_DEBUG_OBJECT(bcmdec, "process get rbuf start...."); - gstbuf = NULL; - - if (!bcmdec->recv_thread && !bcmdec->streaming) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "process get rbuf prepare exiting.."); - done = TRUE; - break; - } - - // If we have enough buffers from the renderer then don't get any more - if(bcmdec->gst_padbuf_que_cnt >= GST_RENDERER_BUF_POOL_SZ) { - usleep(100 * 1000); - GST_DEBUG_OBJECT(bcmdec, "SLEEPING because we have enough buffers"); - continue; - } - - if (gst_queue_element == NULL) - gst_queue_element = bcmdec_get_que_mem_buf(bcmdec); - - if (!gst_queue_element) { - if (!bcmdec->silent) - GST_DEBUG_OBJECT(bcmdec, "mbuf full == TRUE %u", bcmdec->gst_buf_que_sz); - - usleep(1000 * 1000); // Sleep for a second since we have 350 buffers queued up - continue; - } - - bufSz = bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT; - - //GST_DEBUG_OBJECT(bcmdec, "process get rbuf gst_pad_alloc_buffer_and_set_caps ...."); - ret = gst_pad_alloc_buffer_and_set_caps(bcmdec->srcpad, GST_BUFFER_OFFSET_NONE, - bufSz, GST_PAD_CAPS(bcmdec->srcpad), &gstbuf); - if (ret != GST_FLOW_OK) { - if (!bcmdec->silent) - GST_ERROR_OBJECT(bcmdec, "gst_pad_alloc_buffer_and_set_caps failed %d ",ret); - usleep(30 * 1000); - continue; - } - - GST_DEBUG_OBJECT(bcmdec, "Got GST Buf RCnt:%d", bcmdec->gst_padbuf_que_cnt); - - gst_queue_element->gstbuf = gstbuf; - bcmdec_ins_padbuf(bcmdec, gst_queue_element); - gst_queue_element = NULL; - - usleep(5 * 1000); - } - - if (done) { - GST_DEBUG_OBJECT(bcmdec, "process get rbuf done "); - break; - } - } - bcmdec_flush_gstrbuf_queue(bcmdec); - GST_DEBUG_OBJECT(bcmdec, "process get rbuf exiting.. "); - pthread_exit((void *)&result); -} - -static gboolean bcmdec_start_get_rbuf_thread(GstBcmDec *bcmdec) -{ - gboolean result = TRUE; - gint ret = 0; - pthread_attr_t thread_attr; - -// if (!bcmdec_alloc_mem_rbuf_que_pool(bcmdec)) -// GST_ERROR_OBJECT(bcmdec, "rend pool alloc failed/n"); - - bcmdec->gst_padbuf_que_hd = bcmdec->gst_padbuf_que_tl = NULL; - - ret = sem_init(&bcmdec->rbuf_ins_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "get rbuf ins event init failed"); - result = FALSE; - } - - ret = sem_init(&bcmdec->rbuf_start_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "get rbuf start event init failed"); - result = FALSE; - } - - ret = sem_init(&bcmdec->rbuf_stop_event, 0, 0); - if (ret != 0) { - GST_ERROR_OBJECT(bcmdec, "get rbuf stop event init failed"); - result = FALSE; - } - - pthread_attr_init(&thread_attr); - pthread_attr_setdetachstate(&thread_attr, PTHREAD_CREATE_JOINABLE); - pthread_create(&bcmdec->get_rbuf_thread, &thread_attr, - bcmdec_process_get_rbuf, bcmdec); - pthread_attr_destroy(&thread_attr); - - if (!bcmdec->get_rbuf_thread) { - GST_ERROR_OBJECT(bcmdec, "Failed to create Renderer buffer Thread"); - result = FALSE; - } else { - GST_DEBUG_OBJECT(bcmdec, "Success to create Renderer buffer Thread"); - } - - return result; -} - -// static void bcmdec_put_que_mem_padbuf(GstBcmDec *bcmdec, GSTBUF_LIST *gst_queue_element) -// { -// pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); -// -// gst_queue_element->next = bcmdec->gst_mem_padbuf_que_hd; -// bcmdec->gst_mem_padbuf_que_hd = gst_queue_element; -// -// pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); -// } -// -// static GSTBUF_LIST * bcmdec_get_que_mem_padbuf(GstBcmDec *bcmdec) -// { -// GSTBUF_LIST *gst_queue_element; -// -// pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); -// -// gst_queue_element = bcmdec->gst_mem_padbuf_que_hd; -// if (gst_queue_element !=NULL) -// bcmdec->gst_mem_padbuf_que_hd = bcmdec->gst_mem_padbuf_que_hd->next; -// -// pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); -// -// return gst_queue_element; -// } -// -// static gboolean bcmdec_alloc_mem_rbuf_que_pool(GstBcmDec *bcmdec) -// { -// GSTBUF_LIST *gst_queue_element; -// guint i; -// -// bcmdec->gst_mem_padbuf_que_hd = NULL; -// for (i = 1; i < bcmdec->gst_padbuf_que_sz; i++) { -// gst_queue_element = (GSTBUF_LIST *)malloc(sizeof(GSTBUF_LIST)); -// if (!gst_queue_element) { -// GST_ERROR_OBJECT(bcmdec, "mem_rbuf_que_pool malloc failed "); -// return FALSE; -// } -// memset(gst_queue_element, 0, sizeof(GSTBUF_LIST)); -// bcmdec_put_que_mem_padbuf(bcmdec, gst_queue_element); -// } -// -// return TRUE; -// } -// -// static gboolean bcmdec_release_mem_rbuf_que_pool(GstBcmDec *bcmdec) -// { -// GSTBUF_LIST *gst_queue_element; -// guint i = 0; -// -// do { -// gst_queue_element = bcmdec_get_que_mem_padbuf(bcmdec); -// if (gst_queue_element) { -// free(gst_queue_element); -// i++; -// } -// } while (gst_queue_element); -// -// bcmdec->gst_mem_padbuf_que_hd = NULL; -// if (!bcmdec->silent) -// GST_DEBUG_OBJECT(bcmdec, "rend_rbuf_que_pool released... %d", i); -// -// return TRUE; -// } - -static void bcmdec_ins_padbuf(GstBcmDec *bcmdec, GSTBUF_LIST *gst_queue_element) -{ - pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); - - if (!bcmdec->gst_padbuf_que_hd) { - bcmdec->gst_padbuf_que_hd = bcmdec->gst_padbuf_que_tl = gst_queue_element; - } else { - bcmdec->gst_padbuf_que_tl->next = gst_queue_element; - bcmdec->gst_padbuf_que_tl = gst_queue_element; - gst_queue_element->next = NULL; - } - - bcmdec->gst_padbuf_que_cnt++; - GST_DEBUG_OBJECT(bcmdec, "Inc rbuf:%d", bcmdec->gst_padbuf_que_cnt); - - if (sem_post(&bcmdec->rbuf_ins_event) == -1) - GST_ERROR_OBJECT(bcmdec, "rbuf sem_post failed"); - - pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); -} - -static GSTBUF_LIST *bcmdec_rem_padbuf(GstBcmDec *bcmdec) -{ - GSTBUF_LIST *temp; - - pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); - - if (bcmdec->gst_padbuf_que_hd == bcmdec->gst_padbuf_que_tl) { - temp = bcmdec->gst_padbuf_que_hd; - bcmdec->gst_padbuf_que_hd = bcmdec->gst_padbuf_que_tl = NULL; - } else { - temp = bcmdec->gst_padbuf_que_hd; - bcmdec->gst_padbuf_que_hd = temp->next; - } - - if (temp) - bcmdec->gst_padbuf_que_cnt--; - - GST_DEBUG_OBJECT(bcmdec, "Dec rbuf:%d", bcmdec->gst_padbuf_que_cnt); - - pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); - - return temp; -} - -// End of renderer buffer - -/* - * entry point to initialize the plug-in - * initialize the plug-in itself - * register the element factories and other features - */ -static gboolean plugin_init(GstPlugin *bcmdec) -{ - //printf("BcmDec_init"); - - /* - * debug category for fltering log messages - * - * exchange the string 'Template bcmdec' with your description - */ - GST_DEBUG_CATEGORY_INIT(gst_bcmdec_debug, "bcmdec", 0, "Broadcom video decoder"); - - return gst_element_register(bcmdec, "bcmdec", GST_BCMDEC_RANK, GST_TYPE_BCMDEC); -} - -/* gstreamer looks for this structure to register bcmdec */ -GST_PLUGIN_DEFINE(GST_VERSION_MAJOR, GST_VERSION_MINOR, - "bcmdec", "Video decoder", plugin_init, VERSION, - "LGPL", "bcmdec", "http://broadcom.com/") - diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/gstbcmdec.h crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/gstbcmdec.h --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/gstbcmdec.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/gstbcmdec.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,395 +0,0 @@ - /******************************************************************** - * Copyright(c) 2008 Broadcom Corporation. - * - * Name: gstbcmdec.h - * - * Description: Broadcom 70012 Decoder plugin header - * - * AU - * - * HISTORY: - * - ******************************************************************* - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published - * by the Free Software Foundation, either version 2.1 of the License. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - *******************************************************************/ -#ifndef __GST_BCMDEC_H__ -#define __GST_BCMDEC_H__ - - -#define GST_BCMDEC_RANK 0xffff - -#define CLOCK_BASE 9LL -#define CLOC_FREQ_CLOC_BASE * 10000 - -#define GST_BUF_LIST_POOL_SZ 100; - -#define GST_RENDERER_BUF_POOL_SZ 20 - -#define MPEGTIME_TO_GSTTIME(time) ((time) * (GST_MSECOND/10)) / CLOCK_BASE) - -#define GSTIME_TO_MPEGTIME(time) (((time) * CLOCK_BASE) / (GST_MSECOND)/10)) - -const gint64 UNITS = 1000000000; - -#define BRCM_START_CODE_SIZE 4 - -//VC1 prefix 000001 -#define VC1_FRM_SUFFIX 0x0D -#define VC1_SEQ_SUFFIX 0x0F - -//VC1 SM Profile prefix 000001 -#define VC1_SM_FRM_SUFFIX 0xE0 - -//Check WMV SP/MP PES Payload for PTS Info -//#define VC1_SM_MAGIC_WORD 0x5A5A5A5A -//#define VC1_SM_PTS_INFO_START_CODE 0xBD - -//MPEG2 prefix 000001 -#define MPEG2_FRM_SUFFIX 0x00 -#define MPEG2_SEQ_SUFFIX 0xB3 - -#define PAUSE_THRESHOLD 16 -#define RESUME_THRESHOLD 8 -#define SPS_PPS_SIZE 1000 - -#define BCM_GST_SHMEM_KEY 0xDEADBEEF -#define THUMBNAIL_FRAMES 60 - -typedef enum { - H264=0, - MPEG2, - VC1 -}VIDFOMATS; - -typedef enum { - NV12 = 0, - YUY2, - UYVY, - YV12 -}CLRSPACE; - -typedef struct { - guint width; - guint height; - guint8 clr_space; - gdouble framerate; - guint8 aspectratio_x; - guint8 aspectratio_y; - guint32 y_size; - guint32 uv_size; - guint8 stride; - -}OUTPARAMS; - -typedef struct { - guint8* sps_pps_buf; - guint32 pps_size; - gboolean inside_buffer; - guint32 consumed_offset; - guint32 strtcode_offset; - guint32 nal_sz; - guint8 nal_size_bytes; -} CODEC_PARAMS; - - - -typedef struct _GSTBUF_LIST{ - GstBuffer* gstbuf; - struct _GSTBUF_LIST *next; -}GSTBUF_LIST; - -#define MAX_ADV_PROF_SEQ_HDR_SZ 50 - -typedef enum { - UNKNOWN = 0, - THUMBNAIL = 1, - PLAYBACK = 2, -}CURDECODE; - -typedef struct { - guint rendered_frames; - gboolean waiting; - CURDECODE cur_decode; - sem_t inst_ctrl_event; -}GLB_INST_STS; - - -G_BEGIN_DECLS - -#define GST_TYPE_BCMDEC \ - (gst_bcmdec_get_type()) -#define GST_BCMDEC(obj) \ - (G_TYPE_CHECK_INSTANCE_CAST((obj),GST_TYPE_BCMDEC,GstBcmDec)) -#define GST_BCMDEC_CLASS(klass) \ - (G_TYPE_CHECK_CLASS_CAST((klass),GST_TYPE_BCMDEC,GstBcmDecClass)) -#define GST_IS_BCMDEC(obj) \ - (G_TYPE_CHECK_INSTANCE_TYPE((obj),GST_TYPE_BCMDEC)) -#define GST_IS_BCMDEC_CLASS(klass) \ - (G_TYPE_CHECK_CLASS_TYPE((klass),GST_TYPE_BCMDEC)) - -typedef struct _GstBcmDec GstBcmDec; -typedef struct _GstBcmDecClass GstBcmDecClass; - - -struct _GstBcmDec -{ - GstElement element; - GstPad *sinkpad, *srcpad; - gboolean silent; - void* hdevice; - gboolean dec_ready; - gboolean streaming; - gboolean feos; - GMutex *mPlayLock; - BC_MEDIA_SUBTYPE input_format; - OUTPARAMS output_params; - pthread_t recv_thread; - sem_t play_event; - sem_t quit_event; - BcmDecIF decif; - Parse parse; - BC_PIC_INFO_BLOCK pic_info; - gboolean format_reset; - gboolean interlace; - GstClockTime base_time; - FILE *fhnd ; - gboolean play_pending; - GstEvent* ev_eos; - GSTBUF_LIST* gst_buf_que_hd; - GSTBUF_LIST* gst_buf_que_tl; - pthread_mutex_t gst_buf_que_lock; - guint gst_que_cnt; - pthread_t push_thread; - gboolean last_picture_set; - sem_t buf_event; - guint gst_buf_que_sz; - GSTBUF_LIST* gst_mem_buf_que_hd; - - gdouble input_framerate; - guint32 prev_pic; - gboolean paused; - gboolean insert_start_code; - - CODEC_PARAMS codec_params ; - gboolean sec_field; - guint8 input_par_x; - guint8 input_par_y; - - gboolean flushing; - sem_t push_stop_event; - sem_t push_start_event; - sem_t recv_stop_event; - guint ses_nbr; - gboolean insert_pps; - gboolean ses_change; - gboolean push_exit; - pthread_mutex_t fn_lock; - gboolean suspend_mode; - GstClock* gst_clock; - guint32 rpt_pic_cnt; - - gboolean enable_spes; - guint8* dest_buf; - guint32 spes_frame_cnt; - GstClockTime spes_frm_time; - gboolean catchup_on; - GstClockTime last_spes_time; - GstClockTime last_output_spes_time; - GstClockTime frame_time; - GstClockTime base_clock_time; - GstClockTime prev_clock_time; - GstClockTime cur_stream_time; - guint8 proc_in_flags; - - gint frame_width; /*The value from Demux used for WMV9 or VC-1 SP/MP */ - gint frame_height; /*The value from Demux used for WMV9 or VC-1 SP/MP */ - - GSTBUF_LIST* gst_padbuf_que_hd; - GSTBUF_LIST* gst_padbuf_que_tl; - pthread_mutex_t gst_padbuf_que_lock; - guint gst_padbuf_que_cnt; - pthread_t get_rbuf_thread; - sem_t rbuf_start_event; - sem_t rbuf_stop_event; - sem_t rbuf_ins_event; - guint gst_padbuf_que_sz; - GSTBUF_LIST* gst_mem_padbuf_que_hd; - gboolean rbuf_thread_running; -}; - -struct _GstBcmDecClass -{ - GstElementClass parent_class; -}; - -GType gst_bcmdec_get_type (void); - -static void -gst_bcmdec_base_init (gpointer gclass); - -static void -gst_bcmdec_class_init(GstBcmDecClass * klass); - -static void -gst_bcmdec_init(GstBcmDec * bcmdec, - GstBcmDecClass * gclass); - -static void -gst_bcmdec_finalize(GObject * object); - -static GstFlowReturn -gst_bcmdec_chain(GstPad * pad, - GstBuffer * buffer); - -static GstStateChangeReturn -gst_bcmdec_change_state(GstElement * element, - GstStateChange transition); - -static gboolean -gst_bcmdec_sink_set_caps(GstPad * pad, - GstCaps * caps); - -static GstCaps *gst_bcmdec_getcaps (GstPad * pad); - -static gboolean -gst_bcmdec_src_event(GstPad * pad, - GstEvent * event); - -static gboolean -gst_bcmdec_sink_event(GstPad * pad, - GstEvent * event); - -static void -gst_bcmdec_set_property (GObject * object, guint prop_id, - const GValue * value, GParamSpec * pspec); - -static void -gst_bcmdec_get_property (GObject * object, guint prop_id, - GValue * value, GParamSpec * pspec); - -static gboolean -bcmdec_negotiate_format (GstBcmDec * bcmdec); - -static void -bcmdec_reset(GstBcmDec * bcmdec); - -static gboolean -bcmdec_get_buffer(GstBcmDec * bcmdec, GstBuffer ** obuf); - -static void* -bcmdec_process_output(void * ctx); - -static void -bcmdec_init_procout(GstBcmDec * filter,BC_DTS_PROC_OUT* pout, guint8* buf); - -static void -bcmdec_set_framerate(GstBcmDec * filter,guint32 resolution); - -static gboolean -bcmdec_format_change(GstBcmDec * filter,BC_PIC_INFO_BLOCK* pic_info); - -static BC_STATUS -gst_bcmdec_cleanup(GstBcmDec *filter); - -static gboolean -bcmdec_start_recv_thread(GstBcmDec * bcmdec); - -static GstClockTime -bcmdec_get_time_stamp(GstBcmDec* filter, guint32 pic_no,GstClockTime spes_time); - -static gboolean -bcmdec_process_play(GstBcmDec *filter); - -static gboolean -bcmdec_alloc_mem_buf_que_pool(GstBcmDec *filter); - -static gboolean -bcmdec_release_mem_buf_que_pool(GstBcmDec *filter); - -static void -bcmdec_put_que_mem_buf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); - -static GSTBUF_LIST* -bcmdec_get_que_mem_buf(GstBcmDec *filter); - -static void -bcmdec_ins_buf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); - -static GSTBUF_LIST* -bcmdec_rem_buf(GstBcmDec *filter); - -static void* -bcmdec_process_push(void* ctx); - -static gboolean -bcmdec_start_push_thread(GstBcmDec * bcmdec); - -//static BC_STATUS -//bcmdec_insert_startcode(GstBcmDec* filter,GstBuffer* gstbuf, guint8* dest_buf,guint32* sz); - -static BC_STATUS -bcmdec_insert_sps_pps(GstBcmDec* filter,GstBuffer* gstbuf); - -static void -bcmdec_set_aspect_ratio(GstBcmDec *filter,BC_PIC_INFO_BLOCK* pic_info); - -static void -bcmdec_process_flush_start(GstBcmDec* filter); - -static void -bcmdec_process_flush_stop(GstBcmDec* filter); - -static BC_STATUS -bcmdec_resume_callback(GstBcmDec* filter); - -static BC_STATUS -bcmdec_suspend_callback(GstBcmDec* filter); - -static gboolean -bcmdec_mul_inst_cor(GstBcmDec* filter); - -static BC_STATUS -bcmdec_create_shmem(GstBcmDec* filter,int *shmem_id); - -static BC_STATUS -bcmdec_get_shmem(GstBcmDec* filter,int shmid,gboolean newsh); - -static BC_STATUS -bcmdec_del_shmem(GstBcmDec* filter); - -static gboolean -bcmdec_start_get_rbuf_thread(GstBcmDec * bcmdec); - -// static gboolean -// bcmdec_alloc_mem_padbuf_que_pool(GstBcmDec *filter); -// -// static gboolean -// bcmdec_release_mem_padbuf_que_pool(GstBcmDec *filter); - -// static void -// bcmdec_put_que_mem_padbuf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); -// -// static GSTBUF_LIST* -// bcmdec_get_que_mem_padbuf(GstBcmDec *filter); - -static void -bcmdec_ins_padbuf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); - -static GSTBUF_LIST* -bcmdec_rem_padbuf(GstBcmDec *filter); - - -G_END_DECLS - -#endif /* __GST_BCMDEC_H__ */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/Makefile.am crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/Makefile.am --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/Makefile.am 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/Makefile.am 1970-01-01 00:00:00.000000000 +0000 @@ -1,36 +0,0 @@ -# plugindir is set in configure - -ROOTDIR = ../../../.. -CC = g++ -CPP = g++ -INCLUDES = -I./ -I/usr/include -I/usr/include/libcrystalhd - -BCMDEC_CFLAGS = $(INCLUDES) -D__LINUX_USER__ -DWMV_FILE_HANDLING -BCMDEC_CFLAGS += -O2 -g -Wall - -BCMDEC_LDFLAGS = -lcrystalhd - -############################################################################## -# change libgstplugin.la to something more suitable, e.g. libmysomething.la # -############################################################################## -plugin_LTLIBRARIES = libgstbcmdec.la - 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clean-libtool clean-pluginLTLIBRARIES ctags distclean \ - distclean-compile distclean-generic distclean-libtool \ - distclean-tags distdir dvi dvi-am html html-am info info-am \ - install install-am install-data install-data-am install-dvi \ - install-dvi-am install-exec install-exec-am install-html \ - install-html-am install-info install-info-am install-man \ - install-pdf install-pdf-am install-pluginLTLIBRARIES \ - install-ps install-ps-am install-strip installcheck \ - installcheck-am installdirs maintainer-clean \ - maintainer-clean-generic mostlyclean mostlyclean-compile \ - mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ - tags uninstall uninstall-am uninstall-pluginLTLIBRARIES - - -# Tell versions [3.59,3.63) of GNU make to not export all variables. -# Otherwise a system limit (for SysV at least) may be exceeded. -.NOEXPORT: diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/parse.c crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/parse.c --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/parse.c 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/parse.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,297 +0,0 @@ - /******************************************************************* - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published - * by the Free Software Foundation, either version 2.1 of the License. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - *******************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "bc_dts_defs.h" -#include "parse.h" - -void parse_init(Parse *parse) -{ - parse->bIsFirstByteStreamNALU = TRUE; -} - -gboolean parse_find_strt_code(Parse *parse, guint8 input_format, guint8 *in_buffer, - guint32 size, guint32 *poffset) -{ - guint32 i = 0; - guint8 Suffix1 = 0; - guint8 Suffix2 = 0; - - if (input_format == BC_VID_ALGO_VC1) { - Suffix1 = VC1_FRM_SUFFIX; - Suffix2 = VC1_SEQ_SUFFIX; - } - else if (input_format == BC_VID_ALGO_MPEG2) { - Suffix1 = MPEG2_FRM_SUFFIX; - Suffix2 = MPEG2_SEQ_SUFFIX; - } - /* For VC-1 SP/MP */ - else if (input_format == BC_VID_ALGO_VC1MP) { - Suffix1 = VC1_SM_FRM_SUFFIX; - } - - if (input_format == BC_VID_ALGO_H264) { - int nNalType = 0; - uint32_t ulPos = 0; - nNalType = parseAVC(parse, in_buffer, size, &ulPos); - if ((nNalType == NALU_TYPE_SEI) || (nNalType == NALU_TYPE_PPS) || - (nNalType == NALU_TYPE_SPS)) { - *poffset = ulPos; - return TRUE; - } else if ((nNalType == NALU_TYPE_SLICE) | (nNalType == NALU_TYPE_IDR)) { - *poffset = 0; - return TRUE; - } - } else { /* VC1, MPEG2 */ - while (i < size) { - if ((*(in_buffer + i) == Suffix1) || (*(in_buffer + i) == Suffix2)) { - if (i >= 3) { - if ((*(in_buffer + (i - 3)) == 0x00) && - (*(in_buffer + (i - 2)) == 0x00) && - (*(in_buffer + (i - 1)) == 0x01)) { - *poffset = i-3; - return TRUE; - } - } - } - i++; - } - } - - return FALSE; -} - -gint FindBSStartCode(guint8 *Buf, gint ZerosInStartcode) -{ - BOOL bStartCode = TRUE; - gint i; - - for (i = 0; i < ZerosInStartcode; i++) - if (Buf[i] != 0) - bStartCode = FALSE; - - if (Buf[i] != 1) - bStartCode = FALSE; - - return bStartCode; -} - -gint GetNaluType(Parse *parse, guint8 *pInputBuf, guint32 ulSize, NALU_t *pNalu) -{ - gint b20sInSC, b30sInSC; - gint bStartCodeFound, Rewind; - gint nLeadingZero8BitsCount = 0, TrailingZero8Bits = 0; - guint32 Pos = 0; - - while (Pos <= ulSize) { - if ((pInputBuf[Pos++]) == 0) - continue; - else - break; - } - - if (pInputBuf[Pos - 1] != 1) - return -1; - - if (Pos < 3) { - return -1; - } else if (Pos == 3) { - pNalu->StartcodePrefixLen = 3; - nLeadingZero8BitsCount = 0; - } else { - nLeadingZero8BitsCount = Pos - 4; - pNalu->StartcodePrefixLen = 4; - } - - /* - * the 1st byte stream NAL unit can has nLeadingZero8BitsCount, but subsequent - * ones are not allowed to contain it since these zeros (if any) are considered - * trailing_zero_8bits of the previous byte stream NAL unit. - */ - if (!parse->bIsFirstByteStreamNALU && nLeadingZero8BitsCount > 0) - return -1; - - parse->bIsFirstByteStreamNALU = false; - - bStartCodeFound = 0; - b20sInSC = 0; - b30sInSC = 0; - - while ((!bStartCodeFound) && (Pos < ulSize)) { - Pos++; - if (Pos > ulSize) - printf("GetNaluType : Pos > size = %d\n", ulSize); - - b30sInSC = FindBSStartCode((pInputBuf + Pos - 4), 3); - if (b30sInSC != 1) - b20sInSC = FindBSStartCode((pInputBuf + Pos - 3), 2); - bStartCodeFound = (b20sInSC || b30sInSC); - } - - Rewind = 0; -#if 0 - if (!bStartCodeFound) { - //even if next start code is not found pprocess this NAL. - return -1; - } -#endif - - if (bStartCodeFound) { - //Count the trailing_zero_8bits - //TrailingZero8Bits is present only for start code 00 00 00 01 - if (b30sInSC) { - while(pInputBuf[Pos - 5 - TrailingZero8Bits] == 0) - TrailingZero8Bits++; - } - // Here, we have found another start code (and read length of startcode bytes more than we should - // have. Hence, go back in the file - - if (b30sInSC) - Rewind = -4; - else if (b20sInSC) - Rewind = -3; - } - - // Here the leading zeros(if any), Start code, the complete NALU, trailing zeros(if any) - // until the next start code . - // Total size traversed is Pos, Pos+rewind are the number of bytes excluding the next - // start code, and (Pos+rewind)-StartcodePrefixLen-LeadingZero8BitsCount-TrailingZero8Bits - // is the size of the NALU. - - pNalu->Len = (Pos + Rewind) - pNalu->StartcodePrefixLen - nLeadingZero8BitsCount - TrailingZero8Bits; - - pNalu->NalUnitType = (pInputBuf[nLeadingZero8BitsCount + pNalu->StartcodePrefixLen]) & 0x1f; - - return (Pos+Rewind); -} - -gint parseAVC(Parse *parse, guint8 *pInputBuf, guint32 ulSize, guint32 *Offset) -{ - NALU_t Nalu; - gint ret = 0; - guint32 Pos = 0; - gboolean bResult = false; - - while (1) - { - ret = GetNaluType(parse, pInputBuf + Pos, ulSize - Pos, &Nalu); - if (ret <= 0) - return -1; - - Pos += ret; - - switch (Nalu.NalUnitType) { - case NALU_TYPE_SLICE: - case NALU_TYPE_IDR: - bResult = true; - break; - case NALU_TYPE_SEI: - case NALU_TYPE_PPS: - case NALU_TYPE_SPS: - bResult = true; - break; - case NALU_TYPE_DPA: - case NALU_TYPE_DPC: - case NALU_TYPE_AUD: - case NALU_TYPE_EOSEQ: - case NALU_TYPE_EOSTREAM: - case NALU_TYPE_FILL: - default: - break; - } - - if (bResult) { - *Offset = Pos; - break; - } - } - - return Nalu.NalUnitType; -} - -gboolean SiBuffer(SymbInt *simb_int, guint8 *pInputBuffer, guint32 ulSize) -{ - simb_int->m_pCurrent = simb_int->m_pInputBuffer = (guint8 *)pInputBuffer; - simb_int->m_nSize = ulSize; - simb_int->m_pInputBufferEnd = simb_int->m_pInputBuffer + ulSize; - simb_int->m_nUsed = 1; - simb_int->m_ulOffset = 0; - simb_int->m_ulMask = 0x80; - - return TRUE; -} - -gboolean SiUe(SymbInt *simb_int, guint32 *pCode) -{ - guint32 ulSuffix; - int nLeadingZeros; - int nBit; - - nLeadingZeros = -1; - for (nBit = 0; nBit == 0; nLeadingZeros++) { - nBit = NextBit(simb_int); - if (simb_int->m_nUsed >= simb_int->m_nSize) - return FALSE; - } - - *pCode = (1 << nLeadingZeros) - 1; - - ulSuffix = 0; - while (nLeadingZeros-- > 0) { - ulSuffix = (ulSuffix << 1) | NextBit(simb_int); - if (simb_int->m_nUsed >= simb_int->m_nSize) - return FALSE; - } - *pCode += ulSuffix; - - return TRUE; -} - -inline gint NextBit(SymbInt *simb_int) -{ - int nBit; - - nBit = (simb_int->m_pCurrent[0] & simb_int->m_ulMask) ? 1 : 0; - - if ((simb_int->m_ulMask >>= 1) == 0) { - simb_int->m_ulMask = 0x80; - - if (simb_int->m_nUsed == simb_int->m_nSize) - simb_int->m_pCurrent = simb_int->m_pInputBuffer; //reset look again - else { - if (++simb_int->m_pCurrent == simb_int->m_pInputBufferEnd) - simb_int->m_pCurrent = simb_int->m_pInputBuffer; - simb_int->m_nUsed++; - } - } - simb_int->m_ulOffset++; - - return nBit; -} - -guint32 SiOffset(SymbInt *simb_int) -{ - return simb_int->m_ulOffset; -} diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/parse.h crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/parse.h --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/parse.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/parse.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,113 +0,0 @@ -/******************************************************************* - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published - * by the Free Software Foundation, either version 2.1 of the License. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - *******************************************************************/ -#ifndef CPARSE -#define CPARSE - -//VC1 prefix 000001 -#define VC1_FRM_SUFFIX 0x0D -#define VC1_SEQ_SUFFIX 0x0F - -//VC1 SM Profile prefix 000001 -#define VC1_SM_FRM_SUFFIX 0xE0 - -//Check WMV SP/MP PES Payload for PTS Info -#define VC1_SM_MAGIC_WORD 0x5A5A5A5A -#define VC1_SM_PTS_INFO_START_CODE 0xBD - -//MPEG2 prefix 000001 -#define MPEG2_FRM_SUFFIX 0x00 -#define MPEG2_SEQ_SUFFIX 0xB3 - -typedef enum -{ - P_SLICE = 0, - B_SLICE, - I_SLICE, - SP_SLICE, - SI_SLICE -} SliceType; - - -typedef enum -{ - NALU_TYPE_SLICE = 1, - NALU_TYPE_DPA, - NALU_TYPE_DPB, - NALU_TYPE_DPC, - NALU_TYPE_IDR, - NALU_TYPE_SEI, - NALU_TYPE_SPS, - NALU_TYPE_PPS, - NALU_TYPE_AUD, - NALU_TYPE_EOSEQ, - NALU_TYPE_EOSTREAM, - NALU_TYPE_FILL -}NALuType; - -typedef struct -{ - gint StartcodePrefixLen; //! 4 for parameter sets and first slice in picture, 3 for everything else (suggested) - guint Len; //! Length of the NAL unit (Excluding the start code, which does not belong to the NALU) - guint MaxSize; //! Nal Unit Buffer size - gint NalUnitType; //! NALU_TYPE_xxxx - gint ForbiddenBit; //! should be always FALSE - guint8* pNalBuf; -} NALU_t; - -typedef struct -{ - guint8* m_pInputBuffer; - guint8* m_pInputBufferEnd; - guint8* m_pCurrent; - guint32 m_ulMask; - guint32 m_ulOffset; - gint m_nSize; - gint m_nUsed; - guint32 m_ulZero; -}SymbInt; - -typedef struct { - gboolean bIsFirstByteStreamNALU; - SymbInt symb_int; - -}Parse; - - -void -parse_init(Parse* parse); - -gint -parseAVC(Parse* parse,guint8* pInputBuf,guint32 ulSize,guint32* Offset); - -gboolean -parse_find_strt_code(Parse* parse,guint8 input_format,guint8* in_buffer,guint32 size,guint32* poffset); - -gint -GetNaluType(Parse* parse,guint8* pInputBuf, guint32 ulSize, NALU_t* pNalu); - -gboolean -SiBuffer(SymbInt* simb_int,guint8 * pInputBuffer, guint32 ulSize); - -gboolean -SiUe(SymbInt* simb_int,guint32* pCode); - -guint32 -SiOffset(SymbInt*); - -inline gint -NextBit ( SymbInt*); - - -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/version.h crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/version.h --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/version.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/version.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,203 +0,0 @@ -/******************************************************************** -* Copyright(c) 2006 Broadcom Corporation. -* -* Name: version.h -* -* Description: Version numbering for the driver use. -* -* AU -* -* HISTORY: -* -******************************************************************* -* -* This library is free software: you can redistribute it and/or modify -* it under the terms of the GNU Lesser General Public License as published -* by the Free Software Foundation, either version 2.1 of the License. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU Lesser General Public License for more details. -* You should have received a copy of the GNU Lesser General Public License -* along with this library. If not, see . -* -*******************************************************************/ - -#ifndef _BC_DTS_VERSION_ -#define _BC_DTS_VERSION_ -// -// The version format that we are adopting is -// MajorVersion.MinorVersion.Revision -// This will be the same for all the components. -// -// -#define STRINGIFY_VERSION(MAJ,MIN,REV) STRINGIFIED_VERSION(MAJ,MIN,REV) -#define STRINGIFIED_VERSION(MAJ,MIN,REV) #MAJ "." #MIN "." #REV - -#define STRINGIFY_VERSION_W(MAJ,MIN,REV) STRINGIFIED_VERSION_W(MAJ,MIN,REV) -#define STRINGIFIED_VERSION_W(MAJ,MIN,REV) #MAJ "." #MIN "." #REV - -// -// Product Version number is: -// x.y.z.a -// -// x = Major release. 1 = Dozer, 2 = Dozer + Link -// y = Minor release. Should increase +1 per "real" release. -// z = Branch release. 0 for main branch. This is +1 per branch release. -// a = Build number +1 per candidate release. Reset to 0 every "real" release. -// -// -// Enabling Check-In rules enforcement 08092007 -// -#define INVALID_VERSION 0xFFFF - -/*========================== Common For All Components =================================*/ -#define RC_COMPANY_NAME "Broadcom Corporation\0" -#define RC_PRODUCT_VERSION "2.7.0.25" -#define RC_W_PRODUCT_VERSION L"2.7.0.25" -#define RC_PRODUCT_NAME "Broadcom Video Decoder\0" -#define RC_COMMENTS "Broadcom BCM70010/BCM70012 Controller\0" -#define RC_COPYRIGHT "Copyright(c) 2007 Broadcom Corporation" -#define RC_PRIVATE_BUILD "Broadcom Corp. Private\0" -#define RC_LEGAL_TRADEMARKS " \0" -#define BRCM_MAJOR_VERSION 2 - - -/*========================== WDM Driver =================================*/ - -/* - * Version number scheme for driver DVMJVer.DVMNVer.DVRev.UNMODIFIED - * Where DVMJVer = DRIVER_MAJOR_VERSION - * DVMNVer = DRIVER_MINOR_VERSION - * DVRev = DRIVER_REVISION - * UNMODIFIED = This is for Compatibility with windows INF file version scheme. - */ - -#define RC_FILE_DESCRIPTION "Broadcom BCM70010/BCM70012 Driver\0" -#define RC_INTERNAL_NAME "" -#define RC_ORIGINAL_NAME RC_INTERNAL_NAME -#define RC_SPECIAL_BUILD "" - -#define DRIVER_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DRIVER_MINOR_VERSION 31 -#define DRIVER_REVISION 0 - -#define RC_FILE_VERSION STRINGIFY_VERSION(DRIVER_MAJOR_VERSION,DRIVER_MINOR_VERSION,DRIVER_REVISION) ".0" - -/*======================= Device Interface Library ========================*/ -#define DIL_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DIL_MINOR_VERSION 26 -#define DIL_REVISION 0 - -#define DIL_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) - -/*========================== Direct Show Filter ==============================*/ -#define DFILTER_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DFILTER_MINOR_VERSION 26 -#define DFILTER_REVISION 0 - -#define DFILTER_RC_FILE_VERSION STRINGIFY_VERSION(DFILTER_MAJOR_VERSION,DFILTER_MINOR_VERSION,DFILTER_REVISION) - -/*========================== Direct Show NS Filter ==============================*/ -#define NS_DFILTER_MAJOR_VERSION BRCM_MAJOR_VERSION -#define NS_DFILTER_MINOR_VERSION 41 -#define NS_DFILTER_REVISION 0 - -#define NS_DFILTER_RC_FILE_VERSION STRINGIFY_VERSION(NS_DFILTER_MAJOR_VERSION,NS_DFILTER_MINOR_VERSION,NS_DFILTER_REVISION) - -/*========================== deconf utility ==============================*/ -#define DECONF_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DECONF_MINOR_VERSION 10 -#define DECONF_REVISION 0 - -/*========================== MP-4 Demux Filter ==============================*/ -#define MP4DEMUX_MAJOR_VERSION BRCM_MAJOR_VERSION -#define MP4DEMUX_MINOR_VERSION 7 -#define MP4DEMUX_REVISION 0 - -#define MP4DEMUX_RC_FILE_VERSION STRINGIFY_VERSION(MP4DEMUX_MAJOR_VERSION,MP4DEMUX_MINOR_VERSION,MP4DEMUX_REVISION) - -/*========================== MFT Decoder ==============================*/ -#define MFTDECODER_MAJOR_VERSION BRCM_MAJOR_VERSION -#define MFTDECODER_MINOR_VERSION 4 -#define MFTDECODER_REVISION 0 - -#define MFTDECODER_RC_FILE_VERSION STRINGIFY_VERSION(MFTDECODER_MAJOR_VERSION,MFTDECODER_MINOR_VERSION,MFTDECODER_REVISION) - -/*======================= deconft utility ========================*/ -#define DECONFT_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DECONFT_MINOR_VERSION 8 -#define DECONFT_REVISION 0 - -#define DECONFT_RC_FILE_VERSION STRINGIFY_VERSION(DECONFT_MAJOR_VERSION,DECONFT_MINOR_VERSION,DECONFT_REVISION) - -/*======================= Gensig utility ========================*/ -#define GENSIG_MAJOR_VERSION BRCM_MAJOR_VERSION -#define GENSIG_MINOR_VERSION 7 -#define GENSIG_REVISION 0 - -#define GENSIG_RC_FILE_VERSION STRINGIFY_VERSION(GENSIG_MAJOR_VERSION,GENSIG_MINOR_VERSION,GENSIG_REVISION) - -/*======================= FpgaProg utility ========================*/ -#define FPGAPROG_MAJOR_VERSION BRCM_MAJOR_VERSION -#define FPGAPROG_MINOR_VERSION 1 -#define FPGAPROG_REVISION 0 - -#define FPGAPROG_RC_FILE_VERSION STRINGIFY_VERSION(FPGAPROG_MAJOR_VERSION,FPGAPROG_MINOR_VERSION,FPGAPROG_REVISION) - -/*======================= CHDGensig DataBase Library ========================*/ -#define CHDGSDB_MAJOR_VERSION BRCM_MAJOR_VERSION -#define CHDGSDB_MINOR_VERSION 3 -#define CHDGSDB_REVISION 0 - -#define CHDGSDB_RC_FILE_VERSION STRINGIFY_VERSION(CHDGSDB_MAJOR_VERSION,CHDGSDB_MINOR_VERSION,CHDGSDB_REVISION) - -/*======================= CHDDosDiag utility ========================*/ -#define DOSDIAG_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DOSDIAG_MINOR_VERSION 9 -#define DOSDIAG_REVISION 0 - -#define DOSDIAG_RC_FILE_VERSION STRINGIFY_VERSION(DOSDIAG_MAJOR_VERSION,DOSDIAG_MINOR_VERSION,DOSDIAG_REVISION) - -/*======================= CHDWinDiag utility ========================*/ -#define WINDIAG_MAJOR_VERSION BRCM_MAJOR_VERSION -#define WINDIAG_MINOR_VERSION 12 -#define WINDIAG_REVISION 0 - -#define WINDIAG_RC_FILE_VERSION STRINGIFY_VERSION(WINDIAG_MAJOR_VERSION,WINDIAG_MINOR_VERSION,WINDIAG_REVISION) - -/*======================= CHDWinInfo utility ========================*/ -#define WININFO_MAJOR_VERSION BRCM_MAJOR_VERSION -#define WININFO_MINOR_VERSION 1 -#define WININFO_REVISION 0 - -#define WININFO_RC_FILE_VERSION STRINGIFY_VERSION(WININFO_MAJOR_VERSION,WININFO_MINOR_VERSION,WININFO_REVISION) - -/*========================== WDM Encode Driver =================================*/ -#define ENCODE_WDM_COMMENTS "Broadcom Corp. BCM70013 Encoder\0" -#define ENCODE_WDM_PRODUCT_NAME "Broadcom Corp. MediaPC HD Video Encoder\0" -#define ENCODE_WDM_PRIVATE_BUILD "Broadcom Corp. Private\0" - -#define ENCODE_WDM_FILE_DESC "Broadcom Corp BCM70013 WDM Driver\0" -#define ENCODE_WDM_INTRL_NAME "Link B0" -#define ENCODE_WDM_ORIG_NAME ENCODE_WDM_INTRL_NAME -#define ENCODE_WDM_SPECIAL_BUILD "" - -#define ENCODE_WDM_MAJOR_VERSION BRCM_MAJOR_VERSION -#define ENCODE_WDM_MINOR_VERSION 0 -#define ENCODE_WDM_REVISION 1 - -#define ENCODE_WDM_FILE_VERSION STRINGIFY_VERSION(ENCODE_WDM_MAJOR_VERSION,ENCODE_WDM_MINOR_VERSION,ENCODE_WDM_REVISION) ".0" - -/*========================== CmdUtil Application ==============================*/ -#define CMDUTIL_MAJOR_VERSION BRCM_MAJOR_VERSION -#define CMDUTIL_MINOR_VERSION 0 -#define CMDUTIL_REVISION 0 - -/*========================== CmdUtilt utility ==============================*/ -#define CMDUTILT_MAJOR_VERSION BRCM_MAJOR_VERSION -#define CMDUTILT_MINOR_VERSION 0 -#define CMDUTILT_REVISION - -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/version_lnx.h crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/version_lnx.h --- crystalhd-0.0~git20101012.a3a83b8/filters/gst/gst-plugin/src/version_lnx.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/filters/gst/gst-plugin/src/version_lnx.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,111 +0,0 @@ -/******************************************************************** -* Copyright(c) 2006 Broadcom Corporation. -* -* Name: version_lnx.h -* -* Description: Version numbering for the driver use. -* -* AU -* -* HISTORY: -* -******************************************************************* -* -* This library is free software: you can redistribute it and/or modify -* it under the terms of the GNU Lesser General Public License as published -* by the Free Software Foundation, either version 2.1 of the License. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU Lesser General Public License for more details. -* You should have received a copy of the GNU Lesser General Public License -* along with this library. If not, see . -* -*******************************************************************/ - -#ifndef _BC_DTS_VERSION_LNX_ -#define _BC_DTS_VERSION_LNX_ -// -// The version format that we are adopting is -// MajorVersion.MinorVersion.Revision -// This will be the same for all the components. -// -// -#define STRINGIFY_VERSION(MAJ,MIN,REV) STRINGIFIED_VERSION(MAJ,MIN,REV) -#define STRINGIFIED_VERSION(MAJ,MIN,REV) #MAJ "." #MIN "." #REV - -#define STRINGIFY_VERSION_W(MAJ,MIN,REV) STRINGIFIED_VERSION_W(MAJ,MIN,REV) -#define STRINGIFIED_VERSION_W(MAJ,MIN,REV) #MAJ "." #MIN "." #REV - -// -// Product Version number is: -// x.y.z.a -// -// x = Major release. 1 = Dozer, 2 = Dozer + Link -// y = Minor release. Should increase +1 per "real" release. -// z = Branch release. 0 for main branch. This is +1 per branch release. -// a = Build number +1 per candidate release. Reset to 0 every "real" release. -// -// -// Enabling Check-In rules enforcement 08092007 -// -#define INVALID_VERSION 0xFFFF - -/*========================== Common For All Components =================================*/ -#define RC_COMPANY_NAME "Broadcom Corporation\0" -#define RC_PRODUCT_VERSION "2.7.0.23" -#define RC_W_PRODUCT_VERSION L"2.7.0.23" -#define RC_PRODUCT_NAME "Broadcom Video Decoder\0" -#define RC_COMMENTS "Broadcom BCM70010/BCM70012 Controller\0" -#define RC_COPYRIGHT "Copyright(c) 2007 Broadcom Corporation" -#define RC_PRIVATE_BUILD "Broadcom Corp. Private\0" -#define RC_LEGAL_TRADEMARKS " \0" -#define BRCM_MAJOR_VERSION 0 - - -/*========================== WDM Driver =================================*/ - -/* - * Version number scheme for driver DVMJVer.DVMNVer.DVRev.UNMODIFIED - * Where DVMJVer = DRIVER_MAJOR_VERSION - * DVMNVer = DRIVER_MINOR_VERSION - * DVRev = DRIVER_REVISION - * UNMODIFIED = This is for Compatibility with windows INF file version scheme. - */ - -#define RC_FILE_DESCRIPTION "Broadcom BCM70010/BCM70012 Driver\0" -#define RC_INTERNAL_NAME "" -#define RC_ORIGINAL_NAME RC_INTERNAL_NAME -#define RC_SPECIAL_BUILD "" - -#define DRIVER_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DRIVER_MINOR_VERSION 1 -#define DRIVER_REVISION 0 - -#define RC_FILE_VERSION STRINGIFY_VERSION(DRIVER_MAJOR_VERSION,DRIVER_MINOR_VERSION,DRIVER_REVISION) ".0" - -/*======================= Device Interface Library ========================*/ -#define DIL_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DIL_MINOR_VERSION 1 -#define DIL_REVISION 0 - -#define DIL_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) - -/*========================== deconf utility ==============================*/ -#define DECONF_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DECONF_MINOR_VERSION 1 -#define DECONF_REVISION 0 -#define DECONF_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) - -#ifndef _PB_FIX_ME_ -/*======================= deconft utility ========================*/ -#define DECONFT_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DECONFT_MINOR_VERSION 1 -#define DECONFT_REVISION 0 - -#define DECONFT_RC_FILE_VERSION STRINGIFY_VERSION(DECONFT_MAJOR_VERSION,DECONFT_MINOR_VERSION,DECONFT_REVISION) -#endif - - -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/bc_dts_defs.h crystalhd-0.0~git20101029.6df10a0/include/bc_dts_defs.h --- crystalhd-0.0~git20101012.a3a83b8/include/bc_dts_defs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/bc_dts_defs.h 2010-08-16 04:38:08.000000000 +0000 @@ -405,8 +405,6 @@ BC_POUT_FLAGS_SIZE = 0x04, /* Take size information from Application */ BC_POUT_FLAGS_INTERLACED = 0x08, /* copy only half the bytes */ BC_POUT_FLAGS_INTERLEAVED = 0x10, /* interleaved frame */ - BC_POUT_FLAGS_STRIDE_UV = 0x20, /* Stride size is valid (for UV buffers). */ - BC_POUT_FLAGS_MODE = 0x40, /* Take output mode from Application, overrides YV12 flag if on */ /* Flags from Device to APP */ BC_POUT_FLAGS_FMT_CHANGE = 0x10000, /* Data is not VALID when this flag is set */ @@ -461,7 +459,6 @@ uint8_t b422Mode; /* Picture output Mode */ uint8_t bPibEnc; /* PIB encrypted */ uint8_t bRevertScramble; - uint32_t StrideSzUV; /* Caller supplied Stride Size */ } BC_DTS_PROC_OUT; @@ -522,7 +519,6 @@ OUTPUT_MODE420 = 0x0, OUTPUT_MODE422_YUY2 = 0x1, OUTPUT_MODE422_UYVY = 0x2, - OUTPUT_MODE420_NV12 = 0x0, OUTPUT_MODE_INVALID = 0xFF, } BC_OUTPUT_FORMAT; diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/bc_dts_glob_lnx.h crystalhd-0.0~git20101029.6df10a0/include/bc_dts_glob_lnx.h --- crystalhd-0.0~git20101012.a3a83b8/include/bc_dts_glob_lnx.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/bc_dts_glob_lnx.h 2010-08-16 04:38:08.000000000 +0000 @@ -317,9 +317,10 @@ enum _crystalhd_kmod_ver{ crystalhd_kmod_major = 3, - crystalhd_kmod_minor = 8, + crystalhd_kmod_minor = 5, crystalhd_kmod_rev = 0, }; + #endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge_axi_slave.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge_axi_slave.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge_axi_slave.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge_axi_slave.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,90 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_armcr4_bridge_axi_slave.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:28p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:10 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge_axi_slave.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:28p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_ARMCR4_BRIDGE_AXI_SLAVE_H__ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_H__ - -/*************************************************************************** - *ARMCR4_BRIDGE_AXI_SLAVE - AXI Slave indirect registers - ***************************************************************************/ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR 0x000e1000 /* AXI Slave address register */ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ACCESS 0x000e1004 /* AXI Slave write/read access register */ - -/*************************************************************************** - *REG_ADDR - AXI Slave address register - ***************************************************************************/ -/* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: reserved0 [31:27] */ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_reserved0_MASK 0xf8000000 -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_reserved0_SHIFT 27 - -/* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: RAM_sel [26:23] */ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_RAM_sel_MASK 0x07800000 -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_RAM_sel_SHIFT 23 - -/* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: Type_sel [22:19] */ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Type_sel_MASK 0x00780000 -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Type_sel_SHIFT 19 - -/* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: Way_sel [18:15] */ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Way_sel_MASK 0x00078000 -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Way_sel_SHIFT 15 - -/* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: Address [14:00] */ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Address_MASK 0x00007fff -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Address_SHIFT 0 - -/*************************************************************************** - *REG_ACCESS - AXI Slave write/read access register - ***************************************************************************/ -/* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ACCESS :: Access [31:00] */ -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ACCESS_Access_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ACCESS_Access_SHIFT 0 - -#endif /* #ifndef BCHP_ARMCR4_BRIDGE_AXI_SLAVE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,562 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_armcr4_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:28p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:56 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:28p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_ARMCR4_BRIDGE_H__ -#define BCHP_ARMCR4_BRIDGE_H__ - -/*************************************************************************** - *ARMCR4_BRIDGE - ARM Cortex R4 Bridge control registers - ***************************************************************************/ -#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID 0x000e0000 /* ARM Cortex R4 bridge revision ID */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL 0x000e0004 /* Bridge interface and buffer configuration */ -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL 0x000e0008 /* ARM core configuration */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS 0x000e0014 /* Bridge interface and buffer status */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 0x000e0018 /* PCI mailbox #1 */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 0x000e001c /* ARM mailbox #1 */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2 0x000e0020 /* PCI mailbox #2 */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 0x000e0024 /* ARM mailbox #2 */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3 0x000e0028 /* PCI mailbox #3 */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3 0x000e002c /* ARM mailbox #3 */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4 0x000e0030 /* PCI mailbox #4 */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4 0x000e0034 /* ARM mailbox #4 */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1 0x000e0038 /* CPU semaphore #1 */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2 0x000e003c /* CPU semaphore #2 */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3 0x000e0040 /* CPU semaphore #3 */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4 0x000e0044 /* CPU semaphore #4 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1 0x000e0048 /* CPU scratchpad #1 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2 0x000e004c /* CPU scratchpad #2 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3 0x000e0050 /* CPU scratchpad #3 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4 0x000e0054 /* CPU scratchpad #4 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5 0x000e0058 /* CPU scratchpad #5 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6 0x000e005c /* CPU scratchpad #6 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7 0x000e0060 /* CPU scratchpad #7 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8 0x000e0064 /* CPU scratchpad #8 */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9 0x000e0068 /* CPU scratchpad #9 */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG 0x000e006c /* Performance monitor configuration */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT 0x000e0070 /* Performance monitor count threshold */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT 0x000e0074 /* Counts the number of merge buffer updates (hits + misses) */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS 0x000e0078 /* Counts the number of merge buffer misses */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT 0x000e007c /* Counts the number of prefetch buffer accesses (hits + misses) */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS 0x000e0080 /* Counts the number of prefetch buffer misses */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1 0x000e0084 /* ARM memory TM1 control register */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2 0x000e0088 /* ARM memory TM2 control register */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3 0x000e008c /* ARM memory TM3 control register */ -#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS 0x000e0090 /* Fifo Status */ -#define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS 0x000e0094 /* Bridge Out-of-range Checker Status */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4 0x000e0098 /* ARM memory TM4 control register */ - -/*************************************************************************** - *REG_CORE_REV_ID - ARM Cortex R4 bridge revision ID - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_CORE_REV_ID :: reserved0 [31:16] */ -#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_reserved0_MASK 0xffff0000 -#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_reserved0_SHIFT 16 - -/* ARMCR4_BRIDGE :: REG_CORE_REV_ID :: MAJOR [15:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MAJOR_MASK 0x0000ff00 -#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MAJOR_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_CORE_REV_ID :: MINOR [07:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MINOR_MASK 0x000000ff -#define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MINOR_SHIFT 0 - -/*************************************************************************** - *REG_BRIDGE_CTL - Bridge interface and buffer configuration - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: reserved0 [31:24] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved0_MASK 0xff000000 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved0_SHIFT 24 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: timeout [23:12] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_MASK 0x00fff000 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_SHIFT 12 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: reserved1 [11:09] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved1_MASK 0x00000e00 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved1_SHIFT 9 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: ccb_space_alias_en [08:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_ccb_space_alias_en_MASK 0x00000100 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_ccb_space_alias_en_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: timeout_en [07:07] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_en_MASK 0x00000080 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_en_SHIFT 7 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: io_sync_en [06:06] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_io_sync_en_MASK 0x00000040 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_io_sync_en_SHIFT 6 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: prefetch_en [05:05] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_prefetch_en_MASK 0x00000020 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_prefetch_en_SHIFT 5 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: gather_en [04:04] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_gather_en_MASK 0x00000010 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_gather_en_SHIFT 4 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: reserved2 [03:02] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved2_MASK 0x0000000c -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved2_SHIFT 2 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: arm_run_request [01:01] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_MASK 0x00000002 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_SHIFT 1 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: bridge_soft_rst [00:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_bridge_soft_rst_MASK 0x00000001 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_bridge_soft_rst_SHIFT 0 - -/*************************************************************************** - *REG_ARM_CTL - ARM core configuration - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_ARM_CTL :: reserved0 [31:05] */ -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_reserved0_MASK 0xffffffe0 -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_reserved0_SHIFT 5 - -/* ARMCR4_BRIDGE :: REG_ARM_CTL :: DAP_DBGEN [04:04] */ -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_DAP_DBGEN_MASK 0x00000010 -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_DAP_DBGEN_SHIFT 4 - -/* ARMCR4_BRIDGE :: REG_ARM_CTL :: CR4_DBGEN [03:03] */ -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CR4_DBGEN_MASK 0x00000008 -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CR4_DBGEN_SHIFT 3 - -/* ARMCR4_BRIDGE :: REG_ARM_CTL :: CFGNMFI [02:02] */ -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGNMFI_MASK 0x00000004 -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGNMFI_SHIFT 2 - -/* ARMCR4_BRIDGE :: REG_ARM_CTL :: TEINIT [01:01] */ -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_TEINIT_MASK 0x00000002 -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_TEINIT_SHIFT 1 - -/* ARMCR4_BRIDGE :: REG_ARM_CTL :: CFGEE [00:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGEE_MASK 0x00000001 -#define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGEE_SHIFT 0 - -/*************************************************************************** - *REG_BRIDGE_STS - Bridge interface and buffer status - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: reserved0 [31:06] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_reserved0_MASK 0xffffffc0 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_reserved0_SHIFT 6 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: BRIDGE_RESET_DONE [05:05] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_BRIDGE_RESET_DONE_MASK 0x00000020 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_BRIDGE_RESET_DONE_SHIFT 5 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: ARM_STANDBYWFI [04:04] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_ARM_STANDBYWFI_MASK 0x00000010 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_ARM_STANDBYWFI_SHIFT 4 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: prefetch_buff_idle [03:03] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_idle_MASK 0x00000008 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_idle_SHIFT 3 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: prefetch_buff_valid [02:02] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_valid_MASK 0x00000004 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_valid_SHIFT 2 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: merge_buff_idle [01:01] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_idle_MASK 0x00000002 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_idle_SHIFT 1 - -/* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: merge_buff_valid [00:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_valid_MASK 0x00000001 -#define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_valid_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_PCI1 - PCI mailbox #1 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_PCI1 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1_mbox_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_ARM1 - ARM mailbox #1 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_ARM1 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1_mbox_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_PCI2 - PCI mailbox #2 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_PCI2 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2_mbox_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_ARM2 - ARM mailbox #2 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_ARM2 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2_mbox_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_PCI3 - PCI mailbox #3 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_PCI3 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3_mbox_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_ARM3 - ARM mailbox #3 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_ARM3 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3_mbox_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_PCI4 - PCI mailbox #4 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_PCI4 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4_mbox_SHIFT 0 - -/*************************************************************************** - *REG_MBOX_ARM4 - ARM mailbox #4 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MBOX_ARM4 :: mbox [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4_mbox_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4_mbox_SHIFT 0 - -/*************************************************************************** - *REG_SEMAPHORE_1 - CPU semaphore #1 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_1 :: reserved0 [31:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_reserved0_MASK 0xffffff00 -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_reserved0_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_1 :: semaphore [07:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_semaphore_MASK 0x000000ff -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_semaphore_SHIFT 0 - -/*************************************************************************** - *REG_SEMAPHORE_2 - CPU semaphore #2 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_2 :: reserved0 [31:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_reserved0_MASK 0xffffff00 -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_reserved0_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_2 :: semaphore [07:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_semaphore_MASK 0x000000ff -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_semaphore_SHIFT 0 - -/*************************************************************************** - *REG_SEMAPHORE_3 - CPU semaphore #3 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_3 :: reserved0 [31:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_reserved0_MASK 0xffffff00 -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_reserved0_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_3 :: semaphore [07:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_semaphore_MASK 0x000000ff -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_semaphore_SHIFT 0 - -/*************************************************************************** - *REG_SEMAPHORE_4 - CPU semaphore #4 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_4 :: reserved0 [31:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_reserved0_MASK 0xffffff00 -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_reserved0_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_SEMAPHORE_4 :: semaphore [07:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_semaphore_MASK 0x000000ff -#define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_semaphore_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_1 - CPU scratchpad #1 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_1 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_2 - CPU scratchpad #2 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_2 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_3 - CPU scratchpad #3 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_3 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_4 - CPU scratchpad #4 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_4 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_5 - CPU scratchpad #5 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_5 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_6 - CPU scratchpad #6 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_6 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_7 - CPU scratchpad #7 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_7 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_8 - CPU scratchpad #8 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_8 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8_data_SHIFT 0 - -/*************************************************************************** - *REG_SCRATCH_9 - CPU scratchpad #9 - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_SCRATCH_9 :: data [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9_data_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9_data_SHIFT 0 - -/*************************************************************************** - *REG_PERF_CONFIG - Performance monitor configuration - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_PERF_CONFIG :: reserved0 [31:01] */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_reserved0_MASK 0xfffffffe -#define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_reserved0_SHIFT 1 - -/* ARMCR4_BRIDGE :: REG_PERF_CONFIG :: enable [00:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_enable_MASK 0x00000001 -#define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_enable_SHIFT 0 - -/*************************************************************************** - *REG_PERF_LIMIT - Performance monitor count threshold - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_PERF_LIMIT :: count [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT_count_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT_count_SHIFT 0 - -/*************************************************************************** - *REG_PERF_WR_CNT - Counts the number of merge buffer updates (hits + misses) - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_PERF_WR_CNT :: count [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT_count_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT_count_SHIFT 0 - -/*************************************************************************** - *REG_PERF_WR_MISS - Counts the number of merge buffer misses - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_PERF_WR_MISS :: count [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS_count_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS_count_SHIFT 0 - -/*************************************************************************** - *REG_PERF_RD_CNT - Counts the number of prefetch buffer accesses (hits + misses) - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_PERF_RD_CNT :: count [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT_count_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT_count_SHIFT 0 - -/*************************************************************************** - *REG_PERF_RD_MISS - Counts the number of prefetch buffer misses - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_PERF_RD_MISS :: count [31:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS_count_MASK 0xffffffff -#define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS_count_SHIFT 0 - -/*************************************************************************** - *REG_MEMORY_TM1 - ARM memory TM1 control register - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc7 [31:28] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc7_MASK 0xf0000000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc7_SHIFT 28 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc6 [27:24] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc6_MASK 0x0f000000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc6_SHIFT 24 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc5 [23:20] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc5_MASK 0x00f00000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc5_SHIFT 20 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc4 [19:16] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc4_MASK 0x000f0000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc4_SHIFT 16 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc3 [15:12] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc3_MASK 0x0000f000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc3_SHIFT 12 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc2 [11:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc2_MASK 0x00000f00 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc2_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc1 [07:04] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc1_MASK 0x000000f0 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc1_SHIFT 4 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc0 [03:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc0_MASK 0x0000000f -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc0_SHIFT 0 - -/*************************************************************************** - *REG_MEMORY_TM2 - ARM memory TM2 control register - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: reserved0 [31:18] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_reserved0_MASK 0xfffc0000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_reserved0_SHIFT 18 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_dirty [17:16] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_dirty_MASK 0x00030000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_dirty_SHIFT 16 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic6 [15:12] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic6_MASK 0x0000f000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic6_SHIFT 12 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic4 [11:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic4_MASK 0x00000f00 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic4_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic2 [07:04] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic2_MASK 0x000000f0 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic2_SHIFT 4 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic0 [03:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic0_MASK 0x0000000f -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic0_SHIFT 0 - -/*************************************************************************** - *REG_MEMORY_TM3 - ARM memory TM3 control register - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: reserved0 [31:16] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_reserved0_MASK 0xffff0000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_reserved0_SHIFT 16 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it3 [15:14] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it3_MASK 0x0000c000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it3_SHIFT 14 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it2 [13:12] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it2_MASK 0x00003000 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it2_SHIFT 12 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it1 [11:10] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it1_MASK 0x00000c00 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it1_SHIFT 10 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it0 [09:08] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it0_MASK 0x00000300 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it0_SHIFT 8 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt3 [07:06] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt3_MASK 0x000000c0 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt3_SHIFT 6 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt2 [05:04] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt2_MASK 0x00000030 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt2_SHIFT 4 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt1 [03:02] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt1_MASK 0x0000000c -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt1_SHIFT 2 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt0 [01:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt0_MASK 0x00000003 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt0_SHIFT 0 - -/*************************************************************************** - *REG_FIFO_STATUS - Fifo Status - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_FIFO_STATUS :: reserved0 [31:02] */ -#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_reserved0_MASK 0xfffffffc -#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_reserved0_SHIFT 2 - -/* ARMCR4_BRIDGE :: REG_FIFO_STATUS :: CCB_RD_FULL [01:01] */ -#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_RD_FULL_MASK 0x00000002 -#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_RD_FULL_SHIFT 1 - -/* ARMCR4_BRIDGE :: REG_FIFO_STATUS :: CCB_WR_FULL [00:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_WR_FULL_MASK 0x00000001 -#define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_WR_FULL_SHIFT 0 - -/*************************************************************************** - *REG_BORCH_STATUS - Bridge Out-of-range Checker Status - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_BORCH_STATUS :: reserved0 [31:01] */ -#define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_reserved0_SHIFT 1 - -/* ARMCR4_BRIDGE :: REG_BORCH_STATUS :: BORCH_ERROR_STATUS [00:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_BORCH_ERROR_STATUS_MASK 0x00000001 -#define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_BORCH_ERROR_STATUS_SHIFT 0 - -/*************************************************************************** - *REG_MEMORY_TM4 - ARM memory TM4 control register - ***************************************************************************/ -/* ARMCR4_BRIDGE :: REG_MEMORY_TM4 :: reserved0 [31:02] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_reserved0_MASK 0xfffffffc -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_reserved0_SHIFT 2 - -/* ARMCR4_BRIDGE :: REG_MEMORY_TM4 :: tm_pref [01:00] */ -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_tm_pref_MASK 0x00000003 -#define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_tm_pref_SHIFT 0 - -#endif /* #ifndef BCHP_ARMCR4_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_arm_uart.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_arm_uart.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_arm_uart.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_arm_uart.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,134 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_arm_uart.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:28p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:25 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_arm_uart.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:28p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_ARM_UART_H__ -#define BCHP_ARM_UART_H__ - -/*************************************************************************** - *ARM_UART - ARM UART - ***************************************************************************/ -#define BCHP_ARM_UART_DATA 0x000f3000 /* Transmit/receive data */ -#define BCHP_ARM_UART_CTL 0x000f3004 /* Control register and Clock Divider */ -#define BCHP_ARM_UART_STATUS 0x000f3008 /* Status register */ - -/*************************************************************************** - *DATA - Transmit/receive data - ***************************************************************************/ -/* ARM_UART :: DATA :: reserved0 [31:09] */ -#define BCHP_ARM_UART_DATA_reserved0_MASK 0xfffffe00 -#define BCHP_ARM_UART_DATA_reserved0_SHIFT 9 - -/* ARM_UART :: DATA :: PErr [08:08] */ -#define BCHP_ARM_UART_DATA_PErr_MASK 0x00000100 -#define BCHP_ARM_UART_DATA_PErr_SHIFT 8 - -/* ARM_UART :: DATA :: Data [07:00] */ -#define BCHP_ARM_UART_DATA_Data_MASK 0x000000ff -#define BCHP_ARM_UART_DATA_Data_SHIFT 0 - -/*************************************************************************** - *CTL - Control register and Clock Divider - ***************************************************************************/ -/* ARM_UART :: CTL :: ClkDiv [31:16] */ -#define BCHP_ARM_UART_CTL_ClkDiv_MASK 0xffff0000 -#define BCHP_ARM_UART_CTL_ClkDiv_SHIFT 16 - -/* ARM_UART :: CTL :: reserved0 [15:05] */ -#define BCHP_ARM_UART_CTL_reserved0_MASK 0x0000ffe0 -#define BCHP_ARM_UART_CTL_reserved0_SHIFT 5 - -/* ARM_UART :: CTL :: RcvIntEna [04:04] */ -#define BCHP_ARM_UART_CTL_RcvIntEna_MASK 0x00000010 -#define BCHP_ARM_UART_CTL_RcvIntEna_SHIFT 4 - -/* ARM_UART :: CTL :: XmitIntEna [03:03] */ -#define BCHP_ARM_UART_CTL_XmitIntEna_MASK 0x00000008 -#define BCHP_ARM_UART_CTL_XmitIntEna_SHIFT 3 - -/* ARM_UART :: CTL :: EvenParity [02:02] */ -#define BCHP_ARM_UART_CTL_EvenParity_MASK 0x00000004 -#define BCHP_ARM_UART_CTL_EvenParity_SHIFT 2 - -/* ARM_UART :: CTL :: UseParity [01:01] */ -#define BCHP_ARM_UART_CTL_UseParity_MASK 0x00000002 -#define BCHP_ARM_UART_CTL_UseParity_SHIFT 1 - -/* ARM_UART :: CTL :: UartEna [00:00] */ -#define BCHP_ARM_UART_CTL_UartEna_MASK 0x00000001 -#define BCHP_ARM_UART_CTL_UartEna_SHIFT 0 - -/*************************************************************************** - *STATUS - Status register - ***************************************************************************/ -/* ARM_UART :: STATUS :: reserved0 [31:05] */ -#define BCHP_ARM_UART_STATUS_reserved0_MASK 0xffffffe0 -#define BCHP_ARM_UART_STATUS_reserved0_SHIFT 5 - -/* ARM_UART :: STATUS :: XmitOverflow [04:04] */ -#define BCHP_ARM_UART_STATUS_XmitOverflow_MASK 0x00000010 -#define BCHP_ARM_UART_STATUS_XmitOverflow_SHIFT 4 - -/* ARM_UART :: STATUS :: XmitActive [03:03] */ -#define BCHP_ARM_UART_STATUS_XmitActive_MASK 0x00000008 -#define BCHP_ARM_UART_STATUS_XmitActive_SHIFT 3 - -/* ARM_UART :: STATUS :: RcvOverflow [02:02] */ -#define BCHP_ARM_UART_STATUS_RcvOverflow_MASK 0x00000004 -#define BCHP_ARM_UART_STATUS_RcvOverflow_SHIFT 2 - -/* ARM_UART :: STATUS :: reserved1 [01:01] */ -#define BCHP_ARM_UART_STATUS_reserved1_MASK 0x00000002 -#define BCHP_ARM_UART_STATUS_reserved1_SHIFT 1 - -/* ARM_UART :: STATUS :: RcvFifoEmpty [00:00] */ -#define BCHP_ARM_UART_STATUS_RcvFifoEmpty_MASK 0x00000001 -#define BCHP_ARM_UART_STATUS_RcvFifoEmpty_SHIFT 0 - -#endif /* #ifndef BCHP_ARM_UART_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_block_avg_regs_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_block_avg_regs_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_block_avg_regs_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_block_avg_regs_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,206 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_avd_block_avg_regs_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:56p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:49 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_block_avg_regs_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:56p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_AVD_BLOCK_AVG_REGS_0_H__ -#define BCHP_AVD_BLOCK_AVG_REGS_0_H__ - -/*************************************************************************** - *AVD_BLOCK_AVG_REGS_0 - FGT Block Avg Registers 0 - ***************************************************************************/ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_8x8_AVG_BASE_ADDR 0x00861000 /* REG_8x8_AVG_BASE_ADDR */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_4x8_SUM_BASE_ADDR 0x00861004 /* REG_4x8_SUM_BASE_ADDR */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL 0x00861008 /* REG_AVG_CTL */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM 0x0086100c /* REG_IMAGE_PARAM */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR 0x00861010 /* REG_AVG_ERR */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE 0x00861014 /* REG_AVG_DONE */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET 0x00861018 /* REG_AVG_RESET */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP 0x0086101c /* REG_VC1_RRMAP */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_BLOCK_AVG_END 0x0086103c /* REG_BLOCK_AVG_END */ - -/*************************************************************************** - *REG_8x8_AVG_BASE_ADDR - REG_8x8_AVG_BASE_ADDR - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_8x8_AVG_BASE_ADDR :: Value [31:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_8x8_AVG_BASE_ADDR_Value_MASK 0xffffffff -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_8x8_AVG_BASE_ADDR_Value_SHIFT 0 - -/*************************************************************************** - *REG_4x8_SUM_BASE_ADDR - REG_4x8_SUM_BASE_ADDR - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_4x8_SUM_BASE_ADDR :: Value [31:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_4x8_SUM_BASE_ADDR_Value_MASK 0xffffffff -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_4x8_SUM_BASE_ADDR_Value_SHIFT 0 - -/*************************************************************************** - *REG_AVG_CTL - REG_AVG_CTL - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: reserved0 [31:09] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_reserved0_MASK 0xfffffe00 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_reserved0_SHIFT 9 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Enable_stall [08:08] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_stall_MASK 0x00000100 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_stall_SHIFT 8 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Debug [07:07] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Debug_MASK 0x00000080 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Debug_SHIFT 7 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Enable [06:06] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_MASK 0x00000040 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_SHIFT 6 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Monochrome [05:05] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Monochrome_MASK 0x00000020 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Monochrome_SHIFT 5 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: VC1_Interlace [04:04] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_VC1_Interlace_MASK 0x00000010 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_VC1_Interlace_SHIFT 4 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: MBAFF [03:03] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_MBAFF_MASK 0x00000008 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_MBAFF_SHIFT 3 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Frame [02:02] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Frame_MASK 0x00000004 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Frame_SHIFT 2 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Standard [01:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Standard_MASK 0x00000003 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Standard_SHIFT 0 - -/*************************************************************************** - *REG_IMAGE_PARAM - REG_IMAGE_PARAM - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_IMAGE_PARAM :: Image_Width [31:16] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Width_MASK 0xffff0000 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Width_SHIFT 16 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_IMAGE_PARAM :: Image_Height [15:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Height_MASK 0x0000ffff -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Height_SHIFT 0 - -/*************************************************************************** - *REG_AVG_ERR - REG_AVG_ERR - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_ERR :: reserved0 [31:01] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_reserved0_MASK 0xfffffffe -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_reserved0_SHIFT 1 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_ERR :: Overflow_error [00:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_Overflow_error_MASK 0x00000001 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_Overflow_error_SHIFT 0 - -/*************************************************************************** - *REG_AVG_DONE - REG_AVG_DONE - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_DONE :: reserved0 [31:01] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_reserved0_MASK 0xfffffffe -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_reserved0_SHIFT 1 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_DONE :: Average_done [00:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_Average_done_MASK 0x00000001 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_Average_done_SHIFT 0 - -/*************************************************************************** - *REG_AVG_RESET - REG_AVG_RESET - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_RESET :: reserved0 [31:01] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_reserved0_MASK 0xfffffffe -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_reserved0_SHIFT 1 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_RESET :: Reset [00:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_Reset_MASK 0x00000001 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_Reset_SHIFT 0 - -/*************************************************************************** - *REG_VC1_RRMAP - REG_VC1_RRMAP - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: VC1_main [31:31] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_VC1_main_MASK 0x80000000 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_VC1_main_SHIFT 31 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: reserved0 [30:16] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved0_MASK 0x7fff0000 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved0_SHIFT 16 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Luma_range_en [15:15] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_en_MASK 0x00008000 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_en_SHIFT 15 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: reserved1 [14:11] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved1_MASK 0x00007800 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved1_SHIFT 11 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Luma_range [10:08] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_MASK 0x00000700 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_SHIFT 8 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Chroma_range_en [07:07] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_en_MASK 0x00000080 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_en_SHIFT 7 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: reserved2 [06:03] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved2_MASK 0x00000078 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved2_SHIFT 3 - -/* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Chroma_range [02:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_MASK 0x00000007 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_SHIFT 0 - -/*************************************************************************** - *REG_BLOCK_AVG_END - REG_BLOCK_AVG_END - ***************************************************************************/ -/* AVD_BLOCK_AVG_REGS_0 :: REG_BLOCK_AVG_END :: reserved0 [31:00] */ -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_BLOCK_AVG_END_reserved0_MASK 0xffffffff -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_BLOCK_AVG_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_AVD_BLOCK_AVG_REGS_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_cache_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_cache_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_cache_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_cache_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,262 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_avd_cache_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:56p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:03 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_cache_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:56p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_AVD_CACHE_0_H__ -#define BCHP_AVD_CACHE_0_H__ - -/*************************************************************************** - *AVD_CACHE_0 - Mocomp Cache Registers 0 - ***************************************************************************/ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0 0x00862000 /* REG_PCACHE_MODE0 */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1 0x00862004 /* REG_PCACHE_MODE1 */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL 0x00862008 /* REG_PCACHE_CTRL */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_HIT_COUNT 0x0086200c /* REG_PCACHE_HIT_COUNT */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MISS_COUNT 0x00862010 /* REG_PCACHE_MISS_COUNT */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MISS1_COUNT 0x00862014 /* REG_PCACHE_MISS1_COUNT */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_BLOCK_FLAGS 0x00862018 /* REG_PCACHE_BLOCK_FLAGS */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DATA 0x0086201c /* REG_PCACHE_DATA */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS 0x00862020 /* REG_PCACHE_TAG_CONTENTS */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT 0x00862024 /* REG_PCACHE_FLAG_SELECT */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL 0x00862028 /* REG_PCACHE_DEBUG_CTRL */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_LFSR_DATA 0x0086202c /* REG_PCACHE_LFSR_DATA */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_END 0x0086203c /* REG_PCACHE_END */ - -/*************************************************************************** - *REG_PCACHE_MODE0 - REG_PCACHE_MODE0 - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: reserved0 [31:06] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_reserved0_MASK 0xffffffc0 -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_reserved0_SHIFT 6 - -/* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Bypass [05:05] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Bypass_MASK 0x00000020 -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Bypass_SHIFT 5 - -/* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Disable [04:04] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Disable_MASK 0x00000010 -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Disable_SHIFT 4 - -/* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Ygran [03:02] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Ygran_MASK 0x0000000c -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Ygran_SHIFT 2 - -/* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Xgran [01:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Xgran_MASK 0x00000003 -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Xgran_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_MODE1 - REG_PCACHE_MODE1 - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_MODE1 :: reserved0 [31:01] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_reserved0_MASK 0xfffffffe -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_reserved0_SHIFT 1 - -/* AVD_CACHE_0 :: REG_PCACHE_MODE1 :: Mbaff_disable [00:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_Mbaff_disable_MASK 0x00000001 -#define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_Mbaff_disable_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_CTRL - REG_PCACHE_CTRL - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_CTRL :: reserved0 [31:03] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_reserved0_MASK 0xfffffff8 -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_reserved0_SHIFT 3 - -/* AVD_CACHE_0 :: REG_PCACHE_CTRL :: soft_reset [02:02] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_soft_reset_MASK 0x00000004 -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_soft_reset_SHIFT 2 - -/* AVD_CACHE_0 :: REG_PCACHE_CTRL :: Counter_reset [01:01] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Counter_reset_MASK 0x00000002 -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Counter_reset_SHIFT 1 - -/* AVD_CACHE_0 :: REG_PCACHE_CTRL :: Flush [00:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Flush_MASK 0x00000001 -#define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Flush_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_HIT_COUNT - REG_PCACHE_HIT_COUNT - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_HIT_COUNT :: hit_count [31:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_HIT_COUNT_hit_count_MASK 0xffffffff -#define BCHP_AVD_CACHE_0_REG_PCACHE_HIT_COUNT_hit_count_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_MISS_COUNT - REG_PCACHE_MISS_COUNT - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_MISS_COUNT :: miss_count [31:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MISS_COUNT_miss_count_MASK 0xffffffff -#define BCHP_AVD_CACHE_0_REG_PCACHE_MISS_COUNT_miss_count_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_MISS1_COUNT - REG_PCACHE_MISS1_COUNT - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_MISS1_COUNT :: miss1_count [31:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_MISS1_COUNT_miss1_count_MASK 0xffffffff -#define BCHP_AVD_CACHE_0_REG_PCACHE_MISS1_COUNT_miss1_count_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_BLOCK_FLAGS - REG_PCACHE_BLOCK_FLAGS - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_BLOCK_FLAGS :: block_flags [31:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_BLOCK_FLAGS_block_flags_MASK 0xffffffff -#define BCHP_AVD_CACHE_0_REG_PCACHE_BLOCK_FLAGS_block_flags_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_DATA - REG_PCACHE_DATA - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_DATA :: data_word [31:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DATA_data_word_MASK 0xffffffff -#define BCHP_AVD_CACHE_0_REG_PCACHE_DATA_data_word_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_TAG_CONTENTS - REG_PCACHE_TAG_CONTENTS - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved0 [31:25] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved0_MASK 0xfe000000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved0_SHIFT 25 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Valid [24:24] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Valid_MASK 0x01000000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Valid_SHIFT 24 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Picture_Base_ID [23:20] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Picture_Base_ID_MASK 0x00f00000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Picture_Base_ID_SHIFT 20 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved1 [19:18] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved1_MASK 0x000c0000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved1_SHIFT 18 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Component [17:17] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Component_MASK 0x00020000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Component_SHIFT 17 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Field_Frame [16:16] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Field_Frame_MASK 0x00010000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Field_Frame_SHIFT 16 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved2 [15:14] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved2_MASK 0x0000c000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved2_SHIFT 14 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: X_origin [13:08] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_X_origin_MASK 0x00003f00 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_X_origin_SHIFT 8 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved3 [07:06] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved3_MASK 0x000000c0 -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved3_SHIFT 6 - -/* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Y_origin [05:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Y_origin_MASK 0x0000003f -#define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Y_origin_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_FLAG_SELECT - REG_PCACHE_FLAG_SELECT - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: reserved0 [31:16] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved0_MASK 0xffff0000 -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved0_SHIFT 16 - -/* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: Index [15:08] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Index_MASK 0x0000ff00 -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Index_SHIFT 8 - -/* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: reserved1 [07:06] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved1_MASK 0x000000c0 -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved1_SHIFT 6 - -/* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: Sub_block [05:04] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Sub_block_MASK 0x00000030 -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Sub_block_SHIFT 4 - -/* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: blk [03:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_blk_MASK 0x0000000f -#define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_blk_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_DEBUG_CTRL - REG_PCACHE_DEBUG_CTRL - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: reserved0 [31:04] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_reserved0_MASK 0xfffffff0 -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_reserved0_SHIFT 4 - -/* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_fixed [03:03] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_fixed_MASK 0x00000008 -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_fixed_SHIFT 3 - -/* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_cmds [02:02] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_cmds_MASK 0x00000004 -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_cmds_SHIFT 2 - -/* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_qpel_fifo [01:01] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_qpel_fifo_MASK 0x00000002 -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_qpel_fifo_SHIFT 1 - -/* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_mctrl [00:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_mctrl_MASK 0x00000001 -#define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_mctrl_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_LFSR_DATA - REG_PCACHE_LFSR_DATA - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_LFSR_DATA :: data_word [31:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_LFSR_DATA_data_word_MASK 0xffffffff -#define BCHP_AVD_CACHE_0_REG_PCACHE_LFSR_DATA_data_word_SHIFT 0 - -/*************************************************************************** - *REG_PCACHE_END - REG_PCACHE_END - ***************************************************************************/ -/* AVD_CACHE_0 :: REG_PCACHE_END :: reserved0 [31:00] */ -#define BCHP_AVD_CACHE_0_REG_PCACHE_END_reserved0_MASK 0xffffffff -#define BCHP_AVD_CACHE_0_REG_PCACHE_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_AVD_CACHE_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,104 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_avd_gr_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:56p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:03 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:56p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_AVD_GR_0_H__ -#define BCHP_AVD_GR_0_H__ - -/*************************************************************************** - *AVD_GR_0 - ***************************************************************************/ -#define BCHP_AVD_GR_0_REVISION 0x00900400 /* GR Bridge Revision */ -#define BCHP_AVD_GR_0_CTRL 0x00900404 /* GR Bridge Control Register */ -#define BCHP_AVD_GR_0_SW_RESET_0 0x00900408 /* GR Bridge Software Reset 0 Register */ -#define BCHP_AVD_GR_0_SW_RESET_1 0x0090040c /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* AVD_GR_0 :: REVISION :: reserved0 [31:16] */ -#define BCHP_AVD_GR_0_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_AVD_GR_0_REVISION_reserved0_SHIFT 16 - -/* AVD_GR_0 :: REVISION :: MAJOR [15:08] */ -#define BCHP_AVD_GR_0_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_AVD_GR_0_REVISION_MAJOR_SHIFT 8 - -/* AVD_GR_0 :: REVISION :: MINOR [07:00] */ -#define BCHP_AVD_GR_0_REVISION_MINOR_MASK 0x000000ff -#define BCHP_AVD_GR_0_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* AVD_GR_0 :: CTRL :: reserved0 [31:01] */ -#define BCHP_AVD_GR_0_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_AVD_GR_0_CTRL_reserved0_SHIFT 1 - -/* AVD_GR_0 :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_AVD_GR_0_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_AVD_GR_0_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_AVD_GR_0_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_AVD_GR_0_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* AVD_GR_0 :: SW_RESET_0 :: reserved0 [31:00] */ -#define BCHP_AVD_GR_0_SW_RESET_0_reserved0_MASK 0xffffffff -#define BCHP_AVD_GR_0_SW_RESET_0_reserved0_SHIFT 0 - -/*************************************************************************** - *SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* AVD_GR_0 :: SW_RESET_1 :: reserved0 [31:00] */ -#define BCHP_AVD_GR_0_SW_RESET_1_reserved0_MASK 0xffffffff -#define BCHP_AVD_GR_0_SW_RESET_1_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_AVD_GR_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1258 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_avd_intr2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:57p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:50 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:57p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_AVD_INTR2_0_H__ -#define BCHP_AVD_INTR2_0_H__ - -/*************************************************************************** - *AVD_INTR2_0 - ***************************************************************************/ -#define BCHP_AVD_INTR2_0_CPU_STATUS 0x00900000 /* CPU interrupt Status Register */ -#define BCHP_AVD_INTR2_0_CPU_SET 0x00900004 /* CPU interrupt Set Register */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR 0x00900008 /* CPU interrupt Clear Register */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS 0x0090000c /* CPU interrupt Mask Status Register */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET 0x00900010 /* CPU interrupt Mask Set Register */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR 0x00900014 /* CPU interrupt Mask Clear Register */ -#define BCHP_AVD_INTR2_0_PCI_STATUS 0x00900018 /* PCI interrupt Status Register */ -#define BCHP_AVD_INTR2_0_PCI_SET 0x0090001c /* PCI interrupt Set Register */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR 0x00900020 /* PCI interrupt Clear Register */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS 0x00900024 /* PCI interrupt Mask Status Register */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET 0x00900028 /* PCI interrupt Mask Set Register */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR 0x0090002c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: CPU_STATUS :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: CPU_STATUS :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: CPU_STATUS :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: CPU_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: CPU_SET :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_CPU_SET_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_CPU_SET_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: CPU_SET :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_CPU_SET_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_CPU_SET_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: CPU_SET :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_CPU_SET_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_CPU_SET_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: CPU_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: CPU_CLEAR :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: CPU_CLEAR :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: CPU_CLEAR :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: PCI_STATUS :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: PCI_STATUS :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: PCI_STATUS :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: PCI_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: PCI_SET :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_PCI_SET_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_PCI_SET_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: PCI_SET :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_PCI_SET_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_PCI_SET_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: PCI_SET :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_PCI_SET_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_PCI_SET_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: PCI_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: PCI_CLEAR :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: PCI_CLEAR :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: PCI_CLEAR :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR15 [31:31] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR15_MASK 0x80000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR15_SHIFT 31 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR14 [30:30] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR14_MASK 0x40000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR14_SHIFT 30 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR13 [29:29] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR13_MASK 0x20000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR13_SHIFT 29 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR12 [28:28] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR12_MASK 0x10000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR12_SHIFT 28 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR11 [27:27] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR11_MASK 0x08000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR11_SHIFT 27 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR10 [26:26] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR10_MASK 0x04000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR10_SHIFT 26 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR9 [25:25] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR9_MASK 0x02000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR9_SHIFT 25 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR8 [24:24] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR8_MASK 0x01000000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR8_SHIFT 24 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR7 [23:23] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR7_MASK 0x00800000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR7_SHIFT 23 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR6 [22:22] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR6_MASK 0x00400000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR6_SHIFT 22 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR5 [21:21] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR5_MASK 0x00200000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR5_SHIFT 21 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR4 [20:20] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR4_MASK 0x00100000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR4_SHIFT 20 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR3 [19:19] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR3_MASK 0x00080000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR3_SHIFT 19 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR2 [18:18] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR2_MASK 0x00040000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR2_SHIFT 18 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR1 [17:17] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR1_MASK 0x00020000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR1_SHIFT 17 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR0 [16:16] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR0_MASK 0x00010000 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR0_SHIFT 16 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_REG_INTR [05:05] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_REG_INTR_MASK 0x00000020 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_REG_INTR_SHIFT 5 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_SCB_WR_INTR [04:04] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_PFRI_INTR [03:03] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_PFRI_INTR_SHIFT 3 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_MBOX_INTR [02:02] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_MBOX_INTR_SHIFT 2 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_INST_RD_INTR [01:01] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_INST_RD_INTR_SHIFT 1 - -/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 -#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 - -#endif /* #ifndef BCHP_AVD_INTR2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_aes.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_aes.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_aes.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_aes.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,210 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_bop_aes.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:57p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:05 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bop_aes.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:57p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_BOP_AES_H__ -#define BCHP_BOP_AES_H__ - -/*************************************************************************** - *BOP_AES - BOP Top Control Registers - ***************************************************************************/ -#define BCHP_BOP_AES_CTRL 0x00510000 /* AES Control Register */ -#define BCHP_BOP_AES_SCRAMBLE_SETUP 0x00510004 /* AES Scramble Setup Register */ -#define BCHP_BOP_AES_ENCRYPTION_SETUP 0x00510008 /* AES Encryption Setup Register */ -#define BCHP_BOP_AES_STATUS 0x0051000c /* AES Status Register */ -#define BCHP_BOP_AES_SCRAMBLE_NONCE0 0x00510010 /* AES Scramble Nonce Register0 */ -#define BCHP_BOP_AES_SCRAMBLE_NONCE1 0x00510014 /* AES Scramble Nonce Register1 */ -#define BCHP_BOP_AES_INITIAL_VECTOR0 0x00510018 /* AES Initial Vector Register0 */ -#define BCHP_BOP_AES_INITIAL_VECTOR1 0x0051001c /* AES Initial Vector Register1 */ -#define BCHP_BOP_AES_INITIAL_VECTOR2 0x00510020 /* AES Initial Vector Register2 */ -#define BCHP_BOP_AES_INITIAL_VECTOR3 0x00510024 /* AES Initial Vector Register3 */ -#define BCHP_BOP_AES_INITIAL_COUNTER0 0x00510028 /* AES Initial Counter Register0 */ -#define BCHP_BOP_AES_INITIAL_COUNTER1 0x0051002c /* AES Initial Counter Register1 */ -#define BCHP_BOP_AES_INITIAL_COUNTER2 0x00510030 /* AES Initial Counter Register2 */ -#define BCHP_BOP_AES_INITIAL_COUNTER3 0x00510034 /* AES Initial Counter Register3 */ - -/*************************************************************************** - *CTRL - AES Control Register - ***************************************************************************/ -/* BOP_AES :: CTRL :: reserved0 [31:11] */ -#define BCHP_BOP_AES_CTRL_reserved0_MASK 0xfffff800 -#define BCHP_BOP_AES_CTRL_reserved0_SHIFT 11 - -/* BOP_AES :: CTRL :: SCRAMBLE_MODE [10:10] */ -#define BCHP_BOP_AES_CTRL_SCRAMBLE_MODE_MASK 0x00000400 -#define BCHP_BOP_AES_CTRL_SCRAMBLE_MODE_SHIFT 10 - -/* BOP_AES :: CTRL :: ENCRYPTION_MODE [09:08] */ -#define BCHP_BOP_AES_CTRL_ENCRYPTION_MODE_MASK 0x00000300 -#define BCHP_BOP_AES_CTRL_ENCRYPTION_MODE_SHIFT 8 - -/* BOP_AES :: CTRL :: reserved1 [07:05] */ -#define BCHP_BOP_AES_CTRL_reserved1_MASK 0x000000e0 -#define BCHP_BOP_AES_CTRL_reserved1_SHIFT 5 - -/* BOP_AES :: CTRL :: SWAP [04:04] */ -#define BCHP_BOP_AES_CTRL_SWAP_MASK 0x00000010 -#define BCHP_BOP_AES_CTRL_SWAP_SHIFT 4 - -/* BOP_AES :: CTRL :: reserved2 [03:01] */ -#define BCHP_BOP_AES_CTRL_reserved2_MASK 0x0000000e -#define BCHP_BOP_AES_CTRL_reserved2_SHIFT 1 - -/* BOP_AES :: CTRL :: START_ENCRYPTION_SCRAMBLE [00:00] */ -#define BCHP_BOP_AES_CTRL_START_ENCRYPTION_SCRAMBLE_MASK 0x00000001 -#define BCHP_BOP_AES_CTRL_START_ENCRYPTION_SCRAMBLE_SHIFT 0 - -/*************************************************************************** - *SCRAMBLE_SETUP - AES Scramble Setup Register - ***************************************************************************/ -/* BOP_AES :: SCRAMBLE_SETUP :: Length [31:16] */ -#define BCHP_BOP_AES_SCRAMBLE_SETUP_Length_MASK 0xffff0000 -#define BCHP_BOP_AES_SCRAMBLE_SETUP_Length_SHIFT 16 - -/* BOP_AES :: SCRAMBLE_SETUP :: OFFSET [15:00] */ -#define BCHP_BOP_AES_SCRAMBLE_SETUP_OFFSET_MASK 0x0000ffff -#define BCHP_BOP_AES_SCRAMBLE_SETUP_OFFSET_SHIFT 0 - -/*************************************************************************** - *ENCRYPTION_SETUP - AES Encryption Setup Register - ***************************************************************************/ -/* BOP_AES :: ENCRYPTION_SETUP :: Length [31:16] */ -#define BCHP_BOP_AES_ENCRYPTION_SETUP_Length_MASK 0xffff0000 -#define BCHP_BOP_AES_ENCRYPTION_SETUP_Length_SHIFT 16 - -/* BOP_AES :: ENCRYPTION_SETUP :: OFFSET [15:00] */ -#define BCHP_BOP_AES_ENCRYPTION_SETUP_OFFSET_MASK 0x0000ffff -#define BCHP_BOP_AES_ENCRYPTION_SETUP_OFFSET_SHIFT 0 - -/*************************************************************************** - *STATUS - AES Status Register - ***************************************************************************/ -/* BOP_AES :: STATUS :: reserved0 [31:04] */ -#define BCHP_BOP_AES_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_BOP_AES_STATUS_reserved0_SHIFT 4 - -/* BOP_AES :: STATUS :: SCRAMBLE_KEY_NUMBER_IN_USE [03:02] */ -#define BCHP_BOP_AES_STATUS_SCRAMBLE_KEY_NUMBER_IN_USE_MASK 0x0000000c -#define BCHP_BOP_AES_STATUS_SCRAMBLE_KEY_NUMBER_IN_USE_SHIFT 2 - -/* BOP_AES :: STATUS :: ENCRYPTION_KEY_NUMBER_IN_USE [01:00] */ -#define BCHP_BOP_AES_STATUS_ENCRYPTION_KEY_NUMBER_IN_USE_MASK 0x00000003 -#define BCHP_BOP_AES_STATUS_ENCRYPTION_KEY_NUMBER_IN_USE_SHIFT 0 - -/*************************************************************************** - *SCRAMBLE_NONCE0 - AES Scramble Nonce Register0 - ***************************************************************************/ -/* BOP_AES :: SCRAMBLE_NONCE0 :: SCRAMBLE_NONCE [31:00] */ -#define BCHP_BOP_AES_SCRAMBLE_NONCE0_SCRAMBLE_NONCE_MASK 0xffffffff -#define BCHP_BOP_AES_SCRAMBLE_NONCE0_SCRAMBLE_NONCE_SHIFT 0 - -/*************************************************************************** - *SCRAMBLE_NONCE1 - AES Scramble Nonce Register1 - ***************************************************************************/ -/* BOP_AES :: SCRAMBLE_NONCE1 :: SCRAMBLE_NONCE [31:00] */ -#define BCHP_BOP_AES_SCRAMBLE_NONCE1_SCRAMBLE_NONCE_MASK 0xffffffff -#define BCHP_BOP_AES_SCRAMBLE_NONCE1_SCRAMBLE_NONCE_SHIFT 0 - -/*************************************************************************** - *INITIAL_VECTOR0 - AES Initial Vector Register0 - ***************************************************************************/ -/* BOP_AES :: INITIAL_VECTOR0 :: INITIAL_VECTOR [31:00] */ -#define BCHP_BOP_AES_INITIAL_VECTOR0_INITIAL_VECTOR_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_VECTOR0_INITIAL_VECTOR_SHIFT 0 - -/*************************************************************************** - *INITIAL_VECTOR1 - AES Initial Vector Register1 - ***************************************************************************/ -/* BOP_AES :: INITIAL_VECTOR1 :: INITIAL_VECTOR [31:00] */ -#define BCHP_BOP_AES_INITIAL_VECTOR1_INITIAL_VECTOR_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_VECTOR1_INITIAL_VECTOR_SHIFT 0 - -/*************************************************************************** - *INITIAL_VECTOR2 - AES Initial Vector Register2 - ***************************************************************************/ -/* BOP_AES :: INITIAL_VECTOR2 :: INITIAL_VECTOR [31:00] */ -#define BCHP_BOP_AES_INITIAL_VECTOR2_INITIAL_VECTOR_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_VECTOR2_INITIAL_VECTOR_SHIFT 0 - -/*************************************************************************** - *INITIAL_VECTOR3 - AES Initial Vector Register3 - ***************************************************************************/ -/* BOP_AES :: INITIAL_VECTOR3 :: INITIAL_VECTOR [31:00] */ -#define BCHP_BOP_AES_INITIAL_VECTOR3_INITIAL_VECTOR_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_VECTOR3_INITIAL_VECTOR_SHIFT 0 - -/*************************************************************************** - *INITIAL_COUNTER0 - AES Initial Counter Register0 - ***************************************************************************/ -/* BOP_AES :: INITIAL_COUNTER0 :: INITIAL_COUNTER [31:00] */ -#define BCHP_BOP_AES_INITIAL_COUNTER0_INITIAL_COUNTER_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_COUNTER0_INITIAL_COUNTER_SHIFT 0 - -/*************************************************************************** - *INITIAL_COUNTER1 - AES Initial Counter Register1 - ***************************************************************************/ -/* BOP_AES :: INITIAL_COUNTER1 :: INITIAL_COUNTER [31:00] */ -#define BCHP_BOP_AES_INITIAL_COUNTER1_INITIAL_COUNTER_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_COUNTER1_INITIAL_COUNTER_SHIFT 0 - -/*************************************************************************** - *INITIAL_COUNTER2 - AES Initial Counter Register2 - ***************************************************************************/ -/* BOP_AES :: INITIAL_COUNTER2 :: INITIAL_COUNTER [31:00] */ -#define BCHP_BOP_AES_INITIAL_COUNTER2_INITIAL_COUNTER_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_COUNTER2_INITIAL_COUNTER_SHIFT 0 - -/*************************************************************************** - *INITIAL_COUNTER3 - AES Initial Counter Register3 - ***************************************************************************/ -/* BOP_AES :: INITIAL_COUNTER3 :: INITIAL_COUNTER [31:00] */ -#define BCHP_BOP_AES_INITIAL_COUNTER3_INITIAL_COUNTER_MASK 0xffffffff -#define BCHP_BOP_AES_INITIAL_COUNTER3_INITIAL_COUNTER_SHIFT 0 - -#endif /* #ifndef BCHP_BOP_AES_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,116 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_bop_gr_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:57p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:55 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:57p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_BOP_GR_BRIDGE_H__ -#define BCHP_BOP_GR_BRIDGE_H__ - -/*************************************************************************** - *BOP_GR_BRIDGE - BOP GR Bridge Registers - ***************************************************************************/ -#define BCHP_BOP_GR_BRIDGE_REVISION 0x00511000 /* GR Bridge Revision */ -#define BCHP_BOP_GR_BRIDGE_CTRL 0x00511004 /* GR Bridge Control Register */ -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0 0x00511008 /* GR Bridge Software Reset 0 Register */ -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1 0x0051100c /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* BOP_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define BCHP_BOP_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_BOP_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* BOP_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define BCHP_BOP_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_BOP_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* BOP_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define BCHP_BOP_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define BCHP_BOP_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* BOP_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define BCHP_BOP_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_BOP_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* BOP_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* BOP_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* BOP_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - -/*************************************************************************** - *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* BOP_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* BOP_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - -#endif /* #ifndef BCHP_BOP_GR_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_gr_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_gr_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_gr_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_gr_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,116 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_bvnt_gr_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:57p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:06 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_gr_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:57p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_BVNT_GR_BRIDGE_H__ -#define BCHP_BVNT_GR_BRIDGE_H__ - -/*************************************************************************** - *BVNT_GR_BRIDGE - BVN GR Bridge Registers - ***************************************************************************/ -#define BCHP_BVNT_GR_BRIDGE_REVISION 0x00541800 /* GR Bridge Revision */ -#define BCHP_BVNT_GR_BRIDGE_CTRL 0x00541804 /* GR Bridge Control Register */ -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0 0x00541808 /* GR Bridge Software Reset 0 Register */ -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1 0x0054180c /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* BVNT_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define BCHP_BVNT_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_BVNT_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* BVNT_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define BCHP_BVNT_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_BVNT_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* BVNT_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define BCHP_BVNT_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define BCHP_BVNT_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* BVNT_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define BCHP_BVNT_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_BVNT_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* BVNT_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* BVNT_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* BVNT_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - -/*************************************************************************** - *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* BVNT_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* BVNT_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - -#endif /* #ifndef BCHP_BVNT_GR_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,586 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_bvnt_intr2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:57p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:21 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:57p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_BVNT_INTR2_H__ -#define BCHP_BVNT_INTR2_H__ - -/*************************************************************************** - *BVNT_INTR2 - BVN Interrupt Controller Registers - ***************************************************************************/ -#define BCHP_BVNT_INTR2_CPU_STATUS 0x00541200 /* CPU interrupt Status Register */ -#define BCHP_BVNT_INTR2_CPU_SET 0x00541204 /* CPU interrupt Set Register */ -#define BCHP_BVNT_INTR2_CPU_CLEAR 0x00541208 /* CPU interrupt Clear Register */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS 0x0054120c /* CPU interrupt Mask Status Register */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET 0x00541210 /* CPU interrupt Mask Set Register */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR 0x00541214 /* CPU interrupt Mask Clear Register */ -#define BCHP_BVNT_INTR2_PCI_STATUS 0x00541218 /* PCI interrupt Status Register */ -#define BCHP_BVNT_INTR2_PCI_SET 0x0054121c /* PCI interrupt Set Register */ -#define BCHP_BVNT_INTR2_PCI_CLEAR 0x00541220 /* PCI interrupt Clear Register */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS 0x00541224 /* PCI interrupt Mask Status Register */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET 0x00541228 /* PCI interrupt Mask Set Register */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR 0x0054122c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* BVNT_INTR2 :: CPU_STATUS :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_CPU_STATUS_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: CPU_STATUS :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_CPU_STATUS_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: CPU_STATUS :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_CPU_STATUS_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: CPU_STATUS :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_CPU_STATUS_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: CPU_STATUS :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_CPU_STATUS_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: CPU_STATUS :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_CPU_STATUS_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: CPU_STATUS :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_CPU_STATUS_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: CPU_STATUS :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_CPU_STATUS_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: CPU_STATUS :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_CPU_STATUS_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: CPU_STATUS :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_CPU_STATUS_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_CPU_STATUS_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* BVNT_INTR2 :: CPU_SET :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_CPU_SET_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_CPU_SET_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: CPU_SET :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_CPU_SET_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_CPU_SET_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: CPU_SET :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_CPU_SET_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_CPU_SET_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: CPU_SET :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_CPU_SET_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_CPU_SET_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: CPU_SET :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_CPU_SET_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_CPU_SET_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: CPU_SET :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_CPU_SET_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_CPU_SET_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: CPU_SET :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_CPU_SET_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_CPU_SET_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: CPU_SET :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_CPU_SET_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_CPU_SET_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: CPU_SET :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_CPU_SET_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_CPU_SET_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: CPU_SET :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_CPU_SET_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_CPU_SET_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* BVNT_INTR2 :: CPU_CLEAR :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_CPU_CLEAR_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: CPU_CLEAR :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_CPU_CLEAR_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: CPU_CLEAR :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_CPU_CLEAR_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: CPU_CLEAR :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_CPU_CLEAR_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: CPU_CLEAR :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_CPU_CLEAR_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: CPU_CLEAR :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_CPU_CLEAR_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: CPU_CLEAR :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_CPU_CLEAR_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: CPU_CLEAR :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_CPU_CLEAR_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: CPU_CLEAR :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_CPU_CLEAR_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: CPU_CLEAR :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_CPU_CLEAR_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_CPU_CLEAR_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* BVNT_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: CPU_MASK_STATUS :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* BVNT_INTR2 :: CPU_MASK_SET :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: CPU_MASK_SET :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: CPU_MASK_SET :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: CPU_MASK_SET :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: CPU_MASK_SET :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: CPU_MASK_SET :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: CPU_MASK_SET :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: CPU_MASK_SET :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: CPU_MASK_SET :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: CPU_MASK_SET :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_CPU_MASK_SET_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_CPU_MASK_SET_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: CPU_MASK_CLEAR :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* BVNT_INTR2 :: PCI_STATUS :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_PCI_STATUS_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: PCI_STATUS :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_PCI_STATUS_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: PCI_STATUS :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_PCI_STATUS_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: PCI_STATUS :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_PCI_STATUS_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: PCI_STATUS :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_PCI_STATUS_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: PCI_STATUS :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_PCI_STATUS_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: PCI_STATUS :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_PCI_STATUS_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: PCI_STATUS :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_PCI_STATUS_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: PCI_STATUS :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_PCI_STATUS_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: PCI_STATUS :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_PCI_STATUS_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_PCI_STATUS_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* BVNT_INTR2 :: PCI_SET :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_PCI_SET_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_PCI_SET_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: PCI_SET :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_PCI_SET_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_PCI_SET_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: PCI_SET :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_PCI_SET_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_PCI_SET_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: PCI_SET :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_PCI_SET_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_PCI_SET_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: PCI_SET :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_PCI_SET_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_PCI_SET_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: PCI_SET :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_PCI_SET_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_PCI_SET_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: PCI_SET :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_PCI_SET_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_PCI_SET_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: PCI_SET :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_PCI_SET_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_PCI_SET_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: PCI_SET :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_PCI_SET_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_PCI_SET_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: PCI_SET :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_PCI_SET_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_PCI_SET_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* BVNT_INTR2 :: PCI_CLEAR :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_PCI_CLEAR_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: PCI_CLEAR :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_PCI_CLEAR_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: PCI_CLEAR :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_PCI_CLEAR_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: PCI_CLEAR :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_PCI_CLEAR_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: PCI_CLEAR :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_PCI_CLEAR_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: PCI_CLEAR :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_PCI_CLEAR_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: PCI_CLEAR :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_PCI_CLEAR_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: PCI_CLEAR :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_PCI_CLEAR_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: PCI_CLEAR :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_PCI_CLEAR_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: PCI_CLEAR :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_PCI_CLEAR_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_PCI_CLEAR_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* BVNT_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: PCI_MASK_STATUS :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* BVNT_INTR2 :: PCI_MASK_SET :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: PCI_MASK_SET :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: PCI_MASK_SET :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: PCI_MASK_SET :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: PCI_MASK_SET :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: PCI_MASK_SET :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: PCI_MASK_SET :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: PCI_MASK_SET :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: PCI_MASK_SET :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: PCI_MASK_SET :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_PCI_MASK_SET_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_PCI_MASK_SET_MFD_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:09] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 9 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: BOP_EOF_INTR [08:08] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BOP_EOF_INTR_MASK 0x00000100 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BOP_EOF_INTR_SHIFT 8 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: BVN_EOF_INTR [07:07] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BVN_EOF_INTR_MASK 0x00000080 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BVN_EOF_INTR_SHIFT 7 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: METADMA_INTR [06:06] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_METADMA_INTR_MASK 0x00000040 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_METADMA_INTR_SHIFT 6 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: RXDMA3_INTR [05:05] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_RXDMA3_INTR_MASK 0x00000020 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_RXDMA3_INTR_SHIFT 5 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: TXDMA_INTR [04:04] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_TXDMA_INTR_MASK 0x00000010 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_TXDMA_INTR_SHIFT 4 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: SCL_INTR [03:03] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_SCL_INTR_MASK 0x00000008 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_SCL_INTR_SHIFT 3 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: DNR_INTR [02:02] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_DNR_INTR_MASK 0x00000004 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_DNR_INTR_SHIFT 2 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: EOF_INTR [01:01] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_EOF_INTR_MASK 0x00000002 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_EOF_INTR_SHIFT 1 - -/* BVNT_INTR2 :: PCI_MASK_CLEAR :: MFD_INTR [00:00] */ -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_MFD_INTR_MASK 0x00000001 -#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_MFD_INTR_SHIFT 0 - -#endif /* #ifndef BCHP_BVNT_INTR2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,134 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_cce_rgr_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:58p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:58 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:58p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_CCE_RGR_BRIDGE_H__ -#define BCHP_CCE_RGR_BRIDGE_H__ - -/*************************************************************************** - *CCE_RGR_BRIDGE - CCE RGR-bridge related registers - ***************************************************************************/ -#define BCHP_CCE_RGR_BRIDGE_REVISION 0x005033e0 /* RGR Bridge Revision */ -#define BCHP_CCE_RGR_BRIDGE_CTRL 0x005033e4 /* RGR Bridge Control Register */ -#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER 0x005033e8 /* RGR Bridge RBUS Timer Register */ -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x005033ec /* RGR Bridge Software Reset 0 Register */ -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x005033f0 /* RGR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - RGR Bridge Revision - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define BCHP_CCE_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define BCHP_CCE_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define BCHP_CCE_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define BCHP_CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - RGR Bridge Control Register - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ -#define BCHP_CCE_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 - -/* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ -#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 -#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 -#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 -#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 - -/* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *RBUS_TIMER - RGR Bridge RBUS Timer Register - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ -#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 - -/* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ -#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff -#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 - -/*************************************************************************** - *SPARE_SW_RESET_0 - RGR Bridge Software Reset 0 Register - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - -/*************************************************************************** - *SPARE_SW_RESET_1 - RGR Bridge Software Reset 1 Register - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - -#endif /* #ifndef BCHP_CCE_RGR_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,104 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_clk_gr.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:58p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:15 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:58p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_CLK_GR_H__ -#define BCHP_CLK_GR_H__ - -/*************************************************************************** - *CLK_GR - Registers for the clock_gen block's GR bridge - ***************************************************************************/ -#define BCHP_CLK_GR_REVISION 0x00072000 /* GR Bridge Revision */ -#define BCHP_CLK_GR_CTRL 0x00072004 /* GR Bridge Control Register */ -#define BCHP_CLK_GR_SW_RESET_0 0x00072008 /* GR Bridge Software Reset 0 Register */ -#define BCHP_CLK_GR_SW_RESET_1 0x0007200c /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* CLK_GR :: REVISION :: reserved0 [31:16] */ -#define BCHP_CLK_GR_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_CLK_GR_REVISION_reserved0_SHIFT 16 - -/* CLK_GR :: REVISION :: MAJOR [15:08] */ -#define BCHP_CLK_GR_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_CLK_GR_REVISION_MAJOR_SHIFT 8 - -/* CLK_GR :: REVISION :: MINOR [07:00] */ -#define BCHP_CLK_GR_REVISION_MINOR_MASK 0x000000ff -#define BCHP_CLK_GR_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* CLK_GR :: CTRL :: reserved0 [31:01] */ -#define BCHP_CLK_GR_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_CLK_GR_CTRL_reserved0_SHIFT 1 - -/* CLK_GR :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_CLK_GR_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_CLK_GR_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_CLK_GR_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_CLK_GR_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* CLK_GR :: SW_RESET_0 :: reserved0 [31:00] */ -#define BCHP_CLK_GR_SW_RESET_0_reserved0_MASK 0xffffffff -#define BCHP_CLK_GR_SW_RESET_0_reserved0_SHIFT 0 - -/*************************************************************************** - *SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* CLK_GR :: SW_RESET_1 :: reserved0 [31:00] */ -#define BCHP_CLK_GR_SW_RESET_1_reserved0_MASK 0xffffffff -#define BCHP_CLK_GR_SW_RESET_1_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_CLK_GR_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,582 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_clk.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:58p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:39 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:58p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_CLK_H__ -#define BCHP_CLK_H__ - -/*************************************************************************** - *CLK - CLOCK_GEN Registers - ***************************************************************************/ -#define BCHP_CLK_REVISION 0x00070000 /* clock_gen Revision register */ -#define BCHP_CLK_PM_CTRL 0x00070004 /* Software power management control to turn off clocks */ -#define BCHP_CLK_REGULATOR_2P5_VOLTS 0x0007003c /* 2.5V Regulator Voltage Adjustment */ -#define BCHP_CLK_TEMP_MON_CTRL 0x00070040 /* Temperature monitor control. */ -#define BCHP_CLK_TEMP_MON_STATUS 0x00070044 /* Temperature monitor status. */ -#define BCHP_CLK_SCRATCH 0x00070070 /* clock_gen Scratch register */ -#define BCHP_CLK_PLL0_ARM_DIV 0x00070110 /* Main PLL0 channel 3 ARM clock divider settings */ -#define BCHP_CLK_PLL0_LOCK_CNT 0x0007011c /* Main PLL0 Lock Counter */ -#define BCHP_CLK_PLL1_CTRL 0x00070120 /* Main PLL1 reset, enable, powerdown, and control */ -#define BCHP_CLK_PLL1_CTRL_LO 0x00070124 /* Main PLL1 pll_ctrl low 32 bits */ -#define BCHP_CLK_PLL1_AVD_DIV 0x00070128 /* Main PLL1 divider settings for VCO and channel 1 AVD clock */ -#define BCHP_CLK_PLL1_SPARE2_DIV 0x0007012c /* Main PLL1 divider settings for channel 2 spare clock */ -#define BCHP_CLK_PLL1_SPARE3_DIV 0x00070130 /* Main PLL1 divider settings for channel 3 spare clock */ -#define BCHP_CLK_PLL1_LOCK_CNT 0x0007013c /* Main PLL1 Lock Counter */ -#define BCHP_CLK_PLL_LOCK 0x00070200 /* PLL lock status */ -#define BCHP_CLK_PLL_LOCK_CNTR_RESET 0x00070204 /* PLL Lock Counter Resets */ -#define BCHP_CLK_PLL_TEST_SEL 0x00070208 /* PLL core test select */ -#define BCHP_CLK_CLK_OBS_CTRL 0x0007020c /* Clock observation logic select */ -#define BCHP_CLK_GPIO_PAD_CTRL 0x00070300 /* GPIO pad control */ -#define BCHP_CLK_MISC_PAD_CTRL 0x00070304 /* MISC pad control */ - -/*************************************************************************** - *REVISION - clock_gen Revision register - ***************************************************************************/ -/* CLK :: REVISION :: reserved0 [31:16] */ -#define BCHP_CLK_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_CLK_REVISION_reserved0_SHIFT 16 - -/* CLK :: REVISION :: MAJOR [15:08] */ -#define BCHP_CLK_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_CLK_REVISION_MAJOR_SHIFT 8 - -/* CLK :: REVISION :: MINOR [07:00] */ -#define BCHP_CLK_REVISION_MINOR_MASK 0x000000ff -#define BCHP_CLK_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *PM_CTRL - Software power management control to turn off clocks - ***************************************************************************/ -/* CLK :: PM_CTRL :: reserved_for_eco0 [31:26] */ -#define BCHP_CLK_PM_CTRL_reserved_for_eco0_MASK 0xfc000000 -#define BCHP_CLK_PM_CTRL_reserved_for_eco0_SHIFT 26 - -/* CLK :: PM_CTRL :: DIS_SUN_27_LOW_PWR [25:25] */ -#define BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_MASK 0x02000000 -#define BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_SHIFT 25 - -/* CLK :: PM_CTRL :: DIS_SUN_108_LOW_PWR [24:24] */ -#define BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_MASK 0x01000000 -#define BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_SHIFT 24 - -/* CLK :: PM_CTRL :: reserved1 [23:20] */ -#define BCHP_CLK_PM_CTRL_reserved1_MASK 0x00f00000 -#define BCHP_CLK_PM_CTRL_reserved1_SHIFT 20 - -/* CLK :: PM_CTRL :: DIS_MISC_OTP_9_CLK [19:19] */ -#define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_MASK 0x00080000 -#define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_SHIFT 19 -#define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_ARM_CLK [18:18] */ -#define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK 0x00040000 -#define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_SHIFT 18 -#define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_AVD_CLK [17:17] */ -#define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK 0x00020000 -#define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_SHIFT 17 -#define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_Disable 1 - -/* CLK :: PM_CTRL :: reserved2 [16:13] */ -#define BCHP_CLK_PM_CTRL_reserved2_MASK 0x0001e000 -#define BCHP_CLK_PM_CTRL_reserved2_SHIFT 13 - -/* CLK :: PM_CTRL :: DIS_BLINK_108_CLK [12:12] */ -#define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK 0x00001000 -#define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_SHIFT 12 -#define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_DDR_108_CLK [11:11] */ -#define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK 0x00000800 -#define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_SHIFT 11 -#define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_AVD_108_CLK [10:10] */ -#define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK 0x00000400 -#define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_SHIFT 10 -#define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_MISC_108_CLK [09:09] */ -#define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_MASK 0x00000200 -#define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_SHIFT 9 -#define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_Disable 1 - -/* CLK :: PM_CTRL :: reserved3 [08:05] */ -#define BCHP_CLK_PM_CTRL_reserved3_MASK 0x000001e0 -#define BCHP_CLK_PM_CTRL_reserved3_SHIFT 5 - -/* CLK :: PM_CTRL :: DIS_BLINK_216_CLK [04:04] */ -#define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK 0x00000010 -#define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_SHIFT 4 -#define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_DDR_216_CLK [03:03] */ -#define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK 0x00000008 -#define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_SHIFT 3 -#define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_AVD_216_CLK [02:02] */ -#define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK 0x00000004 -#define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_SHIFT 2 -#define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_MISC_216_CLK [01:01] */ -#define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_MASK 0x00000002 -#define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_SHIFT 1 -#define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_Disable 1 - -/* CLK :: PM_CTRL :: DIS_SUN_216_CLK [00:00] */ -#define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_MASK 0x00000001 -#define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_SHIFT 0 -#define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_Enable 0 -#define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_Disable 1 - -/*************************************************************************** - *REGULATOR_2P5_VOLTS - 2.5V Regulator Voltage Adjustment - ***************************************************************************/ -/* CLK :: REGULATOR_2P5_VOLTS :: reserved0 [31:04] */ -#define BCHP_CLK_REGULATOR_2P5_VOLTS_reserved0_MASK 0xfffffff0 -#define BCHP_CLK_REGULATOR_2P5_VOLTS_reserved0_SHIFT 4 - -/* CLK :: REGULATOR_2P5_VOLTS :: ADJUST [03:00] */ -#define BCHP_CLK_REGULATOR_2P5_VOLTS_ADJUST_MASK 0x0000000f -#define BCHP_CLK_REGULATOR_2P5_VOLTS_ADJUST_SHIFT 0 - -/*************************************************************************** - *TEMP_MON_CTRL - Temperature monitor control. - ***************************************************************************/ -/* CLK :: TEMP_MON_CTRL :: reserved0 [31:10] */ -#define BCHP_CLK_TEMP_MON_CTRL_reserved0_MASK 0xfffffc00 -#define BCHP_CLK_TEMP_MON_CTRL_reserved0_SHIFT 10 - -/* CLK :: TEMP_MON_CTRL :: RESETB [09:09] */ -#define BCHP_CLK_TEMP_MON_CTRL_RESETB_MASK 0x00000200 -#define BCHP_CLK_TEMP_MON_CTRL_RESETB_SHIFT 9 -#define BCHP_CLK_TEMP_MON_CTRL_RESETB_Reset 0 -#define BCHP_CLK_TEMP_MON_CTRL_RESETB_Normal 1 - -/* CLK :: TEMP_MON_CTRL :: PWRDN [08:08] */ -#define BCHP_CLK_TEMP_MON_CTRL_PWRDN_MASK 0x00000100 -#define BCHP_CLK_TEMP_MON_CTRL_PWRDN_SHIFT 8 -#define BCHP_CLK_TEMP_MON_CTRL_PWRDN_Powered_Up 0 -#define BCHP_CLK_TEMP_MON_CTRL_PWRDN_Powered_Down 1 - -/* union - case Combined [07:00] */ -/* CLK :: TEMP_MON_CTRL :: Combined :: CTRL [07:00] */ -#define BCHP_CLK_TEMP_MON_CTRL_Combined_CTRL_MASK 0x000000ff -#define BCHP_CLK_TEMP_MON_CTRL_Combined_CTRL_SHIFT 0 - -/* union - case Separate [07:00] */ -/* CLK :: TEMP_MON_CTRL :: Separate :: BIAS_ADJUST [07:02] */ -#define BCHP_CLK_TEMP_MON_CTRL_Separate_BIAS_ADJUST_MASK 0x000000fc -#define BCHP_CLK_TEMP_MON_CTRL_Separate_BIAS_ADJUST_SHIFT 2 - -/* CLK :: TEMP_MON_CTRL :: Separate :: REF_PWRDN [01:01] */ -#define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_MASK 0x00000002 -#define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_SHIFT 1 -#define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_Powered_Up 0 -#define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_Powered_Down 1 - -/* CLK :: TEMP_MON_CTRL :: Separate :: BGAP_PWRDN [00:00] */ -#define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_MASK 0x00000001 -#define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_SHIFT 0 -#define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_Powered_Up 0 -#define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_Powered_Down 1 - -/*************************************************************************** - *TEMP_MON_STATUS - Temperature monitor status. - ***************************************************************************/ -/* CLK :: TEMP_MON_STATUS :: CLK25K [31:31] */ -#define BCHP_CLK_TEMP_MON_STATUS_CLK25K_MASK 0x80000000 -#define BCHP_CLK_TEMP_MON_STATUS_CLK25K_SHIFT 31 - -/* CLK :: TEMP_MON_STATUS :: reserved0 [30:24] */ -#define BCHP_CLK_TEMP_MON_STATUS_reserved0_MASK 0x7f000000 -#define BCHP_CLK_TEMP_MON_STATUS_reserved0_SHIFT 24 - -/* CLK :: TEMP_MON_STATUS :: STROBE_COUNT [23:16] */ -#define BCHP_CLK_TEMP_MON_STATUS_STROBE_COUNT_MASK 0x00ff0000 -#define BCHP_CLK_TEMP_MON_STATUS_STROBE_COUNT_SHIFT 16 - -/* CLK :: TEMP_MON_STATUS :: reserved1 [15:09] */ -#define BCHP_CLK_TEMP_MON_STATUS_reserved1_MASK 0x0000fe00 -#define BCHP_CLK_TEMP_MON_STATUS_reserved1_SHIFT 9 - -/* CLK :: TEMP_MON_STATUS :: DATA [08:00] */ -#define BCHP_CLK_TEMP_MON_STATUS_DATA_MASK 0x000001ff -#define BCHP_CLK_TEMP_MON_STATUS_DATA_SHIFT 0 - -/*************************************************************************** - *SCRATCH - clock_gen Scratch register - ***************************************************************************/ -/* CLK :: SCRATCH :: VALUE [31:00] */ -#define BCHP_CLK_SCRATCH_VALUE_MASK 0xffffffff -#define BCHP_CLK_SCRATCH_VALUE_SHIFT 0 - -/*************************************************************************** - *PLL0_ARM_DIV - Main PLL0 channel 3 ARM clock divider settings - ***************************************************************************/ -/* CLK :: PLL0_ARM_DIV :: reserved0 [31:08] */ -#define BCHP_CLK_PLL0_ARM_DIV_reserved0_MASK 0xffffff00 -#define BCHP_CLK_PLL0_ARM_DIV_reserved0_SHIFT 8 - -/* CLK :: PLL0_ARM_DIV :: M3DIV [07:00] */ -#define BCHP_CLK_PLL0_ARM_DIV_M3DIV_MASK 0x000000ff -#define BCHP_CLK_PLL0_ARM_DIV_M3DIV_SHIFT 0 - -/*************************************************************************** - *PLL0_LOCK_CNT - Main PLL0 Lock Counter - ***************************************************************************/ -/* CLK :: PLL0_LOCK_CNT :: reserved0 [31:12] */ -#define BCHP_CLK_PLL0_LOCK_CNT_reserved0_MASK 0xfffff000 -#define BCHP_CLK_PLL0_LOCK_CNT_reserved0_SHIFT 12 - -/* CLK :: PLL0_LOCK_CNT :: COUNT [11:00] */ -#define BCHP_CLK_PLL0_LOCK_CNT_COUNT_MASK 0x00000fff -#define BCHP_CLK_PLL0_LOCK_CNT_COUNT_SHIFT 0 - -/*************************************************************************** - *PLL1_CTRL - Main PLL1 reset, enable, powerdown, and control - ***************************************************************************/ -/* CLK :: PLL1_CTRL :: CTRL_BITS_37_32 [31:26] */ -#define BCHP_CLK_PLL1_CTRL_CTRL_BITS_37_32_MASK 0xfc000000 -#define BCHP_CLK_PLL1_CTRL_CTRL_BITS_37_32_SHIFT 26 - -/* CLK :: PLL1_CTRL :: reserved0 [25:04] */ -#define BCHP_CLK_PLL1_CTRL_reserved0_MASK 0x03fffff0 -#define BCHP_CLK_PLL1_CTRL_reserved0_SHIFT 4 - -/* CLK :: PLL1_CTRL :: POWERDOWN [03:03] */ -#define BCHP_CLK_PLL1_CTRL_POWERDOWN_MASK 0x00000008 -#define BCHP_CLK_PLL1_CTRL_POWERDOWN_SHIFT 3 -#define BCHP_CLK_PLL1_CTRL_POWERDOWN_Powerdown 1 -#define BCHP_CLK_PLL1_CTRL_POWERDOWN_Normal 0 - -/* CLK :: PLL1_CTRL :: CLOCK_ENA [02:02] */ -#define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_MASK 0x00000004 -#define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_SHIFT 2 -#define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_Enable 1 -#define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_Disable 0 - -/* CLK :: PLL1_CTRL :: RESET [01:01] */ -#define BCHP_CLK_PLL1_CTRL_RESET_MASK 0x00000002 -#define BCHP_CLK_PLL1_CTRL_RESET_SHIFT 1 -#define BCHP_CLK_PLL1_CTRL_RESET_Reset 1 -#define BCHP_CLK_PLL1_CTRL_RESET_Normal 0 - -/* CLK :: PLL1_CTRL :: reserved1 [00:00] */ -#define BCHP_CLK_PLL1_CTRL_reserved1_MASK 0x00000001 -#define BCHP_CLK_PLL1_CTRL_reserved1_SHIFT 0 - -/*************************************************************************** - *PLL1_CTRL_LO - Main PLL1 pll_ctrl low 32 bits - ***************************************************************************/ -/* CLK :: PLL1_CTRL_LO :: CTRL_BITS_31_0 [31:00] */ -#define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_MASK 0xffffffff -#define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_SHIFT 0 -#define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_VCO_Range0 536872384 -#define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_VCO_Range1 939525888 - -/*************************************************************************** - *PLL1_AVD_DIV - Main PLL1 divider settings for VCO and channel 1 AVD clock - ***************************************************************************/ -/* CLK :: PLL1_AVD_DIV :: reserved0 [31:26] */ -#define BCHP_CLK_PLL1_AVD_DIV_reserved0_MASK 0xfc000000 -#define BCHP_CLK_PLL1_AVD_DIV_reserved0_SHIFT 26 - -/* CLK :: PLL1_AVD_DIV :: VCORNG [25:24] */ -#define BCHP_CLK_PLL1_AVD_DIV_VCORNG_MASK 0x03000000 -#define BCHP_CLK_PLL1_AVD_DIV_VCORNG_SHIFT 24 - -/* CLK :: PLL1_AVD_DIV :: reserved1 [23:17] */ -#define BCHP_CLK_PLL1_AVD_DIV_reserved1_MASK 0x00fe0000 -#define BCHP_CLK_PLL1_AVD_DIV_reserved1_SHIFT 17 - -/* CLK :: PLL1_AVD_DIV :: NDIV_INT [16:08] */ -#define BCHP_CLK_PLL1_AVD_DIV_NDIV_INT_MASK 0x0001ff00 -#define BCHP_CLK_PLL1_AVD_DIV_NDIV_INT_SHIFT 8 - -/* CLK :: PLL1_AVD_DIV :: M1DIV [07:00] */ -#define BCHP_CLK_PLL1_AVD_DIV_M1DIV_MASK 0x000000ff -#define BCHP_CLK_PLL1_AVD_DIV_M1DIV_SHIFT 0 - -/*************************************************************************** - *PLL1_SPARE2_DIV - Main PLL1 divider settings for channel 2 spare clock - ***************************************************************************/ -/* CLK :: PLL1_SPARE2_DIV :: reserved0 [31:08] */ -#define BCHP_CLK_PLL1_SPARE2_DIV_reserved0_MASK 0xffffff00 -#define BCHP_CLK_PLL1_SPARE2_DIV_reserved0_SHIFT 8 - -/* CLK :: PLL1_SPARE2_DIV :: M2DIV [07:00] */ -#define BCHP_CLK_PLL1_SPARE2_DIV_M2DIV_MASK 0x000000ff -#define BCHP_CLK_PLL1_SPARE2_DIV_M2DIV_SHIFT 0 - -/*************************************************************************** - *PLL1_SPARE3_DIV - Main PLL1 divider settings for channel 3 spare clock - ***************************************************************************/ -/* CLK :: PLL1_SPARE3_DIV :: reserved0 [31:08] */ -#define BCHP_CLK_PLL1_SPARE3_DIV_reserved0_MASK 0xffffff00 -#define BCHP_CLK_PLL1_SPARE3_DIV_reserved0_SHIFT 8 - -/* CLK :: PLL1_SPARE3_DIV :: M3DIV [07:00] */ -#define BCHP_CLK_PLL1_SPARE3_DIV_M3DIV_MASK 0x000000ff -#define BCHP_CLK_PLL1_SPARE3_DIV_M3DIV_SHIFT 0 - -/*************************************************************************** - *PLL1_LOCK_CNT - Main PLL1 Lock Counter - ***************************************************************************/ -/* CLK :: PLL1_LOCK_CNT :: reserved0 [31:12] */ -#define BCHP_CLK_PLL1_LOCK_CNT_reserved0_MASK 0xfffff000 -#define BCHP_CLK_PLL1_LOCK_CNT_reserved0_SHIFT 12 - -/* CLK :: PLL1_LOCK_CNT :: COUNT [11:00] */ -#define BCHP_CLK_PLL1_LOCK_CNT_COUNT_MASK 0x00000fff -#define BCHP_CLK_PLL1_LOCK_CNT_COUNT_SHIFT 0 - -/*************************************************************************** - *PLL_LOCK - PLL lock status - ***************************************************************************/ -/* CLK :: PLL_LOCK :: reserved0 [31:02] */ -#define BCHP_CLK_PLL_LOCK_reserved0_MASK 0xfffffffc -#define BCHP_CLK_PLL_LOCK_reserved0_SHIFT 2 - -/* CLK :: PLL_LOCK :: PLL1 [01:01] */ -#define BCHP_CLK_PLL_LOCK_PLL1_MASK 0x00000002 -#define BCHP_CLK_PLL_LOCK_PLL1_SHIFT 1 - -/* CLK :: PLL_LOCK :: PLL0 [00:00] */ -#define BCHP_CLK_PLL_LOCK_PLL0_MASK 0x00000001 -#define BCHP_CLK_PLL_LOCK_PLL0_SHIFT 0 - -/*************************************************************************** - *PLL_LOCK_CNTR_RESET - PLL Lock Counter Resets - ***************************************************************************/ -/* CLK :: PLL_LOCK_CNTR_RESET :: reserved0 [31:02] */ -#define BCHP_CLK_PLL_LOCK_CNTR_RESET_reserved0_MASK 0xfffffffc -#define BCHP_CLK_PLL_LOCK_CNTR_RESET_reserved0_SHIFT 2 - -/* CLK :: PLL_LOCK_CNTR_RESET :: PLL1 [01:01] */ -#define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL1_MASK 0x00000002 -#define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL1_SHIFT 1 - -/* CLK :: PLL_LOCK_CNTR_RESET :: PLL0 [00:00] */ -#define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL0_MASK 0x00000001 -#define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL0_SHIFT 0 - -/*************************************************************************** - *PLL_TEST_SEL - PLL core test select - ***************************************************************************/ -/* CLK :: PLL_TEST_SEL :: reserved0 [31:08] */ -#define BCHP_CLK_PLL_TEST_SEL_reserved0_MASK 0xffffff00 -#define BCHP_CLK_PLL_TEST_SEL_reserved0_SHIFT 8 - -/* CLK :: PLL_TEST_SEL :: PLL_SEL [07:04] */ -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_MASK 0x000000f0 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_SHIFT 4 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_None 0 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_MAIN_PLL0 1 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_MAIN_PLL1 2 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_3 3 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_4 4 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_5 5 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_6 6 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_7 7 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_8 8 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_9 9 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_10 10 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_11 11 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_12 12 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_13 13 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_14 14 -#define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_15 15 - -/* CLK :: PLL_TEST_SEL :: SUB_SEL [03:00] */ -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_MASK 0x0000000f -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_SHIFT 0 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_VCO_Vcontrol 0 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_VCO_div_8 1 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Frefi 2 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Fdbki 3 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Watchdog 4 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Clkout_1 5 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Clkout_2 6 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Clkout_3 7 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_1 8 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_2 9 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_3 10 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_4 11 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_5 12 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_6 13 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_7 14 -#define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_8 15 - -/*************************************************************************** - *CLK_OBS_CTRL - Clock observation logic select - ***************************************************************************/ -/* CLK :: CLK_OBS_CTRL :: reserved0 [31:05] */ -#define BCHP_CLK_CLK_OBS_CTRL_reserved0_MASK 0xffffffe0 -#define BCHP_CLK_CLK_OBS_CTRL_reserved0_SHIFT 5 - -/* CLK :: CLK_OBS_CTRL :: DIV_SEL [04:03] */ -#define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_MASK 0x00000018 -#define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_SHIFT 3 -#define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Dont_divide 0 -#define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Divide_by_2 1 -#define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Divide_by_4 2 -#define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Reserved_3 3 - -/* CLK :: CLK_OBS_CTRL :: CLK_SEL [02:00] */ -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_MASK 0x00000007 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_SHIFT 0 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Zero 0 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_216_pll 1 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_arm_pll 2 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_avd_pll 3 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_serdes_pll 4 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Reserved_5 5 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Reserved_6 6 -#define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Reserved_7 7 - -/*************************************************************************** - *GPIO_PAD_CTRL - GPIO pad control - ***************************************************************************/ -/* CLK :: GPIO_PAD_CTRL :: reserved0 [31:07] */ -#define BCHP_CLK_GPIO_PAD_CTRL_reserved0_MASK 0xffffff80 -#define BCHP_CLK_GPIO_PAD_CTRL_reserved0_SHIFT 7 - -/* CLK :: GPIO_PAD_CTRL :: GPIO_PDN [06:06] */ -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_MASK 0x00000040 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_SHIFT 6 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_Disable 0 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_Enable 1 - -/* CLK :: GPIO_PAD_CTRL :: GPIO_PUP [05:05] */ -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_MASK 0x00000020 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_SHIFT 5 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_Disable 0 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_Enable 1 - -/* CLK :: GPIO_PAD_CTRL :: GPIO_HYS_EN [04:04] */ -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_MASK 0x00000010 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_SHIFT 4 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_TTL_input 0 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_Schmitt_trigger_input 1 - -/* CLK :: GPIO_PAD_CTRL :: GPIO_SEL [03:01] */ -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_MASK 0x0000000e -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_SHIFT 1 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_Tri_State 0 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_2_mA 1 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_4_mA 2 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_6_mA 4 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_8_mA 5 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_10_mA 6 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_12_mA 7 - -/* CLK :: GPIO_PAD_CTRL :: GPIO_SLEW [00:00] */ -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_MASK 0x00000001 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_SHIFT 0 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_High_Speed 0 -#define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_Normal 1 - -/*************************************************************************** - *MISC_PAD_CTRL - MISC pad control - ***************************************************************************/ -/* CLK :: MISC_PAD_CTRL :: reserved0 [31:07] */ -#define BCHP_CLK_MISC_PAD_CTRL_reserved0_MASK 0xffffff80 -#define BCHP_CLK_MISC_PAD_CTRL_reserved0_SHIFT 7 - -/* CLK :: MISC_PAD_CTRL :: MISC_PDN [06:06] */ -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_MASK 0x00000040 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_SHIFT 6 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_Disable 0 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_Enable 1 - -/* CLK :: MISC_PAD_CTRL :: MISC_PUP [05:05] */ -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_MASK 0x00000020 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_SHIFT 5 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_Disable 0 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_Enable 1 - -/* CLK :: MISC_PAD_CTRL :: MISC_HYS_EN [04:04] */ -#define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_MASK 0x00000010 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_SHIFT 4 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_TTL_input 0 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_Schmitt_trigger_input 1 - -/* CLK :: MISC_PAD_CTRL :: MISC_SEL [03:01] */ -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_MASK 0x0000000e -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_SHIFT 1 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_Tri_State 0 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_2_mA 1 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_4_mA 2 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_6_mA 4 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_8_mA 5 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_10_mA 6 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_12_mA 7 - -/* CLK :: MISC_PAD_CTRL :: MISC_SLEW [00:00] */ -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_MASK 0x00000001 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_SHIFT 0 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_High_Speed 0 -#define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_Normal 1 - -#endif /* #ifndef BCHP_CLK_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_common.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_common.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_common.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_common.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,741 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_common.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:58p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:41:59 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_common.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:58p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_COMMON_H__ -#define BCHP_COMMON_H__ - -/*************************************************************************** - *BCM70015_A0 - ***************************************************************************/ -#define BCHP_PHYSICAL_OFFSET 0x10000000 -#define BCHP_REGISTER_START 0x00070000 /* CLK is first */ -#define BCHP_REGISTER_END 0x01801250 /* DDR23_PHY_BYTE_LANE_0 is last */ -#define BCHP_REGISTER_SIZE 0x005e4494 /* Number of registers */ - -/**************************************************************************** - * Core instance register start address. - ***************************************************************************/ -#define BCHP_CLK_REG_START 0x00070000 -#define BCHP_CLK_REG_END 0x00070304 -#define BCHP_CLK_GR_REG_START 0x00072000 -#define BCHP_CLK_GR_REG_END 0x0007200c -#define BCHP_ARMCR4_BRIDGE_REG_START 0x000e0000 -#define BCHP_ARMCR4_BRIDGE_REG_END 0x000e0098 -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_START 0x000e1000 -#define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_END 0x000e1004 -#define BCHP_TRB_TOP_REG_START 0x000f0000 -#define BCHP_TRB_TOP_REG_END 0x000f0008 -#define BCHP_WRAP_MISC_GR_BRIDGE_REG_START 0x000f1000 -#define BCHP_WRAP_MISC_GR_BRIDGE_REG_END 0x000f100c -#define BCHP_WRAP_MISC_INTR2_REG_START 0x000f2000 -#define BCHP_WRAP_MISC_INTR2_REG_END 0x000f202c -#define BCHP_ARM_UART_REG_START 0x000f3000 -#define BCHP_ARM_UART_REG_END 0x000f3008 -#define BCHP_SHARF_TOP_REG_START 0x000f4000 -#define BCHP_SHARF_TOP_REG_END 0x000f4094 -#define BCHP_SHARF_MEM_DMA0_REG_START 0x000f4100 -#define BCHP_SHARF_MEM_DMA0_REG_END 0x000f411c -#define BCHP_MEM_DMA_REG_START 0x000f5000 -#define BCHP_MEM_DMA_REG_END 0x000f5024 -#define BCHP_SCRUB_CTRL_REG_START 0x000f6000 -#define BCHP_SCRUB_CTRL_REG_END 0x000f6078 -#define BCHP_MEM_DMA_SECURE_REG_START 0x000fc000 -#define BCHP_MEM_DMA_SECURE_REG_END 0x000fc00c -#define BCHP_MMSCRAM_REG_START 0x000fd000 -#define BCHP_MMSCRAM_REG_END 0x000feffc -#define BCHP_TRIPLE_SEC_REG_START 0x000ff000 -#define BCHP_TRIPLE_SEC_REG_END 0x000ff4fc -#define BCHP_WRAP_MISC_SECURE_INTR2_REG_START 0x000ff500 -#define BCHP_WRAP_MISC_SECURE_INTR2_REG_END 0x000ff52c -#define BCHP_XPT_BUS_IF_REG_START 0x00200000 -#define BCHP_XPT_BUS_IF_REG_END 0x00200074 -#define BCHP_XPT_XMEMIF_REG_START 0x00202000 -#define BCHP_XPT_XMEMIF_REG_END 0x00202064 -#define BCHP_XPT_FE_REG_START 0x00208000 -#define BCHP_XPT_FE_REG_END 0x00208dfc -#define BCHP_XPT_PB0_REG_START 0x0020b000 -#define BCHP_XPT_PB0_REG_END 0x0020b048 -#define BCHP_XPT_PB1_REG_START 0x0020b080 -#define BCHP_XPT_PB1_REG_END 0x0020b0c8 -#define BCHP_XPT_PB2_REG_START 0x0020b100 -#define BCHP_XPT_PB2_REG_END 0x0020b148 -#define BCHP_XPT_RAVE_REG_START 0x00210000 -#define BCHP_XPT_RAVE_REG_END 0x0021a50c -#define BCHP_XPT_XPU_REG_START 0x00220000 -#define BCHP_XPT_XPU_REG_END 0x002227fc -#define BCHP_XPT_PCROFFSET_REG_START 0x00227000 -#define BCHP_XPT_PCROFFSET_REG_END 0x00227ffc -#define BCHP_XPT_GR_REG_START 0x00230000 -#define BCHP_XPT_GR_REG_END 0x0023000c -#define BCHP_SUN_GISB_ARB_REG_START 0x00400000 -#define BCHP_SUN_GISB_ARB_REG_END 0x004000d8 -#define BCHP_SUN_RGR_REG_START 0x00400800 -#define BCHP_SUN_RGR_REG_END 0x00400810 -#define BCHP_SUN_RG_REG_START 0x00401000 -#define BCHP_SUN_RG_REG_END 0x0040100c -#define BCHP_SUN_L2_REG_START 0x00401800 -#define BCHP_SUN_L2_REG_END 0x0040182c -#define BCHP_PM_L2_REG_START 0x00401c00 -#define BCHP_PM_L2_REG_END 0x00401c2c -#define BCHP_SUN_TOP_CTRL_REG_START 0x00404000 -#define BCHP_SUN_TOP_CTRL_REG_END 0x00404608 -#define BCHP_GIO_REG_START 0x00406000 -#define BCHP_GIO_REG_END 0x0040601c -#define BCHP_IRQ0_REG_START 0x00406080 -#define BCHP_IRQ0_REG_END 0x00406084 -#define BCHP_TIMER_REG_START 0x004060c0 -#define BCHP_TIMER_REG_END 0x004060fc -#define BCHP_IRQ1_REG_START 0x00406788 -#define BCHP_IRQ1_REG_END 0x0040678c -#define BCHP_WAKEUP_CTRL2_REG_START 0x00406c00 -#define BCHP_WAKEUP_CTRL2_REG_END 0x00406c14 -#define BCHP_PRI_CLIENT_REGS_REG_START 0x0040c000 -#define BCHP_PRI_CLIENT_REGS_REG_END 0x0040c27c -#define BCHP_PRI_CRIT_L2_REGS_1_REG_START 0x0040c400 -#define BCHP_PRI_CRIT_L2_REGS_1_REG_END 0x0040c42c -#define BCHP_PRI_CRIT_L2_REGS_2_REG_START 0x0040c440 -#define BCHP_PRI_CRIT_L2_REGS_2_REG_END 0x0040c46c -#define BCHP_PRI_CRIT_L2_REGS_3_REG_START 0x0040c480 -#define BCHP_PRI_CRIT_L2_REGS_3_REG_END 0x0040c4ac -#define BCHP_PRI_RTS_L2_REGS_1_REG_START 0x0040c4c0 -#define BCHP_PRI_RTS_L2_REGS_1_REG_END 0x0040c4ec -#define BCHP_PRI_RTS_L2_REGS_2_REG_START 0x0040c500 -#define BCHP_PRI_RTS_L2_REGS_2_REG_END 0x0040c52c -#define BCHP_PRI_RTS_L2_REGS_3_REG_START 0x0040c540 -#define BCHP_PRI_RTS_L2_REGS_3_REG_END 0x0040c56c -#define BCHP_PRI_ARB_TRACE_REGS_REG_START 0x0040c600 -#define BCHP_PRI_ARB_TRACE_REGS_REG_END 0x0040c7ec -#define BCHP_PRI_ARB_MSA_REGS_REG_START 0x0040c800 -#define BCHP_PRI_ARB_MSA_REGS_REG_END 0x0040ca0c -#define BCHP_PRI_ARB_CONTROL_REGS_REG_START 0x0040cb00 -#define BCHP_PRI_ARB_CONTROL_REGS_REG_END 0x0040cb30 -#define BCHP_PRI_ARB_ARCH_REGS_REG_START 0x0040cc00 -#define BCHP_PRI_ARB_ARCH_REGS_REG_END 0x0040cdac -#define BCHP_PRI_ARB_MIPS_L2_REGS_REG_START 0x0040ce00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_REG_END 0x0040ce2c -#define BCHP_PRI_ARB_ARC_L1_REGS_REG_START 0x0040cf00 -#define BCHP_PRI_ARB_ARC_L1_REGS_REG_END 0x0040cf1c -#define BCHP_SENTINEL_REG_START 0x00410000 -#define BCHP_SENTINEL_REG_END 0x00413ffc -#define BCHP_SUN_GISB_ARB_SEC_REG_START 0x00460000 -#define BCHP_SUN_GISB_ARB_SEC_REG_END 0x00460064 -#define BCHP_PRI_ARB_WRCH_REGS_REG_START 0x00461000 -#define BCHP_PRI_ARB_WRCH_REGS_REG_END 0x004610fc -#define BCHP_PRI_ARB_STARCH_REGS_REG_START 0x00461200 -#define BCHP_PRI_ARB_STARCH_REGS_REG_END 0x004613c0 -#define BCHP_PRI_ARB_SARCH_REGS_REG_START 0x00461400 -#define BCHP_PRI_ARB_SARCH_REGS_REG_END 0x0046159c -#define BCHP_PCIE_CFG_REG_START 0x00500000 -#define BCHP_PCIE_CFG_REG_END 0x0050018c -#define BCHP_PCIE_TL_REG_START 0x00500400 -#define BCHP_PCIE_TL_REG_END 0x0050046c -#define BCHP_PCIE_DLL_REG_START 0x00500500 -#define BCHP_PCIE_DLL_REG_END 0x00500554 -#define BCHP_PCIE_PHY_REG_START 0x00500600 -#define BCHP_PCIE_PHY_REG_END 0x0050063c -#define BCHP_INTR_REG_START 0x00500700 -#define BCHP_INTR_REG_END 0x00500734 -#define BCHP_L1_INTR_REG_START 0x00500740 -#define BCHP_L1_INTR_REG_END 0x0050075c -#define BCHP_MDIO_REG_START 0x00500760 -#define BCHP_MDIO_REG_END 0x00500768 -#define BCHP_TGT_RGR_BRIDGE_REG_START 0x00500780 -#define BCHP_TGT_RGR_BRIDGE_REG_END 0x00500790 -#define BCHP_I2C_REG_START 0x00501000 -#define BCHP_I2C_REG_END 0x00501054 -#define BCHP_I2C_GR_BRIDGE_REG_START 0x005013e0 -#define BCHP_I2C_GR_BRIDGE_REG_END 0x005013ec -#define BCHP_MISC1_REG_START 0x00502000 -#define BCHP_MISC1_REG_END 0x005020d0 -#define BCHP_MISC2_REG_START 0x00502100 -#define BCHP_MISC2_REG_END 0x00502120 -#define BCHP_MISC3_REG_START 0x00502200 -#define BCHP_MISC3_REG_END 0x0050222c -#define BCHP_MISC_PERST_REG_START 0x00502280 -#define BCHP_MISC_PERST_REG_END 0x0050229c -#define BCHP_MISC_GR_BRIDGE_REG_START 0x005023e0 -#define BCHP_MISC_GR_BRIDGE_REG_END 0x005023ec -#define BCHP_CCE_RGR_BRIDGE_REG_START 0x005033e0 -#define BCHP_CCE_RGR_BRIDGE_REG_END 0x005033f0 -#define BCHP_BOP_AES_REG_START 0x00510000 -#define BCHP_BOP_AES_REG_END 0x00510034 -#define BCHP_BOP_GR_BRIDGE_REG_START 0x00511000 -#define BCHP_BOP_GR_BRIDGE_REG_END 0x0051100c -#define BCHP_MFD_REG_START 0x00540000 -#define BCHP_MFD_REG_END 0x005400fc -#define BCHP_DNR_REG_START 0x00540400 -#define BCHP_DNR_REG_END 0x005404a0 -#define BCHP_SCL_HD_REG_START 0x00540800 -#define BCHP_SCL_HD_REG_END 0x00540bfc -#define BCHP_CSC_REG_START 0x00541000 -#define BCHP_CSC_REG_END 0x0054103c -#define BCHP_BVNT_INTR2_REG_START 0x00541200 -#define BCHP_BVNT_INTR2_REG_END 0x0054122c -#define BCHP_TMISC_REG_START 0x00541400 -#define BCHP_TMISC_REG_END 0x0054143c -#define BCHP_BVNT_GR_BRIDGE_REG_START 0x00541800 -#define BCHP_BVNT_GR_BRIDGE_REG_END 0x0054180c -#define BCHP_DECODE_MAIN_0_REG_START 0x00800100 -#define BCHP_DECODE_MAIN_0_REG_END 0x008001fc -#define BCHP_DECODE_MCOM_0_REG_START 0x00800300 -#define BCHP_DECODE_MCOM_0_REG_END 0x0080031c -#define BCHP_DECODE_SPRE_0_REG_START 0x00800320 -#define BCHP_DECODE_SPRE_0_REG_END 0x0080033c -#define BCHP_DECODE_WPRD_0_REG_START 0x00800340 -#define BCHP_DECODE_WPRD_0_REG_END 0x0080035c -#define BCHP_DECODE_DQNT_0_REG_START 0x00800400 -#define BCHP_DECODE_DQNT_0_REG_END 0x0080045c -#define BCHP_DECODE_DQNT_8X8_0_REG_START 0x00800500 -#define BCHP_DECODE_DQNT_8X8_0_REG_END 0x0080057c -#define BCHP_DECODE_XFRM_0_REG_START 0x00800700 -#define BCHP_DECODE_XFRM_0_REG_END 0x0080071c -#define BCHP_DECODE_DBLK_0_REG_START 0x00800720 -#define BCHP_DECODE_DBLK_0_REG_END 0x0080073c -#define BCHP_DECODE_MB_0_REG_START 0x00800740 -#define BCHP_DECODE_MB_0_REG_END 0x0080075c -#define BCHP_REG_CABAC2BINS_0_REG_START 0x00800b00 -#define BCHP_REG_CABAC2BINS_0_REG_END 0x00800bfc -#define BCHP_DECODE_SINT_0_REG_START 0x00800c00 -#define BCHP_DECODE_SINT_0_REG_END 0x00800dfc -#define BCHP_DECODE_RVC_0_REG_START 0x00800e00 -#define BCHP_DECODE_RVC_0_REG_END 0x00800efc -#define BCHP_DECODE_CPUREGS_0_REG_START 0x00800f00 -#define BCHP_DECODE_CPUREGS_0_REG_END 0x00800f7c -#define BCHP_DECODE_CPUREGS2_0_REG_START 0x00800f80 -#define BCHP_DECODE_CPUREGS2_0_REG_END 0x00800ffc -#define BCHP_DECODE_CPUDMA_0_REG_START 0x00801800 -#define BCHP_DECODE_CPUDMA_0_REG_END 0x008018fc -#define BCHP_DECODE_DMAMEM_0_REG_START 0x00801a00 -#define BCHP_DECODE_DMAMEM_0_REG_END 0x008021fc -#define BCHP_REG_CABAC2BINS2_0_REG_START 0x00802400 -#define BCHP_REG_CABAC2BINS2_0_REG_END 0x008027fc -#define BCHP_DECODE_WPTBL_0_REG_START 0x00803000 -#define BCHP_DECODE_WPTBL_0_REG_END 0x008031fc -#define BCHP_DECODE_SINT_OLOOP_0_REG_START 0x0080cc00 -#define BCHP_DECODE_SINT_OLOOP_0_REG_END 0x0080ccfc -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START 0x00841000 -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END 0x0084107c -#define BCHP_DECODE_CPUCORE_0_REG_START 0x00844000 -#define BCHP_DECODE_CPUCORE_0_REG_END 0x00844ffc -#define BCHP_DECODE_CPUAUX_0_REG_START 0x00845000 -#define BCHP_DECODE_CPUAUX_0_REG_END 0x00845ffc -#define BCHP_DECODE_CPUIMEM_0_REG_START 0x00846000 -#define BCHP_DECODE_CPUIMEM_0_REG_END 0x00847ffc -#define BCHP_DECODE_CPUDMEM_0_REG_START 0x00848000 -#define BCHP_DECODE_CPUDMEM_0_REG_END 0x0084fffc -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START 0x00851000 -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END 0x0085107c -#define BCHP_DECODE_CPUDMA2_0_REG_START 0x00851800 -#define BCHP_DECODE_CPUDMA2_0_REG_END 0x008518fc -#define BCHP_DECODE_DMAMEM2_0_REG_START 0x00851a00 -#define BCHP_DECODE_DMAMEM2_0_REG_END 0x008521fc -#define BCHP_DECODE_CPUCORE2_0_REG_START 0x00854000 -#define BCHP_DECODE_CPUCORE2_0_REG_END 0x00854ffc -#define BCHP_DECODE_CPUAUX2_0_REG_START 0x00855000 -#define BCHP_DECODE_CPUAUX2_0_REG_END 0x00855ffc -#define BCHP_DECODE_CPUIMEM2_0_REG_START 0x00856000 -#define BCHP_DECODE_CPUIMEM2_0_REG_END 0x00857ffc -#define BCHP_DECODE_CPUDMEM2_0_REG_START 0x00858000 -#define BCHP_DECODE_CPUDMEM2_0_REG_END 0x0085fffc -#define BCHP_DECODE_IP_SHIM_0_REG_START 0x00860000 -#define BCHP_DECODE_IP_SHIM_0_REG_END 0x0086007c -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_START 0x00861000 -#define BCHP_AVD_BLOCK_AVG_REGS_0_REG_END 0x0086103c -#define BCHP_AVD_CACHE_0_REG_START 0x00862000 -#define BCHP_AVD_CACHE_0_REG_END 0x0086203c -#define BCHP_AVD_INTR2_0_REG_START 0x00900000 -#define BCHP_AVD_INTR2_0_REG_END 0x0090002c -#define BCHP_AVD_GR_0_REG_START 0x00900400 -#define BCHP_AVD_GR_0_REG_END 0x0090040c -#define BCHP_VICH_0_REG_START 0x00b00000 -#define BCHP_VICH_0_REG_END 0x00b0004c -#define BCHP_DDR23_CTL_REGS_0_REG_START 0x01800000 -#define BCHP_DDR23_CTL_REGS_0_REG_END 0x018001fc -#define BCHP_DDR23_PHY_CONTROL_REGS_REG_START 0x01801000 -#define BCHP_DDR23_PHY_CONTROL_REGS_REG_END 0x01801044 -#define BCHP_DDR23_PHY_BYTE_LANE_1_REG_START 0x01801100 -#define BCHP_DDR23_PHY_BYTE_LANE_1_REG_END 0x0180114c -#define BCHP_DDR23_PHY_BYTE_LANE_0_REG_START 0x01801200 -#define BCHP_DDR23_PHY_BYTE_LANE_0_REG_END 0x0180124c - - -/*************************************************************************** - *BVN_MFD - ***************************************************************************/ -/*************************************************************************** - *DRAM_DATA_STRUCTURE - DRAM Data Structure - ***************************************************************************/ -/* BVN_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ -#define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff -#define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 - -/*************************************************************************** - *MEM_DMA - ***************************************************************************/ -/*************************************************************************** - *DESC_WORD0 - MEM DMA Descriptor Word 0 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */ -#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK 0xffffffff -#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT 0 - -/*************************************************************************** - *DESC_WORD1 - MEM DMA Descriptor Word 1 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */ -#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK 0xffffffff -#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT 0 - -/*************************************************************************** - *DESC_WORD2 - MEM DMA Descriptor Word 2 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */ -#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK 0x80000000 -#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT 31 - -/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */ -#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK 0x40000000 -#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT 30 - -/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */ -#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK 0x20000000 -#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT 29 - -/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */ -#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK 0x1e000000 -#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT 25 - -/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */ -#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK 0x01ffffff -#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT 0 - -/*************************************************************************** - *DESC_WORD3 - MEM DMA Descriptor Word 3 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */ -#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT 5 - -/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */ -#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK 0x00000018 -#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT 3 - -/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */ -#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK 0x00000004 -#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT 2 -#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN 0 -#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN 1 - -/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */ -#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK 0x00000003 -#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT 0 -#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0 -#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1 -#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2 -#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved 3 - -/*************************************************************************** - *DESC_WORD4 - MEM DMA Descriptor Word 4 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */ -#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK 0xffff0000 -#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT 16 - -/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */ -#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK 0x0000c000 -#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT 14 - -/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */ -#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK 0x00002000 -#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT 13 - -/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */ -#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK 0x00001000 -#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT 12 - -/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */ -#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK 0x00000800 -#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT 11 - -/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */ -#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK 0x00000400 -#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT 10 - -/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */ -#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK 0x00000300 -#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT 8 - -/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */ -#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK 0x000000ff -#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT 0 - -/*************************************************************************** - *DESC_WORD5 - MEM DMA Descriptor Word 5 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */ -#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK 0xffffffff -#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT 0 - -/*************************************************************************** - *DESC_WORD6 - MEM DMA Descriptor Word 6 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */ -#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK 0xffffffff -#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT 0 - -/*************************************************************************** - *DESC_WORD7 - MEM DMA Descriptor Word 7 - ***************************************************************************/ -/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */ -#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK 0xffffffff -#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT 0 - -/*************************************************************************** - *SHARF_MEM_DMA - ***************************************************************************/ -/*************************************************************************** - *DESC_WORD0 - SHARF DMA Descriptor Word 0 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD0_READ_ADDR_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT 0 - -/*************************************************************************** - *DESC_WORD1 - SHARF DMA Descriptor Word 1 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT 0 - -/*************************************************************************** - *DESC_WORD2 - SHARF DMA Descriptor Word 2 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK 0x80000000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT 31 - -/* SHARF_MEM_DMA :: DESC_WORD2 :: LAST [30:30] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_LAST_MASK 0x40000000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_LAST_SHIFT 30 - -/* SHARF_MEM_DMA :: DESC_WORD2 :: reserved0 [29:27] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_reserved0_MASK 0x38000000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_reserved0_SHIFT 27 - -/* SHARF_MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [26:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK 0x07ffffff -#define BCHP_SHARF_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT 0 - -/*************************************************************************** - *DESC_WORD3 - SHARF DMA Descriptor Word 3 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT 5 - -/* SHARF_MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_reserved0_MASK 0x00000018 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_reserved0_SHIFT 3 - -/* SHARF_MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK 0x00000004 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT 2 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN 0 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN 1 - -/* SHARF_MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK 0x00000003 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT 0 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2 -#define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved 3 - -/*************************************************************************** - *DESC_WORD4 - SHARF DMA Descriptor Word 4 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD4 :: reserved0 [31:20] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved0_MASK 0xfff00000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved0_SHIFT 20 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: KEY_UNWRAP_MODE [19:18] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_UNWRAP_MODE_MASK 0x000c0000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_UNWRAP_MODE_SHIFT 18 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: CONTEXT_NUM [17:16] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_CONTEXT_NUM_MASK 0x00030000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_CONTEXT_NUM_SHIFT 16 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: SECURE_FAIL_INTR_ENABLE [15:15] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SECURE_FAIL_INTR_ENABLE_MASK 0x00008000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SECURE_FAIL_INTR_ENABLE_SHIFT 15 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: FAIL_INTR_ENABLE [14:14] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_FAIL_INTR_ENABLE_MASK 0x00004000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_FAIL_INTR_ENABLE_SHIFT 14 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK 0x00002000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT 13 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK 0x00001000 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT 12 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK 0x00000800 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT 11 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: CMP_8_LSBYTES [10:10] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_CMP_8_LSBYTES_MASK 0x00000400 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_CMP_8_LSBYTES_SHIFT 10 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: reserved1 [09:08] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved1_MASK 0x00000300 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved1_SHIFT 8 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: MODE_SEL [07:04] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_MODE_SEL_MASK 0x000000f0 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT 4 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: USE_BSP_KEY [03:03] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_USE_BSP_KEY_MASK 0x00000008 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_USE_BSP_KEY_SHIFT 3 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: reserved2 [02:02] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved2_MASK 0x00000004 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved2_SHIFT 2 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: DIGEST_PRESENT [01:01] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_DIGEST_PRESENT_MASK 0x00000002 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_DIGEST_PRESENT_SHIFT 1 - -/* SHARF_MEM_DMA :: DESC_WORD4 :: KEY_PRESENT [00:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_PRESENT_MASK 0x00000001 -#define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_PRESENT_SHIFT 0 - -/*************************************************************************** - *DESC_WORD5 - SHARF DMA Descriptor Word 5 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD5 :: INDEX [31:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD5_INDEX_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA_DESC_WORD5_INDEX_SHIFT 0 - -/*************************************************************************** - *DESC_WORD6 - SHARF DMA Descriptor Word 6 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD6_reserved0_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA_DESC_WORD6_reserved0_SHIFT 0 - -/*************************************************************************** - *DESC_WORD7 - SHARF DMA Descriptor Word 7 - ***************************************************************************/ -/* SHARF_MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */ -#define BCHP_SHARF_MEM_DMA_DESC_WORD7_reserved0_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA_DESC_WORD7_reserved0_SHIFT 0 - -/*************************************************************************** - *XPT_PB - ***************************************************************************/ -/*************************************************************************** - *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract - ***************************************************************************/ -/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */ -#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK 0xffffffff -#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT 0 - -/*************************************************************************** - *DESC_0 - Playback Linked-List Descriptor Word 0 - ***************************************************************************/ -/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */ -#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK 0xffffffff -#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT 0 - -/*************************************************************************** - *DESC_1 - Playback Linked-List Descriptor Word 1 - ***************************************************************************/ -/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */ -#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK 0xffffffff -#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT 0 - -/*************************************************************************** - *DESC_2 - Playback Linked-List Descriptor Word 2 - ***************************************************************************/ -/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */ -#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK 0x80000000 -#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT 31 - -/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */ -#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK 0x40000000 -#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT 30 - -/* XPT_PB :: DESC_2 :: reserved0 [29:28] */ -#define BCHP_XPT_PB_DESC_2_reserved0_MASK 0x30000000 -#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT 28 - -/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */ -#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK 0x0f000000 -#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT 24 - -/* XPT_PB :: DESC_2 :: reserved1 [23:00] */ -#define BCHP_XPT_PB_DESC_2_reserved1_MASK 0x00ffffff -#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT 0 - -/*************************************************************************** - *DESC_3 - Playback Linked-List Descriptor Word 3 - ***************************************************************************/ -/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */ -#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK 0xfffffff0 -#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT 4 - -/* XPT_PB :: DESC_3 :: reserved0 [03:01] */ -#define BCHP_XPT_PB_DESC_3_reserved0_MASK 0x0000000e -#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT 1 - -/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */ -#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK 0x00000001 -#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT 0 - -/*************************************************************************** - *XPT_RAVE - ***************************************************************************/ -/*************************************************************************** - *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples - ***************************************************************************/ -/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */ -#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0 - -/*************************************************************************** - *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup - ***************************************************************************/ -/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */ -#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0 - -/*************************************************************************** - *NOTEC_PES_LAYER_SELECTION - PES Layer Selection - ***************************************************************************/ -/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */ -#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0 - -/*************************************************************************** - *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general - ***************************************************************************/ -/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */ -#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0 - -/*************************************************************************** - *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video - ***************************************************************************/ -/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video - ***************************************************************************/ -/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio - ***************************************************************************/ -/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio - ***************************************************************************/ -/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio - ***************************************************************************/ -/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEH_DVD_AC3_AUDIO_ES_SETUP - ES Setup - DVD_AC3 Audio - ***************************************************************************/ -/* XPT_RAVE :: NOTEH_DVD_AC3_AUDIO_ES_SETUP :: DVD_AUDIO_AC3_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEI_DVD_LPCM_AUDIO_ES_SETUP - ES Setup - DVD_LPCM Audio - ***************************************************************************/ -/* XPT_RAVE :: NOTEI_DVD_LPCM_AUDIO_ES_SETUP :: DVD_AUDIO_LPCM_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio - ***************************************************************************/ -/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0 - -/*************************************************************************** - *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio - ***************************************************************************/ -/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */ -#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff -#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0 - -#endif /* #ifndef BCHP_COMMON_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_csc.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_csc.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_csc.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_csc.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,214 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_csc.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:58p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:17 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_csc.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:58p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_CSC_H__ -#define BCHP_CSC_H__ - -/*************************************************************************** - *CSC - Color Space Converter Registers - ***************************************************************************/ -#define BCHP_CSC_CSC_CTRL 0x00541000 /* Color Matrix Control */ -#define BCHP_CSC_CSC_COEFF_C00 0x00541010 /* Color Matrix coefficients c00 */ -#define BCHP_CSC_CSC_COEFF_C01 0x00541014 /* Color Matrix coefficients c01 */ -#define BCHP_CSC_CSC_COEFF_C02 0x00541018 /* Color Matrix coefficients c02 */ -#define BCHP_CSC_CSC_COEFF_C03 0x0054101c /* Color Matrix coefficients c03 */ -#define BCHP_CSC_CSC_COEFF_C10 0x00541020 /* Color Matrix coefficients c10 */ -#define BCHP_CSC_CSC_COEFF_C11 0x00541024 /* Color Matrix coefficients c11 */ -#define BCHP_CSC_CSC_COEFF_C12 0x00541028 /* Color Matrix coefficients c12 */ -#define BCHP_CSC_CSC_COEFF_C13 0x0054102c /* Color Matrix coefficients c13 */ -#define BCHP_CSC_CSC_COEFF_C20 0x00541030 /* Color Matrix coefficients c20 */ -#define BCHP_CSC_CSC_COEFF_C21 0x00541034 /* Color Matrix coefficients c21 */ -#define BCHP_CSC_CSC_COEFF_C22 0x00541038 /* Color Matrix coefficients c22 */ -#define BCHP_CSC_CSC_COEFF_C23 0x0054103c /* Color Matrix coefficients c23 */ - -/*************************************************************************** - *CSC_CTRL - Color Matrix Control - ***************************************************************************/ -/* CSC :: CSC_CTRL :: reserved0 [31:01] */ -#define BCHP_CSC_CSC_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_CSC_CSC_CTRL_reserved0_SHIFT 1 - -/* CSC :: CSC_CTRL :: CSC_ENABLE [00:00] */ -#define BCHP_CSC_CSC_CTRL_CSC_ENABLE_MASK 0x00000001 -#define BCHP_CSC_CSC_CTRL_CSC_ENABLE_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C00 - Color Matrix coefficients c00 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C00 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C00_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C00_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C00 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C00_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C00_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C01 - Color Matrix coefficients c01 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C01 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C01_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C01_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C01 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C01_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C01_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C02 - Color Matrix coefficients c02 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C02 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C02_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C02_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C02 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C02_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C02_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C03 - Color Matrix coefficients c03 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C03 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C03_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C03_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C03 :: COEFF_ADD [15:00] */ -#define BCHP_CSC_CSC_COEFF_C03_COEFF_ADD_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C03_COEFF_ADD_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C10 - Color Matrix coefficients c10 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C10 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C10_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C10_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C10 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C10_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C10_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C11 - Color Matrix coefficients c11 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C11 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C11_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C11_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C11 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C11_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C11_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C12 - Color Matrix coefficients c12 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C12 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C12_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C12_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C12 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C12_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C12_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C13 - Color Matrix coefficients c13 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C13 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C13_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C13_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C13 :: COEFF_ADD [15:00] */ -#define BCHP_CSC_CSC_COEFF_C13_COEFF_ADD_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C13_COEFF_ADD_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C20 - Color Matrix coefficients c20 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C20 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C20_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C20_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C20 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C20_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C20_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C21 - Color Matrix coefficients c21 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C21 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C21_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C21_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C21 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C21_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C21_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C22 - Color Matrix coefficients c22 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C22 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C22_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C22_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C22 :: COEFF_MUL [15:00] */ -#define BCHP_CSC_CSC_COEFF_C22_COEFF_MUL_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C22_COEFF_MUL_SHIFT 0 - -/*************************************************************************** - *CSC_COEFF_C23 - Color Matrix coefficients c23 - ***************************************************************************/ -/* CSC :: CSC_COEFF_C23 :: reserved0 [31:16] */ -#define BCHP_CSC_CSC_COEFF_C23_reserved0_MASK 0xffff0000 -#define BCHP_CSC_CSC_COEFF_C23_reserved0_SHIFT 16 - -/* CSC :: CSC_COEFF_C23 :: COEFF_ADD [15:00] */ -#define BCHP_CSC_CSC_COEFF_C23_COEFF_ADD_MASK 0x0000ffff -#define BCHP_CSC_CSC_COEFF_C23_COEFF_ADD_SHIFT 0 - -#endif /* #ifndef BCHP_CSC_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,866 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_ddr23_ctl_regs_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:59p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:08 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:59p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DDR23_CTL_REGS_0_H__ -#define BCHP_DDR23_CTL_REGS_0_H__ - -/*************************************************************************** - *DDR23_CTL_REGS_0 - DDR23 controller registers - ***************************************************************************/ -#define BCHP_DDR23_CTL_REGS_0_REVISION 0x01800000 /* DDR23 Controller revision register */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS 0x01800004 /* DDR23 Controller status register */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1 0x01800010 /* DDR23 Controller Configuration Set #1 */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2 0x01800014 /* DDR23 Controller Configuration Set #2 */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3 0x01800018 /* DDR23 Controller Configuration Set #3 */ -#define BCHP_DDR23_CTL_REGS_0_REFRESH 0x0180001c /* DDR23 Controller Automated Refresh Configuration */ -#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD 0x01800020 /* Host Initiated Refresh Control */ -#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD 0x01800024 /* Host Initiated Precharge Control */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD 0x01800028 /* Host Initiated Load Mode Control */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD 0x0180002c /* Host Initiated Load Extended Mode Control */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD 0x01800030 /* Host Initiated Load Extended Mode #2 Control */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD 0x01800034 /* Host Initiated Load Extended Mode #3 Control */ -#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE 0x01800038 /* Host Initiated ZQ Calibration Cycle */ -#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS 0x0180003c /* Host Command Interface Status */ -#define BCHP_DDR23_CTL_REGS_0_LATENCY 0x01800040 /* DDR2 Controller Access Latency Control */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0 0x01800044 /* Semaphore Register #0 */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1 0x01800048 /* Semaphore Register #1 */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2 0x0180004c /* Semaphore Register #2 */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3 0x01800050 /* Semaphore Register #3 */ -#define BCHP_DDR23_CTL_REGS_0_SCRATCH 0x01800058 /* Scratch Register */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH 0x01800060 /* Stripe Width */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0 0x01800070 /* Stripe Height for picture buffers 0 through 23 */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1 0x01800074 /* Stripe Height for picture buffers 24 through 27 */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2 0x01800078 /* Stripe Height for picture buffers 28 through 31 */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL 0x01800090 /* DDR Phy-Bist Control and Status */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_SEED 0x01800094 /* DDR Phy-Bist PRPG Seed Value */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS 0x01800098 /* DDR Phy-Bist Address & Control Status */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS 0x0180009c /* DDR Phy-Bist DQ Status */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS 0x018000a0 /* DDR Phy-Bist Miscellaneous Status */ -#define BCHP_DDR23_CTL_REGS_0_VDL_CTL 0x018000b0 /* Dynamic VDL Changes Control */ -#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE 0x018000b4 /* Dynamic VDL Changes Base Address */ -#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END 0x018000b8 /* Dynamic VDL Changes End Address */ -#define BCHP_DDR23_CTL_REGS_0_PMON_CTL 0x018000c0 /* Performance Monitoring Control */ -#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD 0x018000c4 /* Performance Monitoring Period Control */ -#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT 0x018000c8 /* Performance Monitoring Active Cycles Count */ -#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT 0x018000cc /* Performance Monitoring Idle Cycles Count */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1 0x018000d0 /* Performance Monitoring Data Channel #1 Read Accesses Count */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2 0x018000d4 /* Performance Monitoring Data Channel #2 Read Accesses Count */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3 0x018000d8 /* Performance Monitoring Data Channel #3 Read Accesses Count */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1 0x018000dc /* Performance Monitoring Data Channel #1 Write Accesses Count */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2 0x018000e0 /* Performance Monitoring Data Channel #2 Write Accesses Count */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3 0x018000e4 /* Performance Monitoring Data Channel #3 Write Accesses Count */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM 0x018000e8 /* RAM Macro TM Control */ -#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL 0x018000f0 /* RAM Macro TM Control */ - -/*************************************************************************** - *REVISION - DDR23 Controller revision register - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: REVISION :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: REVISION :: MAJOR [15:08] */ -#define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_SHIFT 8 - -/* DDR23_CTL_REGS_0 :: REVISION :: MINOR [07:00] */ -#define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_MASK 0x000000ff -#define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTL_STATUS - DDR23 Controller status register - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: CTL_STATUS :: reserved0 [31:07] */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_MASK 0xffffff80 -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_SHIFT 7 - -/* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo3_empty [06:06] */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_MASK 0x00000040 -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_SHIFT 6 - -/* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo2_empty [05:05] */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_MASK 0x00000020 -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_SHIFT 5 - -/* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo1_empty [04:04] */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_MASK 0x00000010 -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_SHIFT 4 - -/* DDR23_CTL_REGS_0 :: CTL_STATUS :: reserved1 [03:02] */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_MASK 0x0000000c -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_SHIFT 2 - -/* DDR23_CTL_REGS_0 :: CTL_STATUS :: clke [01:01] */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK 0x00000002 -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: CTL_STATUS :: idle [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_SHIFT 0 - -/*************************************************************************** - *PARAMS1 - DDR23 Controller Configuration Set #1 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PARAMS1 :: trtp [31:28] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_MASK 0xf0000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_SHIFT 28 - -/* DDR23_CTL_REGS_0 :: PARAMS1 :: twl [27:24] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_MASK 0x0f000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PARAMS1 :: tcas [23:20] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_MASK 0x00f00000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_SHIFT 20 - -/* DDR23_CTL_REGS_0 :: PARAMS1 :: twtr [19:16] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_MASK 0x000f0000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: PARAMS1 :: twr [15:12] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_MASK 0x0000f000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_SHIFT 12 - -/* DDR23_CTL_REGS_0 :: PARAMS1 :: trrd [11:08] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_MASK 0x00000f00 -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_SHIFT 8 - -/* DDR23_CTL_REGS_0 :: PARAMS1 :: trp [07:04] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_MASK 0x000000f0 -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_SHIFT 4 - -/* DDR23_CTL_REGS_0 :: PARAMS1 :: trcd [03:00] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_MASK 0x0000000f -#define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_SHIFT 0 - -/*************************************************************************** - *PARAMS2 - DDR23 Controller Configuration Set #2 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PARAMS2 :: auto_idle [31:31] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_MASK 0x80000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_SHIFT 31 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: row_bits [30:30] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_MASK 0x40000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_SHIFT 30 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: use_chr_hgt [29:29] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_MASK 0x20000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_SHIFT 29 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: clke [28:28] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK 0x10000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_SHIFT 28 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: sd_col_bits [27:26] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_MASK 0x0c000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_SHIFT 26 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: il_sel [25:25] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_MASK 0x02000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_SHIFT 25 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: dis_itlv [24:24] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_MASK 0x01000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: reserved0 [23:23] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_MASK 0x00800000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_SHIFT 23 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: cs0_only [22:22] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_MASK 0x00400000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_SHIFT 22 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: allow_pictmem_rd [21:21] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_MASK 0x00200000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_SHIFT 21 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: bank_bits [20:20] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_MASK 0x00100000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_SHIFT 20 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: trfc [19:12] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_MASK 0x000ff000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_SHIFT 12 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: tfaw [11:06] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_MASK 0x00000fc0 -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_SHIFT 6 - -/* DDR23_CTL_REGS_0 :: PARAMS2 :: tras [05:00] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_MASK 0x0000003f -#define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_SHIFT 0 - -/*************************************************************************** - *PARAMS3 - DDR23 Controller Configuration Set #3 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr3_reset [31:31] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_MASK 0x80000000 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_SHIFT 31 - -/* DDR23_CTL_REGS_0 :: PARAMS3 :: reserved0 [30:06] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_MASK 0x7fffffc0 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_SHIFT 6 - -/* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr_bl [05:05] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_MASK 0x00000020 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_SHIFT 5 - -/* DDR23_CTL_REGS_0 :: PARAMS3 :: cmd_2t [04:04] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_MASK 0x00000010 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_SHIFT 4 - -/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_mode [03:03] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_MASK 0x00000008 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_SHIFT 3 - -/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_te_adj [02:02] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_MASK 0x00000004 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_SHIFT 2 - -/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_le_adj [01:01] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_MASK 0x00000002 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_en [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_SHIFT 0 - -/*************************************************************************** - *REFRESH - DDR23 Controller Automated Refresh Configuration - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: REFRESH :: reserved0 [31:13] */ -#define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_MASK 0xffffe000 -#define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_SHIFT 13 - -/* DDR23_CTL_REGS_0 :: REFRESH :: enable [12:12] */ -#define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_MASK 0x00001000 -#define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_SHIFT 12 - -/* DDR23_CTL_REGS_0 :: REFRESH :: period [11:00] */ -#define BCHP_DDR23_CTL_REGS_0_REFRESH_period_MASK 0x00000fff -#define BCHP_DDR23_CTL_REGS_0_REFRESH_period_SHIFT 0 - -/*************************************************************************** - *REFRESH_CMD - Host Initiated Refresh Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: REFRESH_CMD :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: REFRESH_CMD :: cmd [15:00] */ -#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_MASK 0x0000ffff -#define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_SHIFT 0 - -/*************************************************************************** - *PRECHARGE_CMD - Host Initiated Precharge Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PRECHARGE_CMD :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: PRECHARGE_CMD :: cmd [15:00] */ -#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_MASK 0x0000ffff -#define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_SHIFT 0 - -/*************************************************************************** - *LOAD_MODE_CMD - Host Initiated Load Mode Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: LOAD_MODE_CMD :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: LOAD_MODE_CMD :: cmd [15:00] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_MASK 0x0000ffff -#define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_SHIFT 0 - -/*************************************************************************** - *LOAD_EMODE_CMD - Host Initiated Load Extended Mode Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: LOAD_EMODE_CMD :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: LOAD_EMODE_CMD :: cmd [15:00] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_MASK 0x0000ffff -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_SHIFT 0 - -/*************************************************************************** - *LOAD_EMODE2_CMD - Host Initiated Load Extended Mode #2 Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: LOAD_EMODE2_CMD :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: LOAD_EMODE2_CMD :: cmd [15:00] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_MASK 0x0000ffff -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_SHIFT 0 - -/*************************************************************************** - *LOAD_EMODE3_CMD - Host Initiated Load Extended Mode #3 Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: LOAD_EMODE3_CMD :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: LOAD_EMODE3_CMD :: cmd [15:00] */ -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_MASK 0x0000ffff -#define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_SHIFT 0 - -/*************************************************************************** - *ZQ_CALIBRATE - Host Initiated ZQ Calibration Cycle - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: ZQ_CALIBRATE :: reserved0 [31:16] */ -#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: ZQ_CALIBRATE :: cmd [15:00] */ -#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_MASK 0x0000ffff -#define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_SHIFT 0 - -/*************************************************************************** - *CMD_STATUS - Host Command Interface Status - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: CMD_STATUS :: reserved0 [31:01] */ -#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: CMD_STATUS :: status [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_SHIFT 0 - -/*************************************************************************** - *LATENCY - DDR2 Controller Access Latency Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: LATENCY :: reserved0 [31:10] */ -#define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_MASK 0xfffffc00 -#define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_SHIFT 10 - -/* DDR23_CTL_REGS_0 :: LATENCY :: limit [09:00] */ -#define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_MASK 0x000003ff -#define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE0 - Semaphore Register #0 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: SEMAPHORE0 :: reserved0 [31:01] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: SEMAPHORE0 :: enable [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE1 - Semaphore Register #1 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: SEMAPHORE1 :: reserved0 [31:01] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: SEMAPHORE1 :: enable [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE2 - Semaphore Register #2 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: SEMAPHORE2 :: reserved0 [31:01] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: SEMAPHORE2 :: enable [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE3 - Semaphore Register #3 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: SEMAPHORE3 :: reserved0 [31:01] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: SEMAPHORE3 :: enable [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_SHIFT 0 - -/*************************************************************************** - *SCRATCH - Scratch Register - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: SCRATCH :: scratch [31:00] */ -#define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_MASK 0xffffffff -#define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_SHIFT 0 - -/*************************************************************************** - *STRIPE_WIDTH - Stripe Width - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: STRIPE_WIDTH :: reserved0 [31:02] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_MASK 0xfffffffc -#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_SHIFT 2 - -/* DDR23_CTL_REGS_0 :: STRIPE_WIDTH :: swidth [01:00] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_MASK 0x00000003 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_SHIFT 0 - -/*************************************************************************** - *STRIPE_HEIGHT_0 - Stripe Height for picture buffers 0 through 23 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: reserved0 [31:27] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_MASK 0xf8000000 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_SHIFT 27 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: chroma_height [26:16] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_MASK 0x07ff0000 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: reserved1 [15:11] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_MASK 0x0000f800 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_SHIFT 11 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: luma_height [10:00] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_MASK 0x000007ff -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_SHIFT 0 - -/*************************************************************************** - *STRIPE_HEIGHT_1 - Stripe Height for picture buffers 24 through 27 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: reserved0 [31:27] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_MASK 0xf8000000 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_SHIFT 27 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: chroma_height [26:16] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_MASK 0x07ff0000 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: reserved1 [15:11] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_MASK 0x0000f800 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_SHIFT 11 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: luma_height [10:00] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_MASK 0x000007ff -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_SHIFT 0 - -/*************************************************************************** - *STRIPE_HEIGHT_2 - Stripe Height for picture buffers 28 through 31 - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: reserved0 [31:27] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_MASK 0xf8000000 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_SHIFT 27 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: chroma_height [26:16] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_MASK 0x07ff0000 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: reserved1 [15:11] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_MASK 0x0000f800 -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_SHIFT 11 - -/* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: luma_height [10:00] */ -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_MASK 0x000007ff -#define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_SHIFT 0 - -/*************************************************************************** - *PHYBIST_CNTRL - DDR Phy-Bist Control and Status - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:18] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xfffc0000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 18 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_error_pos [17:16] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_pos_MASK 0x00030000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_pos_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [15:14] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 14 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: reserved2 [07:05] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved2_MASK 0x000000e0 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved2_SHIFT 5 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [04:04] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000010 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 4 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [03:03] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000008 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 3 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_cs_n [02:02] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_cs_n_MASK 0x00000004 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_cs_n_SHIFT 2 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_odt [01:01] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_odt_MASK 0x00000002 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_odt_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_enable_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_enable_SHIFT 0 - -/*************************************************************************** - *PHYBIST_SEED - DDR Phy-Bist PRPG Seed Value - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_SEED_seed_MASK 0xffffffff -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_SEED_seed_SHIFT 0 - -/*************************************************************************** - *PHYBIST_CTL_STATUS - DDR Phy-Bist Address & Control Status - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_ras_n [26:26] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ras_n_MASK 0x04000000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ras_n_SHIFT 26 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_cas_n [25:25] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cas_n_MASK 0x02000000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cas_n_SHIFT 25 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_we_n [24:24] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_we_n_MASK 0x01000000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_we_n_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_cke [23:23] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cke_MASK 0x00800000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cke_SHIFT 23 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_odt [22:22] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_odt_MASK 0x00400000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_odt_SHIFT 22 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_reset [21:21] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_reset_MASK 0x00200000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_reset_SHIFT 21 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_ad [20:07] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ad_MASK 0x001fff80 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ad_SHIFT 7 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_ba [06:04] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ba_MASK 0x00000070 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ba_SHIFT 4 - -/* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_aux [03:00] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_aux_MASK 0x0000000f -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_aux_SHIFT 0 - -/*************************************************************************** - *PHYBIST_DQ_STATUS - DDR Phy-Bist DQ Status - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq3 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq3_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq3_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq2 [23:16] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq2_MASK 0x00ff0000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq2_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq1 [15:08] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq1_MASK 0x0000ff00 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq1_SHIFT 8 - -/* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq0 [07:00] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq0_MASK 0x000000ff -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq0_SHIFT 0 - -/*************************************************************************** - *PHYBIST_MISC_STATUS - DDR Phy-Bist Miscellaneous Status - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: dat_done [31:31] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_dat_done_MASK 0x80000000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_dat_done_SHIFT 31 - -/* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: ctl_done [30:30] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ctl_done_MASK 0x40000000 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ctl_done_SHIFT 30 - -/* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [29:08] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0x3fffff00 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8 - -/* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: ddr_dm [07:04] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_dm_MASK 0x000000f0 -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_dm_SHIFT 4 - -/* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: ddr_clk [03:00] */ -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_clk_MASK 0x0000000f -#define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_clk_SHIFT 0 - -/*************************************************************************** - *VDL_CTL - Dynamic VDL Changes Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: VDL_CTL :: reserved0 [31:01] */ -#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: VDL_CTL :: enable [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_SHIFT 0 - -/*************************************************************************** - *VDL_ADR_BASE - Dynamic VDL Changes Base Address - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: VDL_ADR_BASE :: addr [31:00] */ -#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_MASK 0xffffffff -#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_SHIFT 0 - -/*************************************************************************** - *VDL_ADR_END - Dynamic VDL Changes End Address - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: VDL_ADR_END :: addr [31:00] */ -#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_MASK 0xffffffff -#define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_SHIFT 0 - -/*************************************************************************** - *PMON_CTL - Performance Monitoring Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_CTL :: reserved0 [31:01] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: PMON_CTL :: enable [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_SHIFT 0 - -/*************************************************************************** - *PMON_PERIOD - Performance Monitoring Period Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_PERIOD :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_PERIOD :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_SHIFT 0 - -/*************************************************************************** - *PMON_CYCLE_CNT - Performance Monitoring Active Cycles Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_CYCLE_CNT :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_CYCLE_CNT :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_SHIFT 0 - -/*************************************************************************** - *PMON_IDLE_CNT - Performance Monitoring Idle Cycles Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_IDLE_CNT :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_IDLE_CNT :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_SHIFT 0 - -/*************************************************************************** - *PMON_RD_CNT1 - Performance Monitoring Data Channel #1 Read Accesses Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_RD_CNT1 :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_RD_CNT1 :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_SHIFT 0 - -/*************************************************************************** - *PMON_RD_CNT2 - Performance Monitoring Data Channel #2 Read Accesses Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_RD_CNT2 :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_RD_CNT2 :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_SHIFT 0 - -/*************************************************************************** - *PMON_RD_CNT3 - Performance Monitoring Data Channel #3 Read Accesses Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_RD_CNT3 :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_RD_CNT3 :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_SHIFT 0 - -/*************************************************************************** - *PMON_WR_CNT1 - Performance Monitoring Data Channel #1 Write Accesses Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_WR_CNT1 :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_WR_CNT1 :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_SHIFT 0 - -/*************************************************************************** - *PMON_WR_CNT2 - Performance Monitoring Data Channel #2 Write Accesses Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_WR_CNT2 :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_WR_CNT2 :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_SHIFT 0 - -/*************************************************************************** - *PMON_WR_CNT3 - Performance Monitoring Data Channel #3 Write Accesses Count - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PMON_WR_CNT3 :: reserved0 [31:24] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_MASK 0xff000000 -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_SHIFT 24 - -/* DDR23_CTL_REGS_0 :: PMON_WR_CNT3 :: count [23:00] */ -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_MASK 0x00ffffff -#define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_SHIFT 0 - -/*************************************************************************** - *DDR_TM - RAM Macro TM Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: DDR_TM :: reserved0 [31:22] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_reserved0_MASK 0xffc00000 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_reserved0_SHIFT 22 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: sdc [21:20] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_sdc_MASK 0x00300000 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_sdc_SHIFT 20 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: row [19:18] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_row_MASK 0x000c0000 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_row_SHIFT 18 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: col [17:16] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_col_MASK 0x00030000 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_col_SHIFT 16 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: pic [15:14] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_pic_MASK 0x0000c000 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_pic_SHIFT 14 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: wrf3 [13:12] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf3_MASK 0x00003000 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf3_SHIFT 12 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: wrf2 [11:10] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf2_MASK 0x00000c00 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf2_SHIFT 10 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: wrf1 [09:08] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf1_MASK 0x00000300 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf1_SHIFT 8 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: rdf3 [07:06] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf3_MASK 0x000000c0 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf3_SHIFT 6 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: rdf2 [05:04] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf2_MASK 0x00000030 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf2_SHIFT 4 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: rdf1_1 [03:02] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_1_MASK 0x0000000c -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_1_SHIFT 2 - -/* DDR23_CTL_REGS_0 :: DDR_TM :: rdf1_0 [01:00] */ -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_0_MASK 0x00000003 -#define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_0_SHIFT 0 - -/*************************************************************************** - *UPDATE_VDL - RAM Macro TM Control - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: UPDATE_VDL :: reserved0 [31:02] */ -#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_MASK 0xfffffffc -#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_SHIFT 2 - -/* DDR23_CTL_REGS_0 :: UPDATE_VDL :: force [01:01] */ -#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_MASK 0x00000002 -#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_SHIFT 1 - -/* DDR23_CTL_REGS_0 :: UPDATE_VDL :: refresh [00:00] */ -#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK 0x00000001 -#define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_SHIFT 0 - -/*************************************************************************** - *PICT_BASE%i - Picture Buffer Base Address Ram - ***************************************************************************/ -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_BASE 0x01800100 -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_START 0 -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_END 63 -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *PICT_BASE%i - Picture Buffer Base Address Ram - ***************************************************************************/ -/* DDR23_CTL_REGS_0 :: PICT_BASEi :: address [31:12] */ -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_MASK 0xfffff000 -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_SHIFT 12 - -/* DDR23_CTL_REGS_0 :: PICT_BASEi :: reserved0 [11:00] */ -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_MASK 0x00000fff -#define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_SHIFT 0 - - -#endif /* #ifndef BCHP_DDR23_CTL_REGS_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,635 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_ddr23_phy_byte_lane_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:59p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:18 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:59p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ -#define BCHP_DDR23_PHY_BYTE_LANE_0_H__ - -/*************************************************************************** - *DDR23_PHY_BYTE_LANE_0 - DDR23 DDR23 byte lane #0 control registers - ***************************************************************************/ -#define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION 0x01801200 /* Byte lane revision register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE 0x01801204 /* Byte lane VDL calibration control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS 0x01801208 /* Byte lane VDL calibration status register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x01801210 /* Read DQSP VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x01801214 /* Read DQSN VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x01801218 /* Read Enable VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x0180121c /* Write data and mask VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4 0x01801220 /* Read DQSP VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5 0x01801224 /* Read DQSN VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6 0x01801228 /* Read Enable VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7 0x0180122c /* Write data and mask VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL 0x01801230 /* Byte Lane read channel control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x01801234 /* Read fifo status register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x01801238 /* Read fifo status clear register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x0180123c /* Idle mode SSTL pad control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x01801240 /* SSTL pad drive characteristics control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE 0x01801244 /* Clock pad disable register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x01801248 /* Write cycle preamble control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL 0x0180124c /* Clock Regulator control register */ - - -/*************************************************************************** - *REVISION - Byte lane revision register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: REVISION :: reserved0 [31:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_reserved0_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MAJOR [15:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MAJOR_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MINOR [07:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MINOR_MASK 0x000000ff -#define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *VDL_CALIBRATE - Byte lane VDL calibration control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: reserved0 [31:05] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_reserved0_MASK 0xffffffe0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_reserved0_SHIFT 5 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_clocks [04:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_clocks_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_test [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_test_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_test_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_always [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_always_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_always_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_once [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_once_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_once_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_fast [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_fast_SHIFT 0 - -/*************************************************************************** - *VDL_STATUS - Byte lane VDL calibration status register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved0 [31:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved0_MASK 0xffffc000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved0_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_total [13:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_total_MASK 0x00003ff0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_total_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved1 [03:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved1_MASK 0x0000000c -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved1_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_lock [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_lock_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_lock_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_idle [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_idle_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_idle_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_0 - Read DQSP VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_1 - Read DQSN VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_2 - Read Enable VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_3 - Write data and mask VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_4 - Read DQSP VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_5 - Read DQSN VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_6 - Read Enable VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_7 - Write data and mask VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_step_SHIFT 0 - -/*************************************************************************** - *READ_CONTROL - Byte Lane read channel control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved0 [31:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_MASK 0xfffffc00 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_data_dly [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved1 [07:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_MASK 0x000000f0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_adj [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_SHIFT 0 - -/*************************************************************************** - *READ_FIFO_STATUS - Read fifo status register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: status [03:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_status_MASK 0x0000000f -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_status_SHIFT 0 - -/*************************************************************************** - *READ_FIFO_CLEAR - Read fifo status clear register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: clear [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_clear_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_clear_SHIFT 0 - -/*************************************************************************** - *IDLE_PAD_CONTROL - Idle mode SSTL pad control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK 0x80000000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_SHIFT 31 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_rxenb_MASK 0x00080000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_rxenb_SHIFT 19 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_SHIFT 18 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_reb_MASK 0x00020000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_reb_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_oeb_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_oeb_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00008000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 15 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_reb_MASK 0x00002000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 13 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_oeb_MASK 0x00001000 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00000800 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 11 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00000200 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 9 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00000100 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000080 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 7 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000020 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 5 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000010 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_rxenb_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_rxenb_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_reb_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_reb_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_oeb_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_oeb_SHIFT 0 - -/*************************************************************************** - *DRIVE_PAD_CTL - SSTL pad drive characteristics control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffffc0 -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_MASK 0x00000020 -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_SHIFT 5 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b [04:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: slew [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_SHIFT 0 - -/*************************************************************************** - *CLOCK_PAD_DISABLE - Clock pad disable register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_clk_pad_dis_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_clk_pad_dis_SHIFT 0 - -/*************************************************************************** - *WR_PREAMBLE_MODE - Write cycle preamble control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: mode [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_mode_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_mode_SHIFT 0 - -/*************************************************************************** - *CLOCK_REG_CONTROL - Clock Regulator control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_reserved0_MASK 0xfffffffc -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_reserved0_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: half_power [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_half_power_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_half_power_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_SHIFT 0 - -#endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,634 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_ddr23_phy_byte_lane_1.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:59p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:17 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:59p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ -#define BCHP_DDR23_PHY_BYTE_LANE_1_H__ - -/*************************************************************************** - *DDR23_PHY_BYTE_LANE_1 - DDR23 DDR23 byte lane #1 control registers - ***************************************************************************/ -#define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION 0x01801100 /* Byte lane revision register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE 0x01801104 /* Byte lane VDL calibration control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS 0x01801108 /* Byte lane VDL calibration status register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x01801110 /* Read DQSP VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x01801114 /* Read DQSN VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x01801118 /* Read Enable VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x0180111c /* Write data and mask VDL static override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4 0x01801120 /* Read DQSP VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5 0x01801124 /* Read DQSN VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6 0x01801128 /* Read Enable VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7 0x0180112c /* Write data and mask VDL dynamic override control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL 0x01801130 /* Byte Lane read channel control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x01801134 /* Read fifo status register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x01801138 /* Read fifo status clear register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x0180113c /* Idle mode SSTL pad control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x01801140 /* SSTL pad drive characteristics control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x01801144 /* Clock pad disable register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x01801148 /* Write cycle preamble control register */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL 0x0180114c /* Clock Regulator control register */ - -/*************************************************************************** - *REVISION - Byte lane revision register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: REVISION :: reserved0 [31:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_reserved0_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MAJOR [15:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MAJOR_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MINOR [07:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MINOR_MASK 0x000000ff -#define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *VDL_CALIBRATE - Byte lane VDL calibration control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: reserved0 [31:05] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_reserved0_MASK 0xffffffe0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_reserved0_SHIFT 5 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_clocks [04:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_clocks_MASK 0x00000010 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_clocks_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_test [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_test_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_test_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_always [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_always_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_always_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_once [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_once_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_once_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_fast [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_fast_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_fast_SHIFT 0 - -/*************************************************************************** - *VDL_STATUS - Byte lane VDL calibration status register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved0 [31:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved0_MASK 0xffffc000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved0_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_total [13:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_total_MASK 0x00003ff0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_total_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved1 [03:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved1_MASK 0x0000000c -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved1_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_lock [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_lock_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_lock_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_idle [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_idle_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_idle_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_0 - Read DQSP VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_1 - Read DQSN VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_2 - Read Enable VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_3 - Write data and mask VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_4 - Read DQSP VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_5 - Read DQSN VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_6 - Read Enable VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_step_SHIFT 0 - -/*************************************************************************** - *VDL_OVERRIDE_7 - Write data and mask VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved0_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_en_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved1_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved2_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved3_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_step_SHIFT 0 - -/*************************************************************************** - *READ_CONTROL - Byte Lane read channel control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved0 [31:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_MASK 0xfffffc00 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_data_dly [09:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_data_dly_MASK 0x00000300 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_data_dly_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved1 [07:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_MASK 0x000000f0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_adj [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_adj_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_adj_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_enable_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_enable_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_adj_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_adj_SHIFT 0 - -/*************************************************************************** - *READ_FIFO_STATUS - Read fifo status register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: status [03:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_status_MASK 0x0000000f -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_status_SHIFT 0 - -/*************************************************************************** - *READ_FIFO_CLEAR - Read fifo status clear register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: clear [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_clear_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_clear_SHIFT 0 - -/*************************************************************************** - *IDLE_PAD_CONTROL - Idle mode SSTL pad control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK 0x80000000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_SHIFT 31 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_rxenb_MASK 0x00080000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_rxenb_SHIFT 19 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_SHIFT 18 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_reb_MASK 0x00020000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_reb_SHIFT 17 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_oeb_MASK 0x00010000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_oeb_SHIFT 16 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00008000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 15 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_SHIFT 14 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_reb_MASK 0x00002000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_reb_SHIFT 13 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_oeb_MASK 0x00001000 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_oeb_SHIFT 12 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00000800 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 11 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 10 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00000200 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 9 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00000100 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 8 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000080 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 7 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000020 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_reb_SHIFT 5 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000010 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_rxenb_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_rxenb_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_reb_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_reb_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_oeb_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_oeb_SHIFT 0 - -/*************************************************************************** - *DRIVE_PAD_CTL - SSTL pad drive characteristics control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_MASK 0xffffffc0 -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_SHIFT 6 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_ddr_read_enb_MASK 0x00000020 -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_ddr_read_enb_SHIFT 5 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b [04:04] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_SHIFT 4 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: slew [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_slew_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_slew_SHIFT 0 - -/*************************************************************************** - *CLOCK_PAD_DISABLE - Clock pad disable register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_reserved0_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_SHIFT 0 - -/*************************************************************************** - *WR_PREAMBLE_MODE - Write cycle preamble control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: mode [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_mode_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_mode_SHIFT 0 - -/*************************************************************************** - *CLOCK_REG_CONTROL - Clock Regulator control register - ***************************************************************************/ -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_reserved0_MASK 0xfffffffc -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_reserved0_SHIFT 2 - -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: half_power [01:01] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_half_power_MASK 0x00000002 -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_half_power_SHIFT 1 - -/* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 -#define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_SHIFT 0 - -#endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,542 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_ddr23_phy_control_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:59p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:21 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:59p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ -#define BCHP_DDR23_PHY_CONTROL_REGS_H__ - -/*************************************************************************** - *DDR23_PHY_CONTROL_REGS - DDR23 DDR23 physical interface control registers - ***************************************************************************/ -#define BCHP_DDR23_PHY_CONTROL_REGS_REVISION 0x01801000 /* Address & Control revision register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL 0x01801004 /* PHY clock power management control register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS 0x01801010 /* PHY PLL status register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG 0x01801014 /* PHY PLL configuration register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x01801018 /* PHY PLL pre-divider control register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER 0x0180101c /* PHY PLL divider control register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1 0x01801020 /* PHY PLL analog control register #1 */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2 0x01801024 /* PHY PLL analog control register #2 */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN 0x01801028 /* PHY PLL spread spectrum config register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG 0x0180102c /* PHY PLL spread spectrum config register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x01801030 /* Address & Control VDL static override control register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE 0x01801034 /* Address & Control VDL dynamic override control register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x01801038 /* Idle mode SSTL pad control register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x0180103c /* PVT Compensation control and status register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x01801040 /* SSTL pad drive characteristics control register */ -#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL 0x01801044 /* Clock Regulator control register */ - -/*************************************************************************** - *REVISION - Address & Control revision register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:16] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_reserved0_SHIFT 16 - -/* DDR23_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8 - -/* DDR23_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0x000000ff -#define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CLK_PM_CTRL - PHY clock power management control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: CLK_PM_CTRL :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0 - -/*************************************************************************** - *PLL_STATUS - PHY PLL status register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_reserved0_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT 0 - -/*************************************************************************** - *PLL_CONFIG - PHY PLL configuration register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: DIV2_CLK_RESET [31:31] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DIV2_CLK_RESET_MASK 0x80000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DIV2_CLK_RESET_SHIFT 31 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [30:22] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_MASK 0x7fc00000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_SHIFT 22 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: TEST_SEL [21:17] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_SEL_MASK 0x003e0000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_SEL_SHIFT 17 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: TEST_EN [16:16] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_EN_MASK 0x00010000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_EN_SHIFT 16 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: BGAP_ADJ [15:12] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BGAP_ADJ_MASK 0x0000f000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BGAP_ADJ_SHIFT 12 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved1 [11:08] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_MASK 0x00000f00 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_SHIFT 8 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: VCO_RNG [07:07] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_VCO_RNG_MASK 0x00000080 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_VCO_RNG_SHIFT 7 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN_CH1 [06:06] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_CH1_MASK 0x00000040 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_CH1_SHIFT 6 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: BYPEN [05:05] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BYPEN_MASK 0x00000020 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BYPEN_SHIFT 5 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: ENB_CLKOUT [04:04] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_MASK 0x00000010 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_SHIFT 4 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: DRESET [03:03] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DRESET_MASK 0x00000008 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DRESET_SHIFT 3 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: ARESET [02:02] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ARESET_MASK 0x00000004 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ARESET_SHIFT 2 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved2 [01:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_MASK 0x00000002 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT 0 - -/*************************************************************************** - *PLL_PRE_DIVIDER - PHY PLL pre-divider control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: reserved0 [31:27] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved0_MASK 0xf8000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved0_SHIFT 27 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_DITHER_MFB [26:26] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_MASK 0x04000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_SHIFT 26 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_PWRDN [25:25] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_PWRDN_MASK 0x02000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_PWRDN_SHIFT 25 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: reserved1 [24:23] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved1_MASK 0x01800000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved1_SHIFT 23 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_MODE [22:20] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_MODE_MASK 0x00700000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_MODE_SHIFT 20 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: reserved2 [19:17] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved2_MASK 0x000e0000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved2_SHIFT 17 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_INT [16:08] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_INT_MASK 0x0001ff00 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_INT_SHIFT 8 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: P2DIV [07:04] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P2DIV_MASK 0x000000f0 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P2DIV_SHIFT 4 - -/* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: P1DIV [03:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P1DIV_MASK 0x0000000f -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P1DIV_SHIFT 0 - -/*************************************************************************** - *PLL_DIVIDER - PHY PLL divider control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_DIVIDER :: M1DIV [31:24] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_M1DIV_MASK 0xff000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_M1DIV_SHIFT 24 - -/* DDR23_PHY_CONTROL_REGS :: PLL_DIVIDER :: NDIV_FRAC [23:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_NDIV_FRAC_MASK 0x00ffffff -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_NDIV_FRAC_SHIFT 0 - -/*************************************************************************** - *PLL_CONTROL1 - PHY PLL analog control register #1 - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: TESTA_SEL [31:30] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_TESTA_SEL_MASK 0xc0000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_TESTA_SEL_SHIFT 30 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: KVCO_XS [29:27] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XS_MASK 0x38000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XS_SHIFT 27 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: KVCO_XF [26:24] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XF_MASK 0x07000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XF_SHIFT 24 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: LPF_BW [23:22] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LPF_BW_MASK 0x00c00000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LPF_BW_SHIFT 22 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: LF_ORDER [21:21] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LF_ORDER_MASK 0x00200000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LF_ORDER_SHIFT 21 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: CN [20:19] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CN_MASK 0x00180000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CN_SHIFT 19 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: RN [18:17] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RN_MASK 0x00060000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RN_SHIFT 17 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: CP [16:15] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CP_MASK 0x00018000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CP_SHIFT 15 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: CZ [14:13] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CZ_MASK 0x00006000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CZ_SHIFT 13 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: RZ [12:10] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RZ_MASK 0x00001c00 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RZ_SHIFT 10 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: ICPX [09:05] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICPX_MASK 0x000003e0 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICPX_SHIFT 5 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: ICP_OFF [04:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICP_OFF_MASK 0x0000001f -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICP_OFF_SHIFT 0 - -/*************************************************************************** - *PLL_CONTROL2 - PHY PLL analog control register #2 - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: reserved0 [31:06] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_reserved0_MASK 0xffffffc0 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_reserved0_SHIFT 6 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: PTAP_ADJ [05:04] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_PTAP_ADJ_MASK 0x00000030 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_PTAP_ADJ_SHIFT 4 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: CTAP_ADJ [03:02] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_CTAP_ADJ_MASK 0x0000000c -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_CTAP_ADJ_SHIFT 2 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: LOWCUR_EN [01:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_LOWCUR_EN_MASK 0x00000002 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_LOWCUR_EN_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: BIASIN_EN [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_BIASIN_EN_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_BIASIN_EN_SHIFT 0 - -/*************************************************************************** - *PLL_SS_EN - PHY PLL spread spectrum config register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_SS_EN :: reserved0 [31:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_reserved0_MASK 0xfffffffe -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_reserved0_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: PLL_SS_EN :: SS_EN [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_SS_EN_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_SS_EN_SHIFT 0 - -/*************************************************************************** - *PLL_SS_CFG - PHY PLL spread spectrum config register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: PLL_SS_CFG :: REF_CYC_PER_TICK [31:16] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_REF_CYC_PER_TICK_MASK 0xffff0000 -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_REF_CYC_PER_TICK_SHIFT 16 - -/* DDR23_PHY_CONTROL_REGS :: PLL_SS_CFG :: NDIV_AMP [15:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_NDIV_AMP_MASK 0x0000ffff -#define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_NDIV_AMP_SHIFT 0 - -/*************************************************************************** - *STATIC_VDL_OVERRIDE - Address & Control VDL static override control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved0 [31:21] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved0_MASK 0xffe00000 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved0_SHIFT 21 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_force [20:20] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_force_MASK 0x00100000 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_force_SHIFT 20 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved1 [19:17] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved1_MASK 0x000e0000 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved1_SHIFT 17 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_en_SHIFT 16 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved2 [15:14] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved2_MASK 0x0000c000 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved2_SHIFT 14 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved3 [11:10] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved3_MASK 0x00000c00 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved3_SHIFT 10 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved4 [07:06] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved4_MASK 0x000000c0 -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved4_SHIFT 6 - -/* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_step_SHIFT 0 - -/*************************************************************************** - *DYNAMIC_VDL_OVERRIDE - Address & Control VDL dynamic override control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved0 [31:17] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved0_MASK 0xfffe0000 -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved0_SHIFT 17 - -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_en [16:16] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_en_MASK 0x00010000 -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_en_SHIFT 16 - -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved1 [15:14] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved1_MASK 0x0000c000 -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved1_SHIFT 14 - -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_fall_MASK 0x00003000 -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_fall_SHIFT 12 - -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved2 [11:10] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved2_MASK 0x00000c00 -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved2_SHIFT 10 - -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_rise_MASK 0x00000300 -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_rise_SHIFT 8 - -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved3 [07:06] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved3_MASK 0x000000c0 -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved3_SHIFT 6 - -/* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_step [05:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_step_MASK 0x0000003f -#define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_step_SHIFT 0 - -/*************************************************************************** - *IDLE_PAD_CONTROL - Idle mode SSTL pad control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: idle [31:31] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK 0x80000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_SHIFT 31 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [30:09] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_SHIFT 9 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: rxenb [08:08] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK 0x00000100 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_SHIFT 8 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved1 [07:07] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_SHIFT 7 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved2 [03:03] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_SHIFT 3 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_reb [01:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0 - -/*************************************************************************** - *ZQ_PVT_COMP_CTL - PVT Compensation control and status register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: reserved0 [31:31] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_MASK 0x80000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_SHIFT 31 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_done [30:30] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_MASK 0x40000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_SHIFT 30 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_done [29:29] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_MASK 0x20000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_SHIFT 29 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_done [28:28] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK 0x10000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_SHIFT 28 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: auto_sample_en [27:27] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x08000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 27 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_en [26:26] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK 0x04000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_SHIFT 26 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_ovr_en [25:25] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x02000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 25 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_ovr_en [24:24] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x01000000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 24 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_comp [23:20] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00f00000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 20 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_comp [19:16] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x000f0000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 16 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [15:12] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x0000f000 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 12 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [11:08] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x00000f00 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 8 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [07:04] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x000000f0 -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 4 - -/* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [03:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x0000000f -#define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0 - -/*************************************************************************** - *DRIVE_PAD_CTL - SSTL pad drive characteristics control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:05] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_MASK 0xffffffe0 -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_SHIFT 5 - -/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt60b [04:04] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_SHIFT 4 - -/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 - -/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 - -/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: slew [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_SHIFT 0 - -/*************************************************************************** - *CLOCK_REG_CONTROL - Clock Regulator control register - ***************************************************************************/ -/* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_reserved0_MASK 0xfffffffc -#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_reserved0_SHIFT 2 - -/* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: half_power [01:01] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_half_power_MASK 0x00000002 -#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_half_power_SHIFT 1 - -/* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ -#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 -#define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_SHIFT 0 - -#endif /* #ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpuaux_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:00p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:00 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:00p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUAUX_0_H__ -#define BCHP_DECODE_CPUAUX_0_H__ - -/*************************************************************************** - *DECODE_CPUAUX_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUAUX_0_CPUAUX_REG 0x00845000 /* CPUAUX_REG */ -#define BCHP_DECODE_CPUAUX_0_CPUAUX_END 0x00845ffc /* CPUAUX_END */ - -/*************************************************************************** - *CPUAUX_REG - CPUAUX_REG - ***************************************************************************/ -/* DECODE_CPUAUX_0 :: CPUAUX_REG :: Addr [31:00] */ -#define BCHP_DECODE_CPUAUX_0_CPUAUX_REG_Addr_MASK 0xffffffff -#define BCHP_DECODE_CPUAUX_0_CPUAUX_REG_Addr_SHIFT 0 - -/*************************************************************************** - *CPUAUX_END - CPUAUX_END - ***************************************************************************/ -/* DECODE_CPUAUX_0 :: CPUAUX_END :: reserved0 [31:00] */ -#define BCHP_DECODE_CPUAUX_0_CPUAUX_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_CPUAUX_0_CPUAUX_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_CPUAUX_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpuaux2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 7:59p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:35 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 7:59p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUAUX2_0_H__ -#define BCHP_DECODE_CPUAUX2_0_H__ - -/*************************************************************************** - *DECODE_CPUAUX2_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUAUX2_0_CPUAUX_REG 0x00855000 /* CPUAUX_REG */ -#define BCHP_DECODE_CPUAUX2_0_CPUAUX_END 0x00855ffc /* CPUAUX_END */ - -#endif /* #ifndef BCHP_DECODE_CPUAUX2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpucore_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:00p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:26 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:00p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUCORE_0_H__ -#define BCHP_DECODE_CPUCORE_0_H__ - -/*************************************************************************** - *DECODE_CPUCORE_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUCORE_0_CPUCORE_REG 0x00844000 /* CPUCORE_REG */ -#define BCHP_DECODE_CPUCORE_0_CPUCORE_END 0x00844ffc /* CPUCORE_END */ - -/*************************************************************************** - *CPUCORE_REG - CPUCORE_REG - ***************************************************************************/ -/* DECODE_CPUCORE_0 :: CPUCORE_REG :: Addr [31:00] */ -#define BCHP_DECODE_CPUCORE_0_CPUCORE_REG_Addr_MASK 0xffffffff -#define BCHP_DECODE_CPUCORE_0_CPUCORE_REG_Addr_SHIFT 0 - -/*************************************************************************** - *CPUCORE_END - CPUCORE_END - ***************************************************************************/ -/* DECODE_CPUCORE_0 :: CPUCORE_END :: reserved0 [31:00] */ -#define BCHP_DECODE_CPUCORE_0_CPUCORE_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_CPUCORE_0_CPUCORE_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_CPUCORE_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpucore2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:00p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:08 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:00p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUCORE2_0_H__ -#define BCHP_DECODE_CPUCORE2_0_H__ - -/*************************************************************************** - *DECODE_CPUCORE2_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUCORE2_0_CPUCORE_REG 0x00854000 /* CPUCORE_REG */ -#define BCHP_DECODE_CPUCORE2_0_CPUCORE_END 0x00854ffc /* CPUCORE_END */ - -#endif /* #ifndef BCHP_DECODE_CPUCORE2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,282 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpudma_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:01p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:10 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:01p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUDMA_0_H__ -#define BCHP_DECODE_CPUDMA_0_H__ - -/*************************************************************************** - *DECODE_CPUDMA_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR 0x00801800 /* SDRAM address */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR 0x00801804 /* Local Memory Address */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN 0x00801808 /* Length */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR 0x00801810 /* REG_DMA1_SD_ADDR */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR 0x00801814 /* REG_DMA1_LCL_ADDR */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN 0x00801818 /* REG_DMA1_LEN */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR 0x00801820 /* REG_DMA2_SD_ADDR */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR 0x00801824 /* REG_DMA2_LCL_ADDR */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN 0x00801828 /* REG_DMA2_LEN */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR 0x00801830 /* REG_DMA3_SD_ADDR */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR 0x00801834 /* REG_DMA3_LCL_ADDR */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN 0x00801838 /* REG_DMA3_LEN */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS 0x00801840 /* REG_DMA_STATUS */ -#define BCHP_DECODE_CPUDMA_0_REG_CPUDMA_END 0x008018fc /* REG_CPUDMA_END */ - -/*************************************************************************** - *REG_DMA0_SD_ADDR - SDRAM address - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA0_SD_ADDR :: Sd_Addr [31:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_Sd_Addr_MASK 0xfffffffc -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_Sd_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA0_SD_ADDR :: reserved0 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_reserved0_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_DMA0_LCL_ADDR - Local Memory Address - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA0_LCL_ADDR :: reserved0 [31:10] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved0_MASK 0xfffffc00 -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved0_SHIFT 10 - -/* DECODE_CPUDMA_0 :: REG_DMA0_LCL_ADDR :: Addr [09:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_Addr_MASK 0x000003fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA0_LCL_ADDR :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA0_LEN - Length - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: Swap [31:31] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Swap_MASK 0x80000000 -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Swap_SHIFT 31 - -/* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: reserved0 [30:11] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved0_MASK 0x7ffff800 -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved0_SHIFT 11 - -/* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: Length [10:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Length_MASK 0x000007fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Length_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA1_SD_ADDR - REG_DMA1_SD_ADDR - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA1_SD_ADDR :: Sd_Addr [31:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_Sd_Addr_MASK 0xfffffffc -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_Sd_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA1_SD_ADDR :: reserved0 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_reserved0_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_DMA1_LCL_ADDR - REG_DMA1_LCL_ADDR - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA1_LCL_ADDR :: reserved0 [31:10] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved0_MASK 0xfffffc00 -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved0_SHIFT 10 - -/* DECODE_CPUDMA_0 :: REG_DMA1_LCL_ADDR :: Addr [09:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_Addr_MASK 0x000003fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA1_LCL_ADDR :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA1_LEN - REG_DMA1_LEN - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: Swap [31:31] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Swap_MASK 0x80000000 -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Swap_SHIFT 31 - -/* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: reserved0 [30:11] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved0_MASK 0x7ffff800 -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved0_SHIFT 11 - -/* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: Length [10:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Length_MASK 0x000007fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Length_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA2_SD_ADDR - REG_DMA2_SD_ADDR - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA2_SD_ADDR :: Sd_Addr [31:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_Sd_Addr_MASK 0xfffffffc -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_Sd_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA2_SD_ADDR :: reserved0 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_reserved0_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_DMA2_LCL_ADDR - REG_DMA2_LCL_ADDR - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA2_LCL_ADDR :: reserved0 [31:10] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved0_MASK 0xfffffc00 -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved0_SHIFT 10 - -/* DECODE_CPUDMA_0 :: REG_DMA2_LCL_ADDR :: Addr [09:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_Addr_MASK 0x000003fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA2_LCL_ADDR :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA2_LEN - REG_DMA2_LEN - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: Swap [31:31] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Swap_MASK 0x80000000 -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Swap_SHIFT 31 - -/* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: reserved0 [30:11] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved0_MASK 0x7ffff800 -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved0_SHIFT 11 - -/* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: Length [10:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Length_MASK 0x000007fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Length_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA3_SD_ADDR - REG_DMA3_SD_ADDR - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA3_SD_ADDR :: Sd_Addr [31:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_Sd_Addr_MASK 0xfffffffc -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_Sd_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA3_SD_ADDR :: reserved0 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_reserved0_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_DMA3_LCL_ADDR - REG_DMA3_LCL_ADDR - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA3_LCL_ADDR :: reserved0 [31:10] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved0_MASK 0xfffffc00 -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved0_SHIFT 10 - -/* DECODE_CPUDMA_0 :: REG_DMA3_LCL_ADDR :: Addr [09:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_Addr_MASK 0x000003fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_Addr_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA3_LCL_ADDR :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA3_LEN - REG_DMA3_LEN - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: Swap [31:31] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Swap_MASK 0x80000000 -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Swap_SHIFT 31 - -/* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: reserved0 [30:11] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved0_MASK 0x7ffff800 -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved0_SHIFT 11 - -/* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: Length [10:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Length_MASK 0x000007fc -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Length_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: reserved1 [01:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved1_MASK 0x00000003 -#define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_DMA_STATUS - REG_DMA_STATUS - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: reserved0 [31:04] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_reserved0_SHIFT 4 - -/* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act3 [03:03] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act3_MASK 0x00000008 -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act3_SHIFT 3 - -/* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act2 [02:02] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act2_MASK 0x00000004 -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act2_SHIFT 2 - -/* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act1 [01:01] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act1_MASK 0x00000002 -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act1_SHIFT 1 - -/* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act0 [00:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act0_MASK 0x00000001 -#define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act0_SHIFT 0 - -/*************************************************************************** - *REG_CPUDMA_END - REG_CPUDMA_END - ***************************************************************************/ -/* DECODE_CPUDMA_0 :: REG_CPUDMA_END :: reserved0 [31:00] */ -#define BCHP_DECODE_CPUDMA_0_REG_CPUDMA_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_CPUDMA_0_REG_CPUDMA_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_CPUDMA_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,72 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpudma2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:00p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:26 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:00p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUDMA2_0_H__ -#define BCHP_DECODE_CPUDMA2_0_H__ - -/*************************************************************************** - *DECODE_CPUDMA2_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA0_SD_ADDR 0x00851800 /* SDRAM address */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA0_LCL_ADDR 0x00851804 /* Local Memory Address */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA0_LEN 0x00851808 /* Length */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA1_SD_ADDR 0x00851810 /* REG_DMA1_SD_ADDR */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA1_LCL_ADDR 0x00851814 /* REG_DMA1_LCL_ADDR */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA1_LEN 0x00851818 /* REG_DMA1_LEN */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA2_SD_ADDR 0x00851820 /* REG_DMA2_SD_ADDR */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA2_LCL_ADDR 0x00851824 /* REG_DMA2_LCL_ADDR */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA2_LEN 0x00851828 /* REG_DMA2_LEN */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA3_SD_ADDR 0x00851830 /* REG_DMA3_SD_ADDR */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA3_LCL_ADDR 0x00851834 /* REG_DMA3_LCL_ADDR */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA3_LEN 0x00851838 /* REG_DMA3_LEN */ -#define BCHP_DECODE_CPUDMA2_0_REG_DMA_STATUS 0x00851840 /* REG_DMA_STATUS */ -#define BCHP_DECODE_CPUDMA2_0_REG_CPUDMA_END 0x008518fc /* REG_CPUDMA_END */ - -#endif /* #ifndef BCHP_DECODE_CPUDMA2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpudmem_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:01p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:12 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:01p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUDMEM_0_H__ -#define BCHP_DECODE_CPUDMEM_0_H__ - -/*************************************************************************** - *DECODE_CPUDMEM_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUDMEM_0_CPUDMEM_REG 0x00848000 /* CPUDMEM_REG */ -#define BCHP_DECODE_CPUDMEM_0_CPUDMEM_END 0x0084fffc /* CPUDMEM_END */ - -/*************************************************************************** - *CPUDMEM_REG - CPUDMEM_REG - ***************************************************************************/ -/* DECODE_CPUDMEM_0 :: CPUDMEM_REG :: Addr [31:00] */ -#define BCHP_DECODE_CPUDMEM_0_CPUDMEM_REG_Addr_MASK 0xffffffff -#define BCHP_DECODE_CPUDMEM_0_CPUDMEM_REG_Addr_SHIFT 0 - -/*************************************************************************** - *CPUDMEM_END - CPUDMEM_END - ***************************************************************************/ -/* DECODE_CPUDMEM_0 :: CPUDMEM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_CPUDMEM_0_CPUDMEM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_CPUDMEM_0_CPUDMEM_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_CPUDMEM_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpudmem2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:01p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:29 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:01p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUDMEM2_0_H__ -#define BCHP_DECODE_CPUDMEM2_0_H__ - -/*************************************************************************** - *DECODE_CPUDMEM2_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUDMEM2_0_CPUDMEM_REG 0x00858000 /* CPUDMEM_REG */ -#define BCHP_DECODE_CPUDMEM2_0_CPUDMEM_END 0x0085fffc /* CPUDMEM_END */ - -#endif /* #ifndef BCHP_DECODE_CPUDMEM2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpuimem_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:02p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:14 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:02p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUIMEM_0_H__ -#define BCHP_DECODE_CPUIMEM_0_H__ - -/*************************************************************************** - *DECODE_CPUIMEM_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUIMEM_0_CPUIMEM_REG 0x00846000 /* CPUIMEM_REG */ -#define BCHP_DECODE_CPUIMEM_0_CPUIMEM_END 0x00847ffc /* CPUIMEM_END */ - -/*************************************************************************** - *CPUIMEM_REG - CPUIMEM_REG - ***************************************************************************/ -/* DECODE_CPUIMEM_0 :: CPUIMEM_REG :: Addr [31:00] */ -#define BCHP_DECODE_CPUIMEM_0_CPUIMEM_REG_Addr_MASK 0xffffffff -#define BCHP_DECODE_CPUIMEM_0_CPUIMEM_REG_Addr_SHIFT 0 - -/*************************************************************************** - *CPUIMEM_END - CPUIMEM_END - ***************************************************************************/ -/* DECODE_CPUIMEM_0 :: CPUIMEM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_CPUIMEM_0_CPUIMEM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_CPUIMEM_0_CPUIMEM_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_CPUIMEM_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpuimem2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:01p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:51 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:01p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUIMEM2_0_H__ -#define BCHP_DECODE_CPUIMEM2_0_H__ - -/*************************************************************************** - *DECODE_CPUIMEM2_0 - ***************************************************************************/ -#define BCHP_DECODE_CPUIMEM2_0_CPUIMEM_REG 0x00856000 /* CPUIMEM_REG */ -#define BCHP_DECODE_CPUIMEM2_0_CPUIMEM_END 0x00857ffc /* CPUIMEM_END */ - -#endif /* #ifndef BCHP_DECODE_CPUIMEM2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,530 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpuregs_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:02p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:23 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:02p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUREGS_0_H__ -#define BCHP_DECODE_CPUREGS_0_H__ - -/*************************************************************************** - *DECODE_CPUREGS_0 - Inner Loop CPU Registers 0 - ***************************************************************************/ -#define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_MBX 0x00800f00 /* Host 2 CPU mailbox register */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_MBX 0x00800f04 /* CPU to Host mailbox register */ -#define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT 0x00800f08 /* Mailbox status flags */ -#define BCHP_DECODE_CPUREGS_0_REG_INST_BASE 0x00800f0c /* Instruction base address register */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA 0x00800f10 /* CPU interrupt enable */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT 0x00800f14 /* CPU interrupt status */ -#define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_STAT 0x00800f18 /* Host to CPU status register */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_STAT 0x00800f1c /* CPU to Host status register */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET 0x00800f20 /* CPU interrupt set register */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR 0x00800f24 /* CPU interrupt clear register */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_ICACHE_MISS 0x00800f28 /* Instruction cache miss counter */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK 0x00800f2c /* CPU interrupt mask register */ -#define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE 0x00800f34 /* End of code register */ -#define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE 0x00800f38 /* Global IO base register */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR 0x00800f3c /* CPU debug trace fifo write */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD 0x00800f40 /* CPU debug trace fifo read */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL 0x00800f44 /* CPU debug trace fifo control */ -#define BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR 0x00800f4c /* Watchdog timer register */ -#define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS 0x00800f50 /* SDRAM Status register */ -#define BCHP_DECODE_CPUREGS_0_REG_CPUREGS_END 0x00800f7c /* Dummy end */ - -/*************************************************************************** - *REG_HST2CPU_MBX - Host 2 CPU mailbox register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_HST2CPU_MBX :: Value [31:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_MBX_Value_MASK 0xffffffff -#define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_MBX_Value_SHIFT 0 - -/*************************************************************************** - *REG_CPU2HST_MBX - CPU to Host mailbox register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU2HST_MBX :: Value [31:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_MBX_Value_MASK 0xffffffff -#define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_MBX_Value_SHIFT 0 - -/*************************************************************************** - *REG_MBX_STAT - Mailbox status flags - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_MBX_STAT :: reserved0 [31:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_reserved0_MASK 0xfffffffc -#define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_reserved0_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_MBX_STAT :: C2H [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_C2H_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_C2H_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_MBX_STAT :: H2C [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_H2C_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_H2C_SHIFT 0 - -/*************************************************************************** - *REG_INST_BASE - Instruction base address register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_INST_BASE :: InstBase [31:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_InstBase_MASK 0xfffffc00 -#define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_InstBase_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_INST_BASE :: reserved0 [09:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_reserved0_MASK 0x000003ff -#define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_CPU_INT_ENA - CPU interrupt enable - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: MBx [31:31] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_MBx_MASK 0x80000000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_MBx_SHIFT 31 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: reserved_for_eco0 [30:11] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco0_MASK 0x7ffff800 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco0_SHIFT 11 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: Watchdog [10:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_Watchdog_MASK 0x00000400 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_Watchdog_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: CAB [09:09] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_CAB_MASK 0x00000200 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_CAB_SHIFT 9 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: SI [08:08] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SI_MASK 0x00000100 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SI_SHIFT 8 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: reserved_for_eco1 [07:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco1_MASK 0x000000fc -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco1_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: RB [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_RB_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_RB_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: SD [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SD_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SD_SHIFT 0 - -/*************************************************************************** - *REG_CPU_INT_STAT - CPU interrupt status - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: MBx [31:31] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_MBx_MASK 0x80000000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_MBx_SHIFT 31 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: reserved0 [30:11] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved0_MASK 0x7ffff800 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved0_SHIFT 11 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: Watchdog [10:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_Watchdog_MASK 0x00000400 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_Watchdog_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: CAB [09:09] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_CAB_MASK 0x00000200 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_CAB_SHIFT 9 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: SI [08:08] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SI_MASK 0x00000100 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SI_SHIFT 8 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: reserved1 [07:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved1_MASK 0x000000fc -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved1_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: RB [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_RB_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_RB_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: SD [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SD_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SD_SHIFT 0 - -/*************************************************************************** - *REG_HST2CPU_STAT - Host to CPU status register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_HST2CPU_STAT :: Value [31:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_STAT_Value_MASK 0xffffffff -#define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_STAT_Value_SHIFT 0 - -/*************************************************************************** - *REG_CPU2HST_STAT - CPU to Host status register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU2HST_STAT :: Value [31:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_STAT_Value_MASK 0xffffffff -#define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_STAT_Value_SHIFT 0 - -/*************************************************************************** - *REG_CPU_INTGEN_SET - CPU interrupt set register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: reserved0 [31:16] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_reserved0_SHIFT 16 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_15 [15:15] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_15_MASK 0x00008000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_15_SHIFT 15 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_14 [14:14] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_14_MASK 0x00004000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_14_SHIFT 14 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_13 [13:13] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_13_MASK 0x00002000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_13_SHIFT 13 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_12 [12:12] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_12_MASK 0x00001000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_12_SHIFT 12 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_11 [11:11] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_11_MASK 0x00000800 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_11_SHIFT 11 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_10 [10:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_10_MASK 0x00000400 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_10_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_9 [09:09] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_9_MASK 0x00000200 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_9_SHIFT 9 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_8 [08:08] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_8_MASK 0x00000100 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_8_SHIFT 8 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_7 [07:07] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_7_MASK 0x00000080 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_7_SHIFT 7 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_6 [06:06] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_6_MASK 0x00000040 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_6_SHIFT 6 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_5 [05:05] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_5_MASK 0x00000020 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_5_SHIFT 5 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_4 [04:04] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_4_MASK 0x00000010 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_4_SHIFT 4 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_3 [03:03] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_3_MASK 0x00000008 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_3_SHIFT 3 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_2 [02:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_2_MASK 0x00000004 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_2_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_1 [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_1_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_1_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_0 [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_0_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_0_SHIFT 0 - -/*************************************************************************** - *REG_CPU_INTGEN_CLR - CPU interrupt clear register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: CPU_2_Hst_MBx [31:31] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_CPU_2_Hst_MBx_MASK 0x80000000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_CPU_2_Hst_MBx_SHIFT 31 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Watchdog_Timer [30:30] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Watchdog_Timer_MASK 0x40000000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Watchdog_Timer_SHIFT 30 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: reserved0 [29:16] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_reserved0_MASK 0x3fff0000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_reserved0_SHIFT 16 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_15 [15:15] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_15_MASK 0x00008000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_15_SHIFT 15 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_14 [14:14] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_14_MASK 0x00004000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_14_SHIFT 14 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_13 [13:13] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_13_MASK 0x00002000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_13_SHIFT 13 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_12 [12:12] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_12_MASK 0x00001000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_12_SHIFT 12 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_11 [11:11] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_11_MASK 0x00000800 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_11_SHIFT 11 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_10 [10:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_10_MASK 0x00000400 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_10_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_9 [09:09] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_9_MASK 0x00000200 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_9_SHIFT 9 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_8 [08:08] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_8_MASK 0x00000100 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_8_SHIFT 8 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_7 [07:07] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_7_MASK 0x00000080 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_7_SHIFT 7 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_6 [06:06] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_6_MASK 0x00000040 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_6_SHIFT 6 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_5 [05:05] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_5_MASK 0x00000020 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_5_SHIFT 5 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_4 [04:04] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_4_MASK 0x00000010 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_4_SHIFT 4 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_3 [03:03] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_3_MASK 0x00000008 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_3_SHIFT 3 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_2 [02:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_2_MASK 0x00000004 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_2_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_1 [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_1_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_1_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_0 [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_0_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_0_SHIFT 0 - -/*************************************************************************** - *REG_CPU_ICACHE_MISS - Instruction cache miss counter - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU_ICACHE_MISS :: Count [31:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_ICACHE_MISS_Count_MASK 0xffffffff -#define BCHP_DECODE_CPUREGS_0_REG_CPU_ICACHE_MISS_Count_SHIFT 0 - -/*************************************************************************** - *REG_CPU_INTGEN_MASK - CPU interrupt mask register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: CPU_2_Hst_MBx [31:31] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_CPU_2_Hst_MBx_MASK 0x80000000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_CPU_2_Hst_MBx_SHIFT 31 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Watchdog_Timer [30:30] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Watchdog_Timer_MASK 0x40000000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Watchdog_Timer_SHIFT 30 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: reserved0 [29:16] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_reserved0_MASK 0x3fff0000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_reserved0_SHIFT 16 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_15 [15:15] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_15_MASK 0x00008000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_15_SHIFT 15 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_14 [14:14] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_14_MASK 0x00004000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_14_SHIFT 14 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_13 [13:13] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_13_MASK 0x00002000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_13_SHIFT 13 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_12 [12:12] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_12_MASK 0x00001000 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_12_SHIFT 12 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_11 [11:11] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_11_MASK 0x00000800 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_11_SHIFT 11 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_10 [10:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_10_MASK 0x00000400 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_10_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_9 [09:09] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_9_MASK 0x00000200 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_9_SHIFT 9 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_8 [08:08] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_8_MASK 0x00000100 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_8_SHIFT 8 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_7 [07:07] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_7_MASK 0x00000080 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_7_SHIFT 7 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_6 [06:06] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_6_MASK 0x00000040 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_6_SHIFT 6 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_5 [05:05] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_5_MASK 0x00000020 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_5_SHIFT 5 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_4 [04:04] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_4_MASK 0x00000010 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_4_SHIFT 4 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_3 [03:03] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_3_MASK 0x00000008 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_3_SHIFT 3 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_2 [02:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_2_MASK 0x00000004 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_2_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_1 [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_1_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_1_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_0 [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_0_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_0_SHIFT 0 - -/*************************************************************************** - *REG_END_OF_CODE - End of code register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_END_OF_CODE :: EndOfCode [31:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_EndOfCode_MASK 0xfffffc00 -#define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_EndOfCode_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_END_OF_CODE :: reserved0 [09:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_reserved0_MASK 0x000003ff -#define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_GLOBAL_IO_BASE - Global IO base register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_GLOBAL_IO_BASE :: GlobalIOBase [31:10] */ -#define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_GlobalIOBase_MASK 0xfffffc00 -#define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_GlobalIOBase_SHIFT 10 - -/* DECODE_CPUREGS_0 :: REG_GLOBAL_IO_BASE :: reserved0 [09:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_reserved0_MASK 0x000003ff -#define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_DEBUG_TRACE_FIFO_WR - CPU debug trace fifo write - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_WR :: reserved0 [31:08] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_reserved0_MASK 0xffffff00 -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_reserved0_SHIFT 8 - -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_WR :: Value [07:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_Value_MASK 0x000000ff -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_Value_SHIFT 0 - -/*************************************************************************** - *REG_DEBUG_TRACE_FIFO_RD - CPU debug trace fifo read - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_RD :: reserved0 [31:08] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_reserved0_MASK 0xffffff00 -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_reserved0_SHIFT 8 - -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_RD :: Value [07:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_Value_MASK 0x000000ff -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_Value_SHIFT 0 - -/*************************************************************************** - *REG_DEBUG_TRACE_FIFO_CTL - CPU debug trace fifo control - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: reserved0 [31:03] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_reserved0_MASK 0xfffffff8 -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_reserved0_SHIFT 3 - -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: Freeze [02:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Freeze_MASK 0x00000004 -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Freeze_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: Start_read [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Start_read_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Start_read_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: Clear [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Clear_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Clear_SHIFT 0 - -/*************************************************************************** - *REG_WATCHDOG_TMR - Watchdog timer register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_WATCHDOG_TMR :: Value [31:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR_Value_MASK 0xffffffff -#define BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR_Value_SHIFT 0 - -/*************************************************************************** - *REG_SDRAM_STATUS - SDRAM Status register - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_SDRAM_STATUS :: reserved0 [31:02] */ -#define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_reserved0_MASK 0xfffffffc -#define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_reserved0_SHIFT 2 - -/* DECODE_CPUREGS_0 :: REG_SDRAM_STATUS :: IsWrite [01:01] */ -#define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_IsWrite_MASK 0x00000002 -#define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_IsWrite_SHIFT 1 - -/* DECODE_CPUREGS_0 :: REG_SDRAM_STATUS :: Busy [00:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_Busy_MASK 0x00000001 -#define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_Busy_SHIFT 0 - -/*************************************************************************** - *REG_CPUREGS_END - Dummy end - ***************************************************************************/ -/* DECODE_CPUREGS_0 :: REG_CPUREGS_END :: reserved0 [31:00] */ -#define BCHP_DECODE_CPUREGS_0_REG_CPUREGS_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_CPUREGS_0_REG_CPUREGS_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_CPUREGS_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,78 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_cpuregs2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:02p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:17 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:02p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_CPUREGS2_0_H__ -#define BCHP_DECODE_CPUREGS2_0_H__ - -/*************************************************************************** - *DECODE_CPUREGS2_0 - Outer Loop CPU Registers 0 - ***************************************************************************/ -#define BCHP_DECODE_CPUREGS2_0_REG_HST2CPU_MBX 0x00800f80 /* Host 2 CPU mailbox register */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU2HST_MBX 0x00800f84 /* CPU to Host mailbox register */ -#define BCHP_DECODE_CPUREGS2_0_REG_MBX_STAT 0x00800f88 /* Mailbox status flags */ -#define BCHP_DECODE_CPUREGS2_0_REG_INST_BASE 0x00800f8c /* Instruction base address register */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU_INT_ENA 0x00800f90 /* CPU interrupt enable */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU_INT_STAT 0x00800f94 /* CPU interrupt status */ -#define BCHP_DECODE_CPUREGS2_0_REG_HST2CPU_STAT 0x00800f98 /* Host to CPU status register */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU2HST_STAT 0x00800f9c /* CPU to Host status register */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU_INTGEN_SET 0x00800fa0 /* CPU interrupt set register */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU_INTGEN_CLR 0x00800fa4 /* CPU interrupt clear register */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU_ICACHE_MISS 0x00800fa8 /* Instruction cache miss counter */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPU_INTGEN_MASK 0x00800fac /* CPU interrupt mask register */ -#define BCHP_DECODE_CPUREGS2_0_REG_END_OF_CODE 0x00800fb4 /* End of code register */ -#define BCHP_DECODE_CPUREGS2_0_REG_GLOBAL_IO_BASE 0x00800fb8 /* Global IO base register */ -#define BCHP_DECODE_CPUREGS2_0_REG_DEBUG_TRACE_FIFO_WR 0x00800fbc /* CPU debug trace fifo write */ -#define BCHP_DECODE_CPUREGS2_0_REG_DEBUG_TRACE_FIFO_RD 0x00800fc0 /* CPU debug trace fifo read */ -#define BCHP_DECODE_CPUREGS2_0_REG_DEBUG_TRACE_FIFO_CTL 0x00800fc4 /* CPU debug trace fifo control */ -#define BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR 0x00800fcc /* Watchdog timer register */ -#define BCHP_DECODE_CPUREGS2_0_REG_SDRAM_STATUS 0x00800fd0 /* SDRAM Status register */ -#define BCHP_DECODE_CPUREGS2_0_REG_CPUREGS_END 0x00800ffc /* Dummy end */ - -#endif /* #ifndef BCHP_DECODE_CPUREGS2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dblk_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dblk_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dblk_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dblk_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,904 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_dblk_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:02p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:48 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dblk_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:02p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_DBLK_0_H__ -#define BCHP_DECODE_DBLK_0_H__ - -/*************************************************************************** - *DECODE_DBLK_0 - ***************************************************************************/ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL 0x00800720 /* Deblocking Control */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT 0x00800724 /* Deblocking Output Control */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM 0x00800728 /* REG_OLAP_XFORM - VC-1 only */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT 0x0080072c /* Deblocking Quantization Data */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET 0x00800730 /* Deblocking filter offsets (H.264 only) */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX 0x00800734 /* Deblocking Top Context */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO 0x00800738 /* Deblocking: Transform has non-zero coefs */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF 0x0080073c /* Deblocking Motion Vector Difference */ - -/*************************************************************************** - *REG_DBLK_CTL - Deblocking Control - ***************************************************************************/ -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: reserved0 [31:15] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_reserved0_MASK 0xffff8000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_reserved0_SHIFT 15 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Ctl_Edge_Top [14:14] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Top_MASK 0x00004000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Top_SHIFT 14 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Ctl_Edge_Bottom [13:13] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Bottom_MASK 0x00002000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Bottom_SHIFT 13 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbhz_chr_top_mvdiff [12:12] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_top_mvdiff_MASK 0x00001000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_top_mvdiff_SHIFT 12 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbvt_chr_top_mvdiff [11:11] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_top_mvdiff_MASK 0x00000800 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_top_mvdiff_SHIFT 11 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbhz_chr_mvdiff [10:10] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_mvdiff_MASK 0x00000400 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_mvdiff_SHIFT 10 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbvt_chr_mvdiff [09:09] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_mvdiff_MASK 0x00000200 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_mvdiff_SHIFT 9 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: MPEG [08:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_MPEG_MASK 0x00000100 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_MPEG_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: H264_8x8 [07:07] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_H264_8x8_MASK 0x00000080 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_H264_8x8_SHIFT 7 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Mono [06:06] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Mono_MASK 0x00000040 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Mono_SHIFT 6 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Is_Last [05:05] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Is_Last_MASK 0x00000020 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Is_Last_SHIFT 5 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Intra [04:04] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Intra_MASK 0x00000010 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Intra_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Fleft [03:03] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fleft_MASK 0x00000008 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fleft_SHIFT 3 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Ftop [02:02] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ftop_MASK 0x00000004 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ftop_SHIFT 2 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: Fint [01:01] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fint_MASK 0x00000002 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fint_SHIFT 1 - -/* DECODE_DBLK_0 :: REG_DBLK_CTL :: CES [00:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_CES_MASK 0x00000001 -#define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_CES_SHIFT 0 - -/*************************************************************************** - *REG_DBLK_OUT - Deblocking Output Control - ***************************************************************************/ -/* DECODE_DBLK_0 :: REG_DBLK_OUT :: reserved0 [31:17] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_reserved0_MASK 0xfffe0000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_reserved0_SHIFT 17 - -/* DECODE_DBLK_0 :: REG_DBLK_OUT :: Out2 [16:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_Out2_MASK 0x00010000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_Out2_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_OUT :: PicNum2 [15:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum2_MASK 0x0000ff00 -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum2_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_OUT :: PicNum [07:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum_MASK 0x000000ff -#define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum_SHIFT 0 - -/*************************************************************************** - *REG_OLAP_XFORM - REG_OLAP_XFORM - VC-1 only - ***************************************************************************/ -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: reserved0 [31:30] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved0_MASK 0xc0000000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved0_SHIFT 30 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: TopVIntra [29:29] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopVIntra_MASK 0x20000000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopVIntra_SHIFT 29 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: TopUIntra [28:28] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopUIntra_MASK 0x10000000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopUIntra_SHIFT 28 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: TopLIntra [27:24] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopLIntra_MASK 0x0f000000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopLIntra_SHIFT 24 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: reserved1 [23:22] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved1_MASK 0x00c00000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved1_SHIFT 22 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: Vintra [21:21] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Vintra_MASK 0x00200000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Vintra_SHIFT 21 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: Uintra [20:20] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Uintra_MASK 0x00100000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Uintra_SHIFT 20 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: LumaIntra [19:16] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaIntra_MASK 0x000f0000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaIntra_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: reserved2 [15:12] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved2_MASK 0x0000f000 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved2_SHIFT 12 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: VV [11:11] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VV_MASK 0x00000800 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VV_SHIFT 11 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: VH [10:10] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VH_MASK 0x00000400 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VH_SHIFT 10 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: UV [09:09] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UV_MASK 0x00000200 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UV_SHIFT 9 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: UH [08:08] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UH_MASK 0x00000100 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UH_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: LumaVert [07:04] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaVert_MASK 0x000000f0 -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaVert_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_OLAP_XFORM :: LumaHoriz [03:00] */ -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaHoriz_MASK 0x0000000f -#define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaHoriz_SHIFT 0 - -/*************************************************************************** - *REG_DBLK_QNT - Deblocking Quantization Data - ***************************************************************************/ -/* DECODE_DBLK_0 :: REG_DBLK_QNT :: reserved0 [31:24] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_reserved0_MASK 0xff000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_reserved0_SHIFT 24 - -/* DECODE_DBLK_0 :: REG_DBLK_QNT :: OPvTopTop [23:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTopTop_MASK 0x00ff0000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTopTop_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_QNT :: OPvTop [15:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTop_MASK 0x0000ff00 -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTop_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_QNT :: Opv [07:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_Opv_MASK 0x000000ff -#define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_Opv_SHIFT 0 - -/*************************************************************************** - *REG_DBLK_OFFSET - Deblocking filter offsets (H.264 only) - ***************************************************************************/ -/* DECODE_DBLK_0 :: REG_DBLK_OFFSET :: reserved0 [31:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_reserved0_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_OFFSET :: OffsetB [15:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetB_MASK 0x0000ff00 -#define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetB_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_OFFSET :: OffsetA [07:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetA_MASK 0x000000ff -#define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetA_SHIFT 0 - -/*************************************************************************** - *REG_DBLK_TOP_CTX - Deblocking Top Context - ***************************************************************************/ -/* union - case H264 [31:00] */ -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: reserved0 [31:22] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved0_MASK 0xffc00000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved0_SHIFT 22 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB15 [21:21] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB15_MASK 0x00200000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB15_SHIFT 21 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB14 [20:20] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB14_MASK 0x00100000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB14_SHIFT 20 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB11 [19:19] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB11_MASK 0x00080000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB11_SHIFT 19 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB10 [18:18] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB10_MASK 0x00040000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB10_SHIFT 18 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: reserved1 [17:17] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved1_MASK 0x00020000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved1_SHIFT 17 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: Tintra [16:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Tintra_MASK 0x00010000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Tintra_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: reserved2 [15:06] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved2_MASK 0x0000ffc0 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved2_SHIFT 6 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B15 [05:05] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B15_MASK 0x00000020 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B15_SHIFT 5 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B14 [04:04] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B14_MASK 0x00000010 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B14_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B11 [03:03] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B11_MASK 0x00000008 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B11_SHIFT 3 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B10 [02:02] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B10_MASK 0x00000004 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B10_SHIFT 2 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: Field [01:01] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Field_MASK 0x00000002 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Field_SHIFT 1 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: Intra [00:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Intra_MASK 0x00000001 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Intra_SHIFT 0 - -/* union - case VC1_0 [31:00] */ -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV3 [31:31] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV3_MASK 0x80000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV3_SHIFT 31 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV2 [30:30] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV2_MASK 0x40000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV2_SHIFT 30 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV1 [29:29] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV1_MASK 0x20000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV1_SHIFT 29 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV0 [28:28] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV0_MASK 0x10000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV0_SHIFT 28 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV3 [27:27] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV3_MASK 0x08000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV3_SHIFT 27 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV2 [26:26] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV2_MASK 0x04000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV2_SHIFT 26 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV1 [25:25] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV1_MASK 0x02000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV1_SHIFT 25 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV0 [24:24] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV0_MASK 0x01000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV0_SHIFT 24 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV15 [23:23] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV15_MASK 0x00800000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV15_SHIFT 23 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV14 [22:22] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV14_MASK 0x00400000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV14_SHIFT 22 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV11 [21:21] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV11_MASK 0x00200000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV11_SHIFT 21 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV10 [20:20] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV10_MASK 0x00100000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV10_SHIFT 20 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV7 [19:19] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV7_MASK 0x00080000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV7_SHIFT 19 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV6 [18:18] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV6_MASK 0x00040000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV6_SHIFT 18 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV3 [17:17] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV3_MASK 0x00020000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV3_SHIFT 17 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV2 [16:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV2_MASK 0x00010000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV2_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VH3 [15:15] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH3_MASK 0x00008000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH3_SHIFT 15 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VH2 [14:14] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH2_MASK 0x00004000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH2_SHIFT 14 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: reserved0 [13:12] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved0_MASK 0x00003000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved0_SHIFT 12 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UH3 [11:11] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH3_MASK 0x00000800 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH3_SHIFT 11 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UH2 [10:10] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH2_MASK 0x00000400 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH2_SHIFT 10 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: reserved1 [09:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved1_MASK 0x00000300 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved1_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH15 [07:07] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH15_MASK 0x00000080 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH15_SHIFT 7 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH14 [06:06] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH14_MASK 0x00000040 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH14_SHIFT 6 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH13 [05:05] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH13_MASK 0x00000020 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH13_SHIFT 5 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH12 [04:04] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH12_MASK 0x00000010 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH12_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: reserved2 [03:01] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved2_MASK 0x0000000e -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved2_SHIFT 1 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: TFld [00:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_TFld_MASK 0x00000001 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_TFld_SHIFT 0 - -/* union - case VC1_1 [31:00] */ -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV3 [31:31] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV3_MASK 0x80000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV3_SHIFT 31 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV2 [30:30] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV2_MASK 0x40000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV2_SHIFT 30 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV1 [29:29] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV1_MASK 0x20000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV1_SHIFT 29 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV0 [28:28] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV0_MASK 0x10000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV0_SHIFT 28 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV3 [27:27] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV3_MASK 0x08000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV3_SHIFT 27 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV2 [26:26] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV2_MASK 0x04000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV2_SHIFT 26 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV1 [25:25] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV1_MASK 0x02000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV1_SHIFT 25 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV0 [24:24] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV0_MASK 0x01000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV0_SHIFT 24 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV13 [23:23] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV13_MASK 0x00800000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV13_SHIFT 23 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV12 [22:22] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV12_MASK 0x00400000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV12_SHIFT 22 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV9 [21:21] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV9_MASK 0x00200000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV9_SHIFT 21 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV8 [20:20] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV8_MASK 0x00100000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV8_SHIFT 20 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV5 [19:19] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV5_MASK 0x00080000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV5_SHIFT 19 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV4 [18:18] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV4_MASK 0x00040000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV4_SHIFT 18 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV1 [17:17] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV1_MASK 0x00020000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV1_SHIFT 17 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV0 [16:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV0_MASK 0x00010000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV0_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: reserved0 [15:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_reserved0_MASK 0x0000ffff -#define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_DBLK_XZERO - Deblocking: Transform has non-zero coefs - ***************************************************************************/ -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: reserved0 [31:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_reserved0_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B15 [15:15] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B15_MASK 0x00008000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B15_SHIFT 15 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B14 [14:14] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B14_MASK 0x00004000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B14_SHIFT 14 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B13 [13:13] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B13_MASK 0x00002000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B13_SHIFT 13 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B12 [12:12] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B12_MASK 0x00001000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B12_SHIFT 12 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B11 [11:11] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B11_MASK 0x00000800 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B11_SHIFT 11 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B10 [10:10] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B10_MASK 0x00000400 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B10_SHIFT 10 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B9 [09:09] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B9_MASK 0x00000200 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B9_SHIFT 9 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B8 [08:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B8_MASK 0x00000100 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B8_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B7 [07:07] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B7_MASK 0x00000080 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B7_SHIFT 7 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B6 [06:06] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B6_MASK 0x00000040 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B6_SHIFT 6 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B5 [05:05] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B5_MASK 0x00000020 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B5_SHIFT 5 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B4 [04:04] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B4_MASK 0x00000010 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B4_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B3 [03:03] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B3_MASK 0x00000008 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B3_SHIFT 3 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B2 [02:02] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B2_MASK 0x00000004 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B2_SHIFT 2 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B1 [01:01] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B1_MASK 0x00000002 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B1_SHIFT 1 - -/* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B0 [00:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B0_MASK 0x00000001 -#define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B0_SHIFT 0 - -/*************************************************************************** - *REG_DBLK_MVDIFF - Deblocking Motion Vector Difference - ***************************************************************************/ -/* union - case H264 [31:00] */ -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V15 [31:31] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V15_MASK 0x80000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V15_SHIFT 31 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V14 [30:30] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V14_MASK 0x40000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V14_SHIFT 30 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V13 [29:29] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V13_MASK 0x20000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V13_SHIFT 29 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V12 [28:28] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V12_MASK 0x10000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V12_SHIFT 28 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V11 [27:27] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V11_MASK 0x08000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V11_SHIFT 27 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V10 [26:26] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V10_MASK 0x04000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V10_SHIFT 26 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V9 [25:25] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V9_MASK 0x02000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V9_SHIFT 25 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V8 [24:24] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V8_MASK 0x01000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V8_SHIFT 24 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V7 [23:23] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V7_MASK 0x00800000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V7_SHIFT 23 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V6 [22:22] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V6_MASK 0x00400000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V6_SHIFT 22 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V5 [21:21] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V5_MASK 0x00200000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V5_SHIFT 21 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V4 [20:20] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V4_MASK 0x00100000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V4_SHIFT 20 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V3 [19:19] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V3_MASK 0x00080000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V3_SHIFT 19 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V2 [18:18] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V2_MASK 0x00040000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V2_SHIFT 18 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V1 [17:17] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V1_MASK 0x00020000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V1_SHIFT 17 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V0 [16:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V0_MASK 0x00010000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V0_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H15 [15:15] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H15_MASK 0x00008000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H15_SHIFT 15 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H14 [14:14] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H14_MASK 0x00004000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H14_SHIFT 14 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H13 [13:13] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H13_MASK 0x00002000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H13_SHIFT 13 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H12 [12:12] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H12_MASK 0x00001000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H12_SHIFT 12 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H11 [11:11] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H11_MASK 0x00000800 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H11_SHIFT 11 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H10 [10:10] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H10_MASK 0x00000400 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H10_SHIFT 10 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H9 [09:09] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H9_MASK 0x00000200 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H9_SHIFT 9 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H8 [08:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H8_MASK 0x00000100 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H8_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H7 [07:07] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H7_MASK 0x00000080 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H7_SHIFT 7 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H6 [06:06] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H6_MASK 0x00000040 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H6_SHIFT 6 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H5 [05:05] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H5_MASK 0x00000020 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H5_SHIFT 5 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H4 [04:04] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H4_MASK 0x00000010 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H4_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H3 [03:03] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H3_MASK 0x00000008 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H3_SHIFT 3 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H2 [02:02] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H2_MASK 0x00000004 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H2_SHIFT 2 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H1 [01:01] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H1_MASK 0x00000002 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H1_SHIFT 1 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H0 [00:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H0_MASK 0x00000001 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H0_SHIFT 0 - -/* union - case VC1_0 [31:00] */ -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V15 [31:31] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V15_MASK 0x80000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V15_SHIFT 31 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V14 [30:30] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V14_MASK 0x40000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V14_SHIFT 30 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V13 [29:29] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V13_MASK 0x20000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V13_SHIFT 29 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V12 [28:28] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V12_MASK 0x10000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V12_SHIFT 28 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V11 [27:27] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V11_MASK 0x08000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V11_SHIFT 27 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V10 [26:26] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V10_MASK 0x04000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V10_SHIFT 26 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V9 [25:25] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V9_MASK 0x02000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V9_SHIFT 25 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V8 [24:24] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V8_MASK 0x01000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V8_SHIFT 24 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V7 [23:23] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V7_MASK 0x00800000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V7_SHIFT 23 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V6 [22:22] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V6_MASK 0x00400000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V6_SHIFT 22 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V5 [21:21] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V5_MASK 0x00200000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V5_SHIFT 21 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V4 [20:20] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V4_MASK 0x00100000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V4_SHIFT 20 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V3 [19:19] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V3_MASK 0x00080000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V3_SHIFT 19 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V2 [18:18] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V2_MASK 0x00040000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V2_SHIFT 18 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V1 [17:17] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V1_MASK 0x00020000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V1_SHIFT 17 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V0 [16:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V0_MASK 0x00010000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V0_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H15 [15:15] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H15_MASK 0x00008000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H15_SHIFT 15 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H14 [14:14] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H14_MASK 0x00004000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H14_SHIFT 14 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H13 [13:13] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H13_MASK 0x00002000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H13_SHIFT 13 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H12 [12:12] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H12_MASK 0x00001000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H12_SHIFT 12 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H11 [11:11] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H11_MASK 0x00000800 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H11_SHIFT 11 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H10 [10:10] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H10_MASK 0x00000400 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H10_SHIFT 10 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H9 [09:09] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H9_MASK 0x00000200 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H9_SHIFT 9 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H8 [08:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H8_MASK 0x00000100 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H8_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H7 [07:07] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H7_MASK 0x00000080 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H7_SHIFT 7 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H6 [06:06] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H6_MASK 0x00000040 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H6_SHIFT 6 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H5 [05:05] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H5_MASK 0x00000020 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H5_SHIFT 5 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H4 [04:04] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H4_MASK 0x00000010 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H4_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H3 [03:03] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H3_MASK 0x00000008 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H3_SHIFT 3 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H2 [02:02] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H2_MASK 0x00000004 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H2_SHIFT 2 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H1 [01:01] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H1_MASK 0x00000002 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H1_SHIFT 1 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H0 [00:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H0_MASK 0x00000001 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H0_SHIFT 0 - -/* union - case VC1_1 [31:00] */ -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved0 [31:28] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved0_MASK 0xf0000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved0_SHIFT 28 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV3 [27:27] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV3_MASK 0x08000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV3_SHIFT 27 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV2 [26:26] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV2_MASK 0x04000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV2_SHIFT 26 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV1 [25:25] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV1_MASK 0x02000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV1_SHIFT 25 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV0 [24:24] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV0_MASK 0x01000000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV0_SHIFT 24 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved1 [23:20] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved1_MASK 0x00f00000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved1_SHIFT 20 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV3 [19:19] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV3_MASK 0x00080000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV3_SHIFT 19 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV2 [18:18] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV2_MASK 0x00040000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV2_SHIFT 18 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV1 [17:17] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV1_MASK 0x00020000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV1_SHIFT 17 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV0 [16:16] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV0_MASK 0x00010000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV0_SHIFT 16 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved2 [15:12] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved2_MASK 0x0000f000 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved2_SHIFT 12 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH3 [11:11] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH3_MASK 0x00000800 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH3_SHIFT 11 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH2 [10:10] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH2_MASK 0x00000400 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH2_SHIFT 10 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH1 [09:09] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH1_MASK 0x00000200 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH1_SHIFT 9 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH0 [08:08] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH0_MASK 0x00000100 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH0_SHIFT 8 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved3 [07:04] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved3_MASK 0x000000f0 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved3_SHIFT 4 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH3 [03:03] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH3_MASK 0x00000008 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH3_SHIFT 3 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH2 [02:02] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH2_MASK 0x00000004 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH2_SHIFT 2 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH1 [01:01] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH1_MASK 0x00000002 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH1_SHIFT 1 - -/* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH0 [00:00] */ -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH0_MASK 0x00000001 -#define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_DBLK_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_dmamem_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:03p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:13 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:03p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_DMAMEM_0_H__ -#define BCHP_DECODE_DMAMEM_0_H__ - -/*************************************************************************** - *DECODE_DMAMEM_0 - ***************************************************************************/ -#define BCHP_DECODE_DMAMEM_0_DMA_MEM 0x00801a00 /* DMA_MEM */ -#define BCHP_DECODE_DMAMEM_0_DMA_MEM_END 0x008021fc /* REGION_END */ - -/*************************************************************************** - *DMA_MEM - DMA_MEM - ***************************************************************************/ -/* DECODE_DMAMEM_0 :: DMA_MEM :: Data [31:00] */ -#define BCHP_DECODE_DMAMEM_0_DMA_MEM_Data_MASK 0xffffffff -#define BCHP_DECODE_DMAMEM_0_DMA_MEM_Data_SHIFT 0 - -/*************************************************************************** - *DMA_MEM_END - REGION_END - ***************************************************************************/ -/* DECODE_DMAMEM_0 :: DMA_MEM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_DMAMEM_0_DMA_MEM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_DMAMEM_0_DMA_MEM_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_DMAMEM_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_dmamem2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:03p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:40 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:03p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_DMAMEM2_0_H__ -#define BCHP_DECODE_DMAMEM2_0_H__ - -/*************************************************************************** - *DECODE_DMAMEM2_0 - ***************************************************************************/ -#define BCHP_DECODE_DMAMEM2_0_DMA_MEM 0x00851a00 /* DMA_MEM */ -#define BCHP_DECODE_DMAMEM2_0_DMA_MEM_END 0x008521fc /* REGION_END */ - -#endif /* #ifndef BCHP_DECODE_DMAMEM2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_dqnt_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:03p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:18 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:03p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_DQNT_0_H__ -#define BCHP_DECODE_DQNT_0_H__ - -/*************************************************************************** - *DECODE_DQNT_0 - ***************************************************************************/ -#define BCHP_DECODE_DQNT_0_REG_DQNT_END 0x0080045c /* REG_DQNT_END */ - -/*************************************************************************** - *REG_DQNT_END - REG_DQNT_END - ***************************************************************************/ -/* DECODE_DQNT_0 :: REG_DQNT_END :: reserved0 [31:00] */ -#define BCHP_DECODE_DQNT_0_REG_DQNT_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_DQNT_0_REG_DQNT_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_DQNT_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_8x8_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_8x8_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_8x8_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_8x8_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_dqnt_8x8_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:03p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:35 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_8x8_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:03p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_DQNT_8X8_0_H__ -#define BCHP_DECODE_DQNT_8X8_0_H__ - -/*************************************************************************** - *DECODE_DQNT_8X8_0 - ***************************************************************************/ -#define BCHP_DECODE_DQNT_8X8_0_REG_DQNT_8X8_END 0x0080057c /* REG_DQNT_8X8_END */ - -/*************************************************************************** - *REG_DQNT_8X8_END - REG_DQNT_8X8_END - ***************************************************************************/ -/* DECODE_DQNT_8X8_0 :: REG_DQNT_8X8_END :: reserved0 [31:00] */ -#define BCHP_DECODE_DQNT_8X8_0_REG_DQNT_8X8_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_DQNT_8X8_0_REG_DQNT_8X8_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_DQNT_8X8_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,118 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_ind_sdram_regs_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:04p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:26 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:04p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_IND_SDRAM_REGS_0_H__ -#define BCHP_DECODE_IND_SDRAM_REGS_0_H__ - -/*************************************************************************** - *DECODE_IND_SDRAM_REGS_0 - ***************************************************************************/ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC 0x00841000 /* REG_SDRAM_INC */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR 0x00841004 /* REG_SDRAM_ADDR */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA 0x00841008 /* REG_SDRAM_DATA */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG 0x00841010 /* REG_CPU_DBG */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT 0x00841014 /* REG_SDRAM_STAT */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END 0x0084107c /* REG_SDRAM_END */ - -/*************************************************************************** - *REG_SDRAM_INC - REG_SDRAM_INC - ***************************************************************************/ -/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_INC :: reserved0 [31:01] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_reserved0_MASK 0xfffffffe -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_reserved0_SHIFT 1 - -/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_INC :: Inc [00:00] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_Inc_MASK 0x00000001 -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_Inc_SHIFT 0 - -/*************************************************************************** - *REG_SDRAM_ADDR - REG_SDRAM_ADDR - ***************************************************************************/ -/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_ADDR :: Addr [31:02] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_Addr_MASK 0xfffffffc -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_Addr_SHIFT 2 - -/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_ADDR :: reserved0 [01:00] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_reserved0_MASK 0x00000003 -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SDRAM_DATA - REG_SDRAM_DATA - ***************************************************************************/ -/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_DATA :: Data [31:00] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA_Data_MASK 0xffffffff -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA_Data_SHIFT 0 - -/*************************************************************************** - *REG_CPU_DBG - REG_CPU_DBG - ***************************************************************************/ -/* DECODE_IND_SDRAM_REGS_0 :: REG_CPU_DBG :: reserved0 [31:01] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_reserved0_MASK 0xfffffffe -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_reserved0_SHIFT 1 - -/* DECODE_IND_SDRAM_REGS_0 :: REG_CPU_DBG :: Hst [00:00] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_Hst_MASK 0x00000001 -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_Hst_SHIFT 0 - -/*************************************************************************** - *REG_SDRAM_STAT - REG_SDRAM_STAT - ***************************************************************************/ -/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_STAT :: reserved0 [31:00] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT_reserved0_MASK 0xffffffff -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SDRAM_END - REG_SDRAM_END - ***************************************************************************/ -/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_IND_SDRAM_REGS_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_ind_sdram_regs2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:03p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:41 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:03p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_IND_SDRAM_REGS2_0_H__ -#define BCHP_DECODE_IND_SDRAM_REGS2_0_H__ - -/*************************************************************************** - *DECODE_IND_SDRAM_REGS2_0 - ***************************************************************************/ -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_INC 0x00851000 /* REG_SDRAM_INC */ -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_ADDR 0x00851004 /* REG_SDRAM_ADDR */ -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_DATA 0x00851008 /* REG_SDRAM_DATA */ -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_CPU_DBG 0x00851010 /* REG_CPU_DBG */ -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_STAT 0x00851014 /* REG_SDRAM_STAT */ -#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_END 0x0085107c /* REG_SDRAM_END */ - -#endif /* #ifndef BCHP_DECODE_IND_SDRAM_REGS2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ip_shim_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ip_shim_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ip_shim_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ip_shim_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,694 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_ip_shim_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:04p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:04 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ip_shim_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:04p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_IP_SHIM_0_H__ -#define BCHP_DECODE_IP_SHIM_0_H__ - -/*************************************************************************** - *DECODE_IP_SHIM_0 - AVD Shim Registers 0 - ***************************************************************************/ -#define BCHP_DECODE_IP_SHIM_0_STC0_REG 0x00860000 /* Serial Time Stamp PTS register */ -#define BCHP_DECODE_IP_SHIM_0_STC1_REG 0x00860004 /* Serial Time Stamp PTS register */ -#define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG 0x00860008 /* Stream Endian Control Register */ -#define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG 0x0086000c /* BVN Interrupt Register */ -#define BCHP_DECODE_IP_SHIM_0_CPU_ID 0x00860010 /* Chip ID Regsiter */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE 0x00860014 /* Clock Gate Register */ -#define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG 0x00860034 /* Deblock Intercept Buffer TM register */ -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG 0x00860038 /* ARC TM Register */ -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG 0x0086003c /* ARC TM Register */ -#define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG 0x00860040 /* CPU Debug FIFO TM Register */ -#define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG 0x00860044 /* CABAC TM Register */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG 0x00860048 /* Decode TM Register */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG 0x0086004c /* Frontend FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG 0x00860050 /* ARC FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG 0x00860054 /* SHIM FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG 0x00860058 /* DECODE FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG 0x0086005c /* DEBLOCK FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG 0x00860060 /* IXFORM FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG 0x00860064 /* SI FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG 0x00860068 /* FGTAVE FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG 0x0086006c /* PCACHE FSRF TM Register */ -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG 0x00860070 /* Scratch RAM Address */ -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG 0x00860074 /* Scratch RAM Address */ -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_DATA_REG 0x00860078 /* Scratch RAM Data */ -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_DATA_REG 0x0086007c /* Scratch RAM Data */ - -/*************************************************************************** - *STC0_REG - Serial Time Stamp PTS register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: STC0_REG :: STC [31:00] */ -#define BCHP_DECODE_IP_SHIM_0_STC0_REG_STC_MASK 0xffffffff -#define BCHP_DECODE_IP_SHIM_0_STC0_REG_STC_SHIFT 0 - -/*************************************************************************** - *STC1_REG - Serial Time Stamp PTS register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: STC1_REG :: STC [31:00] */ -#define BCHP_DECODE_IP_SHIM_0_STC1_REG_STC_MASK 0xffffffff -#define BCHP_DECODE_IP_SHIM_0_STC1_REG_STC_SHIFT 0 - -/*************************************************************************** - *ENDIAN_REG - Stream Endian Control Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: ENDIAN_REG :: reserved0 [31:01] */ -#define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_reserved0_MASK 0xfffffffe -#define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_reserved0_SHIFT 1 - -/* DECODE_IP_SHIM_0 :: ENDIAN_REG :: B1L0 [00:00] */ -#define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_B1L0_MASK 0x00000001 -#define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_B1L0_SHIFT 0 - -/*************************************************************************** - *BVN_INT_REG - BVN Interrupt Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: BVN_INT_REG :: reserved0 [31:02] */ -#define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_reserved0_MASK 0xfffffffc -#define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_reserved0_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: BVN_INT_REG :: desc [01:01] */ -#define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_desc_MASK 0x00000002 -#define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_desc_SHIFT 1 - -/* DECODE_IP_SHIM_0 :: BVN_INT_REG :: trigger [00:00] */ -#define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_trigger_MASK 0x00000001 -#define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_trigger_SHIFT 0 - -/*************************************************************************** - *CPU_ID - Chip ID Regsiter - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: CPU_ID :: reserved0 [31:17] */ -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_reserved0_MASK 0xfffe0000 -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_reserved0_SHIFT 17 - -/* DECODE_IP_SHIM_0 :: CPU_ID :: AVD_ID [16:16] */ -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_AVD_ID_MASK 0x00010000 -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_AVD_ID_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: CPU_ID :: IL_CPU_ID [15:08] */ -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_IL_CPU_ID_MASK 0x0000ff00 -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_IL_CPU_ID_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: CPU_ID :: OL_CPU_ID [07:00] */ -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_OL_CPU_ID_MASK 0x000000ff -#define BCHP_DECODE_IP_SHIM_0_CPU_ID_OL_CPU_ID_SHIFT 0 - -/*************************************************************************** - *REG_AVD_CLK_GATE - Clock Gate Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: reserved0 [31:10] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_reserved0_MASK 0xfffffc00 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_reserved0_SHIFT 10 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_ka [09:09] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_ka_MASK 0x00000200 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_ka_SHIFT 9 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_fgt [08:08] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_fgt_MASK 0x00000100 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_fgt_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_cab [07:07] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_cab_MASK 0x00000080 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_cab_SHIFT 7 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_intra [06:06] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_intra_MASK 0x00000040 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_intra_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_vframe [05:05] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vframe_MASK 0x00000020 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vframe_SHIFT 5 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_avc [04:04] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_avc_MASK 0x00000010 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_avc_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_vc1 [03:03] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_MASK 0x00000008 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_SHIFT 3 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_vc1_db [02:02] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_db_MASK 0x00000004 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_db_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_mp4 [01:01] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp4_MASK 0x00000002 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp4_SHIFT 1 - -/* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_mp2 [00:00] */ -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp2_MASK 0x00000001 -#define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp2_SHIFT 0 - -/*************************************************************************** - *DBI_TM_REG - Deblock Intercept Buffer TM register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: DBI_TM_REG :: reserved0 [31:08] */ -#define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_reserved0_MASK 0xffffff00 -#define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_reserved0_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: DBI_TM_REG :: Y_TM [07:04] */ -#define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_Y_TM_MASK 0x000000f0 -#define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_Y_TM_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: DBI_TM_REG :: UV_TM [03:00] */ -#define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_UV_TM_MASK 0x0000000f -#define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_UV_TM_SHIFT 0 - -/*************************************************************************** - *ARC0_TM_REG - ARC TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: reserved0 [31:12] */ -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_reserved0_MASK 0xfffff000 -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_reserved0_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: ISTORE_TM [11:08] */ -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_ISTORE_TM_MASK 0x00000f00 -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_ISTORE_TM_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: DSTORE_TM [07:04] */ -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_DSTORE_TM_MASK 0x000000f0 -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_DSTORE_TM_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: TAG_TM [03:00] */ -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_TAG_TM_MASK 0x0000000f -#define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_TAG_TM_SHIFT 0 - -/*************************************************************************** - *ARC1_TM_REG - ARC TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: reserved0 [31:12] */ -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_reserved0_MASK 0xfffff000 -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_reserved0_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: ISTORE_TM [11:08] */ -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_ISTORE_TM_MASK 0x00000f00 -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_ISTORE_TM_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: DSTORE_TM [07:04] */ -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_DSTORE_TM_MASK 0x000000f0 -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_DSTORE_TM_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: TAG_TM [03:00] */ -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_TAG_TM_MASK 0x0000000f -#define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_TAG_TM_SHIFT 0 - -/*************************************************************************** - *CPU_DBG_TM_REG - CPU Debug FIFO TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: CPU_DBG_TM_REG :: reserved0 [31:04] */ -#define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_reserved0_MASK 0xfffffff0 -#define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_reserved0_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: CPU_DBG_TM_REG :: TM [03:00] */ -#define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_TM_MASK 0x0000000f -#define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_TM_SHIFT 0 - -/*************************************************************************** - *CABAC_TM_REG - CABAC TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: CABAC_TM_REG :: reserved0 [31:04] */ -#define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_reserved0_MASK 0xfffffff0 -#define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_reserved0_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: CABAC_TM_REG :: TM [03:00] */ -#define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_TM_MASK 0x0000000f -#define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_TM_SHIFT 0 - -/*************************************************************************** - *DECODE_TM_REG - Decode TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: reserved0 [31:16] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_reserved0_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: LBYUV_TM [15:12] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_LBYUV_TM_MASK 0x0000f000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_LBYUV_TM_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: PPBUF_2_TM [11:08] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_2_TM_MASK 0x00000f00 -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_2_TM_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: PPBUF_1_TM [07:04] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_1_TM_MASK 0x000000f0 -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_1_TM_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: PPBUF_0_TM [03:00] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_0_TM_MASK 0x0000000f -#define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_0_TM_SHIFT 0 - -/*************************************************************************** - *FRONTEND_FSRF_TM_REG - Frontend FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: reserved0 [31:28] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_reserved0_MASK 0xf0000000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_reserved0_SHIFT 28 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_3 [27:26] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_3_MASK 0x0c000000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_3_SHIFT 26 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_2 [25:24] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_2_MASK 0x03000000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_2_SHIFT 24 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_1 [23:22] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_1_MASK 0x00c00000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_1_SHIFT 22 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_0 [21:20] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_0_MASK 0x00300000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_0_SHIFT 20 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_3 [19:18] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_3_MASK 0x000c0000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_3_SHIFT 18 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_2 [17:16] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_2_MASK 0x00030000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_2_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_1 [15:14] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_1_MASK 0x0000c000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_1_SHIFT 14 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_0 [13:12] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_0_MASK 0x00003000 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_0_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_32X32 [11:10] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_32X32_MASK 0x00000c00 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_32X32_SHIFT 10 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_464X7 [09:08] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_464X7_MASK 0x00000300 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_464X7_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_64X32_2 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_2_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_2_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_64X32_1 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_1_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_1_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_64X32_0 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_0_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_0_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: RVC_64X32 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_RVC_64X32_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_RVC_64X32_SHIFT 0 - -/*************************************************************************** - *ARC_FSRF_TM_REG - ARC FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: reserved0 [31:08] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_reserved0_MASK 0xffffff00 -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_reserved0_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: OLARC_32X32_1 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_1_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_1_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: OLARC_32X32_0 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_0_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_0_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: ILARC_32X32_1 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_1_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_1_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: ILARC_32X32_0 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_0_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_0_SHIFT 0 - -/*************************************************************************** - *SHIM_FSRF_TM_REG - SHIM FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: SHIM_FSRF_TM_REG :: AVD_REGS_96X32 [31:30] */ -#define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_AVD_REGS_96X32_MASK 0xc0000000 -#define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_AVD_REGS_96X32_SHIFT 30 - -/* DECODE_IP_SHIM_0 :: SHIM_FSRF_TM_REG :: reserved0 [29:00] */ -#define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_reserved0_MASK 0x3fffffff -#define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_reserved0_SHIFT 0 - -/*************************************************************************** - *DECODE_FSRF_TM_REG - DECODE FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X8 [31:30] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X8_MASK 0xc0000000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X8_SHIFT 30 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X32_1 [29:28] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_1_MASK 0x30000000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_1_SHIFT 28 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X32_0 [27:26] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_0_MASK 0x0c000000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_0_SHIFT 26 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_3 [25:24] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_3_MASK 0x03000000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_3_SHIFT 24 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_2 [23:22] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_2_MASK 0x00c00000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_2_SHIFT 22 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_1 [21:20] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_1_MASK 0x00300000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_1_SHIFT 20 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_0 [19:18] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_0_MASK 0x000c0000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_0_SHIFT 18 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_128X40_1 [17:16] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_1_MASK 0x00030000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_1_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_128X40_0 [15:14] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_0_MASK 0x0000c000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_0_SHIFT 14 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_128X32 [13:12] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X32_MASK 0x00003000 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X32_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: QPEL_256x32_1 [11:10] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_1_MASK 0x00000c00 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_1_SHIFT 10 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_256X16_1 [09:08] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_1_MASK 0x00000300 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_1_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_256X16_0 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_0_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_0_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: PPBUF_256_256X36 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_256_256X36_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_256_256X36_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: PPBUF_128_128X36 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_128_128X36_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_128_128X36_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: QPEL_256x32_0 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_0_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_0_SHIFT 0 - -/*************************************************************************** - *DEBLOCK_FSRF_TM_REG - DEBLOCK FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: reserved0 [31:16] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_reserved0_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_128X36 [15:14] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_128X36_MASK 0x0000c000 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_128X36_SHIFT 14 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_64X32_1 [13:12] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_1_MASK 0x00003000 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_1_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_64X32_0 [11:10] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_0_MASK 0x00000c00 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_0_SHIFT 10 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_336X32_1 [09:08] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_1_MASK 0x00000300 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_1_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_336X32_0 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_0_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_0_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_32X24 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_32X24_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_32X24_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_192X44_1 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_1_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_1_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_192X44_0 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_0_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_0_SHIFT 0 - -/*************************************************************************** - *IXFORM_FSRF_TM_REG - IXFORM FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: reserved0 [31:18] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_reserved0_MASK 0xfffc0000 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_reserved0_SHIFT 18 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: QPEL_128X14 [17:16] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_QPEL_128X14_MASK 0x00030000 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_QPEL_128X14_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IXFRM_128X20 [15:14] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_128X20_MASK 0x0000c000 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_128X20_SHIFT 14 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: VC1_128X12 [13:12] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X12_MASK 0x00003000 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X12_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: VC1_128X18 [11:10] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X18_MASK 0x00000c00 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X18_SHIFT 10 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IXFRM_256X20 [09:08] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_256X20_MASK 0x00000300 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_256X20_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IDCT_128X16 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X16_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X16_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IDCT_128X24 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X24_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X24_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IDCT_32X32 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_32X32_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_32X32_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IXFRM_32X32 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_32X32_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_32X32_SHIFT 0 - -/*************************************************************************** - *SI_FSRF_TM_REG - SI FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: reserved0 [31:18] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_reserved0_MASK 0xfffc0000 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_reserved0_SHIFT 18 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: OLSI_128X32 [17:16] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_OLSI_128X32_MASK 0x00030000 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_OLSI_128X32_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X32 [15:14] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X32_MASK 0x0000c000 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X32_SHIFT 14 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X8_2 [13:12] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_2_MASK 0x00003000 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_2_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X8_1 [11:10] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_1_MASK 0x00000c00 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_1_SHIFT 10 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X8_0 [09:08] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_0_MASK 0x00000300 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_0_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_256X32 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_256X32_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_256X32_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_32X32 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_32X32_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_32X32_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_64X32_1 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_1_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_1_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_64X32_0 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_0_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_0_SHIFT 0 - -/*************************************************************************** - *FGTAVE_FSRF_TM_REG - FGTAVE FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: reserved0 [31:20] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_reserved0_MASK 0xfff00000 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_reserved0_SHIFT 20 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_128X32 [19:18] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X32_MASK 0x000c0000 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X32_SHIFT 18 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_128X16_1 [17:16] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_1_MASK 0x00030000 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_1_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_128X16_0 [15:14] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_0_MASK 0x0000c000 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_0_SHIFT 14 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_16X28 [13:12] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_16X28_MASK 0x00003000 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_16X28_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_5 [11:10] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_5_MASK 0x00000c00 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_5_SHIFT 10 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_4 [09:08] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_4_MASK 0x00000300 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_4_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_3 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_3_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_3_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_2 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_2_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_2_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_1 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_1_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_1_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_0 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_0_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_0_SHIFT 0 - -/*************************************************************************** - *PCACHE_FSRF_TM_REG - PCACHE FSRF TM Register - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: reserved0 [31:16] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_reserved0_SHIFT 16 - -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_6 [15:14] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_6_MASK 0x0000c000 -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_6_SHIFT 14 - -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_5 [13:12] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_5_MASK 0x00003000 -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_5_SHIFT 12 - -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_4 [11:08] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_4_MASK 0x00000f00 -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_4_SHIFT 8 - -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_3 [07:06] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_3_MASK 0x000000c0 -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_3_SHIFT 6 - -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_2 [05:04] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_2_MASK 0x00000030 -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_2_SHIFT 4 - -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_1 [03:02] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_1_MASK 0x0000000c -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_1_SHIFT 2 - -/* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_0 [01:00] */ -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_0_MASK 0x00000003 -#define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_0_SHIFT 0 - -/*************************************************************************** - *HST_SCRATCH_RAM_ADDR_REG - Scratch RAM Address - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: HST_SCRATCH_RAM_ADDR_REG :: reserved0 [31:07] */ -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_reserved0_MASK 0xffffff80 -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_reserved0_SHIFT 7 - -/* DECODE_IP_SHIM_0 :: HST_SCRATCH_RAM_ADDR_REG :: Addr [06:00] */ -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_Addr_MASK 0x0000007f -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_Addr_SHIFT 0 - -/*************************************************************************** - *ARC_SCRATCH_RAM_ADDR_REG - Scratch RAM Address - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: ARC_SCRATCH_RAM_ADDR_REG :: reserved0 [31:07] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_reserved0_MASK 0xffffff80 -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_reserved0_SHIFT 7 - -/* DECODE_IP_SHIM_0 :: ARC_SCRATCH_RAM_ADDR_REG :: Addr [06:00] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_Addr_MASK 0x0000007f -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_Addr_SHIFT 0 - -/*************************************************************************** - *HST_SCRATCH_RAM_DATA_REG - Scratch RAM Data - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: HST_SCRATCH_RAM_DATA_REG :: Data [31:00] */ -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_DATA_REG_Data_MASK 0xffffffff -#define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_DATA_REG_Data_SHIFT 0 - -/*************************************************************************** - *ARC_SCRATCH_RAM_DATA_REG - Scratch RAM Data - ***************************************************************************/ -/* DECODE_IP_SHIM_0 :: ARC_SCRATCH_RAM_DATA_REG :: Data [31:00] */ -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_DATA_REG_Data_MASK 0xffffffff -#define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_DATA_REG_Data_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_IP_SHIM_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_main_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_main_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_main_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_main_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,286 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_main_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:04p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:33 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_main_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:04p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_MAIN_0_H__ -#define BCHP_DECODE_MAIN_0_H__ - -/*************************************************************************** - *DECODE_MAIN_0 - ***************************************************************************/ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL 0x00800100 /* Decoder Control */ -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE 0x00800104 /* Size of the picture being decoded */ -#define BCHP_DECODE_MAIN_0_REG_DEC_VERSION 0x00800108 /* Version of the decoder core */ -#define BCHP_DECODE_MAIN_0_REG_STATUS 0x00800110 /* Provides back-end decoder processing status */ -#define BCHP_DECODE_MAIN_0_REG_PMONCTL 0x00800120 /* Performance Monitoring */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT0 0x00800124 /* REG_PMONCNT0 */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT1 0x00800128 /* REG_PMONCNT1 */ -#define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL 0x0080012c /* REG_PMON_MBCTL */ -#define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL 0x00800130 /* DBLK_BUFF_CONTROL */ -#define BCHP_DECODE_MAIN_0_REG_MAIN_END 0x008001fc /* REG_MAIN_END */ - -/*************************************************************************** - *REG_MAINCTL - Decoder Control - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_MAINCTL :: USE_2_OFF [31:31] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_USE_2_OFF_MASK 0x80000000 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_USE_2_OFF_SHIFT 31 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: reserved0 [30:29] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved0_MASK 0x60000000 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved0_SHIFT 29 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: QPC_OFFSET2 [28:24] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_QPC_OFFSET2_MASK 0x1f000000 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_QPC_OFFSET2_SHIFT 24 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: reserved1 [23:21] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved1_MASK 0x00e00000 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved1_SHIFT 21 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: QpC_Offset [20:16] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_QpC_Offset_MASK 0x001f0000 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_QpC_Offset_SHIFT 16 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: reserved2 [15:13] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved2_MASK 0x0000e000 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved2_SHIFT 13 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: use_alt_mocomp [12:12] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_mocomp_MASK 0x00001000 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_mocomp_SHIFT 12 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: use_alt_xform [11:11] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_xform_MASK 0x00000800 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_xform_SHIFT 11 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: block_ppbuf_avail [10:10] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_block_ppbuf_avail_MASK 0x00000400 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_block_ppbuf_avail_SHIFT 10 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: Standard [09:07] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_Standard_MASK 0x00000380 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_Standard_SHIFT 7 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: Profile [06:04] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_Profile_MASK 0x00000070 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_Profile_SHIFT 4 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: reserved3 [03:01] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved3_MASK 0x0000000e -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved3_SHIFT 1 - -/* DECODE_MAIN_0 :: REG_MAINCTL :: Rst [00:00] */ -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_Rst_MASK 0x00000001 -#define BCHP_DECODE_MAIN_0_REG_MAINCTL_Rst_SHIFT 0 - -/*************************************************************************** - *REG_FRAMESIZE - Size of the picture being decoded - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_FRAMESIZE :: reserved0 [31:28] */ -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved0_MASK 0xf0000000 -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved0_SHIFT 28 - -/* DECODE_MAIN_0 :: REG_FRAMESIZE :: Lines [27:16] */ -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Lines_MASK 0x0fff0000 -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Lines_SHIFT 16 - -/* DECODE_MAIN_0 :: REG_FRAMESIZE :: reserved1 [15:12] */ -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved1_MASK 0x0000f000 -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved1_SHIFT 12 - -/* DECODE_MAIN_0 :: REG_FRAMESIZE :: Pixels [11:00] */ -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Pixels_MASK 0x00000fff -#define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Pixels_SHIFT 0 - -/*************************************************************************** - *REG_DEC_VERSION - Version of the decoder core - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_DEC_VERSION :: Major [31:16] */ -#define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Major_MASK 0xffff0000 -#define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Major_SHIFT 16 - -/* DECODE_MAIN_0 :: REG_DEC_VERSION :: Minor [15:08] */ -#define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Minor_MASK 0x0000ff00 -#define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Minor_SHIFT 8 - -/* DECODE_MAIN_0 :: REG_DEC_VERSION :: FixID [07:00] */ -#define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_FixID_MASK 0x000000ff -#define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_FixID_SHIFT 0 - -/*************************************************************************** - *REG_STATUS - Provides back-end decoder processing status - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_STATUS :: Ixfm [31:30] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_Ixfm_MASK 0xc0000000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_Ixfm_SHIFT 30 - -/* DECODE_MAIN_0 :: REG_STATUS :: Spre [29:28] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_Spre_MASK 0x30000000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_Spre_SHIFT 28 - -/* DECODE_MAIN_0 :: REG_STATUS :: Mcom [27:26] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_Mcom_MASK 0x0c000000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_Mcom_SHIFT 26 - -/* DECODE_MAIN_0 :: REG_STATUS :: reserved0 [25:22] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_reserved0_MASK 0x03c00000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_reserved0_SHIFT 22 - -/* DECODE_MAIN_0 :: REG_STATUS :: InpBuf_Overflow [21:16] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_InpBuf_Overflow_MASK 0x003f0000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_InpBuf_Overflow_SHIFT 16 - -/* DECODE_MAIN_0 :: REG_STATUS :: mocomp_data_avail [15:15] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_mocomp_data_avail_MASK 0x00008000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_mocomp_data_avail_SHIFT 15 - -/* DECODE_MAIN_0 :: REG_STATUS :: xform_data_avail [14:14] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_xform_data_avail_MASK 0x00004000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_xform_data_avail_SHIFT 14 - -/* DECODE_MAIN_0 :: REG_STATUS :: Output [13:12] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_Output_MASK 0x00003000 -#define BCHP_DECODE_MAIN_0_REG_STATUS_Output_SHIFT 12 - -/* DECODE_MAIN_0 :: REG_STATUS :: Dblk [11:10] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_Dblk_MASK 0x00000c00 -#define BCHP_DECODE_MAIN_0_REG_STATUS_Dblk_SHIFT 10 - -/* DECODE_MAIN_0 :: REG_STATUS :: Recon [09:08] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_Recon_MASK 0x00000300 -#define BCHP_DECODE_MAIN_0_REG_STATUS_Recon_SHIFT 8 - -/* DECODE_MAIN_0 :: REG_STATUS :: reserved1 [07:00] */ -#define BCHP_DECODE_MAIN_0_REG_STATUS_reserved1_MASK 0x000000ff -#define BCHP_DECODE_MAIN_0_REG_STATUS_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_PMONCTL - Performance Monitoring - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_PMONCTL :: reserved0 [31:12] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved0_MASK 0xfffff000 -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved0_SHIFT 12 - -/* DECODE_MAIN_0 :: REG_PMONCTL :: CNT1_SEL [11:08] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT1_SEL_MASK 0x00000f00 -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT1_SEL_SHIFT 8 - -/* DECODE_MAIN_0 :: REG_PMONCTL :: reserved1 [07:04] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved1_MASK 0x000000f0 -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved1_SHIFT 4 - -/* DECODE_MAIN_0 :: REG_PMONCTL :: CNT0_SEL [03:00] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT0_SEL_MASK 0x0000000f -#define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT0_SEL_SHIFT 0 - -/*************************************************************************** - *REG_PMONCNT0 - REG_PMONCNT0 - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_PMONCNT0 :: DATA [31:16] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT0_DATA_MASK 0xffff0000 -#define BCHP_DECODE_MAIN_0_REG_PMONCNT0_DATA_SHIFT 16 - -/* DECODE_MAIN_0 :: REG_PMONCNT0 :: reserved0 [15:12] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT0_reserved0_MASK 0x0000f000 -#define BCHP_DECODE_MAIN_0_REG_PMONCNT0_reserved0_SHIFT 12 - -/* DECODE_MAIN_0 :: REG_PMONCNT0 :: COUNT [11:00] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT0_COUNT_MASK 0x00000fff -#define BCHP_DECODE_MAIN_0_REG_PMONCNT0_COUNT_SHIFT 0 - -/*************************************************************************** - *REG_PMONCNT1 - REG_PMONCNT1 - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_PMONCNT1 :: DATA [31:16] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT1_DATA_MASK 0xffff0000 -#define BCHP_DECODE_MAIN_0_REG_PMONCNT1_DATA_SHIFT 16 - -/* DECODE_MAIN_0 :: REG_PMONCNT1 :: reserved0 [15:12] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT1_reserved0_MASK 0x0000f000 -#define BCHP_DECODE_MAIN_0_REG_PMONCNT1_reserved0_SHIFT 12 - -/* DECODE_MAIN_0 :: REG_PMONCNT1 :: COUNT [11:00] */ -#define BCHP_DECODE_MAIN_0_REG_PMONCNT1_COUNT_MASK 0x00000fff -#define BCHP_DECODE_MAIN_0_REG_PMONCNT1_COUNT_SHIFT 0 - -/*************************************************************************** - *REG_PMON_MBCTL - REG_PMON_MBCTL - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_PMON_MBCTL :: reserved0 [31:02] */ -#define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_reserved0_MASK 0xfffffffc -#define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_reserved0_SHIFT 2 - -/* DECODE_MAIN_0 :: REG_PMON_MBCTL :: SW_Pmon [01:01] */ -#define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_SW_Pmon_MASK 0x00000002 -#define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_SW_Pmon_SHIFT 1 - -/* DECODE_MAIN_0 :: REG_PMON_MBCTL :: MBCtlEna [00:00] */ -#define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_MBCtlEna_MASK 0x00000001 -#define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_MBCtlEna_SHIFT 0 - -/*************************************************************************** - *DBLK_BUFF_CONTROL - DBLK_BUFF_CONTROL - ***************************************************************************/ -/* DECODE_MAIN_0 :: DBLK_BUFF_CONTROL :: reserved0 [31:01] */ -#define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_reserved0_MASK 0xfffffffe -#define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_reserved0_SHIFT 1 - -/* DECODE_MAIN_0 :: DBLK_BUFF_CONTROL :: Enable [00:00] */ -#define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_Enable_MASK 0x00000001 -#define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_Enable_SHIFT 0 - -/*************************************************************************** - *REG_MAIN_END - REG_MAIN_END - ***************************************************************************/ -/* DECODE_MAIN_0 :: REG_MAIN_END :: reserved0 [31:00] */ -#define BCHP_DECODE_MAIN_0_REG_MAIN_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_MAIN_0_REG_MAIN_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_MAIN_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mb_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mb_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mb_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mb_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,184 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_mb_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:04p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:33 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mb_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:04p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_MB_0_H__ -#define BCHP_DECODE_MB_0_H__ - -/*************************************************************************** - *DECODE_MB_0 - ***************************************************************************/ -#define BCHP_DECODE_MB_0_REG_MB_CTL 0x00800740 /* Decode Macroblock Control */ -#define BCHP_DECODE_MB_0_REG_MB_END 0x0080075c /* REG_MB_END */ - -/*************************************************************************** - *REG_MB_CTL - Decode Macroblock Control - ***************************************************************************/ -/* union - case WRITE [31:00] */ -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: reserved0 [31:28] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved0_MASK 0xf0000000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved0_SHIFT 28 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: FCM [27:26] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_FCM_MASK 0x0c000000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_FCM_SHIFT 26 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Type [25:24] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Type_MASK 0x03000000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Type_SHIFT 24 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: reserved1 [23:20] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved1_MASK 0x00f00000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved1_SHIFT 20 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Intra_MB [19:19] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Intra_MB_MASK 0x00080000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Intra_MB_SHIFT 19 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Mbaff [18:18] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Mbaff_MASK 0x00040000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Mbaff_SHIFT 18 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Top [17:17] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Top_MASK 0x00020000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Top_SHIFT 17 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Fld [16:16] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Fld_MASK 0x00010000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Fld_SHIFT 16 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: reserved2 [15:15] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved2_MASK 0x00008000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved2_SHIFT 15 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: YdestMB [14:08] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_YdestMB_MASK 0x00007f00 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_YdestMB_SHIFT 8 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Rv [07:07] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Rv_MASK 0x00000080 -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Rv_SHIFT 7 - -/* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: XdestMB [06:00] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_XdestMB_MASK 0x0000007f -#define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_XdestMB_SHIFT 0 - -/* union - case READ [31:00] */ -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: reserved0 [31:15] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_reserved0_MASK 0xffff8000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_reserved0_SHIFT 15 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: QRdyA [14:14] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyA_MASK 0x00004000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyA_SHIFT 14 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: QEmptyA [13:13] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyA_MASK 0x00002000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyA_SHIFT 13 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: QMBendA [12:12] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendA_MASK 0x00001000 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendA_SHIFT 12 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: QRdyB [11:11] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyB_MASK 0x00000800 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyB_SHIFT 11 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: QEmptyB [10:10] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyB_MASK 0x00000400 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyB_SHIFT 10 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: QMBendB [09:09] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendB_MASK 0x00000200 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendB_SHIFT 9 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: IntraRdy [08:08] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraRdy_MASK 0x00000100 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraRdy_SHIFT 8 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: IntraEmpty [07:07] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraEmpty_MASK 0x00000080 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraEmpty_SHIFT 7 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: IntraMBend [06:06] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraMBend_MASK 0x00000040 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraMBend_SHIFT 6 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: IXformRdy [05:05] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformRdy_MASK 0x00000020 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformRdy_SHIFT 5 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: IXformEmpty [04:04] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformEmpty_MASK 0x00000010 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformEmpty_SHIFT 4 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: IXformMBend [03:03] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformMBend_MASK 0x00000008 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformMBend_SHIFT 3 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: QRdy [02:02] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdy_MASK 0x00000004 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdy_SHIFT 2 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: XRdy [01:01] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_XRdy_MASK 0x00000002 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_XRdy_SHIFT 1 - -/* DECODE_MB_0 :: REG_MB_CTL :: READ :: IRdy [00:00] */ -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IRdy_MASK 0x00000001 -#define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IRdy_SHIFT 0 - -/*************************************************************************** - *REG_MB_END - REG_MB_END - ***************************************************************************/ -/* DECODE_MB_0 :: REG_MB_END :: reserved0 [31:00] */ -#define BCHP_DECODE_MB_0_REG_MB_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_MB_0_REG_MB_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_MB_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mcom_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mcom_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mcom_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mcom_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,282 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_mcom_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:05p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:36 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mcom_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:05p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_MCOM_0_H__ -#define BCHP_DECODE_MCOM_0_H__ - -/*************************************************************************** - *DECODE_MCOM_0 - ***************************************************************************/ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL 0x00800300 /* Motion Compensation Control */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A 0x00800304 /* Motion Compensation Source A */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B 0x00800308 /* Motion Compensation Source */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC 0x0080030c /* VC-1 Mocomp Picture-Level Control */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC 0x00800310 /* VC-1 Mocomp Bottom Pic */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL 0x00800314 /* Weighted Prediction Selection */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC 0x00800318 /* VC-1 Mocomp Back Pic */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_END 0x0080031c /* REG_MCOM_END */ - -/*************************************************************************** - *REG_MCOM_CTL - Motion Compensation Control - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: Bintl [31:31] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bintl_MASK 0x80000000 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bintl_SHIFT 31 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: Bref [30:24] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bref_MASK 0x7f000000 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bref_SHIFT 24 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: Aintl [23:23] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Aintl_MASK 0x00800000 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Aintl_SHIFT 23 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: ARef [22:16] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ARef_MASK 0x007f0000 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ARef_SHIFT 16 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: SubBlock [15:12] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_SubBlock_MASK 0x0000f000 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_SubBlock_SHIFT 12 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: BBot [11:11] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BBot_MASK 0x00000800 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BBot_SHIFT 11 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: BFld [10:10] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BFld_MASK 0x00000400 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BFld_SHIFT 10 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: ABot [09:09] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ABot_MASK 0x00000200 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ABot_SHIFT 9 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: AFld [08:08] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_AFld_MASK 0x00000100 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_AFld_SHIFT 8 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: YSize [07:06] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_YSize_MASK 0x000000c0 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_YSize_SHIFT 6 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: XSize [05:04] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_XSize_MASK 0x00000030 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_XSize_SHIFT 4 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: Luma [03:03] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Luma_MASK 0x00000008 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Luma_SHIFT 3 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: Filter261 [02:02] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Filter261_MASK 0x00000004 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Filter261_SHIFT 2 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: Mde [01:01] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Mde_MASK 0x00000002 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Mde_SHIFT 1 - -/* DECODE_MCOM_0 :: REG_MCOM_CTL :: Back [00:00] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Back_MASK 0x00000001 -#define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Back_SHIFT 0 - -/*************************************************************************** - *REG_MCOM_SRC_A - Motion Compensation Source A - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_MCOM_SRC_A :: YSrc [31:16] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_YSrc_MASK 0xffff0000 -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_YSrc_SHIFT 16 - -/* DECODE_MCOM_0 :: REG_MCOM_SRC_A :: XSrc [15:00] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_XSrc_MASK 0x0000ffff -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_XSrc_SHIFT 0 - -/*************************************************************************** - *REG_MCOM_SRC_B - Motion Compensation Source - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_MCOM_SRC_B :: YSrc [31:16] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_YSrc_MASK 0xffff0000 -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_YSrc_SHIFT 16 - -/* DECODE_MCOM_0 :: REG_MCOM_SRC_B :: XSrc [15:00] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_XSrc_MASK 0x0000ffff -#define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_XSrc_SHIFT 0 - -/*************************************************************************** - *REG_WPRD_VC1_PIC - VC-1 Mocomp Picture-Level Control - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: reserved0 [31:30] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved0_MASK 0xc0000000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved0_SHIFT 30 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: ALT_PAD [29:29] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_ALT_PAD_MASK 0x20000000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_ALT_PAD_SHIFT 29 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: reserved1 [28:28] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved1_MASK 0x10000000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved1_SHIFT 28 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SHIFT2 [27:22] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT2_MASK 0x0fc00000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT2_SHIFT 22 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SCALE2 [21:16] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE2_MASK 0x003f0000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE2_SHIFT 16 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SHIFT1 [15:10] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT1_MASK 0x0000fc00 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT1_SHIFT 10 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SCALE1 [09:04] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE1_MASK 0x000003f0 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE1_SHIFT 4 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: reserved2 [03:02] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved2_MASK 0x0000000c -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved2_SHIFT 2 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: BICUBIC [01:01] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_BICUBIC_MASK 0x00000002 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_BICUBIC_SHIFT 1 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: RND [00:00] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_RND_MASK 0x00000001 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_RND_SHIFT 0 - -/*************************************************************************** - *REG_WPRD_VC1_BOT_PIC - VC-1 Mocomp Bottom Pic - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: reserved0 [31:28] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved0_MASK 0xf0000000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved0_SHIFT 28 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SHIFT2 [27:22] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT2_MASK 0x0fc00000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT2_SHIFT 22 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SCALE2 [21:16] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE2_MASK 0x003f0000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE2_SHIFT 16 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SHIFT1 [15:10] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT1_MASK 0x0000fc00 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT1_SHIFT 10 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SCALE1 [09:04] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE1_MASK 0x000003f0 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE1_SHIFT 4 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: reserved1 [03:00] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved1_MASK 0x0000000f -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_WPRD_SEL - Weighted Prediction Selection - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_WPRD_SEL :: reserved0 [31:30] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved0_MASK 0xc0000000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved0_SHIFT 30 - -/* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecAWtSel0 [29:25] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel0_MASK 0x3e000000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel0_SHIFT 25 - -/* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecBWtSel0 [24:16] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel0_MASK 0x01ff0000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel0_SHIFT 16 - -/* DECODE_MCOM_0 :: REG_WPRD_SEL :: Wt1 [15:15] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_Wt1_MASK 0x00008000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_Wt1_SHIFT 15 - -/* DECODE_MCOM_0 :: REG_WPRD_SEL :: reserved1 [14:14] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved1_MASK 0x00004000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved1_SHIFT 14 - -/* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecAWtSel1 [13:09] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel1_MASK 0x00003e00 -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel1_SHIFT 9 - -/* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecBWtSel1 [08:00] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel1_MASK 0x000001ff -#define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel1_SHIFT 0 - -/*************************************************************************** - *REG_WPRD_VC1_BACK_PIC - VC-1 Mocomp Back Pic - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: reserved0 [31:16] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved0_SHIFT 16 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: Shift1 [15:10] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Shift1_MASK 0x0000fc00 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Shift1_SHIFT 10 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: Scale1 [09:04] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Scale1_MASK 0x000003f0 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Scale1_SHIFT 4 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: reserved1 [03:01] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved1_MASK 0x0000000e -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved1_SHIFT 1 - -/* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: Bot [00:00] */ -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Bot_MASK 0x00000001 -#define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Bot_SHIFT 0 - -/*************************************************************************** - *REG_MCOM_END - REG_MCOM_END - ***************************************************************************/ -/* DECODE_MCOM_0 :: REG_MCOM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_MCOM_0_REG_MCOM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_MCOM_0_REG_MCOM_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_MCOM_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_rvc_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_rvc_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_rvc_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_rvc_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,122 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_rvc_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:05p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:24 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_rvc_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:05p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_RVC_0_H__ -#define BCHP_DECODE_RVC_0_H__ - -/*************************************************************************** - *DECODE_RVC_0 - ***************************************************************************/ -#define BCHP_DECODE_RVC_0_REG_RVC_CTL 0x00800e00 /* REG_RVC_CTL */ -#define BCHP_DECODE_RVC_0_REG_RVC_PUT 0x00800e04 /* REG_RVC_PUT */ -#define BCHP_DECODE_RVC_0_REG_RVC_GET 0x00800e08 /* REG_RVC_GET */ -#define BCHP_DECODE_RVC_0_REG_RVC_BASE 0x00800e0c /* REG_RVC_BASE */ -#define BCHP_DECODE_RVC_0_REG_RVC_END 0x00800e10 /* REG_RVC_END */ -#define BCHP_DECODE_RVC_0_REG_RVC_END_END 0x00800efc /* REG_RVC_END_END */ - -/*************************************************************************** - *REG_RVC_CTL - REG_RVC_CTL - ***************************************************************************/ -/* DECODE_RVC_0 :: REG_RVC_CTL :: reserved0 [31:01] */ -#define BCHP_DECODE_RVC_0_REG_RVC_CTL_reserved0_MASK 0xfffffffe -#define BCHP_DECODE_RVC_0_REG_RVC_CTL_reserved0_SHIFT 1 - -/* DECODE_RVC_0 :: REG_RVC_CTL :: Ena [00:00] */ -#define BCHP_DECODE_RVC_0_REG_RVC_CTL_Ena_MASK 0x00000001 -#define BCHP_DECODE_RVC_0_REG_RVC_CTL_Ena_SHIFT 0 - -/*************************************************************************** - *REG_RVC_PUT - REG_RVC_PUT - ***************************************************************************/ -/* DECODE_RVC_0 :: REG_RVC_PUT :: Put_Ptr [31:00] */ -#define BCHP_DECODE_RVC_0_REG_RVC_PUT_Put_Ptr_MASK 0xffffffff -#define BCHP_DECODE_RVC_0_REG_RVC_PUT_Put_Ptr_SHIFT 0 - -/*************************************************************************** - *REG_RVC_GET - REG_RVC_GET - ***************************************************************************/ -/* DECODE_RVC_0 :: REG_RVC_GET :: Get_Ptr [31:05] */ -#define BCHP_DECODE_RVC_0_REG_RVC_GET_Get_Ptr_MASK 0xffffffe0 -#define BCHP_DECODE_RVC_0_REG_RVC_GET_Get_Ptr_SHIFT 5 - -/* DECODE_RVC_0 :: REG_RVC_GET :: reserved0 [04:00] */ -#define BCHP_DECODE_RVC_0_REG_RVC_GET_reserved0_MASK 0x0000001f -#define BCHP_DECODE_RVC_0_REG_RVC_GET_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_RVC_BASE - REG_RVC_BASE - ***************************************************************************/ -/* DECODE_RVC_0 :: REG_RVC_BASE :: Base_Addr [31:20] */ -#define BCHP_DECODE_RVC_0_REG_RVC_BASE_Base_Addr_MASK 0xfff00000 -#define BCHP_DECODE_RVC_0_REG_RVC_BASE_Base_Addr_SHIFT 20 - -/* DECODE_RVC_0 :: REG_RVC_BASE :: reserved0 [19:00] */ -#define BCHP_DECODE_RVC_0_REG_RVC_BASE_reserved0_MASK 0x000fffff -#define BCHP_DECODE_RVC_0_REG_RVC_BASE_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_RVC_END - REG_RVC_END - ***************************************************************************/ -/* DECODE_RVC_0 :: REG_RVC_END :: End_Addr [31:20] */ -#define BCHP_DECODE_RVC_0_REG_RVC_END_End_Addr_MASK 0xfff00000 -#define BCHP_DECODE_RVC_0_REG_RVC_END_End_Addr_SHIFT 20 - -/* DECODE_RVC_0 :: REG_RVC_END :: reserved0 [19:00] */ -#define BCHP_DECODE_RVC_0_REG_RVC_END_reserved0_MASK 0x000fffff -#define BCHP_DECODE_RVC_0_REG_RVC_END_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_RVC_END_END - REG_RVC_END_END - ***************************************************************************/ -/* DECODE_RVC_0 :: REG_RVC_END_END :: reserved0 [31:00] */ -#define BCHP_DECODE_RVC_0_REG_RVC_END_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_RVC_0_REG_RVC_END_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_RVC_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1727 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_sint_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:05p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:58 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:05p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_SINT_0_H__ -#define BCHP_DECODE_SINT_0_H__ - -/*************************************************************************** - *DECODE_SINT_0 - ***************************************************************************/ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR 0x00800c00 /* REG_SINT_DMA_ADDR */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN 0x00800c04 /* REG_SINT_DMA_LEN */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE 0x00800c08 /* REG_SINT_DMA_BASE */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_END 0x00800c0c /* REG_SINT_DMA_END */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_POS 0x00800c10 /* REG_SINT_STRM_POS */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT 0x00800c14 /* REG_SINT_STRM_STAT */ -#define BCHP_DECODE_SINT_0_REG_SINT_IENA 0x00800c18 /* REG_SINT_IENA */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_BITS 0x00800c1c /* REG_SINT_STRM_BITS */ -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB 0x00800c20 /* REG_SINT_GET_SYMB */ -#define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC 0x00800c24 /* REG_SINT_MPEG_DC */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID 0x00800c28 /* REG_SINT_DO_RESID */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO 0x00800c2c /* REG_SINT_XNZERO */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE 0x00800c30 /* REG_SINT_VEC_MBTYPE */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID 0x00800c34 /* REG_SINT_VEC_RESID */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE 0x00800c38 /* REG_SINT_VEC_DMODE */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOP_LD 0x00800c3c /* REG_SINT_VEC_TOP_LD */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST 0x00800c40 /* REG_SINT_VEC_DO_CONST */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF 0x00800c44 /* Deblocking Motion Vector Difference */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX 0x00800c48 /* REG_SINT_VEC_REFIDX */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF 0x00800c4c /* REG_SINT_VEC_TOPREF */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF 0x00800c50 /* REG_SINT_VEC_TOPTOPREF */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE 0x00800c54 /* REG_SINT_VEC_COL_TYPE */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID 0x00800c58 /* REG_SINT_VEC_COL_REFID */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC 0x00800c5c /* REG_SINT_VEC_TOPPIC */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO 0x00800c60 /* REG_SINT_VEC_VC1_INFO */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC 0x00800c64 /* REG_SINT_VEC_REFPIC - H.264 only */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT 0x00800c68 /* REG_SINT_VEC_COUNT */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVD_FIFO 0x00800c6c /* REG_SINT_VEC_MVD_FIFO */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL 0x00800c70 /* REG_SINT_DIVX_TABSEL */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX 0x00800c74 /* REG_SINT_CTL_AUX */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REGEND 0x00800c7c /* REG_SINT_VEC_REGEND */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL 0x00800c80 /* REG_SINT_CTL */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX 0x00800c84 /* REG_SINT_VLC_TOPCTX */ -#define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID 0x00800c88 /* REG_SINT_SLICE_ID */ -#define BCHP_DECODE_SINT_0_REG_SINT_QP 0x00800c8c /* REG_SINT_QP */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR 0x00800c90 /* REG_SINT_TOP_BASE_ADDR */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIRCTX_WR_ADDR 0x00800c94 /* REG_SINT_DIRCTX_WR_ADDR */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOPCTX_DATA 0x00800c98 /* REG_SINT_TOPCTX_DATA */ -#define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB 0x00800c9c /* REG_SINT_XFER_SYMB */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE 0x00800ca0 /* REG_SINT_SMODE_BASE */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT 0x00800ca4 /* REG_SINT_SMODE_LEFT */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP 0x00800ca8 /* REG_SINT_SMODE_TOP */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_END 0x00800cac /* REG_SINT_SMODE_END */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT 0x00800cb0 /* REG_SINT_CTX_INIT */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX 0x00800cb4 /* REG_SINT_TOP_CTX */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL 0x00800cb8 /* REG_SINT_VC1_TABSEL */ -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA 0x00800cbc /* REG_SINT_CNST_INTRA */ -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE 0x00800cc0 /* Outpic Lookup */ -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_END 0x00800cfc /* REG_SINT_OPIC_MEM_END */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE 0x00800d00 /* Vector Memory */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_END 0x00800dfc /* REG_SINT_VEC_MEM_END */ - -/*************************************************************************** - *REG_SINT_DMA_ADDR - REG_SINT_DMA_ADDR - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_DMA_ADDR :: Addr [31:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_Addr_MASK 0xfffffffc -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_Addr_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_DMA_ADDR :: reserved0 [01:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_reserved0_MASK 0x00000003 -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_DMA_LEN - REG_SINT_DMA_LEN - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_DMA_LEN :: Length [31:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_Length_MASK 0xffffffe0 -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_Length_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_DMA_LEN :: reserved0 [04:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_reserved0_MASK 0x0000001f -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_DMA_BASE - REG_SINT_DMA_BASE - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_DMA_BASE :: Base [31:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Base_MASK 0xffffff00 -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Base_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_DMA_BASE :: reserved0 [07:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_reserved0_MASK 0x000000fe -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_reserved0_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_DMA_BASE :: Endian [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Endian_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Endian_SHIFT 0 - -/*************************************************************************** - *REG_SINT_DMA_END - REG_SINT_DMA_END - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_DMA_END :: End [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_END_End_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_DMA_END_End_SHIFT 0 - -/*************************************************************************** - *REG_SINT_STRM_POS - REG_SINT_STRM_POS - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_STRM_POS :: Bit_pos [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_POS_Bit_pos_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_POS_Bit_pos_SHIFT 0 - -/*************************************************************************** - *REG_SINT_STRM_STAT - REG_SINT_STRM_STAT - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: reserved0 [31:19] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved0_MASK 0xfff80000 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved0_SHIFT 19 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: FlushInput [18:18] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushInput_MASK 0x00040000 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushInput_SHIFT 18 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: FlushCTX [17:17] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushCTX_MASK 0x00020000 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushCTX_SHIFT 17 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Rst [16:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Rst_MASK 0x00010000 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Rst_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: reserved1 [15:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved1_MASK 0x0000f000 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved1_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: CtxDmaAct [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CtxDmaAct_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CtxDmaAct_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: MVD_AVAIL [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_MVD_AVAIL_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_MVD_AVAIL_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Derr [09:09] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Derr_MASK 0x00000200 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Derr_SHIFT 9 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Serr [08:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Serr_MASK 0x00000100 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Serr_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: CgParse [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CgParse_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CgParse_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: CCAc [06:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CCAc_MASK 0x00000040 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CCAc_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: VCAc [05:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_VCAc_MASK 0x00000020 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_VCAc_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Vact [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Vact_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Vact_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Dact [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Dact_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Dact_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Sact [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sact_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sact_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Cact [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Cact_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Cact_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Sval [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sval_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sval_SHIFT 0 - -/*************************************************************************** - *REG_SINT_IENA - REG_SINT_IENA - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_IENA :: reserved0 [31:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved0_MASK 0xfffffc00 -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved0_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_IENA :: Derr [09:09] */ -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_Derr_MASK 0x00000200 -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_Derr_SHIFT 9 - -/* DECODE_SINT_0 :: REG_SINT_IENA :: Serr [08:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_Serr_MASK 0x00000100 -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_Serr_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_IENA :: reserved1 [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved1_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_SINT_STRM_BITS - REG_SINT_STRM_BITS - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_STRM_BITS :: Stream_Bits [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_BITS_Stream_Bits_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_STRM_BITS_Stream_Bits_SHIFT 0 - -/*************************************************************************** - *REG_SINT_GET_SYMB - REG_SINT_GET_SYMB - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: reserved0 [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_reserved0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: Type [15:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_Type_MASK 0x0000f000 -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_Type_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: SubType [11:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_SubType_MASK 0x00000f00 -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_SubType_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: N [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_N_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_N_SHIFT 0 - -/*************************************************************************** - *REG_SINT_MPEG_DC - REG_SINT_MPEG_DC - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_MPEG_DC :: reserved0 [31:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_reserved0_MASK 0xffffc000 -#define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_reserved0_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_MPEG_DC :: Comp [13:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_Comp_MASK 0x00003000 -#define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_Comp_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_MPEG_DC :: DC_Pred [11:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_DC_Pred_MASK 0x00000fff -#define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_DC_Pred_SHIFT 0 - -/*************************************************************************** - *REG_SINT_DO_RESID - REG_SINT_DO_RESID - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: AVS [31:31] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_AVS_MASK 0x80000000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_AVS_SHIFT 31 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: DivX [30:30] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DivX_MASK 0x40000000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DivX_SHIFT 30 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Use_intra_dc_vlc [29:29] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Use_intra_dc_vlc_MASK 0x20000000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Use_intra_dc_vlc_SHIFT 29 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Short_Vid_Hdr [28:28] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Short_Vid_Hdr_MASK 0x10000000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Short_Vid_Hdr_SHIFT 28 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Mpeg4 [27:27] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Mpeg4_MASK 0x08000000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Mpeg4_SHIFT 27 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_TTMbf [26:26] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTMbf_MASK 0x04000000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTMbf_SHIFT 26 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_TTFrmSize [25:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTFrmSize_MASK 0x03000000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTFrmSize_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: reserved0 [23:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_reserved0_MASK 0x00c00000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_reserved0_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_DBlkEna [21:21] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_DBlkEna_MASK 0x00200000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_DBlkEna_SHIFT 21 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_OlapEna [20:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_OlapEna_MASK 0x00100000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_OlapEna_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: FastEna [19:19] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_FastEna_MASK 0x00080000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_FastEna_SHIFT 19 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Skip [18:18] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Skip_MASK 0x00040000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Skip_SHIFT 18 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Intra_264 [17:17] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_264_MASK 0x00020000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_264_SHIFT 17 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Fetch_QP [16:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Fetch_QP_MASK 0x00010000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Fetch_QP_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Type [15:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Type_MASK 0x0000c000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Type_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: SubType [13:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SubType_MASK 0x00003000 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SubType_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: SwapCBP [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SwapCBP_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SwapCBP_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: WrXNZero [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_WrXNZero_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_WrXNZero_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: DCPrecision [09:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DCPrecision_MASK 0x00000300 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DCPrecision_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VLCTable1 [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VLCTable1_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VLCTable1_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Intra [06:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_MASK 0x00000040 -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_DO_RESID :: CBP [05:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_CBP_MASK 0x0000003f -#define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_CBP_SHIFT 0 - -/*************************************************************************** - *REG_SINT_XNZERO - REG_SINT_XNZERO - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: reserved0 [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_reserved0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B15 [15:15] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B15_MASK 0x00008000 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B15_SHIFT 15 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B14 [14:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B14_MASK 0x00004000 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B14_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B13 [13:13] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B13_MASK 0x00002000 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B13_SHIFT 13 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B12 [12:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B12_MASK 0x00001000 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B12_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B11 [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B11_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B11_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B10 [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B10_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B10_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B9 [09:09] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B9_MASK 0x00000200 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B9_SHIFT 9 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B8 [08:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B8_MASK 0x00000100 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B8_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B7 [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B7_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B7_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B6 [06:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B6_MASK 0x00000040 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B6_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B5 [05:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B5_MASK 0x00000020 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B5_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B4 [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B4_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B4_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B3 [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B3_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B3_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B2 [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B2_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B2_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B1 [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B1_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B1_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_XNZERO :: B0 [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B0_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_MBTYPE - REG_SINT_VEC_MBTYPE - ***************************************************************************/ -/* union - case H264 [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved0 [31:25] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved0_MASK 0xfe000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved0_SHIFT 25 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType3 [24:21] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType3_MASK 0x01e00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType3_SHIFT 21 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved1 [20:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved1_MASK 0x00100000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved1_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType2 [19:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType2_MASK 0x000f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType2_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved2 [15:15] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved2_MASK 0x00008000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved2_SHIFT 15 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType1 [14:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType1_MASK 0x00007800 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType1_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved3 [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved3_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved3_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType0 [09:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType0_MASK 0x000003c0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType0_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: MBType [05:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_MBType_MASK 0x0000003e -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_MBType_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: ISB [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_ISB_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_ISB_SHIFT 0 - -/* union - case VC1 [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: reserved0 [31:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved0_MASK 0xffc00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved0_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: BlkPat [21:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BlkPat_MASK 0x003f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BlkPat_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: reserved1 [15:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved1_MASK 0x0000c000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved1_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: MBMode [13:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MBMode_MASK 0x00003f00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MBMode_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: reserved2 [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved2_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved2_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: BMVType [06:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BMVType_MASK 0x00000060 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BMVType_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: MVSW [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MVSW_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MVSW_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: InterpMVP [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_InterpMVP_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_InterpMVP_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: Forward [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Forward_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Forward_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: Direct [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Direct_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Direct_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: Skip [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Skip_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Skip_SHIFT 0 - -/* union - case MPEG4 [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: reserved0 [31:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_reserved0_MASK 0xffffc000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_reserved0_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: qpel [13:13] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_qpel_MASK 0x00002000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_qpel_SHIFT 13 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: gmc [12:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_gmc_MASK 0x00001000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_gmc_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: no_mvd [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_no_mvd_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_no_mvd_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: intra [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_intra_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_intra_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: fcode_back [09:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_back_MASK 0x00000380 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_back_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: fcode_fwd [06:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_fwd_MASK 0x00000070 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_fwd_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: four_mv [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_four_mv_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_four_mv_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: alt_mv [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_alt_mv_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_alt_mv_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: direct [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_direct_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_direct_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: skip [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_skip_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_skip_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_RESID - REG_SINT_VEC_RESID - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_RESID :: Y_Residual [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_Y_Residual_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_Y_Residual_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_RESID :: X_Residual [15:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_X_Residual_MASK 0x0000ffff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_X_Residual_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_DMODE - REG_SINT_VEC_DMODE - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_DMODE :: reserved0 [31:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_reserved0_MASK 0xfffffff0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_reserved0_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DMODE :: Dmode [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_Dmode_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_Dmode_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_TOP_LD - REG_SINT_VEC_TOP_LD - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_TOP_LD :: reserved0 [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOP_LD_reserved0_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOP_LD_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_DO_CONST - REG_SINT_VEC_DO_CONST - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: reserved0 [31:28] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved0_MASK 0xf0000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved0_SHIFT 28 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: direct_frm2fld [27:27] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_direct_frm2fld_MASK 0x08000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_direct_frm2fld_SHIFT 27 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: wholepel_8x8 [26:26] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_8x8_MASK 0x04000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_8x8_SHIFT 26 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: wholepel_all [25:25] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_all_MASK 0x02000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_all_SHIFT 25 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_1ref_is_bot [24:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_1ref_is_bot_MASK 0x01000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_1ref_is_bot_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: refdist_back [23:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_back_MASK 0x00c00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_back_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: refdist_fwd [21:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_fwd_MASK 0x00300000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_fwd_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_2nd_fld [19:19] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2nd_fld_MASK 0x00080000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2nd_fld_SHIFT 19 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Back_is_intl [18:18] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Back_is_intl_MASK 0x00040000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Back_is_intl_SHIFT 18 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Fwd_is_intl [17:17] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Fwd_is_intl_MASK 0x00020000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Fwd_is_intl_SHIFT 17 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_2ref [16:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2ref_MASK 0x00010000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2ref_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_bfract_gt_half [15:15] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_bfract_gt_half_MASK 0x00008000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_bfract_gt_half_SHIFT 15 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_DmvRange [14:13] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_DmvRange_MASK 0x00006000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_DmvRange_SHIFT 13 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_mvRange [12:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_mvRange_MASK 0x00001800 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_mvRange_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_HalfPel [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_HalfPel_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_HalfPel_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: MVDiff [09:09] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_MVDiff_MASK 0x00000200 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_MVDiff_SHIFT 9 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: ROLT [08:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_ROLT_MASK 0x00000100 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_ROLT_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Lcpy [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Lcpy_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Lcpy_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: reserved1 [06:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved1_MASK 0x00000040 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved1_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Pskip [05:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Pskip_MASK 0x00000020 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Pskip_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Intra [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Intra_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Intra_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: reserved2 [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved2_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved2_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_MVDIFF - Deblocking Motion Vector Difference - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V15 [31:31] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V15_MASK 0x80000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V15_SHIFT 31 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V14 [30:30] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V14_MASK 0x40000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V14_SHIFT 30 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V13 [29:29] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V13_MASK 0x20000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V13_SHIFT 29 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V12 [28:28] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V12_MASK 0x10000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V12_SHIFT 28 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V11 [27:27] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V11_MASK 0x08000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V11_SHIFT 27 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V10 [26:26] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V10_MASK 0x04000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V10_SHIFT 26 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V9 [25:25] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V9_MASK 0x02000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V9_SHIFT 25 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V8 [24:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V8_MASK 0x01000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V8_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V7 [23:23] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V7_MASK 0x00800000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V7_SHIFT 23 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V6 [22:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V6_MASK 0x00400000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V6_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V5 [21:21] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V5_MASK 0x00200000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V5_SHIFT 21 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V4 [20:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V4_MASK 0x00100000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V4_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V3 [19:19] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V3_MASK 0x00080000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V3_SHIFT 19 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V2 [18:18] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V2_MASK 0x00040000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V2_SHIFT 18 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V1 [17:17] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V1_MASK 0x00020000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V1_SHIFT 17 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V0 [16:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V0_MASK 0x00010000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H15 [15:15] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H15_MASK 0x00008000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H15_SHIFT 15 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H14 [14:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H14_MASK 0x00004000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H14_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H13 [13:13] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H13_MASK 0x00002000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H13_SHIFT 13 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H12 [12:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H12_MASK 0x00001000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H12_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H11 [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H11_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H11_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H10 [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H10_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H10_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H9 [09:09] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H9_MASK 0x00000200 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H9_SHIFT 9 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H8 [08:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H8_MASK 0x00000100 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H8_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H7 [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H7_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H7_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H6 [06:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H6_MASK 0x00000040 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H6_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H5 [05:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H5_MASK 0x00000020 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H5_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H4 [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H4_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H4_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H3 [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H3_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H3_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H2 [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H2_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H2_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H1 [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H1_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H1_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H0 [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H0_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_REFIDX - REG_SINT_VEC_REFIDX - ***************************************************************************/ -/* union - case WRITE [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved0 [31:30] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved0_MASK 0xc0000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved0_SHIFT 30 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx3 [29:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx3_MASK 0x3f000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx3_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved1 [23:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved1_MASK 0x00c00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved1_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx2 [21:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx2_MASK 0x003f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx2_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved2 [15:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved2_MASK 0x0000c000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved2_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx1 [13:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx1_MASK 0x00003f00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx1_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved3 [07:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved3_MASK 0x000000c0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved3_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx0 [05:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx0_MASK 0x0000003f -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx0_SHIFT 0 - -/* union - case READ [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved0 [31:30] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved0_MASK 0xc0000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved0_SHIFT 30 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref1_L1 [29:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L1_MASK 0x3f000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L1_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved1 [23:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved1_MASK 0x00c00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved1_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref1_L0 [21:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L0_MASK 0x003f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved2 [15:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved2_MASK 0x0000c000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved2_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref0_L1 [13:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L1_MASK 0x00003f00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L1_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved3 [07:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved3_MASK 0x000000c0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved3_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref0_L0 [05:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L0_MASK 0x0000003f -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_TOPREF - REG_SINT_VEC_TOPREF - ***************************************************************************/ -/* union - case H264 [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L1RefB1 [31:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB1_MASK 0xff000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB1_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L1RefB0 [23:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB0_MASK 0x00ff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L0RefB1 [15:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB1_MASK 0x0000ff00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB1_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L0RefB0 [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB0_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB0_SHIFT 0 - -/* union - case VC1 [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: ChrIntra [31:31] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_ChrIntra_MASK 0x80000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_ChrIntra_SHIFT 31 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: IsField [30:30] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_IsField_MASK 0x40000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_IsField_SHIFT 30 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk3Bac [29:28] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Bac_MASK 0x30000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Bac_SHIFT 28 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk2Bac [27:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Bac_MASK 0x0f000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Bac_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk1Back [23:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Back_MASK 0x00f00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Back_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk0Back [19:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Back_MASK 0x000f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Back_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk3Fwd [15:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Fwd_MASK 0x0000f000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Fwd_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk2Fwd [11:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Fwd_MASK 0x00000f00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Fwd_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk1Fwd [07:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Fwd_MASK 0x000000f0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Fwd_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk0Fwd [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Fwd_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Fwd_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_TOPTOPREF - REG_SINT_VEC_TOPTOPREF - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: L1PicB1 [31:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L1PicB1_MASK 0xff000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L1PicB1_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: reserved0 [23:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved0_MASK 0x00ff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: L0PicB1 [15:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L0PicB1_MASK 0x0000ff00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L0PicB1_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: reserved1 [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved1_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_COL_TYPE - REG_SINT_VEC_COL_TYPE - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: MBAFF [31:31] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_MBAFF_MASK 0x80000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_MBAFF_SHIFT 31 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: TFld [30:30] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_TFld_MASK 0x40000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_TFld_SHIFT 30 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Field [29:29] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Field_MASK 0x20000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Field_SHIFT 29 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: reserved0 [28:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_reserved0_MASK 0x1ffff000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_reserved0_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: AvsSpatial1 [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial1_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial1_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: AvsSpatial0 [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial0_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial0_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub3 [09:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub3_MASK 0x00000300 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub3_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub2 [07:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub2_MASK 0x000000c0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub2_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub1 [05:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub1_MASK 0x00000030 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub1_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub0 [03:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub0_MASK 0x0000000c -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub0_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Type [01:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Type_MASK 0x00000003 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Type_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_COL_REFID - REG_SINT_VEC_COL_REFID - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved0 [31:29] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved0_MASK 0xe0000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved0_SHIFT 29 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx3 [28:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx3_MASK 0x1f000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx3_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved1 [23:21] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved1_MASK 0x00e00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved1_SHIFT 21 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx2 [20:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx2_MASK 0x001f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx2_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved2 [15:13] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved2_MASK 0x0000e000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved2_SHIFT 13 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx1 [12:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx1_MASK 0x00001f00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx1_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved3 [07:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved3_MASK 0x000000e0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved3_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx0 [04:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx0_MASK 0x0000001f -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_TOPPIC - REG_SINT_VEC_TOPPIC - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L1PicB1 [31:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB1_MASK 0xff000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB1_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L1PicB0 [23:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB0_MASK 0x00ff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L0PicB1 [15:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB1_MASK 0x0000ff00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB1_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L0PicB0 [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB0_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_VC1_INFO - REG_SINT_VEC_VC1_INFO - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: reserved0 [31:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved0_MASK 0xffc00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved0_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: Intra_Flags [21:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_Intra_Flags_MASK 0x003f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_Intra_Flags_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: reserved1 [15:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved1_MASK 0x0000c000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved1_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: CBPCY [13:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_CBPCY_MASK 0x00003f00 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_CBPCY_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: reserved2 [07:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved2_MASK 0x000000c0 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved2_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: BMV_TYPE [05:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_BMV_TYPE_MASK 0x00000030 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_BMV_TYPE_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: field_4MV [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_field_4MV_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_field_4MV_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: GET_AC_PRED [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_GET_AC_PRED_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_GET_AC_PRED_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: COEFS_PRES [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_COEFS_PRES_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_COEFS_PRES_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: INTRA [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_INTRA_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_INTRA_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_REFPIC - REG_SINT_VEC_REFPIC - H.264 only - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: reserved0 [31:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_reserved0_MASK 0xfffffff8 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_reserved0_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: Hwimpiwt [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_Hwimpiwt_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_Hwimpiwt_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: UserRev [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_UserRev_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_UserRev_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: RamSel [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_RamSel_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_RamSel_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_COUNT - REG_SINT_VEC_COUNT - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_COUNT :: Cnt8x8UA [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8UA_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8UA_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_COUNT :: Cnt8x8 [15:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8_MASK 0x0000ffff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_MVD_FIFO - REG_SINT_VEC_MVD_FIFO - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_MVD_FIFO :: Data [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVD_FIFO_Data_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVD_FIFO_Data_SHIFT 0 - -/*************************************************************************** - *REG_SINT_DIVX_TABSEL - REG_SINT_DIVX_TABSEL - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: reserved0 [31:09] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_reserved0_MASK 0xfffffe00 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_reserved0_SHIFT 9 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: P_frame [08:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_P_frame_MASK 0x00000100 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_P_frame_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_chrom_DCT [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_chrom_DCT_index [06:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_index_MASK 0x00000040 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_index_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_lum_DCT [05:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_MASK 0x00000020 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_lum_DCT_index [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_index_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_index_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_DC_DCT [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_DC_DCT_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_DC_DCT_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_P_AC_DCT [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_P_AC_DCT_index [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_index_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_index_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_P_DC_DCT [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_DC_DCT_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_DC_DCT_SHIFT 0 - -/*************************************************************************** - *REG_SINT_CTL_AUX - REG_SINT_CTL_AUX - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_CTL_AUX :: reserved0 [31:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_reserved0_MASK 0xfffffffc -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_reserved0_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_CTL_AUX :: ref_ld_2bit [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_ref_ld_2bit_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_ref_ld_2bit_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_CTL_AUX :: avs_mode [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_avs_mode_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_avs_mode_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_REGEND - REG_SINT_VEC_REGEND - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_REGEND :: reserved0 [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REGEND_reserved0_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_REGEND_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_CTL - REG_SINT_CTL - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_CTL :: VC1 [31:31] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_VC1_MASK 0x80000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_VC1_SHIFT 31 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: regacc_disable [30:30] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_regacc_disable_MASK 0x40000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_regacc_disable_SHIFT 30 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: use_qs_table [29:29] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_use_qs_table_MASK 0x20000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_use_qs_table_SHIFT 29 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: MPEG4 [28:28] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_MPEG4_MASK 0x10000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_MPEG4_SHIFT 28 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: xform_8x8 [27:27] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_xform_8x8_MASK 0x08000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_xform_8x8_SHIFT 27 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: mode_8x8 [26:26] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_mode_8x8_MASK 0x04000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_mode_8x8_SHIFT 26 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: mono_mode [25:25] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_mono_mode_MASK 0x02000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_mono_mode_SHIFT 25 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: DIVX311 [24:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_DIVX311_MASK 0x01000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_DIVX311_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Profile [23:22] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Profile_MASK 0x00c00000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Profile_SHIFT 22 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: IWtPred [21:21] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_IWtPred_MASK 0x00200000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_IWtPred_SHIFT 21 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: WtPred [20:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_WtPred_MASK 0x00100000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_WtPred_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Use_field_pred [19:19] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Use_field_pred_MASK 0x00080000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Use_field_pred_SHIFT 19 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: bot_field [18:18] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_bot_field_MASK 0x00040000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_bot_field_SHIFT 18 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: L1_Eq_2 [17:17] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_2_MASK 0x00020000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_2_SHIFT 17 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: L1_Eq_1 [16:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_1_MASK 0x00010000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_1_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: L0_Eq_2 [15:15] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_2_MASK 0x00008000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_2_SHIFT 15 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: L0_Eq_1 [14:14] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_1_MASK 0x00004000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_1_SHIFT 14 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: new_slice [13:13] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_new_slice_MASK 0x00002000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_new_slice_SHIFT 13 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: reserved_for_eco0 [12:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_reserved_for_eco0_MASK 0x00001000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_reserved_for_eco0_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Dir_8x8 [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Dir_8x8_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Dir_8x8_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Spa_Dir [10:10] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Spa_Dir_MASK 0x00000400 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Spa_Dir_SHIFT 10 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: PTYPE [09:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_PTYPE_MASK 0x00000300 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_PTYPE_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: MBAFF [07:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_MBAFF_MASK 0x00000080 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_MBAFF_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: TFld [06:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_TFld_MASK 0x00000040 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_TFld_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Field [05:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Field_MASK 0x00000020 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Field_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: CAVLC [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_CAVLC_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_CAVLC_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Uleft [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Uleft_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Uleft_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Top [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Top_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Top_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: Left [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Left_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_Left_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_CTL :: URtAvail [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_URtAvail_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_CTL_URtAvail_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VLC_TOPCTX - REG_SINT_VLC_TOPCTX - ***************************************************************************/ -/* union - case VLC [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: V2 [31:28] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V2_MASK 0xf0000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V2_SHIFT 28 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: V3 [27:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V3_MASK 0x0f000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V3_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: U2 [23:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U2_MASK 0x00f00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U2_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: U3 [19:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U3_MASK 0x000f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U3_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum10 [15:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum10_MASK 0x0000f000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum10_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum11 [11:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum11_MASK 0x00000f00 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum11_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum14 [07:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum14_MASK 0x000000f0 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum14_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum15 [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum15_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum15_SHIFT 0 - -/* union - case VC1 [31:00] */ -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: reserved0 [31:25] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_reserved0_MASK 0xfe000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_reserved0_SHIFT 25 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: Top4x4 [24:21] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_Top4x4_MASK 0x01e00000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_Top4x4_SHIFT 21 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopXNZ [20:13] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopXNZ_MASK 0x001fe000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopXNZ_SHIFT 13 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopOlapEnb [12:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopOlapEnb_MASK 0x00001000 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopOlapEnb_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopIntra [11:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopIntra_MASK 0x00000fc0 -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopIntra_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopCBP [05:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopCBP_MASK 0x0000003f -#define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopCBP_SHIFT 0 - -/*************************************************************************** - *REG_SINT_SLICE_ID - REG_SINT_SLICE_ID - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_SLICE_ID :: reserved0 [31:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_reserved0_MASK 0xfffff000 -#define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_reserved0_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_SLICE_ID :: SliceID [11:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_SliceID_MASK 0x00000fff -#define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_SliceID_SHIFT 0 - -/*************************************************************************** - *REG_SINT_QP - REG_SINT_QP - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_QP :: reserved0 [31:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_QP_reserved0_MASK 0xffffffc0 -#define BCHP_DECODE_SINT_0_REG_SINT_QP_reserved0_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_QP :: qp [05:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_QP_qp_MASK 0x0000003f -#define BCHP_DECODE_SINT_0_REG_SINT_QP_qp_SHIFT 0 - -/*************************************************************************** - *REG_SINT_TOP_BASE_ADDR - REG_SINT_TOP_BASE_ADDR - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_TOP_BASE_ADDR :: Addr [31:06] */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_Addr_MASK 0xffffffc0 -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_Addr_SHIFT 6 - -/* DECODE_SINT_0 :: REG_SINT_TOP_BASE_ADDR :: reserved0 [05:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_reserved0_MASK 0x0000003f -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_DIRCTX_WR_ADDR - REG_SINT_DIRCTX_WR_ADDR - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_DIRCTX_WR_ADDR :: Addr [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_DIRCTX_WR_ADDR_Addr_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_DIRCTX_WR_ADDR_Addr_SHIFT 0 - -/*************************************************************************** - *REG_SINT_TOPCTX_DATA - REG_SINT_TOPCTX_DATA - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_TOPCTX_DATA :: Data [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOPCTX_DATA_Data_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_TOPCTX_DATA_Data_SHIFT 0 - -/*************************************************************************** - *REG_SINT_XFER_SYMB - REG_SINT_XFER_SYMB - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_XFER_SYMB :: reserved0 [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_reserved0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_XFER_SYMB :: Type [15:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_Type_MASK 0x0000ff00 -#define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_Type_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_XFER_SYMB :: N [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_N_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_N_SHIFT 0 - -/*************************************************************************** - *REG_SINT_SMODE_BASE - REG_SINT_SMODE_BASE - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode0 [31:28] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode0_MASK 0xf0000000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode0_SHIFT 28 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode1 [27:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode1_MASK 0x0f000000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode1_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode2 [23:20] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode2_MASK 0x00f00000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode2_SHIFT 20 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode3 [19:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode3_MASK 0x000f0000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode3_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode4 [15:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode4_MASK 0x0000f000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode4_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode5 [11:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode5_MASK 0x00000f00 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode5_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode6 [07:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode6_MASK 0x000000f0 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode6_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode7 [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode7_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode7_SHIFT 0 - -/*************************************************************************** - *REG_SINT_SMODE_LEFT - REG_SINT_SMODE_LEFT - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: reserved0 [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_reserved0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode5 [15:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode5_MASK 0x0000f000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode5_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode7 [11:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode7_MASK 0x00000f00 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode7_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode13 [07:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode13_MASK 0x000000f0 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode13_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode15 [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode15_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode15_SHIFT 0 - -/*************************************************************************** - *REG_SINT_SMODE_TOP - REG_SINT_SMODE_TOP - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: reserved0 [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_reserved0_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode10 [15:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode10_MASK 0x0000f000 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode10_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode11 [11:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode11_MASK 0x00000f00 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode11_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode14 [07:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode14_MASK 0x000000f0 -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode14_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode15 [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode15_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode15_SHIFT 0 - -/*************************************************************************** - *REG_SINT_SMODE_END - REG_SINT_SMODE_END - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_SMODE_END :: reserved0 [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_SMODE_END_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_CTX_INIT - REG_SINT_CTX_INIT - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: reserved0 [31:25] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_reserved0_MASK 0xfe000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_reserved0_SHIFT 25 - -/* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: MBAFF [24:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBAFF_MASK 0x01000000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBAFF_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: MBWIDTH [23:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBWIDTH_MASK 0x00ff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBWIDTH_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: YPOS [15:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_YPOS_MASK 0x0000ff00 -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_YPOS_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: XPOS [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_XPOS_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_XPOS_SHIFT 0 - -/*************************************************************************** - *REG_SINT_TOP_CTX - REG_SINT_TOP_CTX - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_TOP_CTX :: reserved0 [31:05] */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_reserved0_MASK 0xffffffe0 -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_reserved0_SHIFT 5 - -/* DECODE_SINT_0 :: REG_SINT_TOP_CTX :: TOP_TOP [04:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_TOP_TOP_MASK 0x00000010 -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_TOP_TOP_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_TOP_CTX :: RD_OFFSET [03:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_RD_OFFSET_MASK 0x0000000f -#define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_RD_OFFSET_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VC1_TABSEL - REG_SINT_VC1_TABSEL - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: reserved0 [31:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved0_MASK 0xff000000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved0_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: ESC_LVL_SZ [23:23] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_ESC_LVL_SZ_MASK 0x00800000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_ESC_LVL_SZ_SHIFT 23 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: TTYPE [22:21] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_TTYPE_MASK 0x00600000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_TTYPE_SHIFT 21 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: INTER_AC [20:19] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_INTER_AC_MASK 0x00180000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_INTER_AC_SHIFT 19 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: Y_INTRA_AC [18:17] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_Y_INTRA_AC_MASK 0x00060000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_Y_INTRA_AC_SHIFT 17 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: DCTABLE [16:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_DCTABLE_MASK 0x00010000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_DCTABLE_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: reserved_for_eco1 [15:15] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco1_MASK 0x00008000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco1_SHIFT 15 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: MBMODE [14:12] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_MBMODE_MASK 0x00007000 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_MBMODE_SHIFT 12 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: field_2REF [11:11] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2REF_MASK 0x00000800 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2REF_SHIFT 11 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: reserved_for_eco2 [10:07] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco2_MASK 0x00000780 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco2_SHIFT 7 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: CPPCY [06:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_CPPCY_MASK 0x00000070 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_CPPCY_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: field_2MB_PAT [03:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2MB_PAT_MASK 0x0000000c -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2MB_PAT_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: field_4MB_PAT [01:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_4MB_PAT_MASK 0x00000003 -#define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_4MB_PAT_SHIFT 0 - -/*************************************************************************** - *REG_SINT_CNST_INTRA - REG_SINT_CNST_INTRA - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: reserved0 [31:04] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_reserved0_MASK 0xfffffff0 -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_reserved0_SHIFT 4 - -/* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: ULftAvail [03:03] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_ULftAvail_MASK 0x00000008 -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_ULftAvail_SHIFT 3 - -/* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: TopAvail [02:02] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_TopAvail_MASK 0x00000004 -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_TopAvail_SHIFT 2 - -/* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: LeftAvail [01:01] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_LeftAvail_MASK 0x00000002 -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_LeftAvail_SHIFT 1 - -/* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: URtAvail [00:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_URtAvail_MASK 0x00000001 -#define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_URtAvail_SHIFT 0 - -/*************************************************************************** - *REG_SINT_OPIC_MEM_BASE - Outpic Lookup - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic3 [31:24] */ -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic3_MASK 0xff000000 -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic3_SHIFT 24 - -/* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic2 [23:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic2_MASK 0x00ff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic2_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic1 [15:08] */ -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic1_MASK 0x0000ff00 -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic1_SHIFT 8 - -/* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic0 [07:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic0_MASK 0x000000ff -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_OPIC_MEM_END - REG_SINT_OPIC_MEM_END - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_END_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_MEM_BASE - Vector Memory - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_MEM_BASE :: Vector_Y_Delta [31:16] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_Y_Delta_MASK 0xffff0000 -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_Y_Delta_SHIFT 16 - -/* DECODE_SINT_0 :: REG_SINT_VEC_MEM_BASE :: Vector_X_Delta [15:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_X_Delta_MASK 0x0000ffff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_X_Delta_SHIFT 0 - -/*************************************************************************** - *REG_SINT_VEC_MEM_END - REG_SINT_VEC_MEM_END - ***************************************************************************/ -/* DECODE_SINT_0 :: REG_SINT_VEC_MEM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_SINT_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_oloop_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_oloop_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_oloop_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_oloop_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,218 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_sint_oloop_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:05p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:11 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_oloop_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:05p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_SINT_OLOOP_0_H__ -#define BCHP_DECODE_SINT_OLOOP_0_H__ - -/*************************************************************************** - *DECODE_SINT_OLOOP_0 - ***************************************************************************/ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR 0x0080cc00 /* DEC_SINT_DMA_ADDR */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN 0x0080cc04 /* DEC_SINT_DMA_LEN */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE 0x0080cc08 /* DEC_SINT_DMA_BASE */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_END 0x0080cc0c /* DEC_SINT_DMA_END */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_POS 0x0080cc10 /* DEC_SINT_STRM_POS */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT 0x0080cc14 /* DEC_SINT_STRM_STAT */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA 0x0080cc18 /* DEC_SINT_IENA */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_BITS 0x0080cc1c /* DEC_SINT_STRM_BITS */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB 0x0080cc20 /* DEC_SINT_GET_SYMB */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_OLOOP_END 0x0080ccfc /* DEC_OLOOP_END */ - -/*************************************************************************** - *DEC_SINT_DMA_ADDR - DEC_SINT_DMA_ADDR - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_ADDR :: Addr [31:02] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_Addr_MASK 0xfffffffc -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_Addr_SHIFT 2 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_ADDR :: reserved0 [01:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_reserved0_MASK 0x00000003 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_DMA_LEN - DEC_SINT_DMA_LEN - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_LEN :: Length [31:05] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_Length_MASK 0xffffffe0 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_Length_SHIFT 5 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_LEN :: reserved0 [04:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_reserved0_MASK 0x0000001f -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_reserved0_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_DMA_BASE - DEC_SINT_DMA_BASE - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_BASE :: Base [31:08] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Base_MASK 0xffffff00 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Base_SHIFT 8 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_BASE :: reserved0 [07:01] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_reserved0_MASK 0x000000fe -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_reserved0_SHIFT 1 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_BASE :: Endian [00:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Endian_MASK 0x00000001 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Endian_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_DMA_END - DEC_SINT_DMA_END - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_END :: End [31:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_END_End_MASK 0xffffffff -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_END_End_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_STRM_POS - DEC_SINT_STRM_POS - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_POS :: Bit_pos [31:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_POS_Bit_pos_MASK 0xffffffff -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_POS_Bit_pos_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_STRM_STAT - DEC_SINT_STRM_STAT - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved0 [31:19] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved0_MASK 0xfff80000 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved0_SHIFT 19 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: FlushInput [18:18] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_FlushInput_MASK 0x00040000 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_FlushInput_SHIFT 18 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved1 [17:17] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved1_MASK 0x00020000 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved1_SHIFT 17 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Rst [16:16] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Rst_MASK 0x00010000 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Rst_SHIFT 16 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved2 [15:10] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved2_MASK 0x0000fc00 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved2_SHIFT 10 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Derr [09:09] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Derr_MASK 0x00000200 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Derr_SHIFT 9 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Serr [08:08] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Serr_MASK 0x00000100 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Serr_SHIFT 8 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved3 [07:04] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved3_MASK 0x000000f0 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved3_SHIFT 4 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Dact [03:03] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Dact_MASK 0x00000008 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Dact_SHIFT 3 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved4 [02:01] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved4_MASK 0x00000006 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved4_SHIFT 1 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Sval [00:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Sval_MASK 0x00000001 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Sval_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_IENA - DEC_SINT_IENA - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: reserved0 [31:10] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved0_MASK 0xfffffc00 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved0_SHIFT 10 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: Derr [09:09] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Derr_MASK 0x00000200 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Derr_SHIFT 9 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: Serr [08:08] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Serr_MASK 0x00000100 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Serr_SHIFT 8 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: reserved1 [07:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved1_MASK 0x000000ff -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved1_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_STRM_BITS - DEC_SINT_STRM_BITS - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_BITS :: Stream_Bits [31:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_BITS_Stream_Bits_MASK 0xffffffff -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_BITS_Stream_Bits_SHIFT 0 - -/*************************************************************************** - *DEC_SINT_GET_SYMB - DEC_SINT_GET_SYMB - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: reserved0 [31:16] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_reserved0_SHIFT 16 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: Type [15:12] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_Type_MASK 0x0000f000 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_Type_SHIFT 12 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: SubType [11:08] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_SubType_MASK 0x00000f00 -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_SubType_SHIFT 8 - -/* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: N [07:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_N_MASK 0x000000ff -#define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_N_SHIFT 0 - -/*************************************************************************** - *DEC_OLOOP_END - DEC_OLOOP_END - ***************************************************************************/ -/* DECODE_SINT_OLOOP_0 :: DEC_OLOOP_END :: reserved0 [31:00] */ -#define BCHP_DECODE_SINT_OLOOP_0_DEC_OLOOP_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_SINT_OLOOP_0_DEC_OLOOP_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_SINT_OLOOP_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_spre_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_spre_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_spre_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_spre_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,146 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_spre_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:06p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:47 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_spre_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:06p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_SPRE_0_H__ -#define BCHP_DECODE_SPRE_0_H__ - -/*************************************************************************** - *DECODE_SPRE_0 - ***************************************************************************/ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL 0x00800320 /* Spatial Prediction Control */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE 0x00800324 /* Spatial Prediction Luma Mode */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_END 0x0080033c /* REG_SPRE_END */ - -/*************************************************************************** - *REG_SPRE_CTL - Spatial Prediction Control - ***************************************************************************/ -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: reserved0 [31:18] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved0_MASK 0xfffc0000 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved0_SHIFT 18 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: CluMode [17:16] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CluMode_MASK 0x00030000 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CluMode_SHIFT 16 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: reserved1 [15:10] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved1_MASK 0x0000fc00 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved1_SHIFT 10 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: PredType [09:08] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_PredType_MASK 0x00000300 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_PredType_SHIFT 8 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: reserved2 [07:05] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved2_MASK 0x000000e0 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved2_SHIFT 5 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: CNST_INTRA [04:04] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CNST_INTRA_MASK 0x00000010 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CNST_INTRA_SHIFT 4 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: Ulft [03:03] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Ulft_MASK 0x00000008 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Ulft_SHIFT 3 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: Top [02:02] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Top_MASK 0x00000004 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Top_SHIFT 2 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: Left [01:01] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Left_MASK 0x00000002 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Left_SHIFT 1 - -/* DECODE_SPRE_0 :: REG_SPRE_CTL :: Urt [00:00] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Urt_MASK 0x00000001 -#define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Urt_SHIFT 0 - -/*************************************************************************** - *REG_SPRE_MODE - Spatial Prediction Luma Mode - ***************************************************************************/ -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode7 [31:28] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode7_MASK 0xf0000000 -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode7_SHIFT 28 - -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode6 [27:24] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode6_MASK 0x0f000000 -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode6_SHIFT 24 - -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode5 [23:20] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode5_MASK 0x00f00000 -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode5_SHIFT 20 - -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode4 [19:16] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode4_MASK 0x000f0000 -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode4_SHIFT 16 - -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode3 [15:12] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode3_MASK 0x0000f000 -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode3_SHIFT 12 - -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode2 [11:08] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode2_MASK 0x00000f00 -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode2_SHIFT 8 - -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode1 [07:04] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode1_MASK 0x000000f0 -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode1_SHIFT 4 - -/* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode0 [03:00] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode0_MASK 0x0000000f -#define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode0_SHIFT 0 - -/*************************************************************************** - *REG_SPRE_END - REG_SPRE_END - ***************************************************************************/ -/* DECODE_SPRE_0 :: REG_SPRE_END :: reserved0 [31:00] */ -#define BCHP_DECODE_SPRE_0_REG_SPRE_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_SPRE_0_REG_SPRE_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_SPRE_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wprd_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wprd_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wprd_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wprd_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,94 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_wprd_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:06p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:10 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wprd_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:06p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_WPRD_0_H__ -#define BCHP_DECODE_WPRD_0_H__ - -/*************************************************************************** - *DECODE_WPRD_0 - ***************************************************************************/ -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL 0x00800340 /* Weighted Prediction Control */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_END 0x0080035c /* REG_WPRD_END */ - -/*************************************************************************** - *REG_WPRD_CTL - Weighted Prediction Control - ***************************************************************************/ -/* DECODE_WPRD_0 :: REG_WPRD_CTL :: reserved0 [31:15] */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved0_MASK 0xffff8000 -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved0_SHIFT 15 - -/* DECODE_WPRD_0 :: REG_WPRD_CTL :: ChromaDenom [14:12] */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_ChromaDenom_MASK 0x00007000 -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_ChromaDenom_SHIFT 12 - -/* DECODE_WPRD_0 :: REG_WPRD_CTL :: reserved1 [11:11] */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved1_MASK 0x00000800 -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved1_SHIFT 11 - -/* DECODE_WPRD_0 :: REG_WPRD_CTL :: LumDenom [10:08] */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_LumDenom_MASK 0x00000700 -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_LumDenom_SHIFT 8 - -/* DECODE_WPRD_0 :: REG_WPRD_CTL :: reserved2 [07:02] */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved2_MASK 0x000000fc -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved2_SHIFT 2 - -/* DECODE_WPRD_0 :: REG_WPRD_CTL :: PredType [01:00] */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_PredType_MASK 0x00000003 -#define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_PredType_SHIFT 0 - -/*************************************************************************** - *REG_WPRD_END - REG_WPRD_END - ***************************************************************************/ -/* DECODE_WPRD_0 :: REG_WPRD_END :: reserved0 [31:00] */ -#define BCHP_DECODE_WPRD_0_REG_WPRD_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_WPRD_0_REG_WPRD_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_WPRD_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wptbl_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wptbl_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wptbl_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wptbl_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_wptbl_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:06p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:05 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wptbl_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:06p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_WPTBL_0_H__ -#define BCHP_DECODE_WPTBL_0_H__ - -/*************************************************************************** - *DECODE_WPTBL_0 - ***************************************************************************/ -#define BCHP_DECODE_WPTBL_0_WPTBL_END 0x008031fc /* DECODE_WPTBL_END */ - -/*************************************************************************** - *WPTBL_END - DECODE_WPTBL_END - ***************************************************************************/ -/* DECODE_WPTBL_0 :: WPTBL_END :: reserved0 [31:00] */ -#define BCHP_DECODE_WPTBL_0_WPTBL_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_WPTBL_0_WPTBL_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_WPTBL_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_xfrm_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_xfrm_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_xfrm_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_xfrm_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,234 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_decode_xfrm_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:06p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:16 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_xfrm_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:06p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DECODE_XFRM_0_H__ -#define BCHP_DECODE_XFRM_0_H__ - -/*************************************************************************** - *DECODE_XFRM_0 - ***************************************************************************/ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL 0x00800700 /* Inverse Transform Control */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF 0x00800704 /* Inverse Transform Coefficients */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_OUT 0x00800708 /* Residual buffer IDs */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM 0x0080070c /* PCM Pixel data */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN 0x00800710 /* REG_IXFM_264_COEF_NORUN */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE 0x00800714 /* REG_IXFM_BLK_SIZE */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE 0x00800718 /* Slice ID */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_END 0x0080071c /* REG_IXFM_END */ - -/*************************************************************************** - *REG_IXFM_CTL - Inverse Transform Control - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: Xfm [31:30] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Xfm_MASK 0xc0000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Xfm_SHIFT 30 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: Scan [29:29] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Scan_MASK 0x20000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Scan_SHIFT 29 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: USE_QS_TAB [28:28] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_USE_QS_TAB_MASK 0x10000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_USE_QS_TAB_SHIFT 28 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: CoefOrder_8x8 [27:27] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CoefOrder_8x8_MASK 0x08000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CoefOrder_8x8_SHIFT 27 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: Fld [26:26] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Fld_MASK 0x04000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Fld_SHIFT 26 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: Odd_ [25:25] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Odd__MASK 0x02000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Odd__SHIFT 25 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: Type [24:24] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Type_MASK 0x01000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Type_SHIFT 24 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: reserved0 [23:23] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved0_MASK 0x00800000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved0_SHIFT 23 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: QpY [22:16] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_QpY_MASK 0x007f0000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_QpY_SHIFT 16 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: reserved1 [15:13] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved1_MASK 0x0000e000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved1_SHIFT 13 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: OVERLAPTXM_BIT_SHIFT [12:12] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_OVERLAPTXM_BIT_SHIFT_MASK 0x00001000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_OVERLAPTXM_BIT_SHIFT_SHIFT 12 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: NonUniform [11:11] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_NonUniform_MASK 0x00000800 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_NonUniform_SHIFT 11 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: ACPred [10:10] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_ACPred_MASK 0x00000400 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_ACPred_SHIFT 10 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: HalfQP [09:09] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_HalfQP_MASK 0x00000200 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_HalfQP_SHIFT 9 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: TopAvail [08:08] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_TopAvail_MASK 0x00000100 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_TopAvail_SHIFT 8 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: reserved2 [07:05] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved2_MASK 0x000000e0 -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved2_SHIFT 5 - -/* DECODE_XFRM_0 :: REG_IXFM_CTL :: CBP [04:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CBP_MASK 0x0000001f -#define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CBP_SHIFT 0 - -/*************************************************************************** - *REG_IXFM_COEF - Inverse Transform Coefficients - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_COEF :: Run0 [31:28] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run0_MASK 0xf0000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run0_SHIFT 28 - -/* DECODE_XFRM_0 :: REG_IXFM_COEF :: Coef0 [27:16] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef0_MASK 0x0fff0000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef0_SHIFT 16 - -/* DECODE_XFRM_0 :: REG_IXFM_COEF :: Run1 [15:12] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run1_MASK 0x0000f000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run1_SHIFT 12 - -/* DECODE_XFRM_0 :: REG_IXFM_COEF :: Coef1 [11:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef1_MASK 0x00000fff -#define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef1_SHIFT 0 - -/*************************************************************************** - *REG_IXFM_OUT - Residual buffer IDs - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_OUT :: reserved0 [31:16] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_reserved0_MASK 0xffff0000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_reserved0_SHIFT 16 - -/* DECODE_XFRM_0 :: REG_IXFM_OUT :: Pict1 [15:08] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict1_MASK 0x0000ff00 -#define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict1_SHIFT 8 - -/* DECODE_XFRM_0 :: REG_IXFM_OUT :: Pict0 [07:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict0_MASK 0x000000ff -#define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict0_SHIFT 0 - -/*************************************************************************** - *REG_IXFM_PCM - PCM Pixel data - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel0 [31:24] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel0_MASK 0xff000000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel0_SHIFT 24 - -/* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel1 [23:16] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel1_MASK 0x00ff0000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel1_SHIFT 16 - -/* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel2 [15:08] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel2_MASK 0x0000ff00 -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel2_SHIFT 8 - -/* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel3 [07:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel3_MASK 0x000000ff -#define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel3_SHIFT 0 - -/*************************************************************************** - *REG_IXFM_264_COEF_NORUN - REG_IXFM_264_COEF_NORUN - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_264_COEF_NORUN :: coef1 [31:16] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef1_MASK 0xffff0000 -#define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef1_SHIFT 16 - -/* DECODE_XFRM_0 :: REG_IXFM_264_COEF_NORUN :: coef0 [15:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef0_MASK 0x0000ffff -#define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef0_SHIFT 0 - -/*************************************************************************** - *REG_IXFM_BLK_SIZE - REG_IXFM_BLK_SIZE - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_BLK_SIZE :: reserved0 [31:03] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_reserved0_MASK 0xfffffff8 -#define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_reserved0_SHIFT 3 - -/* DECODE_XFRM_0 :: REG_IXFM_BLK_SIZE :: Intra [02:02] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_Intra_MASK 0x00000004 -#define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_Intra_SHIFT 2 - -/* DECODE_XFRM_0 :: REG_IXFM_BLK_SIZE :: SIZE [01:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_SIZE_MASK 0x00000003 -#define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_SIZE_SHIFT 0 - -/*************************************************************************** - *REG_IXFM_SLICE - Slice ID - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_SLICE :: reserved0 [31:07] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_reserved0_MASK 0xffffff80 -#define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_reserved0_SHIFT 7 - -/* DECODE_XFRM_0 :: REG_IXFM_SLICE :: Slice_ID [06:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_Slice_ID_MASK 0x0000007f -#define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_Slice_ID_SHIFT 0 - -/*************************************************************************** - *REG_IXFM_END - REG_IXFM_END - ***************************************************************************/ -/* DECODE_XFRM_0 :: REG_IXFM_END :: reserved0 [31:00] */ -#define BCHP_DECODE_XFRM_0_REG_IXFM_END_reserved0_MASK 0xffffffff -#define BCHP_DECODE_XFRM_0_REG_IXFM_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_DECODE_XFRM_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_dnr.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_dnr.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_dnr.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_dnr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,611 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_dnr.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:07p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:06 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_dnr.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:07p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_DNR_H__ -#define BCHP_DNR_H__ - -/*************************************************************************** - *DNR - Digital Noise Reduction Registers - ***************************************************************************/ -#define BCHP_DNR_REVISION 0x00540400 /* Digital Noise Reduction (DNR) Revision ID */ -#define BCHP_DNR_DNR_TOP_CTRL 0x00540404 /* DNR Top Level Control */ -#define BCHP_DNR_LINE_STORE_CONFIG 0x00540408 /* Line Store Configuration */ -#define BCHP_DNR_SRC_PIC_SIZE 0x0054040c /* Source Picture Size */ -#define BCHP_DNR_SRC_SCAN_SETTING 0x00540410 /* Source Scan Setting */ -#define BCHP_DNR_BNR_CTRL 0x00540414 /* Block Noise Reduction Control */ -#define BCHP_DNR_VBNR_CONFIG 0x00540418 /* Vertical Block Noise Reduction Configuration */ -#define BCHP_DNR_HBNR_CONFIG 0x0054041c /* Horizontal Block Noise Reduction Configuration */ -#define BCHP_DNR_MNR_CTRL 0x00540420 /* Mosquito Noise Reduction Control */ -#define BCHP_DNR_MNR_CONFIG 0x00540424 /* Mosquito Noise Reduction Configuration */ -#define BCHP_DNR_EXT_FILT_CTRL 0x00540428 /* Extreme Filter Control */ -#define BCHP_DNR_EXT_FILT_CONFIG 0x0054042c /* Extreme Filter Configuration */ -#define BCHP_DNR_FILT_EFFECT_STATUS 0x00540430 /* DNR Filters Effect Status */ -#define BCHP_DNR_BVB_IN_STATUS 0x00540434 /* DNR BVB Input Status */ -#define BCHP_DNR_BVB_IN_STATUS_CLEAR 0x00540438 /* DNR BVB Input Status Clear */ -#define BCHP_DNR_SCRATCH_REGISTER 0x0054043c /* DNR Scratch Register */ -#define BCHP_DNR_DNR_DEMO_SETTING 0x00540440 /* DNR Demo Setting */ -#define BCHP_DNR_DCR_CTRL 0x00540480 /* Digital Contour Removal Control */ -#define BCHP_DNR_DCR_FILT_LIMIT 0x00540484 /* DCR Filtering Limits */ -#define BCHP_DNR_DCR_FILT_CONFIG 0x00540488 /* DCR Filtering Configuration */ -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN 0x00540490 /* DCR Ordered Dither Pattern Control */ -#define BCHP_DNR_DCR_DITH_ORDER_VALUE 0x00540494 /* DCR Ordered Dither Value */ -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN 0x00540498 /* DCR Random Dither Pattern Control */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE 0x0054049c /* DCR Random Dither Values */ -#define BCHP_DNR_DCR_DITH_OUT_CTRL 0x005404a0 /* DCR Dither Output Control */ - -/*************************************************************************** - *REVISION - Digital Noise Reduction (DNR) Revision ID - ***************************************************************************/ -/* DNR :: REVISION :: reserved0 [31:16] */ -#define BCHP_DNR_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_DNR_REVISION_reserved0_SHIFT 16 - -/* DNR :: REVISION :: MAJOR [15:08] */ -#define BCHP_DNR_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_DNR_REVISION_MAJOR_SHIFT 8 - -/* DNR :: REVISION :: MINOR [07:00] */ -#define BCHP_DNR_REVISION_MINOR_MASK 0x000000ff -#define BCHP_DNR_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *DNR_TOP_CTRL - DNR Top Level Control - ***************************************************************************/ -/* DNR :: DNR_TOP_CTRL :: reserved0 [31:02] */ -#define BCHP_DNR_DNR_TOP_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_DNR_DNR_TOP_CTRL_reserved0_SHIFT 2 - -/* DNR :: DNR_TOP_CTRL :: DNR_DEMO_ENABLE [01:01] */ -#define BCHP_DNR_DNR_TOP_CTRL_DNR_DEMO_ENABLE_MASK 0x00000002 -#define BCHP_DNR_DNR_TOP_CTRL_DNR_DEMO_ENABLE_SHIFT 1 - -/* DNR :: DNR_TOP_CTRL :: DNR_ENABLE [00:00] */ -#define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_MASK 0x00000001 -#define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_SHIFT 0 -#define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_DISABLE 0 -#define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_ENABLE 1 - -/*************************************************************************** - *LINE_STORE_CONFIG - Line Store Configuration - ***************************************************************************/ -/* DNR :: LINE_STORE_CONFIG :: reserved0 [31:17] */ -#define BCHP_DNR_LINE_STORE_CONFIG_reserved0_MASK 0xfffe0000 -#define BCHP_DNR_LINE_STORE_CONFIG_reserved0_SHIFT 17 - -/* DNR :: LINE_STORE_CONFIG :: LS_MODE [16:16] */ -#define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_MASK 0x00010000 -#define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_SHIFT 16 -#define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_SD 0 -#define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_HD 1 - -/* DNR :: LINE_STORE_CONFIG :: reserved1 [15:00] */ -#define BCHP_DNR_LINE_STORE_CONFIG_reserved1_MASK 0x0000ffff -#define BCHP_DNR_LINE_STORE_CONFIG_reserved1_SHIFT 0 - -/*************************************************************************** - *SRC_PIC_SIZE - Source Picture Size - ***************************************************************************/ -/* DNR :: SRC_PIC_SIZE :: reserved0 [31:27] */ -#define BCHP_DNR_SRC_PIC_SIZE_reserved0_MASK 0xf8000000 -#define BCHP_DNR_SRC_PIC_SIZE_reserved0_SHIFT 27 - -/* DNR :: SRC_PIC_SIZE :: HSIZE [26:16] */ -#define BCHP_DNR_SRC_PIC_SIZE_HSIZE_MASK 0x07ff0000 -#define BCHP_DNR_SRC_PIC_SIZE_HSIZE_SHIFT 16 - -/* DNR :: SRC_PIC_SIZE :: reserved1 [15:11] */ -#define BCHP_DNR_SRC_PIC_SIZE_reserved1_MASK 0x0000f800 -#define BCHP_DNR_SRC_PIC_SIZE_reserved1_SHIFT 11 - -/* DNR :: SRC_PIC_SIZE :: VSIZE [10:00] */ -#define BCHP_DNR_SRC_PIC_SIZE_VSIZE_MASK 0x000007ff -#define BCHP_DNR_SRC_PIC_SIZE_VSIZE_SHIFT 0 - -/*************************************************************************** - *SRC_SCAN_SETTING - Source Scan Setting - ***************************************************************************/ -/* DNR :: SRC_SCAN_SETTING :: reserved0 [31:19] */ -#define BCHP_DNR_SRC_SCAN_SETTING_reserved0_MASK 0xfff80000 -#define BCHP_DNR_SRC_SCAN_SETTING_reserved0_SHIFT 19 - -/* DNR :: SRC_SCAN_SETTING :: H_OFFSET [18:16] */ -#define BCHP_DNR_SRC_SCAN_SETTING_H_OFFSET_MASK 0x00070000 -#define BCHP_DNR_SRC_SCAN_SETTING_H_OFFSET_SHIFT 16 - -/* DNR :: SRC_SCAN_SETTING :: reserved1 [15:11] */ -#define BCHP_DNR_SRC_SCAN_SETTING_reserved1_MASK 0x0000f800 -#define BCHP_DNR_SRC_SCAN_SETTING_reserved1_SHIFT 11 - -/* DNR :: SRC_SCAN_SETTING :: V_OFFSET [10:08] */ -#define BCHP_DNR_SRC_SCAN_SETTING_V_OFFSET_MASK 0x00000700 -#define BCHP_DNR_SRC_SCAN_SETTING_V_OFFSET_SHIFT 8 - -/* DNR :: SRC_SCAN_SETTING :: reserved2 [07:02] */ -#define BCHP_DNR_SRC_SCAN_SETTING_reserved2_MASK 0x000000fc -#define BCHP_DNR_SRC_SCAN_SETTING_reserved2_SHIFT 2 - -/* DNR :: SRC_SCAN_SETTING :: SRC_FORMAT [01:01] */ -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_MASK 0x00000002 -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_SHIFT 1 -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_FIELD 0 -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_FRAME 1 - -/* DNR :: SRC_SCAN_SETTING :: SRC_FIELD_ID [00:00] */ -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_MASK 0x00000001 -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_SHIFT 0 -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_TOP 0 -#define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_BOTTOM 1 - -/*************************************************************************** - *BNR_CTRL - Block Noise Reduction Control - ***************************************************************************/ -/* DNR :: BNR_CTRL :: reserved0 [31:02] */ -#define BCHP_DNR_BNR_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_DNR_BNR_CTRL_reserved0_SHIFT 2 - -/* DNR :: BNR_CTRL :: HBNR_ENABLE [01:01] */ -#define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_MASK 0x00000002 -#define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_SHIFT 1 -#define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_DISABLE 0 -#define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_ENABLE 1 - -/* DNR :: BNR_CTRL :: VBNR_ENABLE [00:00] */ -#define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_MASK 0x00000001 -#define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_SHIFT 0 -#define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_DISABLE 0 -#define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_ENABLE 1 - -/*************************************************************************** - *VBNR_CONFIG - Vertical Block Noise Reduction Configuration - ***************************************************************************/ -/* DNR :: VBNR_CONFIG :: reserved0 [31:30] */ -#define BCHP_DNR_VBNR_CONFIG_reserved0_MASK 0xc0000000 -#define BCHP_DNR_VBNR_CONFIG_reserved0_SHIFT 30 - -/* DNR :: VBNR_CONFIG :: VBNR_LR_LIMIT [29:24] */ -#define BCHP_DNR_VBNR_CONFIG_VBNR_LR_LIMIT_MASK 0x3f000000 -#define BCHP_DNR_VBNR_CONFIG_VBNR_LR_LIMIT_SHIFT 24 - -/* DNR :: VBNR_CONFIG :: reserved1 [23:20] */ -#define BCHP_DNR_VBNR_CONFIG_reserved1_MASK 0x00f00000 -#define BCHP_DNR_VBNR_CONFIG_reserved1_SHIFT 20 - -/* DNR :: VBNR_CONFIG :: VBNR_REL [19:16] */ -#define BCHP_DNR_VBNR_CONFIG_VBNR_REL_MASK 0x000f0000 -#define BCHP_DNR_VBNR_CONFIG_VBNR_REL_SHIFT 16 - -/* DNR :: VBNR_CONFIG :: reserved2 [15:09] */ -#define BCHP_DNR_VBNR_CONFIG_reserved2_MASK 0x0000fe00 -#define BCHP_DNR_VBNR_CONFIG_reserved2_SHIFT 9 - -/* DNR :: VBNR_CONFIG :: VBNR_LIMIT [08:00] */ -#define BCHP_DNR_VBNR_CONFIG_VBNR_LIMIT_MASK 0x000001ff -#define BCHP_DNR_VBNR_CONFIG_VBNR_LIMIT_SHIFT 0 - -/*************************************************************************** - *HBNR_CONFIG - Horizontal Block Noise Reduction Configuration - ***************************************************************************/ -/* DNR :: HBNR_CONFIG :: HBNR_SMALL_GRID [31:31] */ -#define BCHP_DNR_HBNR_CONFIG_HBNR_SMALL_GRID_MASK 0x80000000 -#define BCHP_DNR_HBNR_CONFIG_HBNR_SMALL_GRID_SHIFT 31 - -/* DNR :: HBNR_CONFIG :: reserved0 [30:20] */ -#define BCHP_DNR_HBNR_CONFIG_reserved0_MASK 0x7ff00000 -#define BCHP_DNR_HBNR_CONFIG_reserved0_SHIFT 20 - -/* DNR :: HBNR_CONFIG :: HBNR_REL [19:16] */ -#define BCHP_DNR_HBNR_CONFIG_HBNR_REL_MASK 0x000f0000 -#define BCHP_DNR_HBNR_CONFIG_HBNR_REL_SHIFT 16 - -/* DNR :: HBNR_CONFIG :: reserved1 [15:09] */ -#define BCHP_DNR_HBNR_CONFIG_reserved1_MASK 0x0000fe00 -#define BCHP_DNR_HBNR_CONFIG_reserved1_SHIFT 9 - -/* DNR :: HBNR_CONFIG :: HBNR_LIMIT [08:00] */ -#define BCHP_DNR_HBNR_CONFIG_HBNR_LIMIT_MASK 0x000001ff -#define BCHP_DNR_HBNR_CONFIG_HBNR_LIMIT_SHIFT 0 - -/*************************************************************************** - *MNR_CTRL - Mosquito Noise Reduction Control - ***************************************************************************/ -/* DNR :: MNR_CTRL :: reserved0 [31:01] */ -#define BCHP_DNR_MNR_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_DNR_MNR_CTRL_reserved0_SHIFT 1 - -/* DNR :: MNR_CTRL :: MNR_ENABLE [00:00] */ -#define BCHP_DNR_MNR_CTRL_MNR_ENABLE_MASK 0x00000001 -#define BCHP_DNR_MNR_CTRL_MNR_ENABLE_SHIFT 0 -#define BCHP_DNR_MNR_CTRL_MNR_ENABLE_DISABLE 0 -#define BCHP_DNR_MNR_CTRL_MNR_ENABLE_ENABLE 1 - -/*************************************************************************** - *MNR_CONFIG - Mosquito Noise Reduction Configuration - ***************************************************************************/ -/* DNR :: MNR_CONFIG :: MNR_SPOT [31:31] */ -#define BCHP_DNR_MNR_CONFIG_MNR_SPOT_MASK 0x80000000 -#define BCHP_DNR_MNR_CONFIG_MNR_SPOT_SHIFT 31 - -/* DNR :: MNR_CONFIG :: reserved0 [30:27] */ -#define BCHP_DNR_MNR_CONFIG_reserved0_MASK 0x78000000 -#define BCHP_DNR_MNR_CONFIG_reserved0_SHIFT 27 - -/* DNR :: MNR_CONFIG :: MNR_MERGE [26:24] */ -#define BCHP_DNR_MNR_CONFIG_MNR_MERGE_MASK 0x07000000 -#define BCHP_DNR_MNR_CONFIG_MNR_MERGE_SHIFT 24 - -/* DNR :: MNR_CONFIG :: reserved1 [23:23] */ -#define BCHP_DNR_MNR_CONFIG_reserved1_MASK 0x00800000 -#define BCHP_DNR_MNR_CONFIG_reserved1_SHIFT 23 - -/* DNR :: MNR_CONFIG :: MNR_REL [22:16] */ -#define BCHP_DNR_MNR_CONFIG_MNR_REL_MASK 0x007f0000 -#define BCHP_DNR_MNR_CONFIG_MNR_REL_SHIFT 16 - -/* DNR :: MNR_CONFIG :: MNR_BLOCK_BOUND [15:15] */ -#define BCHP_DNR_MNR_CONFIG_MNR_BLOCK_BOUND_MASK 0x00008000 -#define BCHP_DNR_MNR_CONFIG_MNR_BLOCK_BOUND_SHIFT 15 - -/* DNR :: MNR_CONFIG :: reserved2 [14:09] */ -#define BCHP_DNR_MNR_CONFIG_reserved2_MASK 0x00007e00 -#define BCHP_DNR_MNR_CONFIG_reserved2_SHIFT 9 - -/* DNR :: MNR_CONFIG :: MNR_LIMIT [08:00] */ -#define BCHP_DNR_MNR_CONFIG_MNR_LIMIT_MASK 0x000001ff -#define BCHP_DNR_MNR_CONFIG_MNR_LIMIT_SHIFT 0 - -/*************************************************************************** - *EXT_FILT_CTRL - Extreme Filter Control - ***************************************************************************/ -/* DNR :: EXT_FILT_CTRL :: reserved0 [31:01] */ -#define BCHP_DNR_EXT_FILT_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_DNR_EXT_FILT_CTRL_reserved0_SHIFT 1 - -/* DNR :: EXT_FILT_CTRL :: ENABLE [00:00] */ -#define BCHP_DNR_EXT_FILT_CTRL_ENABLE_MASK 0x00000001 -#define BCHP_DNR_EXT_FILT_CTRL_ENABLE_SHIFT 0 -#define BCHP_DNR_EXT_FILT_CTRL_ENABLE_DISABLE 0 -#define BCHP_DNR_EXT_FILT_CTRL_ENABLE_ENABLE 1 - -/*************************************************************************** - *EXT_FILT_CONFIG - Extreme Filter Configuration - ***************************************************************************/ -/* DNR :: EXT_FILT_CONFIG :: reserved0 [31:01] */ -#define BCHP_DNR_EXT_FILT_CONFIG_reserved0_MASK 0xfffffffe -#define BCHP_DNR_EXT_FILT_CONFIG_reserved0_SHIFT 1 - -/* DNR :: EXT_FILT_CONFIG :: CONFIG [00:00] */ -#define BCHP_DNR_EXT_FILT_CONFIG_CONFIG_MASK 0x00000001 -#define BCHP_DNR_EXT_FILT_CONFIG_CONFIG_SHIFT 0 - -/*************************************************************************** - *FILT_EFFECT_STATUS - DNR Filters Effect Status - ***************************************************************************/ -/* DNR :: FILT_EFFECT_STATUS :: FILT_EFFECT [31:00] */ -#define BCHP_DNR_FILT_EFFECT_STATUS_FILT_EFFECT_MASK 0xffffffff -#define BCHP_DNR_FILT_EFFECT_STATUS_FILT_EFFECT_SHIFT 0 - -/*************************************************************************** - *BVB_IN_STATUS - DNR BVB Input Status - ***************************************************************************/ -/* DNR :: BVB_IN_STATUS :: reserved0 [31:05] */ -#define BCHP_DNR_BVB_IN_STATUS_reserved0_MASK 0xffffffe0 -#define BCHP_DNR_BVB_IN_STATUS_reserved0_SHIFT 5 - -/* DNR :: BVB_IN_STATUS :: MISSING_SYNC [04:04] */ -#define BCHP_DNR_BVB_IN_STATUS_MISSING_SYNC_MASK 0x00000010 -#define BCHP_DNR_BVB_IN_STATUS_MISSING_SYNC_SHIFT 4 - -/* DNR :: BVB_IN_STATUS :: LONG_SOURCE [03:03] */ -#define BCHP_DNR_BVB_IN_STATUS_LONG_SOURCE_MASK 0x00000008 -#define BCHP_DNR_BVB_IN_STATUS_LONG_SOURCE_SHIFT 3 - -/* DNR :: BVB_IN_STATUS :: SHORT_SOURCE [02:02] */ -#define BCHP_DNR_BVB_IN_STATUS_SHORT_SOURCE_MASK 0x00000004 -#define BCHP_DNR_BVB_IN_STATUS_SHORT_SOURCE_SHIFT 2 - -/* DNR :: BVB_IN_STATUS :: LONG_LINE [01:01] */ -#define BCHP_DNR_BVB_IN_STATUS_LONG_LINE_MASK 0x00000002 -#define BCHP_DNR_BVB_IN_STATUS_LONG_LINE_SHIFT 1 - -/* DNR :: BVB_IN_STATUS :: SHORT_LINE [00:00] */ -#define BCHP_DNR_BVB_IN_STATUS_SHORT_LINE_MASK 0x00000001 -#define BCHP_DNR_BVB_IN_STATUS_SHORT_LINE_SHIFT 0 - -/*************************************************************************** - *BVB_IN_STATUS_CLEAR - DNR BVB Input Status Clear - ***************************************************************************/ -/* DNR :: BVB_IN_STATUS_CLEAR :: reserved0 [31:05] */ -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_reserved0_MASK 0xffffffe0 -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_reserved0_SHIFT 5 - -/* DNR :: BVB_IN_STATUS_CLEAR :: MISSING_SYNC [04:04] */ -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_MISSING_SYNC_MASK 0x00000010 -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_MISSING_SYNC_SHIFT 4 - -/* DNR :: BVB_IN_STATUS_CLEAR :: LONG_SOURCE [03:03] */ -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_SOURCE_MASK 0x00000008 -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_SOURCE_SHIFT 3 - -/* DNR :: BVB_IN_STATUS_CLEAR :: SHORT_SOURCE [02:02] */ -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_MASK 0x00000004 -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_SHIFT 2 - -/* DNR :: BVB_IN_STATUS_CLEAR :: LONG_LINE [01:01] */ -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_LINE_MASK 0x00000002 -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_LINE_SHIFT 1 - -/* DNR :: BVB_IN_STATUS_CLEAR :: SHORT_LINE [00:00] */ -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_LINE_MASK 0x00000001 -#define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_LINE_SHIFT 0 - -/*************************************************************************** - *SCRATCH_REGISTER - DNR Scratch Register - ***************************************************************************/ -/* DNR :: SCRATCH_REGISTER :: reserved0 [31:16] */ -#define BCHP_DNR_SCRATCH_REGISTER_reserved0_MASK 0xffff0000 -#define BCHP_DNR_SCRATCH_REGISTER_reserved0_SHIFT 16 - -/* DNR :: SCRATCH_REGISTER :: VALUE [15:00] */ -#define BCHP_DNR_SCRATCH_REGISTER_VALUE_MASK 0x0000ffff -#define BCHP_DNR_SCRATCH_REGISTER_VALUE_SHIFT 0 - -/*************************************************************************** - *DNR_DEMO_SETTING - DNR Demo Setting - ***************************************************************************/ -/* DNR :: DNR_DEMO_SETTING :: reserved0 [31:17] */ -#define BCHP_DNR_DNR_DEMO_SETTING_reserved0_MASK 0xfffe0000 -#define BCHP_DNR_DNR_DEMO_SETTING_reserved0_SHIFT 17 - -/* DNR :: DNR_DEMO_SETTING :: DEMO_L_R [16:16] */ -#define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_MASK 0x00010000 -#define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_SHIFT 16 -#define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_LEFT 1 -#define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_RIGHT 0 - -/* DNR :: DNR_DEMO_SETTING :: reserved1 [15:11] */ -#define BCHP_DNR_DNR_DEMO_SETTING_reserved1_MASK 0x0000f800 -#define BCHP_DNR_DNR_DEMO_SETTING_reserved1_SHIFT 11 - -/* DNR :: DNR_DEMO_SETTING :: DEMO_BOUNDARY [10:00] */ -#define BCHP_DNR_DNR_DEMO_SETTING_DEMO_BOUNDARY_MASK 0x000007ff -#define BCHP_DNR_DNR_DEMO_SETTING_DEMO_BOUNDARY_SHIFT 0 - -/*************************************************************************** - *DCR_CTRL - Digital Contour Removal Control - ***************************************************************************/ -/* DNR :: DCR_CTRL :: reserved0 [31:02] */ -#define BCHP_DNR_DCR_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_DNR_DCR_CTRL_reserved0_SHIFT 2 - -/* DNR :: DCR_CTRL :: DITH_ENABLE [01:01] */ -#define BCHP_DNR_DCR_CTRL_DITH_ENABLE_MASK 0x00000002 -#define BCHP_DNR_DCR_CTRL_DITH_ENABLE_SHIFT 1 -#define BCHP_DNR_DCR_CTRL_DITH_ENABLE_DISABLE 0 -#define BCHP_DNR_DCR_CTRL_DITH_ENABLE_ENABLE 1 - -/* DNR :: DCR_CTRL :: FILT_ENABLE [00:00] */ -#define BCHP_DNR_DCR_CTRL_FILT_ENABLE_MASK 0x00000001 -#define BCHP_DNR_DCR_CTRL_FILT_ENABLE_SHIFT 0 -#define BCHP_DNR_DCR_CTRL_FILT_ENABLE_DISABLE 0 -#define BCHP_DNR_DCR_CTRL_FILT_ENABLE_ENABLE 1 - -/*************************************************************************** - *DCR_FILT_LIMIT - DCR Filtering Limits - ***************************************************************************/ -/* DNR :: DCR_FILT_LIMIT :: reserved0 [31:28] */ -#define BCHP_DNR_DCR_FILT_LIMIT_reserved0_MASK 0xf0000000 -#define BCHP_DNR_DCR_FILT_LIMIT_reserved0_SHIFT 28 - -/* DNR :: DCR_FILT_LIMIT :: FILT_3_LIMIT [27:24] */ -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_3_LIMIT_MASK 0x0f000000 -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_3_LIMIT_SHIFT 24 - -/* DNR :: DCR_FILT_LIMIT :: reserved1 [23:20] */ -#define BCHP_DNR_DCR_FILT_LIMIT_reserved1_MASK 0x00f00000 -#define BCHP_DNR_DCR_FILT_LIMIT_reserved1_SHIFT 20 - -/* DNR :: DCR_FILT_LIMIT :: FILT_2_LIMIT [19:16] */ -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_2_LIMIT_MASK 0x000f0000 -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_2_LIMIT_SHIFT 16 - -/* DNR :: DCR_FILT_LIMIT :: reserved2 [15:12] */ -#define BCHP_DNR_DCR_FILT_LIMIT_reserved2_MASK 0x0000f000 -#define BCHP_DNR_DCR_FILT_LIMIT_reserved2_SHIFT 12 - -/* DNR :: DCR_FILT_LIMIT :: FILT_1_LIMIT [11:08] */ -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_1_LIMIT_MASK 0x00000f00 -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_1_LIMIT_SHIFT 8 - -/* DNR :: DCR_FILT_LIMIT :: reserved3 [07:04] */ -#define BCHP_DNR_DCR_FILT_LIMIT_reserved3_MASK 0x000000f0 -#define BCHP_DNR_DCR_FILT_LIMIT_reserved3_SHIFT 4 - -/* DNR :: DCR_FILT_LIMIT :: FILT_0_LIMIT [03:00] */ -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_0_LIMIT_MASK 0x0000000f -#define BCHP_DNR_DCR_FILT_LIMIT_FILT_0_LIMIT_SHIFT 0 - -/*************************************************************************** - *DCR_FILT_CONFIG - DCR Filtering Configuration - ***************************************************************************/ -/* DNR :: DCR_FILT_CONFIG :: reserved0 [31:11] */ -#define BCHP_DNR_DCR_FILT_CONFIG_reserved0_MASK 0xfffff800 -#define BCHP_DNR_DCR_FILT_CONFIG_reserved0_SHIFT 11 - -/* DNR :: DCR_FILT_CONFIG :: BRIGHT_2 [10:10] */ -#define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_2_MASK 0x00000400 -#define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_2_SHIFT 10 - -/* DNR :: DCR_FILT_CONFIG :: BRIGHT_1 [09:09] */ -#define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_1_MASK 0x00000200 -#define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_1_SHIFT 9 - -/* DNR :: DCR_FILT_CONFIG :: BRIGHT_0 [08:08] */ -#define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_0_MASK 0x00000100 -#define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_0_SHIFT 8 - -/* DNR :: DCR_FILT_CONFIG :: reserved1 [07:07] */ -#define BCHP_DNR_DCR_FILT_CONFIG_reserved1_MASK 0x00000080 -#define BCHP_DNR_DCR_FILT_CONFIG_reserved1_SHIFT 7 - -/* DNR :: DCR_FILT_CONFIG :: FILT_CLAMP [06:00] */ -#define BCHP_DNR_DCR_FILT_CONFIG_FILT_CLAMP_MASK 0x0000007f -#define BCHP_DNR_DCR_FILT_CONFIG_FILT_CLAMP_SHIFT 0 - -/*************************************************************************** - *DCR_DITH_ORDER_PATTERN - DCR Ordered Dither Pattern Control - ***************************************************************************/ -/* DNR :: DCR_DITH_ORDER_PATTERN :: reserved0 [31:05] */ -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_reserved0_MASK 0xffffffe0 -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_reserved0_SHIFT 5 - -/* DNR :: DCR_DITH_ORDER_PATTERN :: ALTERNATE_Y [04:04] */ -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_Y_MASK 0x00000010 -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_Y_SHIFT 4 - -/* DNR :: DCR_DITH_ORDER_PATTERN :: ALTERNATE_X [03:03] */ -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_X_MASK 0x00000008 -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_X_SHIFT 3 - -/* DNR :: DCR_DITH_ORDER_PATTERN :: INVERT_Y [02:02] */ -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_Y_MASK 0x00000004 -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_Y_SHIFT 2 - -/* DNR :: DCR_DITH_ORDER_PATTERN :: INVERT_X [01:01] */ -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_X_MASK 0x00000002 -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_X_SHIFT 1 - -/* DNR :: DCR_DITH_ORDER_PATTERN :: AUTO_DITH [00:00] */ -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_AUTO_DITH_MASK 0x00000001 -#define BCHP_DNR_DCR_DITH_ORDER_PATTERN_AUTO_DITH_SHIFT 0 - -/*************************************************************************** - *DCR_DITH_ORDER_VALUE - DCR Ordered Dither Value - ***************************************************************************/ -/* DNR :: DCR_DITH_ORDER_VALUE :: reserved0 [31:15] */ -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved0_MASK 0xffff8000 -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved0_SHIFT 15 - -/* DNR :: DCR_DITH_ORDER_VALUE :: ORDER_B [14:08] */ -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_B_MASK 0x00007f00 -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_B_SHIFT 8 - -/* DNR :: DCR_DITH_ORDER_VALUE :: reserved1 [07:07] */ -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved1_MASK 0x00000080 -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved1_SHIFT 7 - -/* DNR :: DCR_DITH_ORDER_VALUE :: ORDER_A [06:00] */ -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_A_MASK 0x0000007f -#define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_A_SHIFT 0 - -/*************************************************************************** - *DCR_DITH_RANDOM_PATTERN - DCR Random Dither Pattern Control - ***************************************************************************/ -/* DNR :: DCR_DITH_RANDOM_PATTERN :: reserved0 [31:18] */ -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_reserved0_MASK 0xfffc0000 -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_reserved0_SHIFT 18 - -/* DNR :: DCR_DITH_RANDOM_PATTERN :: RNG_MODE [17:16] */ -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_MASK 0x00030000 -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_SHIFT 16 -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_RUN 0 -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_RNG_FIELD 1 -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_RNG_FRAME 2 - -/* DNR :: DCR_DITH_RANDOM_PATTERN :: RNG_SEED [15:00] */ -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_SEED_MASK 0x0000ffff -#define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_SEED_SHIFT 0 - -/*************************************************************************** - *DCR_DITH_RANDOM_VALUE - DCR Random Dither Values - ***************************************************************************/ -/* DNR :: DCR_DITH_RANDOM_VALUE :: reserved0 [31:31] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved0_MASK 0x80000000 -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved0_SHIFT 31 - -/* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_D [30:24] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_D_MASK 0x7f000000 -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_D_SHIFT 24 - -/* DNR :: DCR_DITH_RANDOM_VALUE :: reserved1 [23:23] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved1_MASK 0x00800000 -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved1_SHIFT 23 - -/* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_C [22:16] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_C_MASK 0x007f0000 -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_C_SHIFT 16 - -/* DNR :: DCR_DITH_RANDOM_VALUE :: reserved2 [15:15] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved2_MASK 0x00008000 -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved2_SHIFT 15 - -/* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_B [14:08] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_B_MASK 0x00007f00 -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_B_SHIFT 8 - -/* DNR :: DCR_DITH_RANDOM_VALUE :: reserved3 [07:07] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved3_MASK 0x00000080 -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved3_SHIFT 7 - -/* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_A [06:00] */ -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_A_MASK 0x0000007f -#define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_A_SHIFT 0 - -/*************************************************************************** - *DCR_DITH_OUT_CTRL - DCR Dither Output Control - ***************************************************************************/ -/* DNR :: DCR_DITH_OUT_CTRL :: reserved0 [31:08] */ -#define BCHP_DNR_DCR_DITH_OUT_CTRL_reserved0_MASK 0xffffff00 -#define BCHP_DNR_DCR_DITH_OUT_CTRL_reserved0_SHIFT 8 - -/* DNR :: DCR_DITH_OUT_CTRL :: DITH_CLAMP [07:00] */ -#define BCHP_DNR_DCR_DITH_OUT_CTRL_DITH_CLAMP_MASK 0x000000ff -#define BCHP_DNR_DCR_DITH_OUT_CTRL_DITH_CLAMP_SHIFT 0 - -#endif /* #ifndef BCHP_DNR_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,154 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_gio.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:07p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:13 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:07p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_GIO_H__ -#define BCHP_GIO_H__ - -/*************************************************************************** - *GIO - GPIO - ***************************************************************************/ -#define BCHP_GIO_ODEN_LO 0x00406000 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0] */ -#define BCHP_GIO_DATA_LO 0x00406004 /* GENERAL PURPOSE I/O DATA [31:0] */ -#define BCHP_GIO_IODIR_LO 0x00406008 /* GENERAL PURPOSE I/O DIRECTION [31:0] */ -#define BCHP_GIO_EC_LO 0x0040600c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0] */ -#define BCHP_GIO_EI_LO 0x00406010 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0] */ -#define BCHP_GIO_MASK_LO 0x00406014 /* GENERAL PURPOSE I/O INTERRUPT MASK [31:0] */ -#define BCHP_GIO_LEVEL_LO 0x00406018 /* GENERAL PURPOSE I/O INTERRUPT TYPE [31:0] */ -#define BCHP_GIO_STAT_LO 0x0040601c /* GENERAL PURPOSE I/O INTERRUPT STATUS [31:0] */ - -/*************************************************************************** - *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0] - ***************************************************************************/ -/* GIO :: ODEN_LO :: reserved0 [31:12] */ -#define BCHP_GIO_ODEN_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_ODEN_LO_reserved0_SHIFT 12 - -/* GIO :: ODEN_LO :: oden [11:00] */ -#define BCHP_GIO_ODEN_LO_oden_MASK 0x00000fff -#define BCHP_GIO_ODEN_LO_oden_SHIFT 0 - -/*************************************************************************** - *DATA_LO - GENERAL PURPOSE I/O DATA [31:0] - ***************************************************************************/ -/* GIO :: DATA_LO :: reserved0 [31:12] */ -#define BCHP_GIO_DATA_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_DATA_LO_reserved0_SHIFT 12 - -/* GIO :: DATA_LO :: data [11:00] */ -#define BCHP_GIO_DATA_LO_data_MASK 0x00000fff -#define BCHP_GIO_DATA_LO_data_SHIFT 0 - -/*************************************************************************** - *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [31:0] - ***************************************************************************/ -/* GIO :: IODIR_LO :: reserved0 [31:12] */ -#define BCHP_GIO_IODIR_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_IODIR_LO_reserved0_SHIFT 12 - -/* GIO :: IODIR_LO :: iodir [11:00] */ -#define BCHP_GIO_IODIR_LO_iodir_MASK 0x00000fff -#define BCHP_GIO_IODIR_LO_iodir_SHIFT 0 - -/*************************************************************************** - *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0] - ***************************************************************************/ -/* GIO :: EC_LO :: reserved0 [31:12] */ -#define BCHP_GIO_EC_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_EC_LO_reserved0_SHIFT 12 - -/* GIO :: EC_LO :: edge_config [11:00] */ -#define BCHP_GIO_EC_LO_edge_config_MASK 0x00000fff -#define BCHP_GIO_EC_LO_edge_config_SHIFT 0 - -/*************************************************************************** - *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0] - ***************************************************************************/ -/* GIO :: EI_LO :: reserved0 [31:12] */ -#define BCHP_GIO_EI_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_EI_LO_reserved0_SHIFT 12 - -/* GIO :: EI_LO :: edge_insensitive [11:00] */ -#define BCHP_GIO_EI_LO_edge_insensitive_MASK 0x00000fff -#define BCHP_GIO_EI_LO_edge_insensitive_SHIFT 0 - -/*************************************************************************** - *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [31:0] - ***************************************************************************/ -/* GIO :: MASK_LO :: reserved0 [31:12] */ -#define BCHP_GIO_MASK_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_MASK_LO_reserved0_SHIFT 12 - -/* GIO :: MASK_LO :: irq_mask [11:00] */ -#define BCHP_GIO_MASK_LO_irq_mask_MASK 0x00000fff -#define BCHP_GIO_MASK_LO_irq_mask_SHIFT 0 - -/*************************************************************************** - *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [31:0] - ***************************************************************************/ -/* GIO :: LEVEL_LO :: reserved0 [31:12] */ -#define BCHP_GIO_LEVEL_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_LEVEL_LO_reserved0_SHIFT 12 - -/* GIO :: LEVEL_LO :: level [11:00] */ -#define BCHP_GIO_LEVEL_LO_level_MASK 0x00000fff -#define BCHP_GIO_LEVEL_LO_level_SHIFT 0 - -/*************************************************************************** - *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [31:0] - ***************************************************************************/ -/* GIO :: STAT_LO :: reserved0 [31:12] */ -#define BCHP_GIO_STAT_LO_reserved0_MASK 0xfffff000 -#define BCHP_GIO_STAT_LO_reserved0_SHIFT 12 - -/* GIO :: STAT_LO :: irq_status [11:00] */ -#define BCHP_GIO_STAT_LO_irq_status_MASK 0x00000fff -#define BCHP_GIO_STAT_LO_irq_status_SHIFT 0 - -#endif /* #ifndef BCHP_GIO_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,116 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_i2c_gr_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:08p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:01 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:08p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_I2C_GR_BRIDGE_H__ -#define BCHP_I2C_GR_BRIDGE_H__ - -/*************************************************************************** - *I2C_GR_BRIDGE - I2C GR bridge registers - ***************************************************************************/ -#define BCHP_I2C_GR_BRIDGE_REVISION 0x005013e0 /* GR Bridge Revision */ -#define BCHP_I2C_GR_BRIDGE_CTRL 0x005013e4 /* GR Bridge Control Register */ -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x005013e8 /* GR Bridge Software Reset 0 Register */ -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x005013ec /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* I2C_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define BCHP_I2C_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_I2C_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* I2C_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define BCHP_I2C_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_I2C_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* I2C_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define BCHP_I2C_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define BCHP_I2C_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* I2C_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define BCHP_I2C_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_I2C_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* I2C_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - -/*************************************************************************** - *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - -#endif /* #ifndef BCHP_I2C_GR_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,374 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_i2c.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:07p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:05 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_i2c.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:07p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_I2C_H__ -#define BCHP_I2C_H__ - -/*************************************************************************** - *I2C - I2C related registers - ***************************************************************************/ -#define BCHP_I2C_CHIP_ADDRESS 0x00501000 /* I2C Chip Address And Read/Write Control */ -#define BCHP_I2C_DATA_IN0 0x00501004 /* I2C Write Data Byte 0 */ -#define BCHP_I2C_DATA_IN1 0x00501008 /* I2C Write Data Byte 1 */ -#define BCHP_I2C_DATA_IN2 0x0050100c /* I2C Write Data Byte 2 */ -#define BCHP_I2C_DATA_IN3 0x00501010 /* I2C Write Data Byte 3 */ -#define BCHP_I2C_DATA_IN4 0x00501014 /* I2C Write Data Byte 4 */ -#define BCHP_I2C_DATA_IN5 0x00501018 /* I2C Write Data Byte 5 */ -#define BCHP_I2C_DATA_IN6 0x0050101c /* I2C Write Data Byte 6 */ -#define BCHP_I2C_DATA_IN7 0x00501020 /* I2C Write Data Byte 7 */ -#define BCHP_I2C_CNT_REG 0x00501024 /* I2C Transfer Count Register */ -#define BCHP_I2C_CTL_REG 0x00501028 /* I2C Control Register */ -#define BCHP_I2C_IIC_ENABLE 0x0050102c /* I2C Read/Write Enable And Interrupt */ -#define BCHP_I2C_DATA_OUT0 0x00501030 /* I2C Read Data Byte 0 */ -#define BCHP_I2C_DATA_OUT1 0x00501034 /* I2C Read Data Byte 1 */ -#define BCHP_I2C_DATA_OUT2 0x00501038 /* I2C Read Data Byte 2 */ -#define BCHP_I2C_DATA_OUT3 0x0050103c /* I2C Read Data Byte 3 */ -#define BCHP_I2C_DATA_OUT4 0x00501040 /* I2C Read Data Byte 4 */ -#define BCHP_I2C_DATA_OUT5 0x00501044 /* I2C Read Data Byte 5 */ -#define BCHP_I2C_DATA_OUT6 0x00501048 /* I2C Read Data Byte 6 */ -#define BCHP_I2C_DATA_OUT7 0x0050104c /* I2C Read Data Byte 7 */ -#define BCHP_I2C_CTLHI_REG 0x00501050 /* I2C Control Register */ -#define BCHP_I2C_SCL_PARAM 0x00501054 /* I2C SCL Parameter Register */ - -/*************************************************************************** - *CHIP_ADDRESS - I2C Chip Address And Read/Write Control - ***************************************************************************/ -/* I2C :: CHIP_ADDRESS :: reserved0 [31:08] */ -#define BCHP_I2C_CHIP_ADDRESS_reserved0_MASK 0xffffff00 -#define BCHP_I2C_CHIP_ADDRESS_reserved0_SHIFT 8 - -/* I2C :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ -#define BCHP_I2C_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe -#define BCHP_I2C_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 - -/* I2C :: CHIP_ADDRESS :: RESERVED [00:00] */ -#define BCHP_I2C_CHIP_ADDRESS_RESERVED_MASK 0x00000001 -#define BCHP_I2C_CHIP_ADDRESS_RESERVED_SHIFT 0 - -/*************************************************************************** - *DATA_IN0 - I2C Write Data Byte 0 - ***************************************************************************/ -/* I2C :: DATA_IN0 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN0_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN0_reserved0_SHIFT 8 - -/* I2C :: DATA_IN0 :: DATA_IN0 [07:00] */ -#define BCHP_I2C_DATA_IN0_DATA_IN0_MASK 0x000000ff -#define BCHP_I2C_DATA_IN0_DATA_IN0_SHIFT 0 - -/*************************************************************************** - *DATA_IN1 - I2C Write Data Byte 1 - ***************************************************************************/ -/* I2C :: DATA_IN1 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN1_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN1_reserved0_SHIFT 8 - -/* I2C :: DATA_IN1 :: DATA_IN1 [07:00] */ -#define BCHP_I2C_DATA_IN1_DATA_IN1_MASK 0x000000ff -#define BCHP_I2C_DATA_IN1_DATA_IN1_SHIFT 0 - -/*************************************************************************** - *DATA_IN2 - I2C Write Data Byte 2 - ***************************************************************************/ -/* I2C :: DATA_IN2 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN2_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN2_reserved0_SHIFT 8 - -/* I2C :: DATA_IN2 :: DATA_IN2 [07:00] */ -#define BCHP_I2C_DATA_IN2_DATA_IN2_MASK 0x000000ff -#define BCHP_I2C_DATA_IN2_DATA_IN2_SHIFT 0 - -/*************************************************************************** - *DATA_IN3 - I2C Write Data Byte 3 - ***************************************************************************/ -/* I2C :: DATA_IN3 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN3_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN3_reserved0_SHIFT 8 - -/* I2C :: DATA_IN3 :: DATA_IN3 [07:00] */ -#define BCHP_I2C_DATA_IN3_DATA_IN3_MASK 0x000000ff -#define BCHP_I2C_DATA_IN3_DATA_IN3_SHIFT 0 - -/*************************************************************************** - *DATA_IN4 - I2C Write Data Byte 4 - ***************************************************************************/ -/* I2C :: DATA_IN4 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN4_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN4_reserved0_SHIFT 8 - -/* I2C :: DATA_IN4 :: DATA_IN4 [07:00] */ -#define BCHP_I2C_DATA_IN4_DATA_IN4_MASK 0x000000ff -#define BCHP_I2C_DATA_IN4_DATA_IN4_SHIFT 0 - -/*************************************************************************** - *DATA_IN5 - I2C Write Data Byte 5 - ***************************************************************************/ -/* I2C :: DATA_IN5 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN5_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN5_reserved0_SHIFT 8 - -/* I2C :: DATA_IN5 :: DATA_IN5 [07:00] */ -#define BCHP_I2C_DATA_IN5_DATA_IN5_MASK 0x000000ff -#define BCHP_I2C_DATA_IN5_DATA_IN5_SHIFT 0 - -/*************************************************************************** - *DATA_IN6 - I2C Write Data Byte 6 - ***************************************************************************/ -/* I2C :: DATA_IN6 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN6_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN6_reserved0_SHIFT 8 - -/* I2C :: DATA_IN6 :: DATA_IN6 [07:00] */ -#define BCHP_I2C_DATA_IN6_DATA_IN6_MASK 0x000000ff -#define BCHP_I2C_DATA_IN6_DATA_IN6_SHIFT 0 - -/*************************************************************************** - *DATA_IN7 - I2C Write Data Byte 7 - ***************************************************************************/ -/* I2C :: DATA_IN7 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_IN7_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_IN7_reserved0_SHIFT 8 - -/* I2C :: DATA_IN7 :: DATA_IN7 [07:00] */ -#define BCHP_I2C_DATA_IN7_DATA_IN7_MASK 0x000000ff -#define BCHP_I2C_DATA_IN7_DATA_IN7_SHIFT 0 - -/*************************************************************************** - *CNT_REG - I2C Transfer Count Register - ***************************************************************************/ -/* I2C :: CNT_REG :: reserved0 [31:08] */ -#define BCHP_I2C_CNT_REG_reserved0_MASK 0xffffff00 -#define BCHP_I2C_CNT_REG_reserved0_SHIFT 8 - -/* I2C :: CNT_REG :: CNT_REG2 [07:04] */ -#define BCHP_I2C_CNT_REG_CNT_REG2_MASK 0x000000f0 -#define BCHP_I2C_CNT_REG_CNT_REG2_SHIFT 4 - -/* I2C :: CNT_REG :: CNT_REG1 [03:00] */ -#define BCHP_I2C_CNT_REG_CNT_REG1_MASK 0x0000000f -#define BCHP_I2C_CNT_REG_CNT_REG1_SHIFT 0 - -/*************************************************************************** - *CTL_REG - I2C Control Register - ***************************************************************************/ -/* I2C :: CTL_REG :: reserved0 [31:08] */ -#define BCHP_I2C_CTL_REG_reserved0_MASK 0xffffff00 -#define BCHP_I2C_CTL_REG_reserved0_SHIFT 8 - -/* I2C :: CTL_REG :: DIV_CLK [07:07] */ -#define BCHP_I2C_CTL_REG_DIV_CLK_MASK 0x00000080 -#define BCHP_I2C_CTL_REG_DIV_CLK_SHIFT 7 - -/* I2C :: CTL_REG :: INT_EN [06:06] */ -#define BCHP_I2C_CTL_REG_INT_EN_MASK 0x00000040 -#define BCHP_I2C_CTL_REG_INT_EN_SHIFT 6 - -/* I2C :: CTL_REG :: SCL_SEL [05:04] */ -#define BCHP_I2C_CTL_REG_SCL_SEL_MASK 0x00000030 -#define BCHP_I2C_CTL_REG_SCL_SEL_SHIFT 4 - -/* I2C :: CTL_REG :: DELAY_DIS [03:03] */ -#define BCHP_I2C_CTL_REG_DELAY_DIS_MASK 0x00000008 -#define BCHP_I2C_CTL_REG_DELAY_DIS_SHIFT 3 - -/* I2C :: CTL_REG :: DEGLITCH_DIS [02:02] */ -#define BCHP_I2C_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 -#define BCHP_I2C_CTL_REG_DEGLITCH_DIS_SHIFT 2 - -/* I2C :: CTL_REG :: DTF [01:00] */ -#define BCHP_I2C_CTL_REG_DTF_MASK 0x00000003 -#define BCHP_I2C_CTL_REG_DTF_SHIFT 0 - -/*************************************************************************** - *IIC_ENABLE - I2C Read/Write Enable And Interrupt - ***************************************************************************/ -/* I2C :: IIC_ENABLE :: reserved0 [31:07] */ -#define BCHP_I2C_IIC_ENABLE_reserved0_MASK 0xffffff80 -#define BCHP_I2C_IIC_ENABLE_reserved0_SHIFT 7 - -/* I2C :: IIC_ENABLE :: RESTART [06:06] */ -#define BCHP_I2C_IIC_ENABLE_RESTART_MASK 0x00000040 -#define BCHP_I2C_IIC_ENABLE_RESTART_SHIFT 6 - -/* I2C :: IIC_ENABLE :: NO_START [05:05] */ -#define BCHP_I2C_IIC_ENABLE_NO_START_MASK 0x00000020 -#define BCHP_I2C_IIC_ENABLE_NO_START_SHIFT 5 - -/* I2C :: IIC_ENABLE :: NO_STOP [04:04] */ -#define BCHP_I2C_IIC_ENABLE_NO_STOP_MASK 0x00000010 -#define BCHP_I2C_IIC_ENABLE_NO_STOP_SHIFT 4 - -/* I2C :: IIC_ENABLE :: reserved1 [03:03] */ -#define BCHP_I2C_IIC_ENABLE_reserved1_MASK 0x00000008 -#define BCHP_I2C_IIC_ENABLE_reserved1_SHIFT 3 - -/* I2C :: IIC_ENABLE :: NO_ACK [02:02] */ -#define BCHP_I2C_IIC_ENABLE_NO_ACK_MASK 0x00000004 -#define BCHP_I2C_IIC_ENABLE_NO_ACK_SHIFT 2 - -/* I2C :: IIC_ENABLE :: INTRP [01:01] */ -#define BCHP_I2C_IIC_ENABLE_INTRP_MASK 0x00000002 -#define BCHP_I2C_IIC_ENABLE_INTRP_SHIFT 1 - -/* I2C :: IIC_ENABLE :: ENABLE [00:00] */ -#define BCHP_I2C_IIC_ENABLE_ENABLE_MASK 0x00000001 -#define BCHP_I2C_IIC_ENABLE_ENABLE_SHIFT 0 - -/*************************************************************************** - *DATA_OUT0 - I2C Read Data Byte 0 - ***************************************************************************/ -/* I2C :: DATA_OUT0 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT0_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT0_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT0 :: DATA_OUT0 [07:00] */ -#define BCHP_I2C_DATA_OUT0_DATA_OUT0_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT0_DATA_OUT0_SHIFT 0 - -/*************************************************************************** - *DATA_OUT1 - I2C Read Data Byte 1 - ***************************************************************************/ -/* I2C :: DATA_OUT1 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT1_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT1_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT1 :: DATA_OUT1 [07:00] */ -#define BCHP_I2C_DATA_OUT1_DATA_OUT1_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT1_DATA_OUT1_SHIFT 0 - -/*************************************************************************** - *DATA_OUT2 - I2C Read Data Byte 2 - ***************************************************************************/ -/* I2C :: DATA_OUT2 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT2_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT2_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT2 :: DATA_OUT2 [07:00] */ -#define BCHP_I2C_DATA_OUT2_DATA_OUT2_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT2_DATA_OUT2_SHIFT 0 - -/*************************************************************************** - *DATA_OUT3 - I2C Read Data Byte 3 - ***************************************************************************/ -/* I2C :: DATA_OUT3 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT3_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT3_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT3 :: DATA_OUT3 [07:00] */ -#define BCHP_I2C_DATA_OUT3_DATA_OUT3_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT3_DATA_OUT3_SHIFT 0 - -/*************************************************************************** - *DATA_OUT4 - I2C Read Data Byte 4 - ***************************************************************************/ -/* I2C :: DATA_OUT4 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT4_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT4_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT4 :: DATA_OUT4 [07:00] */ -#define BCHP_I2C_DATA_OUT4_DATA_OUT4_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT4_DATA_OUT4_SHIFT 0 - -/*************************************************************************** - *DATA_OUT5 - I2C Read Data Byte 5 - ***************************************************************************/ -/* I2C :: DATA_OUT5 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT5_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT5_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT5 :: DATA_OUT5 [07:00] */ -#define BCHP_I2C_DATA_OUT5_DATA_OUT5_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT5_DATA_OUT5_SHIFT 0 - -/*************************************************************************** - *DATA_OUT6 - I2C Read Data Byte 6 - ***************************************************************************/ -/* I2C :: DATA_OUT6 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT6_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT6_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT6 :: DATA_OUT6 [07:00] */ -#define BCHP_I2C_DATA_OUT6_DATA_OUT6_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT6_DATA_OUT6_SHIFT 0 - -/*************************************************************************** - *DATA_OUT7 - I2C Read Data Byte 7 - ***************************************************************************/ -/* I2C :: DATA_OUT7 :: reserved0 [31:08] */ -#define BCHP_I2C_DATA_OUT7_reserved0_MASK 0xffffff00 -#define BCHP_I2C_DATA_OUT7_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT7 :: DATA_OUT7 [07:00] */ -#define BCHP_I2C_DATA_OUT7_DATA_OUT7_MASK 0x000000ff -#define BCHP_I2C_DATA_OUT7_DATA_OUT7_SHIFT 0 - -/*************************************************************************** - *CTLHI_REG - I2C Control Register - ***************************************************************************/ -/* I2C :: CTLHI_REG :: reserved0 [31:02] */ -#define BCHP_I2C_CTLHI_REG_reserved0_MASK 0xfffffffc -#define BCHP_I2C_CTLHI_REG_reserved0_SHIFT 2 - -/* I2C :: CTLHI_REG :: IGNORE_ACK [01:01] */ -#define BCHP_I2C_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 -#define BCHP_I2C_CTLHI_REG_IGNORE_ACK_SHIFT 1 - -/* I2C :: CTLHI_REG :: WAIT_DIS [00:00] */ -#define BCHP_I2C_CTLHI_REG_WAIT_DIS_MASK 0x00000001 -#define BCHP_I2C_CTLHI_REG_WAIT_DIS_SHIFT 0 - -/*************************************************************************** - *SCL_PARAM - I2C SCL Parameter Register - ***************************************************************************/ -/* I2C :: SCL_PARAM :: reserved0 [31:00] */ -#define BCHP_I2C_SCL_PARAM_reserved0_MASK 0xffffffff -#define BCHP_I2C_SCL_PARAM_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_I2C_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_irq0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_irq0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_irq0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_irq0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_int_id_irq0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:08p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:38 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility unknown - * RDB Parser 3.0 - * generate_int_id.pl 1.0 - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_irq0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:08p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#include "bchp.h" -#include "bchp_irq0.h" - -#ifndef BCHP_INT_ID_IRQ0_H__ -#define BCHP_INT_ID_IRQ0_H__ - -#define BCHP_INT_ID_gio_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_gio_irqen_SHIFT) -#define BCHP_INT_ID_icap_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_icap_irqen_SHIFT) -#define BCHP_INT_ID_iica_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iica_irqen_SHIFT) -#define BCHP_INT_ID_iicb_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT) -#define BCHP_INT_ID_iicc_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT) -#define BCHP_INT_ID_iicd_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT) -#define BCHP_INT_ID_iice_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iice_irqen_SHIFT) -#define BCHP_INT_ID_kbd1_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_kbd1_irqen_SHIFT) -#define BCHP_INT_ID_ldk_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ldk_irqen_SHIFT) -#define BCHP_INT_ID_spi_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_spi_irqen_SHIFT) -#define BCHP_INT_ID_ua_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ua_irqen_SHIFT) -#define BCHP_INT_ID_uarta_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT) -#define BCHP_INT_ID_uartb_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT) -#define BCHP_INT_ID_uartc_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT) -#define BCHP_INT_ID_uartd_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uartd_irqen_SHIFT) -#define BCHP_INT_ID_ub_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ub_irqen_SHIFT) -#define BCHP_INT_ID_uc_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uc_irqen_SHIFT) -#define BCHP_INT_ID_ud_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ud_irqen_SHIFT) - -#endif /* #ifndef BCHP_INT_ID_IRQ0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_timer.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_timer.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_timer.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_timer.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,63 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_int_id_timer.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:08p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:39 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility unknown - * RDB Parser 3.0 - * generate_int_id.pl 1.0 - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_timer.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:08p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#include "bchp.h" -#include "bchp_timer.h" - -#ifndef BCHP_INT_ID_TIMER_H__ -#define BCHP_INT_ID_TIMER_H__ - -#define BCHP_INT_ID_TMR0TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT) -#define BCHP_INT_ID_TMR1TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT) -#define BCHP_INT_ID_TMR2TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT) -#define BCHP_INT_ID_TMR3TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT) -#define BCHP_INT_ID_WDINT BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_WDINT_SHIFT) - -#endif /* #ifndef BCHP_INT_ID_TIMER_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,67 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_int_id_xpt_pb0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:08p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:40 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility unknown - * RDB Parser 3.0 - * generate_int_id.pl 1.0 - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:08p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#include "bchp.h" -#include "bchp_xpt_pb0.h" - -#ifndef BCHP_INT_ID_XPT_PB0_H__ -#define BCHP_INT_ID_XPT_PB0_H__ - -#define BCHP_INT_ID_XPT_PB0_DONE_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_DONE_INT_SHIFT) -#define BCHP_INT_ID_XPT_PB0_PARSER_CONTINUITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB0_PARSER_LENGTH_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB0_PARSER_SEC_CC_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB0_PARSER_TRANSPORT_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB0_PB_COPYRIGHT_CHANGE BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT) -#define BCHP_INT_ID_XPT_PB0_SE_OUT_OF_SYNC_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT) -#define BCHP_INT_ID_XPT_PB0_TS_PARITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB0_TS_RANGE_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT) - -#endif /* #ifndef BCHP_INT_ID_XPT_PB0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb1.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb1.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb1.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb1.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,68 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_int_id_xpt_pb1.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:08p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:40 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility unknown - * RDB Parser 3.0 - * generate_int_id.pl 1.0 - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb1.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:08p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#include "bchp.h" -#include "bchp_xpt_pb0.h" -#include "bchp_xpt_pb1.h" - -#ifndef BCHP_INT_ID_XPT_PB1_H__ -#define BCHP_INT_ID_XPT_PB1_H__ - -#define BCHP_INT_ID_XPT_PB1_DONE_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_DONE_INT_SHIFT) -#define BCHP_INT_ID_XPT_PB1_PARSER_CONTINUITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB1_PARSER_LENGTH_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB1_PARSER_SEC_CC_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB1_PARSER_TRANSPORT_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB1_PB_COPYRIGHT_CHANGE BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT) -#define BCHP_INT_ID_XPT_PB1_SE_OUT_OF_SYNC_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT) -#define BCHP_INT_ID_XPT_PB1_TS_PARITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB1_TS_RANGE_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT) - -#endif /* #ifndef BCHP_INT_ID_XPT_PB1_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,68 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_int_id_xpt_pb2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:09p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:41 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility unknown - * RDB Parser 3.0 - * generate_int_id.pl 1.0 - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:09p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#include "bchp.h" -#include "bchp_xpt_pb0.h" -#include "bchp_xpt_pb2.h" - -#ifndef BCHP_INT_ID_XPT_PB2_H__ -#define BCHP_INT_ID_XPT_PB2_H__ - -#define BCHP_INT_ID_XPT_PB2_DONE_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_DONE_INT_SHIFT) -#define BCHP_INT_ID_XPT_PB2_PARSER_CONTINUITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB2_PARSER_LENGTH_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB2_PARSER_SEC_CC_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB2_PARSER_TRANSPORT_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB2_PB_COPYRIGHT_CHANGE BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT) -#define BCHP_INT_ID_XPT_PB2_SE_OUT_OF_SYNC_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT) -#define BCHP_INT_ID_XPT_PB2_TS_PARITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT) -#define BCHP_INT_ID_XPT_PB2_TS_RANGE_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT) - -#endif /* #ifndef BCHP_INT_ID_XPT_PB2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_rave.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_rave.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_rave.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_rave.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,71 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_int_id_xpt_rave.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:09p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:42 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility unknown - * RDB Parser 3.0 - * generate_int_id.pl 1.0 - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_rave.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:09p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#include "bchp.h" -#include "bchp_xpt_rave.h" - -#ifndef BCHP_INT_ID_XPT_RAVE_H__ -#define BCHP_INT_ID_XPT_RAVE_H__ - -#define BCHP_INT_ID_XPT_RAVE_CC_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_CDB_LOWER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_CDB_OVERFLOW_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_CDB_UPPER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_EMU_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_ITB_LOWER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_ITB_OVERFLOW_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_ITB_UPPER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_LAST_CMD_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_PUSI_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_SCD_INDEX BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_SPLICE_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_SHIFT) -#define BCHP_INT_ID_XPT_RAVE_TEI_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_SHIFT) - -#endif /* #ifndef BCHP_INT_ID_XPT_RAVE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1222 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_intr.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:09p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:44 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:09p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_INTR_H__ -#define BCHP_INTR_H__ - -/*************************************************************************** - *INTR - TGT L2 Interrupt Controller Registers - ***************************************************************************/ -#define BCHP_INTR_INTR_STATUS 0x00500700 /* Interrupt Status Register */ -#define BCHP_INTR_INTR_SET 0x00500704 /* Interrupt Set Register */ -#define BCHP_INTR_INTR_CLR_REG 0x00500708 /* Interrupt Clear Register */ -#define BCHP_INTR_INTR_MSK_STS_REG 0x0050070c /* Interrupt Mask Status Register */ -#define BCHP_INTR_INTR_MSK_SET_REG 0x00500710 /* Interrupt Mask Set Register */ -#define BCHP_INTR_INTR_MSK_CLR_REG 0x00500714 /* Interrupt Mask Clear Register */ -#define BCHP_INTR_EOI_CTRL 0x00500718 /* End of interrupt control register */ -#define BCHP_INTR_CPU_INTR_STATUS 0x00500720 /* CPU_Interrupt Status Register */ -#define BCHP_INTR_CPU_INTR_SET 0x00500724 /* CPU_Interrupt Set Register */ -#define BCHP_INTR_CPU_INTR_CLR_REG 0x00500728 /* CPU_Interrupt Clear Register */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG 0x0050072c /* CPU_Interrupt Mask Status Register */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG 0x00500730 /* CPU Interrupt Mask Set Register */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG 0x00500734 /* CPU Interrupt Mask Clear Register */ - -/*************************************************************************** - *INTR_STATUS - Interrupt Status Register - ***************************************************************************/ -/* INTR :: INTR_STATUS :: reserved0 [31:27] */ -#define BCHP_INTR_INTR_STATUS_reserved0_MASK 0xf8000000 -#define BCHP_INTR_INTR_STATUS_reserved0_SHIFT 27 - -/* INTR :: INTR_STATUS :: HAT_INTR [26:26] */ -#define BCHP_INTR_INTR_STATUS_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_INTR_STATUS_HAT_INTR_SHIFT 26 - -/* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_STATUS :: reserved1 [23:20] */ -#define BCHP_INTR_INTR_STATUS_reserved1_MASK 0x00f00000 -#define BCHP_INTR_INTR_STATUS_reserved1_SHIFT 20 - -/* INTR :: INTR_STATUS :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_INTR_STATUS_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_INTR_STATUS_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: INTR_STATUS :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_INTR_STATUS_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_INTR_STATUS_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: INTR_STATUS :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_INTR_STATUS_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_INTR_STATUS_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: INTR_STATUS :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_INTR_STATUS_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_INTR_STATUS_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: INTR_STATUS :: reserved2 [15:14] */ -#define BCHP_INTR_INTR_STATUS_reserved2_MASK 0x0000c000 -#define BCHP_INTR_INTR_STATUS_reserved2_SHIFT 14 - -/* INTR :: INTR_STATUS :: L1_HIF_RX_DMA_ERR_INTR [13:13] */ -#define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_MASK 0x00002000 -#define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_SHIFT 13 - -/* INTR :: INTR_STATUS :: L1_HIF_RX_DMA_DONE_INTR [12:12] */ -#define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_MASK 0x00001000 -#define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_SHIFT 12 - -/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ -#define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 -#define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 - -/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ -#define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 -#define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 - -/* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ -#define BCHP_INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 -#define BCHP_INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 - -/* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ -#define BCHP_INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 -#define BCHP_INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 - -/* INTR :: INTR_STATUS :: reserved3 [07:06] */ -#define BCHP_INTR_INTR_STATUS_reserved3_MASK 0x000000c0 -#define BCHP_INTR_INTR_STATUS_reserved3_SHIFT 6 - -/* INTR :: INTR_STATUS :: L0_HIF_RX_DMA_ERR_INTR [05:05] */ -#define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_MASK 0x00000020 -#define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_SHIFT 5 - -/* INTR :: INTR_STATUS :: L0_HIF_RX_DMA_DONE_INTR [04:04] */ -#define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_MASK 0x00000010 -#define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_SHIFT 4 - -/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ -#define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 -#define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 - -/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ -#define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 -#define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 - -/* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ -#define BCHP_INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 -#define BCHP_INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 - -/* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ -#define BCHP_INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 -#define BCHP_INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 - -/*************************************************************************** - *INTR_SET - Interrupt Set Register - ***************************************************************************/ -/* INTR :: INTR_SET :: reserved0 [31:27] */ -#define BCHP_INTR_INTR_SET_reserved0_MASK 0xf8000000 -#define BCHP_INTR_INTR_SET_reserved0_SHIFT 27 - -/* INTR :: INTR_SET :: HAT_INTR [26:26] */ -#define BCHP_INTR_INTR_SET_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_INTR_SET_HAT_INTR_SHIFT 26 - -/* INTR :: INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_SET :: reserved1 [23:20] */ -#define BCHP_INTR_INTR_SET_reserved1_MASK 0x00f00000 -#define BCHP_INTR_INTR_SET_reserved1_SHIFT 20 - -/* INTR :: INTR_SET :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_INTR_SET_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_INTR_SET_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: INTR_SET :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_INTR_SET_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_INTR_SET_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: INTR_SET :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_INTR_SET_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_INTR_SET_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: INTR_SET :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_INTR_SET_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_INTR_SET_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: INTR_SET :: reserved2 [15:14] */ -#define BCHP_INTR_INTR_SET_reserved2_MASK 0x0000c000 -#define BCHP_INTR_INTR_SET_reserved2_SHIFT 14 - -/* INTR :: INTR_SET :: HIF_RX_DMA_L1_ERR_INTR [13:13] */ -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_MASK 0x00002000 -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_SHIFT 13 - -/* INTR :: INTR_SET :: HIF_RX_DMA_L1_DONE_INTR [12:12] */ -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_MASK 0x00001000 -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_SHIFT 12 - -/* INTR :: INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 - -/* INTR :: INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 - -/* INTR :: INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ -#define BCHP_INTR_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 -#define BCHP_INTR_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 - -/* INTR :: INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ -#define BCHP_INTR_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 -#define BCHP_INTR_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 - -/* INTR :: INTR_SET :: reserved3 [07:06] */ -#define BCHP_INTR_INTR_SET_reserved3_MASK 0x000000c0 -#define BCHP_INTR_INTR_SET_reserved3_SHIFT 6 - -/* INTR :: INTR_SET :: HIF_RX_DMA_L0_ERR_INTR [05:05] */ -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_MASK 0x00000020 -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_SHIFT 5 - -/* INTR :: INTR_SET :: HIF_RX_DMA_L0_DONE_INTR [04:04] */ -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_MASK 0x00000010 -#define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_SHIFT 4 - -/* INTR :: INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 - -/* INTR :: INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 -#define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 - -/* INTR :: INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ -#define BCHP_INTR_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 -#define BCHP_INTR_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 - -/* INTR :: INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ -#define BCHP_INTR_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 -#define BCHP_INTR_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 - -/*************************************************************************** - *INTR_CLR_REG - Interrupt Clear Register - ***************************************************************************/ -/* INTR :: INTR_CLR_REG :: reserved0 [31:27] */ -#define BCHP_INTR_INTR_CLR_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_INTR_CLR_REG_reserved0_SHIFT 27 - -/* INTR :: INTR_CLR_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_INTR_CLR_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_INTR_CLR_REG_HAT_INTR_SHIFT 26 - -/* INTR :: INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_CLR_REG :: reserved1 [23:20] */ -#define BCHP_INTR_INTR_CLR_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_INTR_CLR_REG_reserved1_SHIFT 20 - -/* INTR :: INTR_CLR_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: INTR_CLR_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: INTR_CLR_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: INTR_CLR_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_INTR_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: INTR_CLR_REG :: reserved2 [15:14] */ -#define BCHP_INTR_INTR_CLR_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_INTR_CLR_REG_reserved2_SHIFT 14 - -/* INTR :: INTR_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_CLR [13:13] */ -#define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 -#define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 13 - -/* INTR :: INTR_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_CLR [12:12] */ -#define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 -#define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 12 - -/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ -#define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 -#define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 - -/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ -#define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 -#define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 - -/* INTR :: INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ -#define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 -#define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 - -/* INTR :: INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ -#define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 -#define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 - -/* INTR :: INTR_CLR_REG :: reserved3 [07:06] */ -#define BCHP_INTR_INTR_CLR_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_INTR_CLR_REG_reserved3_SHIFT 6 - -/* INTR :: INTR_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_CLR [05:05] */ -#define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 -#define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 5 - -/* INTR :: INTR_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_CLR [04:04] */ -#define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 -#define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 4 - -/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ -#define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 -#define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 - -/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ -#define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 -#define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 - -/* INTR :: INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ -#define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 -#define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 - -/* INTR :: INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ -#define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 -#define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 - -/*************************************************************************** - *INTR_MSK_STS_REG - Interrupt Mask Status Register - ***************************************************************************/ -/* INTR :: INTR_MSK_STS_REG :: reserved0 [31:27] */ -#define BCHP_INTR_INTR_MSK_STS_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_INTR_MSK_STS_REG_reserved0_SHIFT 27 - -/* INTR :: INTR_MSK_STS_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_INTR_MSK_STS_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_INTR_MSK_STS_REG_HAT_INTR_SHIFT 26 - -/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_MSK_STS_REG :: reserved1 [23:20] */ -#define BCHP_INTR_INTR_MSK_STS_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_INTR_MSK_STS_REG_reserved1_SHIFT 20 - -/* INTR :: INTR_MSK_STS_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: INTR_MSK_STS_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: INTR_MSK_STS_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: INTR_MSK_STS_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: INTR_MSK_STS_REG :: reserved2 [15:14] */ -#define BCHP_INTR_INTR_MSK_STS_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_INTR_MSK_STS_REG_reserved2_SHIFT 14 - -/* INTR :: INTR_MSK_STS_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK [13:13] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 -#define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 13 - -/* INTR :: INTR_MSK_STS_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK [12:12] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 -#define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 12 - -/* INTR :: INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ -#define BCHP_INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 -#define BCHP_INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 - -/* INTR :: INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 -#define BCHP_INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 - -/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 -#define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 - -/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 -#define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 - -/* INTR :: INTR_MSK_STS_REG :: reserved3 [07:06] */ -#define BCHP_INTR_INTR_MSK_STS_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_INTR_MSK_STS_REG_reserved3_SHIFT 6 - -/* INTR :: INTR_MSK_STS_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK [05:05] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 -#define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 5 - -/* INTR :: INTR_MSK_STS_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK [04:04] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 -#define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 4 - -/* INTR :: INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ -#define BCHP_INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 -#define BCHP_INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 - -/* INTR :: INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 -#define BCHP_INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 - -/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 -#define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 - -/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ -#define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 -#define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 - -/*************************************************************************** - *INTR_MSK_SET_REG - Interrupt Mask Set Register - ***************************************************************************/ -/* INTR :: INTR_MSK_SET_REG :: reserved0 [31:27] */ -#define BCHP_INTR_INTR_MSK_SET_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_INTR_MSK_SET_REG_reserved0_SHIFT 27 - -/* INTR :: INTR_MSK_SET_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_INTR_MSK_SET_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_INTR_MSK_SET_REG_HAT_INTR_SHIFT 26 - -/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_MSK_SET_REG :: reserved1 [23:20] */ -#define BCHP_INTR_INTR_MSK_SET_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_INTR_MSK_SET_REG_reserved1_SHIFT 20 - -/* INTR :: INTR_MSK_SET_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: INTR_MSK_SET_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: INTR_MSK_SET_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: INTR_MSK_SET_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: INTR_MSK_SET_REG :: reserved2 [15:14] */ -#define BCHP_INTR_INTR_MSK_SET_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_INTR_MSK_SET_REG_reserved2_SHIFT 14 - -/* INTR :: INTR_MSK_SET_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_SET [13:13] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 -#define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 - -/* INTR :: INTR_MSK_SET_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_SET [12:12] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 -#define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 - -/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 -#define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 - -/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 -#define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 - -/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 -#define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 - -/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 -#define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 - -/* INTR :: INTR_MSK_SET_REG :: reserved3 [07:06] */ -#define BCHP_INTR_INTR_MSK_SET_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_INTR_MSK_SET_REG_reserved3_SHIFT 6 - -/* INTR :: INTR_MSK_SET_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_SET [05:05] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 -#define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 - -/* INTR :: INTR_MSK_SET_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_SET [04:04] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 -#define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 - -/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 -#define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 - -/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 -#define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 - -/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 -#define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 - -/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ -#define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 -#define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 - -/*************************************************************************** - *INTR_MSK_CLR_REG - Interrupt Mask Clear Register - ***************************************************************************/ -/* INTR :: INTR_MSK_CLR_REG :: reserved0 [31:27] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved0_SHIFT 27 - -/* INTR :: INTR_MSK_CLR_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_INTR_MSK_CLR_REG_HAT_INTR_SHIFT 26 - -/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_MSK_CLR_REG :: reserved1 [23:20] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved1_SHIFT 20 - -/* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: INTR_MSK_CLR_REG :: reserved2 [15:14] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved2_SHIFT 14 - -/* INTR :: INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 - -/* INTR :: INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 - -/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 - -/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 - -/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 - -/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 -#define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 - -/* INTR :: INTR_MSK_CLR_REG :: reserved3 [07:06] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_INTR_MSK_CLR_REG_reserved3_SHIFT 6 - -/* INTR :: INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 - -/* INTR :: INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 - -/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 - -/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 - -/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 - -/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 -#define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 - -/*************************************************************************** - *EOI_CTRL - End of interrupt control register - ***************************************************************************/ -/* INTR :: EOI_CTRL :: reserved0 [31:01] */ -#define BCHP_INTR_EOI_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_INTR_EOI_CTRL_reserved0_SHIFT 1 - -/* INTR :: EOI_CTRL :: EOI [00:00] */ -#define BCHP_INTR_EOI_CTRL_EOI_MASK 0x00000001 -#define BCHP_INTR_EOI_CTRL_EOI_SHIFT 0 - -/*************************************************************************** - *CPU_INTR_STATUS - CPU_Interrupt Status Register - ***************************************************************************/ -/* INTR :: CPU_INTR_STATUS :: reserved0 [31:27] */ -#define BCHP_INTR_CPU_INTR_STATUS_reserved0_MASK 0xf8000000 -#define BCHP_INTR_CPU_INTR_STATUS_reserved0_SHIFT 27 - -/* INTR :: CPU_INTR_STATUS :: HAT_INTR [26:26] */ -#define BCHP_INTR_CPU_INTR_STATUS_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_CPU_INTR_STATUS_HAT_INTR_SHIFT 26 - -/* INTR :: CPU_INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: CPU_INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: CPU_INTR_STATUS :: reserved1 [23:20] */ -#define BCHP_INTR_CPU_INTR_STATUS_reserved1_MASK 0x00f00000 -#define BCHP_INTR_CPU_INTR_STATUS_reserved1_SHIFT 20 - -/* INTR :: CPU_INTR_STATUS :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: CPU_INTR_STATUS :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: CPU_INTR_STATUS :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: CPU_INTR_STATUS :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: CPU_INTR_STATUS :: reserved2 [15:14] */ -#define BCHP_INTR_CPU_INTR_STATUS_reserved2_MASK 0x0000c000 -#define BCHP_INTR_CPU_INTR_STATUS_reserved2_SHIFT 14 - -/* INTR :: CPU_INTR_STATUS :: L1_HIF_RX_DMA_ERR_INTR [13:13] */ -#define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_MASK 0x00002000 -#define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_SHIFT 13 - -/* INTR :: CPU_INTR_STATUS :: L1_HIF_RX_DMA_DONE_INTR [12:12] */ -#define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_MASK 0x00001000 -#define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_SHIFT 12 - -/* INTR :: CPU_INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ -#define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 -#define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 - -/* INTR :: CPU_INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ -#define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 -#define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 - -/* INTR :: CPU_INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ -#define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 -#define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 - -/* INTR :: CPU_INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ -#define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 -#define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 - -/* INTR :: CPU_INTR_STATUS :: reserved3 [07:06] */ -#define BCHP_INTR_CPU_INTR_STATUS_reserved3_MASK 0x000000c0 -#define BCHP_INTR_CPU_INTR_STATUS_reserved3_SHIFT 6 - -/* INTR :: CPU_INTR_STATUS :: L0_HIF_RX_DMA_ERR_INTR [05:05] */ -#define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_MASK 0x00000020 -#define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_SHIFT 5 - -/* INTR :: CPU_INTR_STATUS :: L0_HIF_RX_DMA_DONE_INTR [04:04] */ -#define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_MASK 0x00000010 -#define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_SHIFT 4 - -/* INTR :: CPU_INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ -#define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 -#define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 - -/* INTR :: CPU_INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ -#define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 -#define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 - -/* INTR :: CPU_INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ -#define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 -#define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 - -/* INTR :: CPU_INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ -#define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 -#define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_INTR_SET - CPU_Interrupt Set Register - ***************************************************************************/ -/* INTR :: CPU_INTR_SET :: reserved0 [31:27] */ -#define BCHP_INTR_CPU_INTR_SET_reserved0_MASK 0xf8000000 -#define BCHP_INTR_CPU_INTR_SET_reserved0_SHIFT 27 - -/* INTR :: CPU_INTR_SET :: HAT_INTR [26:26] */ -#define BCHP_INTR_CPU_INTR_SET_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_CPU_INTR_SET_HAT_INTR_SHIFT 26 - -/* INTR :: CPU_INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: CPU_INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: CPU_INTR_SET :: reserved1 [23:20] */ -#define BCHP_INTR_CPU_INTR_SET_reserved1_MASK 0x00f00000 -#define BCHP_INTR_CPU_INTR_SET_reserved1_SHIFT 20 - -/* INTR :: CPU_INTR_SET :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: CPU_INTR_SET :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: CPU_INTR_SET :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: CPU_INTR_SET :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_CPU_INTR_SET_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: CPU_INTR_SET :: reserved2 [15:14] */ -#define BCHP_INTR_CPU_INTR_SET_reserved2_MASK 0x0000c000 -#define BCHP_INTR_CPU_INTR_SET_reserved2_SHIFT 14 - -/* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L1_ERR_INTR [13:13] */ -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_MASK 0x00002000 -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_SHIFT 13 - -/* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L1_DONE_INTR [12:12] */ -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_MASK 0x00001000 -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_SHIFT 12 - -/* INTR :: CPU_INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 - -/* INTR :: CPU_INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 - -/* INTR :: CPU_INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 - -/* INTR :: CPU_INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 - -/* INTR :: CPU_INTR_SET :: reserved3 [07:06] */ -#define BCHP_INTR_CPU_INTR_SET_reserved3_MASK 0x000000c0 -#define BCHP_INTR_CPU_INTR_SET_reserved3_SHIFT 6 - -/* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L0_ERR_INTR [05:05] */ -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_MASK 0x00000020 -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_SHIFT 5 - -/* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L0_DONE_INTR [04:04] */ -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_MASK 0x00000010 -#define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_SHIFT 4 - -/* INTR :: CPU_INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 - -/* INTR :: CPU_INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 -#define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 - -/* INTR :: CPU_INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 - -/* INTR :: CPU_INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 -#define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_INTR_CLR_REG - CPU_Interrupt Clear Register - ***************************************************************************/ -/* INTR :: CPU_INTR_CLR_REG :: reserved0 [31:27] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved0_SHIFT 27 - -/* INTR :: CPU_INTR_CLR_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_CPU_INTR_CLR_REG_HAT_INTR_SHIFT 26 - -/* INTR :: CPU_INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: CPU_INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: CPU_INTR_CLR_REG :: reserved1 [23:20] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved1_SHIFT 20 - -/* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: CPU_INTR_CLR_REG :: reserved2 [15:14] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved2_SHIFT 14 - -/* INTR :: CPU_INTR_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_CLR [13:13] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 13 - -/* INTR :: CPU_INTR_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_CLR [12:12] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 12 - -/* INTR :: CPU_INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 - -/* INTR :: CPU_INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 - -/* INTR :: CPU_INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 - -/* INTR :: CPU_INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 -#define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 - -/* INTR :: CPU_INTR_CLR_REG :: reserved3 [07:06] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_CPU_INTR_CLR_REG_reserved3_SHIFT 6 - -/* INTR :: CPU_INTR_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_CLR [05:05] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 5 - -/* INTR :: CPU_INTR_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_CLR [04:04] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 4 - -/* INTR :: CPU_INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 - -/* INTR :: CPU_INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 - -/* INTR :: CPU_INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 - -/* INTR :: CPU_INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 -#define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 - -/*************************************************************************** - *CPU_INTR_MSK_STS_REG - CPU_Interrupt Mask Status Register - ***************************************************************************/ -/* INTR :: CPU_INTR_MSK_STS_REG :: reserved0 [31:27] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved0_SHIFT 27 - -/* INTR :: CPU_INTR_MSK_STS_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_HAT_INTR_SHIFT 26 - -/* INTR :: CPU_INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: CPU_INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: CPU_INTR_MSK_STS_REG :: reserved1 [23:20] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved1_SHIFT 20 - -/* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: CPU_INTR_MSK_STS_REG :: reserved2 [15:14] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved2_SHIFT 14 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK [13:13] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 13 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK [12:12] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 12 - -/* INTR :: CPU_INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 - -/* INTR :: CPU_INTR_MSK_STS_REG :: reserved3 [07:06] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved3_SHIFT 6 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK [05:05] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 5 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK [04:04] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 4 - -/* INTR :: CPU_INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 - -/* INTR :: CPU_INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 -#define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 - -/*************************************************************************** - *CPU_INTR_MSK_SET_REG - CPU Interrupt Mask Set Register - ***************************************************************************/ -/* INTR :: CPU_INTR_MSK_SET_REG :: reserved0 [31:27] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved0_SHIFT 27 - -/* INTR :: CPU_INTR_MSK_SET_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_HAT_INTR_SHIFT 26 - -/* INTR :: CPU_INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: CPU_INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: CPU_INTR_MSK_SET_REG :: reserved1 [23:20] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved1_SHIFT 20 - -/* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: CPU_INTR_MSK_SET_REG :: reserved2 [15:14] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved2_SHIFT 14 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_SET [13:13] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_SET [12:12] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 - -/* INTR :: CPU_INTR_MSK_SET_REG :: reserved3 [07:06] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved3_SHIFT 6 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_SET [05:05] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_SET [04:04] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 - -/* INTR :: CPU_INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 -#define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 - -/*************************************************************************** - *CPU_INTR_MSK_CLR_REG - CPU Interrupt Mask Clear Register - ***************************************************************************/ -/* INTR :: CPU_INTR_MSK_CLR_REG :: reserved0 [31:27] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved0_MASK 0xf8000000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved0_SHIFT 27 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: HAT_INTR [26:26] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_HAT_INTR_MASK 0x04000000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_HAT_INTR_SHIFT 26 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: reserved1 [23:20] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved1_MASK 0x00f00000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved1_SHIFT 20 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX3_INTR [19:19] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX2_INTR [18:18] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX1_INTR [17:17] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX0_INTR [16:16] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: reserved2 [15:14] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved2_MASK 0x0000c000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved2_SHIFT 14 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: reserved3 [07:06] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved3_MASK 0x000000c0 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved3_SHIFT 6 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 - -/* INTR :: CPU_INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 -#define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 - -#endif /* #ifndef BCHP_INTR_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,266 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_irq0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:09p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:47 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_irq0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:09p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_IRQ0_H__ -#define BCHP_IRQ0_H__ - -/*************************************************************************** - *IRQ0 - Level 2 CPU Interrupt Enable/Status - ***************************************************************************/ -#define BCHP_IRQ0_IRQEN 0x00406080 /* Interrupt Enable */ -#define BCHP_IRQ0_IRQSTAT 0x00406084 /* Interrupt Status */ - -/*************************************************************************** - *IRQEN - Interrupt Enable - ***************************************************************************/ -/* IRQ0 :: IRQEN :: reserved_for_eco0 [31:29] */ -#define BCHP_IRQ0_IRQEN_reserved_for_eco0_MASK 0xe0000000 -#define BCHP_IRQ0_IRQEN_reserved_for_eco0_SHIFT 29 - -/* IRQ0 :: IRQEN :: iice_irqen [28:28] */ -#define BCHP_IRQ0_IRQEN_iice_irqen_MASK 0x10000000 -#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT 28 - -/* IRQ0 :: IRQEN :: iicd_irqen [27:27] */ -#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK 0x08000000 -#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT 27 - -/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */ -#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK 0x04000000 -#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT 26 - -/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */ -#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK 0x02000000 -#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT 25 - -/* IRQ0 :: IRQEN :: iica_irqen [24:24] */ -#define BCHP_IRQ0_IRQEN_iica_irqen_MASK 0x01000000 -#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT 24 - -/* IRQ0 :: IRQEN :: reserved_for_eco1 [23:21] */ -#define BCHP_IRQ0_IRQEN_reserved_for_eco1_MASK 0x00e00000 -#define BCHP_IRQ0_IRQEN_reserved_for_eco1_SHIFT 21 - -/* IRQ0 :: IRQEN :: spi_irqen [20:20] */ -#define BCHP_IRQ0_IRQEN_spi_irqen_MASK 0x00100000 -#define BCHP_IRQ0_IRQEN_spi_irqen_SHIFT 20 - -/* IRQ0 :: IRQEN :: uartd_irqen [19:19] */ -#define BCHP_IRQ0_IRQEN_uartd_irqen_MASK 0x00080000 -#define BCHP_IRQ0_IRQEN_uartd_irqen_SHIFT 19 - -/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */ -#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK 0x00040000 -#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT 18 - -/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */ -#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK 0x00020000 -#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT 17 - -/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */ -#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK 0x00010000 -#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT 16 - -/* IRQ0 :: IRQEN :: reserved_for_eco2 [15:12] */ -#define BCHP_IRQ0_IRQEN_reserved_for_eco2_MASK 0x0000f000 -#define BCHP_IRQ0_IRQEN_reserved_for_eco2_SHIFT 12 - -/* IRQ0 :: IRQEN :: ud_irqen [11:11] */ -#define BCHP_IRQ0_IRQEN_ud_irqen_MASK 0x00000800 -#define BCHP_IRQ0_IRQEN_ud_irqen_SHIFT 11 - -/* IRQ0 :: IRQEN :: reserved_for_eco3 [10:10] */ -#define BCHP_IRQ0_IRQEN_reserved_for_eco3_MASK 0x00000400 -#define BCHP_IRQ0_IRQEN_reserved_for_eco3_SHIFT 10 - -/* IRQ0 :: IRQEN :: uc_irqen [09:09] */ -#define BCHP_IRQ0_IRQEN_uc_irqen_MASK 0x00000200 -#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT 9 - -/* IRQ0 :: IRQEN :: reserved_for_eco4 [08:08] */ -#define BCHP_IRQ0_IRQEN_reserved_for_eco4_MASK 0x00000100 -#define BCHP_IRQ0_IRQEN_reserved_for_eco4_SHIFT 8 - -/* IRQ0 :: IRQEN :: icap_irqen [07:07] */ -#define BCHP_IRQ0_IRQEN_icap_irqen_MASK 0x00000080 -#define BCHP_IRQ0_IRQEN_icap_irqen_SHIFT 7 - -/* IRQ0 :: IRQEN :: gio_irqen [06:06] */ -#define BCHP_IRQ0_IRQEN_gio_irqen_MASK 0x00000040 -#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT 6 - -/* IRQ0 :: IRQEN :: reserved_for_eco5 [05:05] */ -#define BCHP_IRQ0_IRQEN_reserved_for_eco5_MASK 0x00000020 -#define BCHP_IRQ0_IRQEN_reserved_for_eco5_SHIFT 5 - -/* IRQ0 :: IRQEN :: ua_irqen [04:04] */ -#define BCHP_IRQ0_IRQEN_ua_irqen_MASK 0x00000010 -#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT 4 - -/* IRQ0 :: IRQEN :: ub_irqen [03:03] */ -#define BCHP_IRQ0_IRQEN_ub_irqen_MASK 0x00000008 -#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT 3 - -/* IRQ0 :: IRQEN :: reserved_for_eco6 [02:02] */ -#define BCHP_IRQ0_IRQEN_reserved_for_eco6_MASK 0x00000004 -#define BCHP_IRQ0_IRQEN_reserved_for_eco6_SHIFT 2 - -/* IRQ0 :: IRQEN :: ldk_irqen [01:01] */ -#define BCHP_IRQ0_IRQEN_ldk_irqen_MASK 0x00000002 -#define BCHP_IRQ0_IRQEN_ldk_irqen_SHIFT 1 - -/* IRQ0 :: IRQEN :: kbd1_irqen [00:00] */ -#define BCHP_IRQ0_IRQEN_kbd1_irqen_MASK 0x00000001 -#define BCHP_IRQ0_IRQEN_kbd1_irqen_SHIFT 0 - -/*************************************************************************** - *IRQSTAT - Interrupt Status - ***************************************************************************/ -/* IRQ0 :: IRQSTAT :: reserved0 [31:29] */ -#define BCHP_IRQ0_IRQSTAT_reserved0_MASK 0xe0000000 -#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT 29 - -/* IRQ0 :: IRQSTAT :: iiceirq [28:28] */ -#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK 0x10000000 -#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT 28 - -/* IRQ0 :: IRQSTAT :: iicdirq [27:27] */ -#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK 0x08000000 -#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT 27 - -/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */ -#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK 0x04000000 -#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT 26 - -/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */ -#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK 0x02000000 -#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT 25 - -/* IRQ0 :: IRQSTAT :: iicairq [24:24] */ -#define BCHP_IRQ0_IRQSTAT_iicairq_MASK 0x01000000 -#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT 24 - -/* IRQ0 :: IRQSTAT :: reserved1 [23:21] */ -#define BCHP_IRQ0_IRQSTAT_reserved1_MASK 0x00e00000 -#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT 21 - -/* IRQ0 :: IRQSTAT :: spiirq [20:20] */ -#define BCHP_IRQ0_IRQSTAT_spiirq_MASK 0x00100000 -#define BCHP_IRQ0_IRQSTAT_spiirq_SHIFT 20 - -/* IRQ0 :: IRQSTAT :: uartd_irq [19:19] */ -#define BCHP_IRQ0_IRQSTAT_uartd_irq_MASK 0x00080000 -#define BCHP_IRQ0_IRQSTAT_uartd_irq_SHIFT 19 - -/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */ -#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK 0x00040000 -#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT 18 - -/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */ -#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK 0x00020000 -#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT 17 - -/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */ -#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK 0x00010000 -#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT 16 - -/* IRQ0 :: IRQSTAT :: reserved2 [15:12] */ -#define BCHP_IRQ0_IRQSTAT_reserved2_MASK 0x0000f000 -#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT 12 - -/* IRQ0 :: IRQSTAT :: udirq [11:11] */ -#define BCHP_IRQ0_IRQSTAT_udirq_MASK 0x00000800 -#define BCHP_IRQ0_IRQSTAT_udirq_SHIFT 11 - -/* IRQ0 :: IRQSTAT :: reserved3 [10:10] */ -#define BCHP_IRQ0_IRQSTAT_reserved3_MASK 0x00000400 -#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT 10 - -/* IRQ0 :: IRQSTAT :: ucirq [09:09] */ -#define BCHP_IRQ0_IRQSTAT_ucirq_MASK 0x00000200 -#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT 9 - -/* IRQ0 :: IRQSTAT :: reserved4 [08:08] */ -#define BCHP_IRQ0_IRQSTAT_reserved4_MASK 0x00000100 -#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT 8 - -/* IRQ0 :: IRQSTAT :: icapirq [07:07] */ -#define BCHP_IRQ0_IRQSTAT_icapirq_MASK 0x00000080 -#define BCHP_IRQ0_IRQSTAT_icapirq_SHIFT 7 - -/* IRQ0 :: IRQSTAT :: gioirq [06:06] */ -#define BCHP_IRQ0_IRQSTAT_gioirq_MASK 0x00000040 -#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT 6 - -/* IRQ0 :: IRQSTAT :: reserved5 [05:05] */ -#define BCHP_IRQ0_IRQSTAT_reserved5_MASK 0x00000020 -#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT 5 - -/* IRQ0 :: IRQSTAT :: uairq [04:04] */ -#define BCHP_IRQ0_IRQSTAT_uairq_MASK 0x00000010 -#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT 4 - -/* IRQ0 :: IRQSTAT :: ubirq [03:03] */ -#define BCHP_IRQ0_IRQSTAT_ubirq_MASK 0x00000008 -#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT 3 - -/* IRQ0 :: IRQSTAT :: reserved6 [02:02] */ -#define BCHP_IRQ0_IRQSTAT_reserved6_MASK 0x00000004 -#define BCHP_IRQ0_IRQSTAT_reserved6_SHIFT 2 - -/* IRQ0 :: IRQSTAT :: ldkirq [01:01] */ -#define BCHP_IRQ0_IRQSTAT_ldkirq_MASK 0x00000002 -#define BCHP_IRQ0_IRQSTAT_ldkirq_SHIFT 1 - -/* IRQ0 :: IRQSTAT :: kbd1irq [00:00] */ -#define BCHP_IRQ0_IRQSTAT_kbd1irq_MASK 0x00000001 -#define BCHP_IRQ0_IRQSTAT_kbd1irq_SHIFT 0 - -#endif /* #ifndef BCHP_IRQ0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq1.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq1.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq1.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq1.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_irq1.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:10p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:34 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_irq1.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:10p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_IRQ1_H__ -#define BCHP_IRQ1_H__ - -/*************************************************************************** - *IRQ1 - Level 2 PCI Interrupt Enable/Status - ***************************************************************************/ -#define BCHP_IRQ1_IRQEN 0x00406788 /* Interrupt Enable */ -#define BCHP_IRQ1_IRQSTAT 0x0040678c /* Interrupt Status */ - -#endif /* #ifndef BCHP_IRQ1_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,378 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_l1_intr.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:10p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:52 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:10p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_L1_INTR_H__ -#define BCHP_L1_INTR_H__ - -/*************************************************************************** - *L1_INTR - TGT L1 Interrupt Controller Registers (feeds into L2 above) - ***************************************************************************/ -#define BCHP_L1_INTR_INTR_W0_STATUS 0x00500740 /* Interrupt Status Register */ -#define BCHP_L1_INTR_INTR_W1_STATUS 0x00500744 /* Interrupt Status Register */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS 0x00500748 /* Interrupt Mask Status Register */ -#define BCHP_L1_INTR_INTR_W1_MASK_STATUS 0x0050074c /* Interrupt Mask Status Register */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET 0x00500750 /* Interrupt Mask Set Register */ -#define BCHP_L1_INTR_INTR_W1_MASK_SET 0x00500754 /* Interrupt Mask Set Register */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR 0x00500758 /* Interrupt Mask Clear Register */ -#define BCHP_L1_INTR_INTR_W1_MASK_CLEAR 0x0050075c /* Interrupt Mask Clear Register */ - -/*************************************************************************** - *INTR_W0_STATUS - Interrupt Status Register - ***************************************************************************/ -/* L1_INTR :: INTR_W0_STATUS :: reserved0 [31:16] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_reserved0_MASK 0xffff0000 -#define BCHP_L1_INTR_INTR_W0_STATUS_reserved0_SHIFT 16 - -/* L1_INTR :: INTR_W0_STATUS :: BVN_INTR [15:15] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_BVN_INTR_MASK 0x00008000 -#define BCHP_L1_INTR_INTR_W0_STATUS_BVN_INTR_SHIFT 15 - -/* L1_INTR :: INTR_W0_STATUS :: BLINK_INTR [14:14] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_BLINK_INTR_MASK 0x00004000 -#define BCHP_L1_INTR_INTR_W0_STATUS_BLINK_INTR_SHIFT 14 - -/* L1_INTR :: INTR_W0_STATUS :: SECURE_INTR [13:13] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_SECURE_INTR_MASK 0x00002000 -#define BCHP_L1_INTR_INTR_W0_STATUS_SECURE_INTR_SHIFT 13 - -/* L1_INTR :: INTR_W0_STATUS :: ARB_RTS_INTR [12:12] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_RTS_INTR_MASK 0x00001000 -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_RTS_INTR_SHIFT 12 - -/* L1_INTR :: INTR_W0_STATUS :: ARB_CRIT_INTR [11:11] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_CRIT_INTR_MASK 0x00000800 -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_CRIT_INTR_SHIFT 11 - -/* L1_INTR :: INTR_W0_STATUS :: ARB_ARCH_INTR [10:10] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_ARCH_INTR_MASK 0x00000400 -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_ARCH_INTR_SHIFT 10 - -/* L1_INTR :: INTR_W0_STATUS :: ARB_MEM_INTR [09:09] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_MEM_INTR_MASK 0x00000200 -#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_MEM_INTR_SHIFT 9 - -/* L1_INTR :: INTR_W0_STATUS :: UPG_MAIN_INTR [08:08] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_MAIN_INTR_MASK 0x00000100 -#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_MAIN_INTR_SHIFT 8 - -/* L1_INTR :: INTR_W0_STATUS :: UPG_TMR_INTR [07:07] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_TMR_INTR_MASK 0x00000080 -#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_TMR_INTR_SHIFT 7 - -/* L1_INTR :: INTR_W0_STATUS :: SUN_INTR [06:06] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_SUN_INTR_MASK 0x00000040 -#define BCHP_L1_INTR_INTR_W0_STATUS_SUN_INTR_SHIFT 6 - -/* L1_INTR :: INTR_W0_STATUS :: AVD_INTR [05:05] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_AVD_INTR_MASK 0x00000020 -#define BCHP_L1_INTR_INTR_W0_STATUS_AVD_INTR_SHIFT 5 - -/* L1_INTR :: INTR_W0_STATUS :: XPT_STATUS_INTR [04:04] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_STATUS_INTR_MASK 0x00000010 -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_STATUS_INTR_SHIFT 4 - -/* L1_INTR :: INTR_W0_STATUS :: XPT_PCR_INTR [03:03] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_PCR_INTR_MASK 0x00000008 -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_PCR_INTR_SHIFT 3 - -/* L1_INTR :: INTR_W0_STATUS :: XPT_FE_INTR [02:02] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_FE_INTR_MASK 0x00000004 -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_FE_INTR_SHIFT 2 - -/* L1_INTR :: INTR_W0_STATUS :: XPT_RAV_INTR [01:01] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_RAV_INTR_MASK 0x00000002 -#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_RAV_INTR_SHIFT 1 - -/* L1_INTR :: INTR_W0_STATUS :: WRAP_MISC_INTR [00:00] */ -#define BCHP_L1_INTR_INTR_W0_STATUS_WRAP_MISC_INTR_MASK 0x00000001 -#define BCHP_L1_INTR_INTR_W0_STATUS_WRAP_MISC_INTR_SHIFT 0 - -/*************************************************************************** - *INTR_W1_STATUS - Interrupt Status Register - ***************************************************************************/ -/* L1_INTR :: INTR_W1_STATUS :: reserved0 [31:00] */ -#define BCHP_L1_INTR_INTR_W1_STATUS_reserved0_MASK 0xffffffff -#define BCHP_L1_INTR_INTR_W1_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *INTR_W0_MASK_STATUS - Interrupt Mask Status Register - ***************************************************************************/ -/* L1_INTR :: INTR_W0_MASK_STATUS :: reserved0 [31:16] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_reserved0_MASK 0xffff0000 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_reserved0_SHIFT 16 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: BVN_MASK [15:15] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BVN_MASK_MASK 0x00008000 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BVN_MASK_SHIFT 15 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: BLINK_MASK [14:14] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BLINK_MASK_MASK 0x00004000 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BLINK_MASK_SHIFT 14 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: SECURE_MASK [13:13] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SECURE_MASK_MASK 0x00002000 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SECURE_MASK_SHIFT 13 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_RTS_MASK [12:12] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_RTS_MASK_MASK 0x00001000 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_RTS_MASK_SHIFT 12 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_CRIT_MASK [11:11] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_CRIT_MASK_MASK 0x00000800 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_CRIT_MASK_SHIFT 11 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_ARCH_MASK [10:10] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_ARCH_MASK_MASK 0x00000400 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_ARCH_MASK_SHIFT 10 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_MEM_MASK [09:09] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_MEM_MASK_MASK 0x00000200 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_MEM_MASK_SHIFT 9 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: UPG_MAIN_MASK [08:08] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_MAIN_MASK_MASK 0x00000100 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_MAIN_MASK_SHIFT 8 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: UPG_TMR_MASK [07:07] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_TMR_MASK_MASK 0x00000080 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_TMR_MASK_SHIFT 7 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: SUN_MASK [06:06] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SUN_MASK_MASK 0x00000040 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SUN_MASK_SHIFT 6 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: AVD_MASK [05:05] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_AVD_MASK_MASK 0x00000020 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_AVD_MASK_SHIFT 5 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_STATUS_MASK [04:04] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_STATUS_MASK_MASK 0x00000010 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_STATUS_MASK_SHIFT 4 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_PCR_MASK [03:03] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_PCR_MASK_MASK 0x00000008 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_PCR_MASK_SHIFT 3 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_FE_MASK [02:02] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_FE_MASK_MASK 0x00000004 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_FE_MASK_SHIFT 2 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_RAV_MASK [01:01] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_RAV_MASK_MASK 0x00000002 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_RAV_MASK_SHIFT 1 - -/* L1_INTR :: INTR_W0_MASK_STATUS :: WRAP_MISC_MASK [00:00] */ -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_WRAP_MISC_MASK_MASK 0x00000001 -#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_WRAP_MISC_MASK_SHIFT 0 - -/*************************************************************************** - *INTR_W1_MASK_STATUS - Interrupt Mask Status Register - ***************************************************************************/ -/* L1_INTR :: INTR_W1_MASK_STATUS :: reserved0 [31:00] */ -#define BCHP_L1_INTR_INTR_W1_MASK_STATUS_reserved0_MASK 0xffffffff -#define BCHP_L1_INTR_INTR_W1_MASK_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *INTR_W0_MASK_SET - Interrupt Mask Set Register - ***************************************************************************/ -/* L1_INTR :: INTR_W0_MASK_SET :: reserved0 [31:16] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_reserved0_MASK 0xffff0000 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_reserved0_SHIFT 16 - -/* L1_INTR :: INTR_W0_MASK_SET :: BVN_MASK [15:15] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_BVN_MASK_MASK 0x00008000 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_BVN_MASK_SHIFT 15 - -/* L1_INTR :: INTR_W0_MASK_SET :: BLINK_MASK [14:14] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_BLINK_MASK_MASK 0x00004000 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_BLINK_MASK_SHIFT 14 - -/* L1_INTR :: INTR_W0_MASK_SET :: SECURE_MASK [13:13] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_SECURE_MASK_MASK 0x00002000 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_SECURE_MASK_SHIFT 13 - -/* L1_INTR :: INTR_W0_MASK_SET :: ARB_RTS_MASK [12:12] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_RTS_MASK_MASK 0x00001000 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_RTS_MASK_SHIFT 12 - -/* L1_INTR :: INTR_W0_MASK_SET :: ARB_CRIT_MASK [11:11] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_CRIT_MASK_MASK 0x00000800 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_CRIT_MASK_SHIFT 11 - -/* L1_INTR :: INTR_W0_MASK_SET :: ARB_ARCH_MASK [10:10] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_ARCH_MASK_MASK 0x00000400 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_ARCH_MASK_SHIFT 10 - -/* L1_INTR :: INTR_W0_MASK_SET :: ARB_MEM_MASK [09:09] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_MEM_MASK_MASK 0x00000200 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_MEM_MASK_SHIFT 9 - -/* L1_INTR :: INTR_W0_MASK_SET :: UPG_MAIN_MASK [08:08] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_MAIN_MASK_MASK 0x00000100 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_MAIN_MASK_SHIFT 8 - -/* L1_INTR :: INTR_W0_MASK_SET :: UPG_TMR_MASK [07:07] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_TMR_MASK_MASK 0x00000080 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_TMR_MASK_SHIFT 7 - -/* L1_INTR :: INTR_W0_MASK_SET :: SUN_MASK [06:06] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_SUN_MASK_MASK 0x00000040 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_SUN_MASK_SHIFT 6 - -/* L1_INTR :: INTR_W0_MASK_SET :: AVD_MASK [05:05] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_AVD_MASK_MASK 0x00000020 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_AVD_MASK_SHIFT 5 - -/* L1_INTR :: INTR_W0_MASK_SET :: XPT_STATUS_MASK [04:04] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_STATUS_MASK_MASK 0x00000010 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_STATUS_MASK_SHIFT 4 - -/* L1_INTR :: INTR_W0_MASK_SET :: XPT_PCR_MASK [03:03] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_PCR_MASK_MASK 0x00000008 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_PCR_MASK_SHIFT 3 - -/* L1_INTR :: INTR_W0_MASK_SET :: XPT_FE_MASK [02:02] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_FE_MASK_MASK 0x00000004 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_FE_MASK_SHIFT 2 - -/* L1_INTR :: INTR_W0_MASK_SET :: XPT_RAV_MASK [01:01] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_RAV_MASK_MASK 0x00000002 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_RAV_MASK_SHIFT 1 - -/* L1_INTR :: INTR_W0_MASK_SET :: WRAP_MISC_MASK [00:00] */ -#define BCHP_L1_INTR_INTR_W0_MASK_SET_WRAP_MISC_MASK_MASK 0x00000001 -#define BCHP_L1_INTR_INTR_W0_MASK_SET_WRAP_MISC_MASK_SHIFT 0 - -/*************************************************************************** - *INTR_W1_MASK_SET - Interrupt Mask Set Register - ***************************************************************************/ -/* L1_INTR :: INTR_W1_MASK_SET :: reserved0 [31:00] */ -#define BCHP_L1_INTR_INTR_W1_MASK_SET_reserved0_MASK 0xffffffff -#define BCHP_L1_INTR_INTR_W1_MASK_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register - ***************************************************************************/ -/* L1_INTR :: INTR_W0_MASK_CLEAR :: reserved0 [31:16] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_reserved0_MASK 0xffff0000 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_reserved0_SHIFT 16 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: BVN_MASK [15:15] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BVN_MASK_MASK 0x00008000 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BVN_MASK_SHIFT 15 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: BLINK_MASK [14:14] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BLINK_MASK_MASK 0x00004000 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BLINK_MASK_SHIFT 14 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: SECURE_MASK [13:13] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SECURE_MASK_MASK 0x00002000 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SECURE_MASK_SHIFT 13 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_RTS_MASK [12:12] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_RTS_MASK_MASK 0x00001000 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_RTS_MASK_SHIFT 12 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_CRIT_MASK [11:11] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_CRIT_MASK_MASK 0x00000800 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_CRIT_MASK_SHIFT 11 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_ARCH_MASK [10:10] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_ARCH_MASK_MASK 0x00000400 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_ARCH_MASK_SHIFT 10 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_MEM_MASK [09:09] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_MEM_MASK_MASK 0x00000200 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_MEM_MASK_SHIFT 9 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: UPG_MAIN_MASK [08:08] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_MAIN_MASK_MASK 0x00000100 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_MAIN_MASK_SHIFT 8 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: UPG_TMR_MASK [07:07] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_TMR_MASK_MASK 0x00000080 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_TMR_MASK_SHIFT 7 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: SUN_MASK [06:06] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SUN_MASK_MASK 0x00000040 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SUN_MASK_SHIFT 6 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: AVD_MASK [05:05] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_AVD_MASK_MASK 0x00000020 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_AVD_MASK_SHIFT 5 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_STATUS_MASK [04:04] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_STATUS_MASK_MASK 0x00000010 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_STATUS_MASK_SHIFT 4 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_PCR_MASK [03:03] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_PCR_MASK_MASK 0x00000008 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_PCR_MASK_SHIFT 3 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_FE_MASK [02:02] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_FE_MASK_MASK 0x00000004 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_FE_MASK_SHIFT 2 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_RAV_MASK [01:01] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_RAV_MASK_MASK 0x00000002 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_RAV_MASK_SHIFT 1 - -/* L1_INTR :: INTR_W0_MASK_CLEAR :: WRAP_MISC_MASK [00:00] */ -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_WRAP_MISC_MASK_MASK 0x00000001 -#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_WRAP_MISC_MASK_SHIFT 0 - -/*************************************************************************** - *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register - ***************************************************************************/ -/* L1_INTR :: INTR_W1_MASK_CLEAR :: reserved0 [31:00] */ -#define BCHP_L1_INTR_INTR_W1_MASK_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_L1_INTR_INTR_W1_MASK_CLEAR_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_L1_INTR_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mdio.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mdio.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mdio.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mdio.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,114 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_mdio.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:10p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:08 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mdio.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:10p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MDIO_H__ -#define BCHP_MDIO_H__ - -/*************************************************************************** - *MDIO - PCIE MDIO Registers - ***************************************************************************/ -#define BCHP_MDIO_CTRL0 0x00500760 /* PCIE Serdes MDIO Control Register 0 */ -#define BCHP_MDIO_CTRL1 0x00500764 /* PCIE Serdes MDIO Control Register 1 */ -#define BCHP_MDIO_CTRL2 0x00500768 /* PCIE Serdes MDIO Control Register 2 */ - -/*************************************************************************** - *CTRL0 - PCIE Serdes MDIO Control Register 0 - ***************************************************************************/ -/* MDIO :: CTRL0 :: reserved0 [31:22] */ -#define BCHP_MDIO_CTRL0_reserved0_MASK 0xffc00000 -#define BCHP_MDIO_CTRL0_reserved0_SHIFT 22 - -/* MDIO :: CTRL0 :: WRITE_READ_COMMAND [21:21] */ -#define BCHP_MDIO_CTRL0_WRITE_READ_COMMAND_MASK 0x00200000 -#define BCHP_MDIO_CTRL0_WRITE_READ_COMMAND_SHIFT 21 - -/* MDIO :: CTRL0 :: PHYAD [20:16] */ -#define BCHP_MDIO_CTRL0_PHYAD_MASK 0x001f0000 -#define BCHP_MDIO_CTRL0_PHYAD_SHIFT 16 - -/* MDIO :: CTRL0 :: reserved1 [15:05] */ -#define BCHP_MDIO_CTRL0_reserved1_MASK 0x0000ffe0 -#define BCHP_MDIO_CTRL0_reserved1_SHIFT 5 - -/* MDIO :: CTRL0 :: REGAD [04:00] */ -#define BCHP_MDIO_CTRL0_REGAD_MASK 0x0000001f -#define BCHP_MDIO_CTRL0_REGAD_SHIFT 0 - -/*************************************************************************** - *CTRL1 - PCIE Serdes MDIO Control Register 1 - ***************************************************************************/ -/* MDIO :: CTRL1 :: WR_STATUS [31:31] */ -#define BCHP_MDIO_CTRL1_WR_STATUS_MASK 0x80000000 -#define BCHP_MDIO_CTRL1_WR_STATUS_SHIFT 31 - -/* MDIO :: CTRL1 :: reserved0 [30:16] */ -#define BCHP_MDIO_CTRL1_reserved0_MASK 0x7fff0000 -#define BCHP_MDIO_CTRL1_reserved0_SHIFT 16 - -/* MDIO :: CTRL1 :: Write_Data [15:00] */ -#define BCHP_MDIO_CTRL1_Write_Data_MASK 0x0000ffff -#define BCHP_MDIO_CTRL1_Write_Data_SHIFT 0 - -/*************************************************************************** - *CTRL2 - PCIE Serdes MDIO Control Register 2 - ***************************************************************************/ -/* MDIO :: CTRL2 :: RD_STATUS [31:31] */ -#define BCHP_MDIO_CTRL2_RD_STATUS_MASK 0x80000000 -#define BCHP_MDIO_CTRL2_RD_STATUS_SHIFT 31 - -/* MDIO :: CTRL2 :: reserved0 [30:16] */ -#define BCHP_MDIO_CTRL2_reserved0_MASK 0x7fff0000 -#define BCHP_MDIO_CTRL2_reserved0_SHIFT 16 - -/* MDIO :: CTRL2 :: Read_Data [15:00] */ -#define BCHP_MDIO_CTRL2_Read_Data_MASK 0x0000ffff -#define BCHP_MDIO_CTRL2_Read_Data_SHIFT 0 - -#endif /* #ifndef BCHP_MDIO_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,154 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_mem_dma.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:10p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:25 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:10p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MEM_DMA_H__ -#define BCHP_MEM_DMA_H__ - -/*************************************************************************** - *MEM_DMA - MEM_DMA Registers - ***************************************************************************/ -#define BCHP_MEM_DMA_REVISION 0x000f5000 /* MEM_DMA REVISION */ -#define BCHP_MEM_DMA_FIRST_DESC 0x000f5004 /* MEM_DMA First Descriptor Address Register */ -#define BCHP_MEM_DMA_CTRL 0x000f5008 /* MEM_DMA Control Register */ -#define BCHP_MEM_DMA_WAKE_CTRL 0x000f500c /* MEM_DMA Wake Control Register */ -#define BCHP_MEM_DMA_STATUS 0x000f5014 /* MEM_DMA Status Register */ -#define BCHP_MEM_DMA_CUR_DESC 0x000f5018 /* MEM_DMA Current Descriptor Address Register */ -#define BCHP_MEM_DMA_CUR_BYTE 0x000f501c /* MEM_DMA Current Byte Count Register */ -#define BCHP_MEM_DMA_SCRATCH 0x000f5024 /* MEM_DMA Scratch Register */ - -/*************************************************************************** - *REVISION - MEM_DMA REVISION - ***************************************************************************/ -/* MEM_DMA :: REVISION :: reserved0 [31:16] */ -#define BCHP_MEM_DMA_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_MEM_DMA_REVISION_reserved0_SHIFT 16 - -/* MEM_DMA :: REVISION :: MAJOR [15:08] */ -#define BCHP_MEM_DMA_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_MEM_DMA_REVISION_MAJOR_SHIFT 8 - -/* MEM_DMA :: REVISION :: MINOR [07:00] */ -#define BCHP_MEM_DMA_REVISION_MINOR_MASK 0x000000ff -#define BCHP_MEM_DMA_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *FIRST_DESC - MEM_DMA First Descriptor Address Register - ***************************************************************************/ -/* MEM_DMA :: FIRST_DESC :: ADDR [31:00] */ -#define BCHP_MEM_DMA_FIRST_DESC_ADDR_MASK 0xffffffff -#define BCHP_MEM_DMA_FIRST_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *CTRL - MEM_DMA Control Register - ***************************************************************************/ -/* MEM_DMA :: CTRL :: reserved0 [31:01] */ -#define BCHP_MEM_DMA_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_MEM_DMA_CTRL_reserved0_SHIFT 1 - -/* MEM_DMA :: CTRL :: RUN [00:00] */ -#define BCHP_MEM_DMA_CTRL_RUN_MASK 0x00000001 -#define BCHP_MEM_DMA_CTRL_RUN_SHIFT 0 - -/*************************************************************************** - *WAKE_CTRL - MEM_DMA Wake Control Register - ***************************************************************************/ -/* MEM_DMA :: WAKE_CTRL :: reserved0 [31:02] */ -#define BCHP_MEM_DMA_WAKE_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_MEM_DMA_WAKE_CTRL_reserved0_SHIFT 2 - -/* MEM_DMA :: WAKE_CTRL :: WAKE_MODE [01:01] */ -#define BCHP_MEM_DMA_WAKE_CTRL_WAKE_MODE_MASK 0x00000002 -#define BCHP_MEM_DMA_WAKE_CTRL_WAKE_MODE_SHIFT 1 - -/* MEM_DMA :: WAKE_CTRL :: WAKE [00:00] */ -#define BCHP_MEM_DMA_WAKE_CTRL_WAKE_MASK 0x00000001 -#define BCHP_MEM_DMA_WAKE_CTRL_WAKE_SHIFT 0 - -/*************************************************************************** - *STATUS - MEM_DMA Status Register - ***************************************************************************/ -/* MEM_DMA :: STATUS :: reserved0 [31:02] */ -#define BCHP_MEM_DMA_STATUS_reserved0_MASK 0xfffffffc -#define BCHP_MEM_DMA_STATUS_reserved0_SHIFT 2 - -/* MEM_DMA :: STATUS :: DMA_STATUS [01:00] */ -#define BCHP_MEM_DMA_STATUS_DMA_STATUS_MASK 0x00000003 -#define BCHP_MEM_DMA_STATUS_DMA_STATUS_SHIFT 0 -#define BCHP_MEM_DMA_STATUS_DMA_STATUS_Idle 0 -#define BCHP_MEM_DMA_STATUS_DMA_STATUS_Busy 1 -#define BCHP_MEM_DMA_STATUS_DMA_STATUS_Sleep 2 -#define BCHP_MEM_DMA_STATUS_DMA_STATUS_Reserved 3 - -/*************************************************************************** - *CUR_DESC - MEM_DMA Current Descriptor Address Register - ***************************************************************************/ -/* MEM_DMA :: CUR_DESC :: ADDR [31:00] */ -#define BCHP_MEM_DMA_CUR_DESC_ADDR_MASK 0xffffffff -#define BCHP_MEM_DMA_CUR_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *CUR_BYTE - MEM_DMA Current Byte Count Register - ***************************************************************************/ -/* MEM_DMA :: CUR_BYTE :: reserved0 [31:25] */ -#define BCHP_MEM_DMA_CUR_BYTE_reserved0_MASK 0xfe000000 -#define BCHP_MEM_DMA_CUR_BYTE_reserved0_SHIFT 25 - -/* MEM_DMA :: CUR_BYTE :: COUNT [24:00] */ -#define BCHP_MEM_DMA_CUR_BYTE_COUNT_MASK 0x01ffffff -#define BCHP_MEM_DMA_CUR_BYTE_COUNT_SHIFT 0 - -/*************************************************************************** - *SCRATCH - MEM_DMA Scratch Register - ***************************************************************************/ -/* MEM_DMA :: SCRATCH :: SCRATCH_BIT [31:00] */ -#define BCHP_MEM_DMA_SCRATCH_SCRATCH_BIT_MASK 0xffffffff -#define BCHP_MEM_DMA_SCRATCH_SCRATCH_BIT_SHIFT 0 - -#endif /* #ifndef BCHP_MEM_DMA_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma_secure.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma_secure.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma_secure.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma_secure.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_mem_dma_secure.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:10p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:56 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma_secure.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:10p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MEM_DMA_SECURE_H__ -#define BCHP_MEM_DMA_SECURE_H__ - -/*************************************************************************** - *MEM_DMA_SECURE - MEM_DMA Secure Registers - ***************************************************************************/ -#define BCHP_MEM_DMA_SECURE_RSV_S 0x000fc000 /* RESERVED */ -#define BCHP_MEM_DMA_SECURE_RSV_E 0x000fc00c /* RESERVED */ - -/*************************************************************************** - *RSV_S - RESERVED - ***************************************************************************/ -/* MEM_DMA_SECURE :: RSV_S :: reserved0 [31:00] */ -#define BCHP_MEM_DMA_SECURE_RSV_S_reserved0_MASK 0xffffffff -#define BCHP_MEM_DMA_SECURE_RSV_S_reserved0_SHIFT 0 - -/*************************************************************************** - *RSV_E - RESERVED - ***************************************************************************/ -/* MEM_DMA_SECURE :: RSV_E :: reserved0 [31:00] */ -#define BCHP_MEM_DMA_SECURE_RSV_E_reserved0_MASK 0xffffffff -#define BCHP_MEM_DMA_SECURE_RSV_E_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_MEM_DMA_SECURE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mfd.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mfd.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mfd.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mfd.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1001 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_mfd.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:11p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:31 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mfd.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:11p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MFD_H__ -#define BCHP_MFD_H__ - -/*************************************************************************** - *MFD - MPEG Feeder Registers - ***************************************************************************/ -#define BCHP_MFD_REVISION_ID 0x00540000 /* MPEG/Video Feeder Revision Register */ -#define BCHP_MFD_FEEDER_CNTL 0x00540004 /* MPEG/Video Feeder Control Register */ -#define BCHP_MFD_FIXED_COLOUR 0x00540008 /* MPEG/Video Feeder Fixed Colour Value Register */ -#define BCHP_MFD_LAC_CNTL 0x0054000c /* MPEG/Video Feeder LAC Control Register */ -#define BCHP_MFD_STRIDE 0x00540010 /* MPEG/Video Feeder Stride Register */ -#define BCHP_MFD_DISP_HSIZE 0x00540014 /* MPEG/Video Feeder Horizontal Display Size Register */ -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW 0x00540018 /* MPEG/Video Feeder Display Vertical Window Register */ -#define BCHP_MFD_PICTURE0_LINE_ADDR_0 0x0054001c /* MPEG/Video Feeder Line Address0 Register */ -#define BCHP_MFD_PICTURE0_LINE_ADDR_1 0x00540020 /* MPEG/Video Feeder Line Address1 Register */ -#define BCHP_MFD_CHROMA_SAMPLING_CNTL 0x00540024 /* MPEG Feeder Chroma Sampling Control Register */ -#define BCHP_MFD_LUMA_NMBY 0x00540028 /* MPEG Feeder Luma NMBY Size Register */ -#define BCHP_MFD_CHROMA_NMBY 0x0054002c /* MPEG Feeder Chroma NMBY Size Register */ -#define BCHP_MFD_PIC_FEED_CMD 0x00540030 /* MPEG/Video Feeder Picture Feed Command Register */ -#define BCHP_MFD_CRC_CTRL 0x00540034 /* MPEG/Video Feeder CRC Control Register */ -#define BCHP_MFD_CRC_SEED 0x00540038 /* MPEG/Video Feeder CRC Seed Register */ -#define BCHP_MFD_LUMA_CRC 0x0054003c /* MPEG/Video Feeder Luma CRC Register */ -#define BCHP_MFD_CHROMA_CRC 0x00540040 /* MPEG/Video Feeder Chroma CRC Register */ -#define BCHP_MFD_DATA_MODE 0x00540044 /* MPEG/Video Feeder Data Mode Register */ -#define BCHP_MFD_PIC_OFFSET 0x00540048 /* MPEG/Video Feeder Picture Offset Register */ -#define BCHP_MFD_RANGE_EXP_REMAP_CNTL 0x0054004c /* MPEG/Video Feeder Range Expansion / Remapping Control Register */ -#define BCHP_MFD_FEED_STATUS 0x00540050 /* MPEG/Video Feeder Feed Status Register */ -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0 0x00540054 /* MPEG/Video Feeder Line Address Computer Line Address0 Register */ -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1 0x00540058 /* MPEG/Video Feeder Line Address Computer Line Address1 Register */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG 0x0054005c /* MPEG/Video Feeder Line Address Computer Chroma Vertical Filter Configuration Register */ -#define BCHP_MFD_LAC_LINE_FEED_CNTL 0x00540060 /* MPEG/Video Feeder Line Address Computer Line Feed Control Register */ -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL 0x00540064 /* MPEG/Video Feeder Timeout and Repeat Picture Control Register */ -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL 0x00540068 /* MPEG/Video Feeder BVB Receiver Stall Timeout Control Register */ -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS 0x0054006c /* MPEG/Video Feeder Error Interrupt Status Register */ -#define BCHP_MFD_FEEDER_BVB_STATUS 0x00540070 /* MPEG/Video Feeder BVB Status Register */ -#define BCHP_MFD_TEST_MODE_CNTL 0x00540074 /* MPEG/Video Feeder Test Mode Control Register */ -#define BCHP_MFD_BVB_SAMPLE_DATA 0x00540078 /* MPEG/Video Feeder BVB Output Sample Data Register */ -#define BCHP_MFD_TEST_PORT_CNTL 0x0054007c /* MPEG/Video Feeder Test port Control Register */ -#define BCHP_MFD_TEST_PORT_DATA 0x00540080 /* MPEG/Video Feeder Test port Data Register */ -#define BCHP_MFD_SCRATCH_REGISTER_0 0x005400f8 /* MPEG/Video Feeder Scratch 0 Register */ -#define BCHP_MFD_SCRATCH_REGISTER_1 0x005400fc /* MPEG/Video Feeder Scratch 1 Register */ - -/*************************************************************************** - *REVISION_ID - MPEG/Video Feeder Revision Register - ***************************************************************************/ -/* MFD :: REVISION_ID :: reserved0 [31:16] */ -#define BCHP_MFD_REVISION_ID_reserved0_MASK 0xffff0000 -#define BCHP_MFD_REVISION_ID_reserved0_SHIFT 16 - -/* MFD :: REVISION_ID :: MAJOR [15:08] */ -#define BCHP_MFD_REVISION_ID_MAJOR_MASK 0x0000ff00 -#define BCHP_MFD_REVISION_ID_MAJOR_SHIFT 8 - -/* MFD :: REVISION_ID :: MINOR [07:00] */ -#define BCHP_MFD_REVISION_ID_MINOR_MASK 0x000000ff -#define BCHP_MFD_REVISION_ID_MINOR_SHIFT 0 - -/*************************************************************************** - *FEEDER_CNTL - MPEG/Video Feeder Control Register - ***************************************************************************/ -/* MFD :: FEEDER_CNTL :: reserved0 [31:04] */ -#define BCHP_MFD_FEEDER_CNTL_reserved0_MASK 0xfffffff0 -#define BCHP_MFD_FEEDER_CNTL_reserved0_SHIFT 4 - -/* MFD :: FEEDER_CNTL :: FIXED_COLOUR_ENABLE [03:03] */ -#define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_MASK 0x00000008 -#define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_SHIFT 3 -#define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_OFF 0 -#define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_ON 1 - -/* MFD :: FEEDER_CNTL :: PACKING_TYPE [02:01] */ -#define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_MASK 0x00000006 -#define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_SHIFT 1 -#define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_U0_Y0_V0_Y1 0 -#define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_V0_Y0_U0_Y1 1 -#define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_Y0_U0_Y1_V0 2 -#define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_Y0_V0_Y1_U0 3 - -/* MFD :: FEEDER_CNTL :: IMAGE_FORMAT [00:00] */ -#define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_MASK 0x00000001 -#define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_SHIFT 0 -#define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_AVC_MPEG 0 -#define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_PACKED 1 - -/*************************************************************************** - *FIXED_COLOUR - MPEG/Video Feeder Fixed Colour Value Register - ***************************************************************************/ -/* MFD :: FIXED_COLOUR :: reserved0 [31:24] */ -#define BCHP_MFD_FIXED_COLOUR_reserved0_MASK 0xff000000 -#define BCHP_MFD_FIXED_COLOUR_reserved0_SHIFT 24 - -/* MFD :: FIXED_COLOUR :: LUMA [23:16] */ -#define BCHP_MFD_FIXED_COLOUR_LUMA_MASK 0x00ff0000 -#define BCHP_MFD_FIXED_COLOUR_LUMA_SHIFT 16 - -/* MFD :: FIXED_COLOUR :: CB [15:08] */ -#define BCHP_MFD_FIXED_COLOUR_CB_MASK 0x0000ff00 -#define BCHP_MFD_FIXED_COLOUR_CB_SHIFT 8 - -/* MFD :: FIXED_COLOUR :: CR [07:00] */ -#define BCHP_MFD_FIXED_COLOUR_CR_MASK 0x000000ff -#define BCHP_MFD_FIXED_COLOUR_CR_SHIFT 0 - -/*************************************************************************** - *LAC_CNTL - MPEG/Video Feeder LAC Control Register - ***************************************************************************/ -/* MFD :: LAC_CNTL :: reserved0 [31:11] */ -#define BCHP_MFD_LAC_CNTL_reserved0_MASK 0xfffff800 -#define BCHP_MFD_LAC_CNTL_reserved0_SHIFT 11 - -/* MFD :: LAC_CNTL :: STRIPE_WIDTH_SEL [10:10] */ -#define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_MASK 0x00000400 -#define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_SHIFT 10 -#define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_BYTES_64 0 -#define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_BYTES_128 1 - -/* MFD :: LAC_CNTL :: SKIP_LINE_SIZE [09:06] */ -#define BCHP_MFD_LAC_CNTL_SKIP_LINE_SIZE_MASK 0x000003c0 -#define BCHP_MFD_LAC_CNTL_SKIP_LINE_SIZE_SHIFT 6 - -/* MFD :: LAC_CNTL :: reserved1 [05:05] */ -#define BCHP_MFD_LAC_CNTL_reserved1_MASK 0x00000020 -#define BCHP_MFD_LAC_CNTL_reserved1_SHIFT 5 - -/* MFD :: LAC_CNTL :: CHROMA_VERT_POSITION [04:04] */ -#define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_MASK 0x00000010 -#define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_SHIFT 4 -#define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_COLOCATED_WITH_LUMA 0 -#define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_HALF_PIXEL_GRID_BETWEEN_LUMA 1 - -/* MFD :: LAC_CNTL :: CHROMA_INTERPOLATION [03:03] */ -#define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_MASK 0x00000008 -#define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_SHIFT 3 -#define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_FIELD 0 -#define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_FRAME 1 - -/* MFD :: LAC_CNTL :: OUTPUT_FIELD_POLARITY [02:02] */ -#define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_MASK 0x00000004 -#define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_SHIFT 2 -#define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_TOP 0 -#define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_BOTTOM 1 - -/* MFD :: LAC_CNTL :: OUTPUT_TYPE [01:01] */ -#define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_MASK 0x00000002 -#define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_SHIFT 1 -#define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_INTERLACED 0 -#define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_PROGRESSIVE 1 - -/* MFD :: LAC_CNTL :: CHROMA_TYPE [00:00] */ -#define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_MASK 0x00000001 -#define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_SHIFT 0 -#define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_CHROMA_420 0 -#define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_CHROMA_422 1 - -/*************************************************************************** - *STRIDE - MPEG/Video Feeder Stride Register - ***************************************************************************/ -/* union - case AVC_MPEG [31:00] */ -/* MFD :: STRIDE :: AVC_MPEG :: CHROMA_LINE_STRIDE [31:16] */ -#define BCHP_MFD_STRIDE_AVC_MPEG_CHROMA_LINE_STRIDE_MASK 0xffff0000 -#define BCHP_MFD_STRIDE_AVC_MPEG_CHROMA_LINE_STRIDE_SHIFT 16 - -/* MFD :: STRIDE :: AVC_MPEG :: LUMA_LINE_STRIDE [15:00] */ -#define BCHP_MFD_STRIDE_AVC_MPEG_LUMA_LINE_STRIDE_MASK 0x0000ffff -#define BCHP_MFD_STRIDE_AVC_MPEG_LUMA_LINE_STRIDE_SHIFT 0 - -/* union - case PACKED [31:00] */ -/* MFD :: STRIDE :: PACKED :: reserved0 [31:16] */ -#define BCHP_MFD_STRIDE_PACKED_reserved0_MASK 0xffff0000 -#define BCHP_MFD_STRIDE_PACKED_reserved0_SHIFT 16 - -/* MFD :: STRIDE :: PACKED :: LINE_STRIDE [15:00] */ -#define BCHP_MFD_STRIDE_PACKED_LINE_STRIDE_MASK 0x0000ffff -#define BCHP_MFD_STRIDE_PACKED_LINE_STRIDE_SHIFT 0 - -/*************************************************************************** - *DISP_HSIZE - MPEG/Video Feeder Horizontal Display Size Register - ***************************************************************************/ -/* MFD :: DISP_HSIZE :: reserved0 [31:13] */ -#define BCHP_MFD_DISP_HSIZE_reserved0_MASK 0xffffe000 -#define BCHP_MFD_DISP_HSIZE_reserved0_SHIFT 13 - -/* MFD :: DISP_HSIZE :: VALUE [12:00] */ -#define BCHP_MFD_DISP_HSIZE_VALUE_MASK 0x00001fff -#define BCHP_MFD_DISP_HSIZE_VALUE_SHIFT 0 - -/*************************************************************************** - *PICTURE0_DISP_VERT_WINDOW - MPEG/Video Feeder Display Vertical Window Register - ***************************************************************************/ -/* MFD :: PICTURE0_DISP_VERT_WINDOW :: reserved0 [31:29] */ -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved0_MASK 0xe0000000 -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved0_SHIFT 29 - -/* MFD :: PICTURE0_DISP_VERT_WINDOW :: START [28:16] */ -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_START_MASK 0x1fff0000 -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_START_SHIFT 16 - -/* MFD :: PICTURE0_DISP_VERT_WINDOW :: reserved1 [15:13] */ -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved1_MASK 0x0000e000 -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved1_SHIFT 13 - -/* MFD :: PICTURE0_DISP_VERT_WINDOW :: END [12:00] */ -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_END_MASK 0x00001fff -#define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_END_SHIFT 0 - -/*************************************************************************** - *PICTURE0_LINE_ADDR_0 - MPEG/Video Feeder Line Address0 Register - ***************************************************************************/ -/* union - case AVC_MPEG [31:00] */ -/* MFD :: PICTURE0_LINE_ADDR_0 :: AVC_MPEG :: LUMA_ADDR [31:00] */ -#define BCHP_MFD_PICTURE0_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_SHIFT 0 - -/* union - case PACKED [31:00] */ -/* MFD :: PICTURE0_LINE_ADDR_0 :: PACKED :: LUMA_CHROMA_ADDR [31:00] */ -#define BCHP_MFD_PICTURE0_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_SHIFT 0 - -/*************************************************************************** - *PICTURE0_LINE_ADDR_1 - MPEG/Video Feeder Line Address1 Register - ***************************************************************************/ -/* union - case AVC_MPEG [31:00] */ -/* MFD :: PICTURE0_LINE_ADDR_1 :: AVC_MPEG :: CHROMA_ADDR [31:00] */ -#define BCHP_MFD_PICTURE0_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_SHIFT 0 - -/* union - case PACKED [31:00] */ -/* MFD :: PICTURE0_LINE_ADDR_1 :: PACKED :: reserved0 [31:00] */ -#define BCHP_MFD_PICTURE0_LINE_ADDR_1_PACKED_reserved0_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LINE_ADDR_1_PACKED_reserved0_SHIFT 0 - -/*************************************************************************** - *CHROMA_SAMPLING_CNTL - MPEG Feeder Chroma Sampling Control Register - ***************************************************************************/ -/* MFD :: CHROMA_SAMPLING_CNTL :: reserved0 [31:01] */ -#define BCHP_MFD_CHROMA_SAMPLING_CNTL_reserved0_MASK 0xfffffffe -#define BCHP_MFD_CHROMA_SAMPLING_CNTL_reserved0_SHIFT 1 - -/* MFD :: CHROMA_SAMPLING_CNTL :: CHROMA_REPOSITION_ENABLE [00:00] */ -#define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_MASK 0x00000001 -#define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_SHIFT 0 -#define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_OFF 0 -#define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_ON 1 - -/*************************************************************************** - *LUMA_NMBY - MPEG Feeder Luma NMBY Size Register - ***************************************************************************/ -/* MFD :: LUMA_NMBY :: reserved0 [31:10] */ -#define BCHP_MFD_LUMA_NMBY_reserved0_MASK 0xfffffc00 -#define BCHP_MFD_LUMA_NMBY_reserved0_SHIFT 10 - -/* MFD :: LUMA_NMBY :: VALUE [09:00] */ -#define BCHP_MFD_LUMA_NMBY_VALUE_MASK 0x000003ff -#define BCHP_MFD_LUMA_NMBY_VALUE_SHIFT 0 - -/*************************************************************************** - *CHROMA_NMBY - MPEG Feeder Chroma NMBY Size Register - ***************************************************************************/ -/* MFD :: CHROMA_NMBY :: reserved0 [31:10] */ -#define BCHP_MFD_CHROMA_NMBY_reserved0_MASK 0xfffffc00 -#define BCHP_MFD_CHROMA_NMBY_reserved0_SHIFT 10 - -/* MFD :: CHROMA_NMBY :: VALUE [09:00] */ -#define BCHP_MFD_CHROMA_NMBY_VALUE_MASK 0x000003ff -#define BCHP_MFD_CHROMA_NMBY_VALUE_SHIFT 0 - -/*************************************************************************** - *PIC_FEED_CMD - MPEG/Video Feeder Picture Feed Command Register - ***************************************************************************/ -/* MFD :: PIC_FEED_CMD :: reserved0 [31:01] */ -#define BCHP_MFD_PIC_FEED_CMD_reserved0_MASK 0xfffffffe -#define BCHP_MFD_PIC_FEED_CMD_reserved0_SHIFT 1 - -/* MFD :: PIC_FEED_CMD :: START_FEED [00:00] */ -#define BCHP_MFD_PIC_FEED_CMD_START_FEED_MASK 0x00000001 -#define BCHP_MFD_PIC_FEED_CMD_START_FEED_SHIFT 0 - -/*************************************************************************** - *CRC_CTRL - MPEG/Video Feeder CRC Control Register - ***************************************************************************/ -/* MFD :: CRC_CTRL :: reserved0 [31:03] */ -#define BCHP_MFD_CRC_CTRL_reserved0_MASK 0xfffffff8 -#define BCHP_MFD_CRC_CTRL_reserved0_SHIFT 3 - -/* MFD :: CRC_CTRL :: ENABLE [02:02] */ -#define BCHP_MFD_CRC_CTRL_ENABLE_MASK 0x00000004 -#define BCHP_MFD_CRC_CTRL_ENABLE_SHIFT 2 -#define BCHP_MFD_CRC_CTRL_ENABLE_OFF 0 -#define BCHP_MFD_CRC_CTRL_ENABLE_ON 1 - -/* MFD :: CRC_CTRL :: MODE [01:01] */ -#define BCHP_MFD_CRC_CTRL_MODE_MASK 0x00000002 -#define BCHP_MFD_CRC_CTRL_MODE_SHIFT 1 -#define BCHP_MFD_CRC_CTRL_MODE_DISPLAY 0 -#define BCHP_MFD_CRC_CTRL_MODE_DEBUG 1 - -/* MFD :: CRC_CTRL :: LOAD_CRC_SEED [00:00] */ -#define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_MASK 0x00000001 -#define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_SHIFT 0 -#define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_AT_SOF 0 -#define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_ONCE 1 - -/*************************************************************************** - *CRC_SEED - MPEG/Video Feeder CRC Seed Register - ***************************************************************************/ -/* MFD :: CRC_SEED :: VALUE [31:00] */ -#define BCHP_MFD_CRC_SEED_VALUE_MASK 0xffffffff -#define BCHP_MFD_CRC_SEED_VALUE_SHIFT 0 - -/*************************************************************************** - *LUMA_CRC - MPEG/Video Feeder Luma CRC Register - ***************************************************************************/ -/* MFD :: LUMA_CRC :: VALUE [31:00] */ -#define BCHP_MFD_LUMA_CRC_VALUE_MASK 0xffffffff -#define BCHP_MFD_LUMA_CRC_VALUE_SHIFT 0 - -/*************************************************************************** - *CHROMA_CRC - MPEG/Video Feeder Chroma CRC Register - ***************************************************************************/ -/* MFD :: CHROMA_CRC :: VALUE [31:00] */ -#define BCHP_MFD_CHROMA_CRC_VALUE_MASK 0xffffffff -#define BCHP_MFD_CHROMA_CRC_VALUE_SHIFT 0 - -/*************************************************************************** - *DATA_MODE - MPEG/Video Feeder Data Mode Register - ***************************************************************************/ -/* MFD :: DATA_MODE :: reserved0 [31:01] */ -#define BCHP_MFD_DATA_MODE_reserved0_MASK 0xfffffffe -#define BCHP_MFD_DATA_MODE_reserved0_SHIFT 1 - -/* MFD :: DATA_MODE :: PIXEL_WIDTH [00:00] */ -#define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_MASK 0x00000001 -#define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_SHIFT 0 -#define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_MODE_8_BIT 0 -#define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_MODE_10_BIT 1 - -/*************************************************************************** - *PIC_OFFSET - MPEG/Video Feeder Picture Offset Register - ***************************************************************************/ -/* MFD :: PIC_OFFSET :: reserved0 [31:03] */ -#define BCHP_MFD_PIC_OFFSET_reserved0_MASK 0xfffffff8 -#define BCHP_MFD_PIC_OFFSET_reserved0_SHIFT 3 - -/* MFD :: PIC_OFFSET :: H_OFFSET [02:00] */ -#define BCHP_MFD_PIC_OFFSET_H_OFFSET_MASK 0x00000007 -#define BCHP_MFD_PIC_OFFSET_H_OFFSET_SHIFT 0 - -/*************************************************************************** - *RANGE_EXP_REMAP_CNTL - MPEG/Video Feeder Range Expansion / Remapping Control Register - ***************************************************************************/ -/* MFD :: RANGE_EXP_REMAP_CNTL :: reserved0 [31:10] */ -#define BCHP_MFD_RANGE_EXP_REMAP_CNTL_reserved0_MASK 0xfffffc00 -#define BCHP_MFD_RANGE_EXP_REMAP_CNTL_reserved0_SHIFT 10 - -/* MFD :: RANGE_EXP_REMAP_CNTL :: SCALE_C [09:05] */ -#define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_C_MASK 0x000003e0 -#define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_C_SHIFT 5 - -/* MFD :: RANGE_EXP_REMAP_CNTL :: SCALE_Y [04:00] */ -#define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_Y_MASK 0x0000001f -#define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_Y_SHIFT 0 - -/*************************************************************************** - *FEED_STATUS - MPEG/Video Feeder Feed Status Register - ***************************************************************************/ -/* MFD :: FEED_STATUS :: reserved0 [31:30] */ -#define BCHP_MFD_FEED_STATUS_reserved0_MASK 0xc0000000 -#define BCHP_MFD_FEED_STATUS_reserved0_SHIFT 30 - -/* MFD :: FEED_STATUS :: LAST_LINE [29:29] */ -#define BCHP_MFD_FEED_STATUS_LAST_LINE_MASK 0x20000000 -#define BCHP_MFD_FEED_STATUS_LAST_LINE_SHIFT 29 - -/* MFD :: FEED_STATUS :: reserved1 [28:13] */ -#define BCHP_MFD_FEED_STATUS_reserved1_MASK 0x1fffe000 -#define BCHP_MFD_FEED_STATUS_reserved1_SHIFT 13 - -/* MFD :: FEED_STATUS :: LINE_COUNT [12:00] */ -#define BCHP_MFD_FEED_STATUS_LINE_COUNT_MASK 0x00001fff -#define BCHP_MFD_FEED_STATUS_LINE_COUNT_SHIFT 0 - -/*************************************************************************** - *PICTURE0_LAC_LINE_ADDR_0 - MPEG/Video Feeder Line Address Computer Line Address0 Register - ***************************************************************************/ -/* union - case AVC_MPEG [31:00] */ -/* MFD :: PICTURE0_LAC_LINE_ADDR_0 :: AVC_MPEG :: LUMA_ADDR [31:00] */ -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_SHIFT 0 - -/* union - case PACKED [31:00] */ -/* MFD :: PICTURE0_LAC_LINE_ADDR_0 :: PACKED :: LUMA_CHROMA_ADDR [31:00] */ -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_SHIFT 0 - -/*************************************************************************** - *PICTURE0_LAC_LINE_ADDR_1 - MPEG/Video Feeder Line Address Computer Line Address1 Register - ***************************************************************************/ -/* union - case AVC_MPEG [31:00] */ -/* MFD :: PICTURE0_LAC_LINE_ADDR_1 :: AVC_MPEG :: CHROMA_ADDR [31:00] */ -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_SHIFT 0 - -/* union - case PACKED [31:00] */ -/* MFD :: PICTURE0_LAC_LINE_ADDR_1 :: PACKED :: reserved0 [31:00] */ -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_PACKED_reserved0_MASK 0xffffffff -#define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_PACKED_reserved0_SHIFT 0 - -/*************************************************************************** - *PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG - MPEG/Video Feeder Line Address Computer Chroma Vertical Filter Configuration Register - ***************************************************************************/ -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: reserved0 [31:20] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_reserved0_MASK 0xfff00000 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_reserved0_SHIFT 20 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_RD_ADDR_UPDATE_1 [19:19] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_MASK 0x00080000 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_SHIFT 19 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_OFF 0 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_ON 1 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_RD_ADDR_UPDATE_0 [18:18] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_MASK 0x00040000 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_SHIFT 18 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_OFF 0 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_ON 1 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_WREN_1 [17:17] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_MASK 0x00020000 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_SHIFT 17 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_ENABLE 0 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_DISABLE 1 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_WREN_0 [16:16] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_MASK 0x00010000 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_SHIFT 16 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_ENABLE 0 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_DISABLE 1 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CR_COEFF_TOP [15:12] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_TOP_MASK 0x0000f000 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_TOP_SHIFT 12 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CR_COEFF_BOT [11:08] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_BOT_MASK 0x00000f00 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_BOT_SHIFT 8 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CB_COEFF_TOP [07:04] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_TOP_MASK 0x000000f0 -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_TOP_SHIFT 4 - -/* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CB_COEFF_BOT [03:00] */ -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_BOT_MASK 0x0000000f -#define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_BOT_SHIFT 0 - -/*************************************************************************** - *LAC_LINE_FEED_CNTL - MPEG/Video Feeder Line Address Computer Line Feed Control Register - ***************************************************************************/ -/* MFD :: LAC_LINE_FEED_CNTL :: reserved0 [31:02] */ -#define BCHP_MFD_LAC_LINE_FEED_CNTL_reserved0_MASK 0xfffffffc -#define BCHP_MFD_LAC_LINE_FEED_CNTL_reserved0_SHIFT 2 - -/* MFD :: LAC_LINE_FEED_CNTL :: FIRST_LINE [01:01] */ -#define BCHP_MFD_LAC_LINE_FEED_CNTL_FIRST_LINE_MASK 0x00000002 -#define BCHP_MFD_LAC_LINE_FEED_CNTL_FIRST_LINE_SHIFT 1 - -/* MFD :: LAC_LINE_FEED_CNTL :: START_LINE_FEED [00:00] */ -#define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_MASK 0x00000001 -#define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_SHIFT 0 -#define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_PENDING 0 -#define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_COMPLETE 1 - -/*************************************************************************** - *FEEDER_TIMEOUT_REPEAT_PIC_CNTL - MPEG/Video Feeder Timeout and Repeat Picture Control Register - ***************************************************************************/ -/* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: reserved0 [31:26] */ -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_reserved0_MASK 0xfc000000 -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_reserved0_SHIFT 26 - -/* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: FEEDER_TIMEOUT_ENABLE [25:25] */ -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_MASK 0x02000000 -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_SHIFT 25 -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_OFF 0 -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_ON 1 - -/* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: REPEAT_PIC_ENABLE [24:24] */ -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_MASK 0x01000000 -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_SHIFT 24 -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_OFF 0 -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_ON 1 - -/* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: TIMEOUT_COUNT [23:00] */ -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_TIMEOUT_COUNT_MASK 0x00ffffff -#define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_TIMEOUT_COUNT_SHIFT 0 - -/*************************************************************************** - *BVB_RX_STALL_TIMEOUT_CNTL - MPEG/Video Feeder BVB Receiver Stall Timeout Control Register - ***************************************************************************/ -/* MFD :: BVB_RX_STALL_TIMEOUT_CNTL :: reserved0 [31:25] */ -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_reserved0_MASK 0xfe000000 -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_reserved0_SHIFT 25 - -/* MFD :: BVB_RX_STALL_TIMEOUT_CNTL :: RX_STALL_TIMEOUT_ENABLE [24:24] */ -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_MASK 0x01000000 -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_SHIFT 24 -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_OFF 0 -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_ON 1 - -/* MFD :: BVB_RX_STALL_TIMEOUT_CNTL :: TIMEOUT_COUNT [23:00] */ -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_TIMEOUT_COUNT_MASK 0x00ffffff -#define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_TIMEOUT_COUNT_SHIFT 0 - -/*************************************************************************** - *FEEDER_ERROR_INTERRUPT_STATUS - MPEG/Video Feeder Error Interrupt Status Register - ***************************************************************************/ -/* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: reserved0 [31:03] */ -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_reserved0_MASK 0xfffffff8 -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_reserved0_SHIFT 3 - -/* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: PIC_FEED_CMD_OVER_WR [02:02] */ -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_PIC_FEED_CMD_OVER_WR_MASK 0x00000004 -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_PIC_FEED_CMD_OVER_WR_SHIFT 2 - -/* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: RX_STALL_TIMEOUT [01:01] */ -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_RX_STALL_TIMEOUT_MASK 0x00000002 -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_RX_STALL_TIMEOUT_SHIFT 1 - -/* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: FEEDER_TIMEOUT [00:00] */ -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_FEEDER_TIMEOUT_MASK 0x00000001 -#define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_FEEDER_TIMEOUT_SHIFT 0 - -/*************************************************************************** - *FEEDER_BVB_STATUS - MPEG/Video Feeder BVB Status Register - ***************************************************************************/ -/* MFD :: FEEDER_BVB_STATUS :: reserved0 [31:02] */ -#define BCHP_MFD_FEEDER_BVB_STATUS_reserved0_MASK 0xfffffffc -#define BCHP_MFD_FEEDER_BVB_STATUS_reserved0_SHIFT 2 - -/* MFD :: FEEDER_BVB_STATUS :: EOF [01:01] */ -#define BCHP_MFD_FEEDER_BVB_STATUS_EOF_MASK 0x00000002 -#define BCHP_MFD_FEEDER_BVB_STATUS_EOF_SHIFT 1 - -/* MFD :: FEEDER_BVB_STATUS :: EOL [00:00] */ -#define BCHP_MFD_FEEDER_BVB_STATUS_EOL_MASK 0x00000001 -#define BCHP_MFD_FEEDER_BVB_STATUS_EOL_SHIFT 0 - -/*************************************************************************** - *TEST_MODE_CNTL - MPEG/Video Feeder Test Mode Control Register - ***************************************************************************/ -/* MFD :: TEST_MODE_CNTL :: reserved0 [31:04] */ -#define BCHP_MFD_TEST_MODE_CNTL_reserved0_MASK 0xfffffff0 -#define BCHP_MFD_TEST_MODE_CNTL_reserved0_SHIFT 4 - -/* MFD :: TEST_MODE_CNTL :: BVB_TEST_MODE [03:03] */ -#define BCHP_MFD_TEST_MODE_CNTL_BVB_TEST_MODE_MASK 0x00000008 -#define BCHP_MFD_TEST_MODE_CNTL_BVB_TEST_MODE_SHIFT 3 - -/* MFD :: TEST_MODE_CNTL :: PIXEL_SATURATION_ENABLE [02:02] */ -#define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_MASK 0x00000004 -#define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_SHIFT 2 -#define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_OFF 0 -#define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_ON 1 - -/* MFD :: TEST_MODE_CNTL :: ACCEPT_STATE [01:01] */ -#define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_STATE_MASK 0x00000002 -#define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_STATE_SHIFT 1 - -/* MFD :: TEST_MODE_CNTL :: ACCEPT_PULSE [00:00] */ -#define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_PULSE_MASK 0x00000001 -#define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_PULSE_SHIFT 0 - -/*************************************************************************** - *BVB_SAMPLE_DATA - MPEG/Video Feeder BVB Output Sample Data Register - ***************************************************************************/ -/* MFD :: BVB_SAMPLE_DATA :: reserved0 [31:26] */ -#define BCHP_MFD_BVB_SAMPLE_DATA_reserved0_MASK 0xfc000000 -#define BCHP_MFD_BVB_SAMPLE_DATA_reserved0_SHIFT 26 - -/* MFD :: BVB_SAMPLE_DATA :: PICTURE_SYNC [25:24] */ -#define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_MASK 0x03000000 -#define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_SHIFT 24 -#define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_NORMAL_PIXEL 0 -#define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_FIRST_PIXEL 1 -#define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_LAST_PIXEL 2 - -/* MFD :: BVB_SAMPLE_DATA :: LINE_SYNC [23:22] */ -#define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_MASK 0x00c00000 -#define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_SHIFT 22 -#define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_NORMAL_PIXEL 0 -#define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_FIRST_PIXEL 1 -#define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_LAST_PIXEL 2 - -/* MFD :: BVB_SAMPLE_DATA :: COLOUR_SYNC [21:20] */ -#define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_MASK 0x00300000 -#define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_SHIFT 20 -#define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_FIRST_BEAT 0 -#define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_SECOND_BEAT 1 -#define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_THIRD_BEAT 2 -#define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_FOURTH_BEAT 3 - -/* MFD :: BVB_SAMPLE_DATA :: LUMA [19:10] */ -#define BCHP_MFD_BVB_SAMPLE_DATA_LUMA_MASK 0x000ffc00 -#define BCHP_MFD_BVB_SAMPLE_DATA_LUMA_SHIFT 10 - -/* MFD :: BVB_SAMPLE_DATA :: CHROMA [09:00] */ -#define BCHP_MFD_BVB_SAMPLE_DATA_CHROMA_MASK 0x000003ff -#define BCHP_MFD_BVB_SAMPLE_DATA_CHROMA_SHIFT 0 - -/*************************************************************************** - *TEST_PORT_CNTL - MPEG/Video Feeder Test port Control Register - ***************************************************************************/ -/* MFD :: TEST_PORT_CNTL :: reserved0 [31:04] */ -#define BCHP_MFD_TEST_PORT_CNTL_reserved0_MASK 0xfffffff0 -#define BCHP_MFD_TEST_PORT_CNTL_reserved0_SHIFT 4 - -/* MFD :: TEST_PORT_CNTL :: ADDR_SEL [03:03] */ -#define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_MASK 0x00000008 -#define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_SHIFT 3 -#define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_PIN_INPUT 0 -#define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_SOFT_INPUT 1 - -/* MFD :: TEST_PORT_CNTL :: TP_ADDR [02:00] */ -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_MASK 0x00000007 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_SHIFT 0 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_HAC_0 0 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_HAC_1 1 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_LAC_HAC_2 2 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_PX_RD_SM 3 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_PX_RD_BVB 4 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_CLB_0 5 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_CLB_1 6 -#define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_BVB_OUT 7 - -/*************************************************************************** - *TEST_PORT_DATA - MPEG/Video Feeder Test port Data Register - ***************************************************************************/ -/* union - case HAC_0 [31:00] */ -/* MFD :: TEST_PORT_DATA :: HAC_0 :: HAC_LUMA_ADDR [31:00] */ -#define BCHP_MFD_TEST_PORT_DATA_HAC_0_HAC_LUMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_TEST_PORT_DATA_HAC_0_HAC_LUMA_ADDR_SHIFT 0 - -/* union - case HAC_1 [31:00] */ -/* MFD :: TEST_PORT_DATA :: HAC_1 :: HAC_CHROMA_ADDR [31:00] */ -#define BCHP_MFD_TEST_PORT_DATA_HAC_1_HAC_CHROMA_ADDR_MASK 0xffffffff -#define BCHP_MFD_TEST_PORT_DATA_HAC_1_HAC_CHROMA_ADDR_SHIFT 0 - -/* union - case LAC_HAC_2 [31:00] */ -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: reserved0 [31:30] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved0_MASK 0xc0000000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved0_SHIFT 30 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: FIRST_LINE_TRIG [29:29] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_FIRST_LINE_TRIG_MASK 0x20000000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_FIRST_LINE_TRIG_SHIFT 29 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LAC_SOL [28:28] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_SOL_MASK 0x10000000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_SOL_SHIFT 28 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LAC_BUSY [27:27] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_BUSY_MASK 0x08000000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_BUSY_SHIFT 27 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: reserved1 [26:26] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved1_MASK 0x04000000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved1_SHIFT 26 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LINE_ADDR_SEL [25:25] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_SEL_MASK 0x02000000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_SEL_SHIFT 25 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LINE_ADDR_INCR [24:23] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_MASK 0x01800000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_SHIFT 23 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_NO_UPDATE 0 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_PACKED_LINE_STRIDE 1 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_AVC_MPEG_LUMA_LINE_STRIDE 2 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_AVC_MPEG_CHROMA_LINE_STRIDE 3 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: CSM_TRIG [22:22] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CSM_TRIG_MASK 0x00400000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CSM_TRIG_SHIFT 22 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LUMA_LINE_PHASE [21:21] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_MASK 0x00200000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_SHIFT 21 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_EVEN 0 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_ODD 1 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: BUF_AVIAL [20:20] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_BUF_AVIAL_MASK 0x00100000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_BUF_AVIAL_SHIFT 20 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: CURRENT_BUF [19:19] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CURRENT_BUF_MASK 0x00080000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CURRENT_BUF_SHIFT 19 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: DBUF_DEPTH [18:17] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_MASK 0x00060000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_SHIFT 17 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_EMPTY 0 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_HALF_FULL 1 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_FULL 2 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: WSM_TRIG [16:16] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_TRIG_MASK 0x00010000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_TRIG_SHIFT 16 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: WSM_WR_DONE [15:15] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_WR_DONE_MASK 0x00008000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_WR_DONE_SHIFT 15 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: WSM_CUR_STATE [14:13] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_MASK 0x00006000 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_SHIFT 13 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_IDLE 0 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_DBUF_WRITE 1 -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_BUF_AVAIL 2 - -/* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LUMA_HORZ_CURSOR [12:00] */ -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_HORZ_CURSOR_MASK 0x00001fff -#define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_HORZ_CURSOR_SHIFT 0 - -/* union - case PX_RD_SM [31:00] */ -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: reserved0 [31:30] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_reserved0_MASK 0xc0000000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_reserved0_SHIFT 30 - -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: BUF_READY [29:29] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_READY_MASK 0x20000000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_READY_SHIFT 29 - -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: NUM_ACTIVE_PIXEL [28:19] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_NUM_ACTIVE_PIXEL_MASK 0x1ff80000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_NUM_ACTIVE_PIXEL_SHIFT 19 - -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: INIT_PIX_OFFSET [18:15] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_INIT_PIX_OFFSET_MASK 0x00078000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_INIT_PIX_OFFSET_SHIFT 15 - -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: RSM_CUR_STATE [14:12] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_MASK 0x00007000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_SHIFT 12 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_IDLE 0 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_SEND_FIXED_COLOUR 1 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_READ_BUF_CHECK 2 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_PRIME_LUMA_BUF 3 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_PRIME_CHROMA_BUF 4 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_SEND_PIXEL 5 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_BUFFER_READ_DONE 6 - -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: DBUF_RD_ON [11:11] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_DBUF_RD_ON_MASK 0x00000800 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_DBUF_RD_ON_SHIFT 11 - -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: RD_PIXEL_CNT [10:01] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RD_PIXEL_CNT_MASK 0x000007fe -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RD_PIXEL_CNT_SHIFT 1 - -/* MFD :: TEST_PORT_DATA :: PX_RD_SM :: BUF_RD_DONE [00:00] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_RD_DONE_MASK 0x00000001 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_RD_DONE_SHIFT 0 - -/* union - case PX_RD_BVB [31:00] */ -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: reserved0 [31:30] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_reserved0_MASK 0xc0000000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_reserved0_SHIFT 30 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: CSM_CUR_STATE [29:27] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_MASK 0x38000000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_SHIFT 27 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_IDLE 0 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_BUF_CHECK 1 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_WAIT_ACK_LUMA 2 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_REQ_CHROMA 3 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_WAIT_ACK_CHROMA 4 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_WAIT_WSM_DONE_CHROMA 5 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: DBUF_WR_ADDR [26:21] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_WR_ADDR_MASK 0x07e00000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_WR_ADDR_SHIFT 21 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: DBUF_RD_ADDR [20:15] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_RD_ADDR_MASK 0x001f8000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_RD_ADDR_SHIFT 15 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIRST_BUF [14:14] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_BUF_MASK 0x00004000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_BUF_SHIFT 14 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: LAST_BUF [13:13] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_BUF_MASK 0x00002000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_BUF_SHIFT 13 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: PIXEL_STROBE [12:12] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STROBE_MASK 0x00001000 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STROBE_SHIFT 12 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: CHROMA_PHASE [11:11] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CHROMA_PHASE_MASK 0x00000800 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CHROMA_PHASE_SHIFT 11 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIRST_PIXEL [10:10] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_PIXEL_MASK 0x00000400 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_PIXEL_SHIFT 10 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: LAST_PIXEL [09:09] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_PIXEL_MASK 0x00000200 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_PIXEL_SHIFT 9 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIRST_LINE [08:08] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_LINE_MASK 0x00000100 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_LINE_SHIFT 8 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: LAST_LINE [07:07] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_LINE_MASK 0x00000080 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_LINE_SHIFT 7 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIFO_FULL [06:06] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_FULL_MASK 0x00000040 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_FULL_SHIFT 6 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIFO_EMPTY [05:05] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_EMPTY_MASK 0x00000020 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_EMPTY_SHIFT 5 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIFO_DEPTH_CNT [04:03] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_DEPTH_CNT_MASK 0x00000018 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_DEPTH_CNT_SHIFT 3 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: PIXEL_STOP [02:02] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STOP_MASK 0x00000004 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STOP_SHIFT 2 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: BVB_EOL [01:01] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOL_MASK 0x00000002 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOL_SHIFT 1 - -/* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: BVB_EOF [00:00] */ -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOF_MASK 0x00000001 -#define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOF_SHIFT 0 - -/* union - case CLB_0 [31:00] */ -/* MFD :: TEST_PORT_DATA :: CLB_0 :: reserved0 [31:31] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_reserved0_MASK 0x80000000 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_reserved0_SHIFT 31 - -/* MFD :: TEST_PORT_DATA :: CLB_0 :: BURST_SIZE [30:26] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_BURST_SIZE_MASK 0x7c000000 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_BURST_SIZE_SHIFT 26 - -/* MFD :: TEST_PORT_DATA :: CLB_0 :: TOP_TAP_SEL [25:24] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_MASK 0x03000000 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_SHIFT 24 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_LIVE_CHROMA 0 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_CLB0_CHROMA 1 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_CLB1_CHROMA 2 - -/* MFD :: TEST_PORT_DATA :: CLB_0 :: BOT_TAP_SEL [23:22] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_MASK 0x00c00000 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_SHIFT 22 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_LIVE_CHROMA 0 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_CLB0_CHROMA 1 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_CLB1_CHROMA 2 - -/* MFD :: TEST_PORT_DATA :: CLB_0 :: ADDR_A [21:12] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_A_MASK 0x003ff000 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_A_SHIFT 12 - -/* MFD :: TEST_PORT_DATA :: CLB_0 :: ADDR_B [11:02] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_B_MASK 0x00000ffc -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_B_SHIFT 2 - -/* MFD :: TEST_PORT_DATA :: CLB_0 :: WR_RDB_A [01:01] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_MASK 0x00000002 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_SHIFT 1 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_READ 0 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_WRITE 1 - -/* MFD :: TEST_PORT_DATA :: CLB_0 :: WR_RDB_B [00:00] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_MASK 0x00000001 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_SHIFT 0 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_READ 0 -#define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_WRITE 1 - -/* union - case CLB_1 [31:00] */ -/* MFD :: TEST_PORT_DATA :: CLB_1 :: WR_DATA_A [31:16] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_1_WR_DATA_A_MASK 0xffff0000 -#define BCHP_MFD_TEST_PORT_DATA_CLB_1_WR_DATA_A_SHIFT 16 - -/* MFD :: TEST_PORT_DATA :: CLB_1 :: RD_DATA_B [15:00] */ -#define BCHP_MFD_TEST_PORT_DATA_CLB_1_RD_DATA_B_MASK 0x0000ffff -#define BCHP_MFD_TEST_PORT_DATA_CLB_1_RD_DATA_B_SHIFT 0 - -/* union - case BVB_OUT [31:00] */ -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: reserved0 [31:28] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_reserved0_MASK 0xf0000000 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_reserved0_SHIFT 28 - -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: ACCEPT [27:27] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_ACCEPT_MASK 0x08000000 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_ACCEPT_SHIFT 27 - -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: READY [26:26] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_READY_MASK 0x04000000 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_READY_SHIFT 26 - -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: PICTURE_SYNC [25:24] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_MASK 0x03000000 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_SHIFT 24 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_NORMAL_PIXEL 0 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_FIRST_PIXEL 1 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_LAST_PIXEL 2 - -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: LINE_SYNC [23:22] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_MASK 0x00c00000 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_SHIFT 22 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_NORMAL_PIXEL 0 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_FIRST_PIXEL 1 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_LAST_PIXEL 2 - -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: COLOUR_SYNC [21:20] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_MASK 0x00300000 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_SHIFT 20 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_FIRST_BEAT 0 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_SECOND_BEAT 1 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_THIRD_BEAT 2 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_FOURTH_BEAT 3 - -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: LUMA_DATA [19:10] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LUMA_DATA_MASK 0x000ffc00 -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LUMA_DATA_SHIFT 10 - -/* MFD :: TEST_PORT_DATA :: BVB_OUT :: CHROMA_DATA [09:00] */ -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_CHROMA_DATA_MASK 0x000003ff -#define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_CHROMA_DATA_SHIFT 0 - -/*************************************************************************** - *SCRATCH_REGISTER_0 - MPEG/Video Feeder Scratch 0 Register - ***************************************************************************/ -/* MFD :: SCRATCH_REGISTER_0 :: VALUE [31:00] */ -#define BCHP_MFD_SCRATCH_REGISTER_0_VALUE_MASK 0xffffffff -#define BCHP_MFD_SCRATCH_REGISTER_0_VALUE_SHIFT 0 - -/*************************************************************************** - *SCRATCH_REGISTER_1 - MPEG/Video Feeder Scratch 1 Register - ***************************************************************************/ -/* MFD :: SCRATCH_REGISTER_1 :: VALUE [31:00] */ -#define BCHP_MFD_SCRATCH_REGISTER_1_VALUE_MASK 0xffffffff -#define BCHP_MFD_SCRATCH_REGISTER_1_VALUE_SHIFT 0 - -#endif /* #ifndef BCHP_MFD_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,830 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_misc1.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:11p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:40 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:11p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MISC1_H__ -#define BCHP_MISC1_H__ - -/*************************************************************************** - *MISC1 - Registers for DMA List Control - ***************************************************************************/ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00502000 /* Tx DMA Descriptor List0 First Descriptor lower Address */ -#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00502004 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00502008 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ -#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x0050200c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00502010 /* Tx DMA Software Descriptor List Control and Status */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS 0x00502018 /* Tx DMA Engine Error Status */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR 0x0050201c /* Tx DMA List0 Current Descriptor Lower Address */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR 0x00502020 /* Tx DMA List0 Current Descriptor Upper Address */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM 0x00502024 /* Tx DMA List0 Current Descriptor Upper Address */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR 0x00502028 /* Tx DMA List1 Current Descriptor Lower Address */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR 0x0050202c /* Tx DMA List1 Current Descriptor Upper Address */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM 0x00502030 /* Tx DMA List1 Current Descriptor Upper Address */ -#define BCHP_MISC1_TX_DMA_CTRL 0x00502034 /* Tx DMA Flea Interface Control */ -#define BCHP_MISC1_TX_DMA_STATE 0x00502038 /* Tx DMA Flea Interface State */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0 0x00502040 /* Y Rx Descriptor List0 First Descriptor Lower Address */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0 0x00502044 /* Y Rx Descriptor List0 First Descriptor Upper Address */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1 0x00502048 /* Y Rx Descriptor List1 First Descriptor Lower Address */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1 0x0050204c /* Y Rx Descriptor List1 First Descriptor Upper Address */ -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00502050 /* Y Rx Software Descriptor List Control and Status */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS 0x00502054 /* Y Rx Engine Error Status */ -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR 0x00502058 /* Y Rx List0 Current Descriptor Lower Address */ -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR 0x0050205c /* Y Rx List0 Current Descriptor Upper Address */ -#define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00502060 /* Y Rx List0 Current Descriptor Byte Count */ -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR 0x00502064 /* Y Rx List1 Current Descriptor Lower address */ -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR 0x00502068 /* Y Rx List1 Current Descriptor Upper address */ -#define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x0050206c /* Y Rx List1 Current Descriptor Byte Count */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0 0x00502080 /* HIF Rx Descriptor List0 First Descriptor lower Address */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST0 0x00502084 /* HIF Rx Descriptor List0 First Descriptor Upper Address */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1 0x00502088 /* HIF Rx Descriptor List1 First Descriptor Lower Address */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST1 0x0050208c /* HIF Rx Descriptor List1 First Descriptor Upper Address */ -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS 0x00502090 /* HIF Rx Software Descriptor List Control and Status */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS 0x00502094 /* HIF Rx Engine Error Status */ -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR 0x00502098 /* HIF Rx List0 Current Descriptor Lower Address */ -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_U_ADDR 0x0050209c /* HIF Rx List0 Current Descriptor Upper Address */ -#define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT 0x005020a0 /* HIF Rx List0 Current Descriptor Byte Count */ -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR 0x005020a4 /* HIF Rx List1 Current Descriptor Lower Address */ -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_U_ADDR 0x005020a8 /* HIF Rx List1 Current Descriptor Upper Address */ -#define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT 0x005020ac /* HIF Rx List1 Current Descriptor Byte Count */ -#define BCHP_MISC1_HIF_DMA_CTRL 0x005020b0 /* HIF Rx DMA Flea Interface Control */ -#define BCHP_MISC1_HIF_DMA_STATE 0x005020b4 /* HIF Rx DMA Flea Interface State */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG 0x005020c0 /* DMA Debug Options Register */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS 0x005020c4 /* Read Channel Error Status */ -#define BCHP_MISC1_PCIE_DMA_CTRL 0x005020c8 /* PCIE DMA Control Register */ -#define BCHP_MISC1_HIF_RXDMA_BASE_ADDR 0x005020cc /* HIF Rx DMA Base DRAM Address */ -#define BCHP_MISC1_HIF_RXDMA_LENGTH 0x005020d0 /* HIF Rx DMA Transfer Length */ - -/*************************************************************************** - *TX_FIRST_DESC_L_ADDR_LIST0 - Tx DMA Descriptor List0 First Descriptor lower Address - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001 -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0 - -/*************************************************************************** - *TX_FIRST_DESC_U_ADDR_LIST0 - Tx DMA Descriptor List0 First Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ -#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff -#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *TX_FIRST_DESC_L_ADDR_LIST1 - Tx DMA Descriptor List1 First Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */ -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001 -#define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0 - -/*************************************************************************** - *TX_FIRST_DESC_U_ADDR_LIST1 - Tx DMA Descriptor List1 First Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ -#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff -#define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *TX_SW_DESC_LIST_CTRL_STS - Tx DMA Software Descriptor List Control and Status - ***************************************************************************/ -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 -#define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 - -/*************************************************************************** - *TX_DMA_ERROR_STATUS - Tx DMA Engine Error Status - ***************************************************************************/ -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 -#define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 - -/*************************************************************************** - *TX_DMA_LIST0_CUR_DESC_L_ADDR - Tx DMA List0 Current Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: TX_DMA_L0_CUR_DESC_L_ADDR [31:05] */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *TX_DMA_LIST0_CUR_DESC_U_ADDR - Tx DMA List0 Current Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR :: TX_DMA_L0_CUR_DESC_U_ADDR [31:00] */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_MASK 0xffffffff -#define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_SHIFT 0 - -/*************************************************************************** - *TX_DMA_LIST0_CUR_BYTE_CNT_REM - Tx DMA List0 Current Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 -#define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 - -/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: TX_DMA_L0_CUR_BYTE_CNT_REM [23:02] */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_MASK 0x00fffffc -#define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_SHIFT 2 - -/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ -#define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 -#define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 - -/*************************************************************************** - *TX_DMA_LIST1_CUR_DESC_L_ADDR - Tx DMA List1 Current Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: TX_DMA_L1_CUR_DESC_L_ADDR [31:05] */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *TX_DMA_LIST1_CUR_DESC_U_ADDR - Tx DMA List1 Current Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR :: TX_DMA_L1_CUR_DESC_U_ADDR [31:00] */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_MASK 0xffffffff -#define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_SHIFT 0 - -/*************************************************************************** - *TX_DMA_LIST1_CUR_BYTE_CNT_REM - Tx DMA List1 Current Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 -#define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 - -/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: TX_DMA_L1_CUR_BYTE_CNT_REM [23:02] */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_MASK 0x00fffffc -#define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_SHIFT 2 - -/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ -#define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 -#define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 - -/*************************************************************************** - *TX_DMA_CTRL - Tx DMA Flea Interface Control - ***************************************************************************/ -/* MISC1 :: TX_DMA_CTRL :: reserved0 [31:02] */ -#define BCHP_MISC1_TX_DMA_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_MISC1_TX_DMA_CTRL_reserved0_SHIFT 2 - -/* MISC1 :: TX_DMA_CTRL :: TX_DMA_FLUSH_REQUEST [01:01] */ -#define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_FLUSH_REQUEST_MASK 0x00000002 -#define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_FLUSH_REQUEST_SHIFT 1 - -/* MISC1 :: TX_DMA_CTRL :: TX_DMA_ENABLE [00:00] */ -#define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_ENABLE_MASK 0x00000001 -#define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_ENABLE_SHIFT 0 - -/*************************************************************************** - *TX_DMA_STATE - Tx DMA Flea Interface State - ***************************************************************************/ -/* MISC1 :: TX_DMA_STATE :: reserved0 [31:04] */ -#define BCHP_MISC1_TX_DMA_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_MISC1_TX_DMA_STATE_reserved0_SHIFT 4 - -/* MISC1 :: TX_DMA_STATE :: TX_DMA_ERROR [03:03] */ -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ERROR_MASK 0x00000008 -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ERROR_SHIFT 3 - -/* MISC1 :: TX_DMA_STATE :: TX_DMA_FLUSH_ACTIVE [02:02] */ -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FLUSH_ACTIVE_MASK 0x00000004 -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FLUSH_ACTIVE_SHIFT 2 - -/* MISC1 :: TX_DMA_STATE :: TX_DMA_FIFO_ACTIVE [01:01] */ -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FIFO_ACTIVE_MASK 0x00000002 -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FIFO_ACTIVE_SHIFT 1 - -/* MISC1 :: TX_DMA_STATE :: TX_DMA_ACTIVE [00:00] */ -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ACTIVE_MASK 0x00000001 -#define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ACTIVE_SHIFT 0 - -/*************************************************************************** - *Y_RX_FIRST_DESC_L_ADDR_LIST0 - Y Rx Descriptor List0 First Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 - -/*************************************************************************** - *Y_RX_FIRST_DESC_U_ADDR_LIST0 - Y Rx Descriptor List0 First Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff -#define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *Y_RX_FIRST_DESC_L_ADDR_LIST1 - Y Rx Descriptor List1 First Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 -#define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 - -/*************************************************************************** - *Y_RX_FIRST_DESC_U_ADDR_LIST1 - Y Rx Descriptor List1 First Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ -#define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff -#define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *Y_RX_SW_DESC_LIST_CTRL_STS - Y Rx Software Descriptor List Control and Status - ***************************************************************************/ -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 -#define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 - -/*************************************************************************** - *Y_RX_ERROR_STATUS - Y Rx Engine Error Status - ***************************************************************************/ -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 -#define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 - -/*************************************************************************** - *Y_RX_LIST0_CUR_DESC_L_ADDR - Y Rx List0 Current Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *Y_RX_LIST0_CUR_DESC_U_ADDR - Y Rx List0 Current Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff -#define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 - -/*************************************************************************** - *Y_RX_LIST0_CUR_BYTE_CNT - Y Rx List0 Current Descriptor Byte Count - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ -#define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff -#define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 - -/*************************************************************************** - *Y_RX_LIST1_CUR_DESC_L_ADDR - Y Rx List1 Current Descriptor Lower address - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *Y_RX_LIST1_CUR_DESC_U_ADDR - Y Rx List1 Current Descriptor Upper address - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff -#define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 - -/*************************************************************************** - *Y_RX_LIST1_CUR_BYTE_CNT - Y Rx List1 Current Descriptor Byte Count - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ -#define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff -#define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 - -/*************************************************************************** - *HIF_RX_FIRST_DESC_L_ADDR_LIST0 - HIF Rx Descriptor List0 First Descriptor lower Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 - -/* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 - -/* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 - -/*************************************************************************** - *HIF_RX_FIRST_DESC_U_ADDR_LIST0 - HIF Rx Descriptor List0 First Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff -#define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *HIF_RX_FIRST_DESC_L_ADDR_LIST1 - HIF Rx Descriptor List1 First Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 - -/* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 - -/* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 -#define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 - -/*************************************************************************** - *HIF_RX_FIRST_DESC_U_ADDR_LIST1 - HIF Rx Descriptor List1 First Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ -#define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff -#define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *HIF_RX_SW_DESC_LIST_CTRL_STS - HIF Rx Software Descriptor List Control and Status - ***************************************************************************/ -/* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 - -/* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 - -/* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 - -/* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 - -/* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 -#define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 - -/*************************************************************************** - *HIF_RX_ERROR_STATUS - HIF Rx Engine Error Status - ***************************************************************************/ -/* MISC1 :: HIF_RX_ERROR_STATUS :: reserved0 [31:14] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved0_SHIFT 14 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: reserved1 [08:08] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved1_MASK 0x00000100 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved1_SHIFT 8 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: reserved2 [06:05] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved2_MASK 0x00000060 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved2_SHIFT 5 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: reserved3 [03:02] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved3_MASK 0x0000000c -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved3_SHIFT 2 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 - -/* MISC1 :: HIF_RX_ERROR_STATUS :: reserved4 [00:00] */ -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved4_MASK 0x00000001 -#define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved4_SHIFT 0 - -/*************************************************************************** - *HIF_RX_LIST0_CUR_DESC_L_ADDR - HIF Rx List0 Current Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: HIF_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *HIF_RX_LIST0_CUR_DESC_U_ADDR - HIF Rx List0 Current Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff -#define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 - -/*************************************************************************** - *HIF_RX_LIST0_CUR_BYTE_CNT - HIF Rx List0 Current Descriptor Byte Count - ***************************************************************************/ -/* MISC1 :: HIF_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ -#define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff -#define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 - -/*************************************************************************** - *HIF_RX_LIST1_CUR_DESC_L_ADDR - HIF Rx List1 Current Descriptor Lower Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: HIF_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *HIF_RX_LIST1_CUR_DESC_U_ADDR - HIF Rx List1 Current Descriptor Upper Address - ***************************************************************************/ -/* MISC1 :: HIF_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff -#define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 - -/*************************************************************************** - *HIF_RX_LIST1_CUR_BYTE_CNT - HIF Rx List1 Current Descriptor Byte Count - ***************************************************************************/ -/* MISC1 :: HIF_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ -#define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff -#define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 - -/*************************************************************************** - *HIF_DMA_CTRL - HIF Rx DMA Flea Interface Control - ***************************************************************************/ -/* MISC1 :: HIF_DMA_CTRL :: reserved0 [31:01] */ -#define BCHP_MISC1_HIF_DMA_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_MISC1_HIF_DMA_CTRL_reserved0_SHIFT 1 - -/* MISC1 :: HIF_DMA_CTRL :: RX_DMA_ENABLE [00:00] */ -#define BCHP_MISC1_HIF_DMA_CTRL_RX_DMA_ENABLE_MASK 0x00000001 -#define BCHP_MISC1_HIF_DMA_CTRL_RX_DMA_ENABLE_SHIFT 0 - -/*************************************************************************** - *HIF_DMA_STATE - HIF Rx DMA Flea Interface State - ***************************************************************************/ -/* MISC1 :: HIF_DMA_STATE :: reserved0 [31:03] */ -#define BCHP_MISC1_HIF_DMA_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_MISC1_HIF_DMA_STATE_reserved0_SHIFT 3 - -/* MISC1 :: HIF_DMA_STATE :: RX_DMA_ERROR [02:02] */ -#define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ERROR_MASK 0x00000004 -#define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ERROR_SHIFT 2 - -/* MISC1 :: HIF_DMA_STATE :: RX_DMA_FIFO_ACTIVE [01:01] */ -#define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_FIFO_ACTIVE_MASK 0x00000002 -#define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_FIFO_ACTIVE_SHIFT 1 - -/* MISC1 :: HIF_DMA_STATE :: RX_DMA_ACTIVE [00:00] */ -#define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ACTIVE_MASK 0x00000001 -#define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ACTIVE_SHIFT 0 - -/*************************************************************************** - *DMA_DEBUG_OPTIONS_REG - DMA Debug Options Register - ***************************************************************************/ -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:05] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0fffffe0 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 5 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_1 [03:03] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_MASK 0x00000008 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_SHIFT 3 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_2 [00:00] */ -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_MASK 0x00000001 -#define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_SHIFT 0 - -/*************************************************************************** - *READ_CHANNEL_ERROR_STATUS - Read Channel Error Status - ***************************************************************************/ -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000 -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000 -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000 -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000 -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000 -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00 -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0 -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */ -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f -#define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0 - -/*************************************************************************** - *PCIE_DMA_CTRL - PCIE DMA Control Register - ***************************************************************************/ -/* MISC1 :: PCIE_DMA_CTRL :: reserved0 [31:18] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_MISC1_PCIE_DMA_CTRL_reserved0_SHIFT 18 - -/* MISC1 :: PCIE_DMA_CTRL :: DESC_ENDIAN_MODE [17:16] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_MASK 0x00030000 -#define BCHP_MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_SHIFT 16 - -/* MISC1 :: PCIE_DMA_CTRL :: reserved1 [15:09] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_reserved1_MASK 0x0000fe00 -#define BCHP_MISC1_PCIE_DMA_CTRL_reserved1_SHIFT 9 - -/* MISC1 :: PCIE_DMA_CTRL :: EN_ROUND_ROBIN [08:08] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_MASK 0x00000100 -#define BCHP_MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_SHIFT 8 - -/* MISC1 :: PCIE_DMA_CTRL :: reserved2 [07:05] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_reserved2_MASK 0x000000e0 -#define BCHP_MISC1_PCIE_DMA_CTRL_reserved2_SHIFT 5 - -/* MISC1 :: PCIE_DMA_CTRL :: RELAXED_ORDERING [04:04] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_MASK 0x00000010 -#define BCHP_MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_SHIFT 4 - -/* MISC1 :: PCIE_DMA_CTRL :: NO_SNOOP [03:03] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_NO_SNOOP_MASK 0x00000008 -#define BCHP_MISC1_PCIE_DMA_CTRL_NO_SNOOP_SHIFT 3 - -/* MISC1 :: PCIE_DMA_CTRL :: TRAFFIC_CLASS [02:00] */ -#define BCHP_MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_MASK 0x00000007 -#define BCHP_MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_SHIFT 0 - -/*************************************************************************** - *HIF_RXDMA_BASE_ADDR - HIF Rx DMA Base DRAM Address - ***************************************************************************/ -/* MISC1 :: HIF_RXDMA_BASE_ADDR :: BASE_ADDR [31:00] */ -#define BCHP_MISC1_HIF_RXDMA_BASE_ADDR_BASE_ADDR_MASK 0xffffffff -#define BCHP_MISC1_HIF_RXDMA_BASE_ADDR_BASE_ADDR_SHIFT 0 - -/*************************************************************************** - *HIF_RXDMA_LENGTH - HIF Rx DMA Transfer Length - ***************************************************************************/ -/* MISC1 :: HIF_RXDMA_LENGTH :: ACTIVE [31:31] */ -#define BCHP_MISC1_HIF_RXDMA_LENGTH_ACTIVE_MASK 0x80000000 -#define BCHP_MISC1_HIF_RXDMA_LENGTH_ACTIVE_SHIFT 31 - -/* MISC1 :: HIF_RXDMA_LENGTH :: reserved0 [30:23] */ -#define BCHP_MISC1_HIF_RXDMA_LENGTH_reserved0_MASK 0x7f800000 -#define BCHP_MISC1_HIF_RXDMA_LENGTH_reserved0_SHIFT 23 - -/* MISC1 :: HIF_RXDMA_LENGTH :: LENGTH [22:00] */ -#define BCHP_MISC1_HIF_RXDMA_LENGTH_LENGTH_MASK 0x007fffff -#define BCHP_MISC1_HIF_RXDMA_LENGTH_LENGTH_SHIFT 0 - -#endif /* #ifndef BCHP_MISC1_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,238 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_misc2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:11p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:37 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:11p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MISC2_H__ -#define BCHP_MISC2_H__ - -/*************************************************************************** - *MISC2 - Registers for Meta DMA, Direct DRAM Access, Global Controls - ***************************************************************************/ -#define BCHP_MISC2_GLOBAL_CTRL 0x00502100 /* Global Control Register */ -#define BCHP_MISC2_INTERNAL_STATUS 0x00502104 /* Internal Status Register */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL 0x00502108 /* Internal Debug Mux Control */ -#define BCHP_MISC2_DEBUG_FIFO_LENGTH 0x0050210c /* Debug FIFO Length */ -#define BCHP_MISC2_WRITE_BLOCKOUT_COUNT 0x00502110 /* Write Blockout Count */ -#define BCHP_MISC2_META_DATA_BASE_ADDR 0x00502114 /* Meta Data Base DRAM Address */ -#define BCHP_MISC2_META_DATA_LENGTH 0x00502118 /* Meta Data Length */ -#define BCHP_MISC2_DIRECT_WINDOW_STATUS 0x0050211c /* Direct DRAM Access Window Status */ -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL 0x00502120 /* Direct DRAM Access Window Control */ - -/*************************************************************************** - *GLOBAL_CTRL - Global Control Register - ***************************************************************************/ -/* MISC2 :: GLOBAL_CTRL :: reserved0 [31:07] */ -#define BCHP_MISC2_GLOBAL_CTRL_reserved0_MASK 0xffffff80 -#define BCHP_MISC2_GLOBAL_CTRL_reserved0_SHIFT 7 - -/* MISC2 :: GLOBAL_CTRL :: BURST_64_BYTES [06:06] */ -#define BCHP_MISC2_GLOBAL_CTRL_BURST_64_BYTES_MASK 0x00000040 -#define BCHP_MISC2_GLOBAL_CTRL_BURST_64_BYTES_SHIFT 6 - -/* MISC2 :: GLOBAL_CTRL :: BOP_DRAIN [05:05] */ -#define BCHP_MISC2_GLOBAL_CTRL_BOP_DRAIN_MASK 0x00000020 -#define BCHP_MISC2_GLOBAL_CTRL_BOP_DRAIN_SHIFT 5 - -/* MISC2 :: GLOBAL_CTRL :: META_DMA_ENABLE [04:04] */ -#define BCHP_MISC2_GLOBAL_CTRL_META_DMA_ENABLE_MASK 0x00000010 -#define BCHP_MISC2_GLOBAL_CTRL_META_DMA_ENABLE_SHIFT 4 - -/* MISC2 :: GLOBAL_CTRL :: BVN_CHECKSUM_10BITS [03:03] */ -#define BCHP_MISC2_GLOBAL_CTRL_BVN_CHECKSUM_10BITS_MASK 0x00000008 -#define BCHP_MISC2_GLOBAL_CTRL_BVN_CHECKSUM_10BITS_SHIFT 3 - -/* MISC2 :: GLOBAL_CTRL :: BVN_10B_TO_8B [02:02] */ -#define BCHP_MISC2_GLOBAL_CTRL_BVN_10B_TO_8B_MASK 0x00000004 -#define BCHP_MISC2_GLOBAL_CTRL_BVN_10B_TO_8B_SHIFT 2 - -/* MISC2 :: GLOBAL_CTRL :: BVN_YUY2_MODE [01:01] */ -#define BCHP_MISC2_GLOBAL_CTRL_BVN_YUY2_MODE_MASK 0x00000002 -#define BCHP_MISC2_GLOBAL_CTRL_BVN_YUY2_MODE_SHIFT 1 - -/* MISC2 :: GLOBAL_CTRL :: BVN_420_MODE [00:00] */ -#define BCHP_MISC2_GLOBAL_CTRL_BVN_420_MODE_MASK 0x00000001 -#define BCHP_MISC2_GLOBAL_CTRL_BVN_420_MODE_SHIFT 0 - -/*************************************************************************** - *INTERNAL_STATUS - Internal Status Register - ***************************************************************************/ -/* MISC2 :: INTERNAL_STATUS :: META_DATA_ACTIVE [31:31] */ -#define BCHP_MISC2_INTERNAL_STATUS_META_DATA_ACTIVE_MASK 0x80000000 -#define BCHP_MISC2_INTERNAL_STATUS_META_DATA_ACTIVE_SHIFT 31 - -/* MISC2 :: INTERNAL_STATUS :: reserved0 [30:10] */ -#define BCHP_MISC2_INTERNAL_STATUS_reserved0_MASK 0x7ffffc00 -#define BCHP_MISC2_INTERNAL_STATUS_reserved0_SHIFT 10 - -/* MISC2 :: INTERNAL_STATUS :: BVN_BYTE_COUNT_FIFO_FULL [09:09] */ -#define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_FULL_MASK 0x00000200 -#define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_FULL_SHIFT 9 - -/* MISC2 :: INTERNAL_STATUS :: BVN_DATA_FIFO_FULL [08:08] */ -#define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_FULL_MASK 0x00000100 -#define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_FULL_SHIFT 8 - -/* MISC2 :: INTERNAL_STATUS :: reserved1 [07:06] */ -#define BCHP_MISC2_INTERNAL_STATUS_reserved1_MASK 0x000000c0 -#define BCHP_MISC2_INTERNAL_STATUS_reserved1_SHIFT 6 - -/* MISC2 :: INTERNAL_STATUS :: BVN_BYTE_COUNT_FIFO_EMPTY [05:05] */ -#define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000020 -#define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_EMPTY_SHIFT 5 - -/* MISC2 :: INTERNAL_STATUS :: BVN_DATA_FIFO_EMPTY [04:04] */ -#define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_EMPTY_MASK 0x00000010 -#define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_EMPTY_SHIFT 4 - -/* MISC2 :: INTERNAL_STATUS :: reserved2 [03:00] */ -#define BCHP_MISC2_INTERNAL_STATUS_reserved2_MASK 0x0000000f -#define BCHP_MISC2_INTERNAL_STATUS_reserved2_SHIFT 0 - -/*************************************************************************** - *INTERNAL_STATUS_MUX_CTRL - Internal Debug Mux Control - ***************************************************************************/ -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved0 [31:16] */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_MASK 0xffff0000 -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_SHIFT 16 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: CLK_OUT_ALT_SRC [15:15] */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_MASK 0x00008000 -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_SHIFT 15 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CLK_SEL [14:12] */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_MASK 0x00007000 -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_SHIFT 12 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved1 [11:09] */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_MASK 0x00000e00 -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_SHIFT 9 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_TOP_CORE_SEL [08:08] */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_MASK 0x00000100 -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_SHIFT 8 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CORE_BLK_SEL [07:04] */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_MASK 0x000000f0 -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_SHIFT 4 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_VECTOR_SEL [03:00] */ -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_MASK 0x0000000f -#define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_SHIFT 0 - -/*************************************************************************** - *DEBUG_FIFO_LENGTH - Debug FIFO Length - ***************************************************************************/ -/* MISC2 :: DEBUG_FIFO_LENGTH :: reserved0 [31:21] */ -#define BCHP_MISC2_DEBUG_FIFO_LENGTH_reserved0_MASK 0xffe00000 -#define BCHP_MISC2_DEBUG_FIFO_LENGTH_reserved0_SHIFT 21 - -/* MISC2 :: DEBUG_FIFO_LENGTH :: FIFO_LENGTH [20:00] */ -#define BCHP_MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_MASK 0x001fffff -#define BCHP_MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_SHIFT 0 - -/*************************************************************************** - *WRITE_BLOCKOUT_COUNT - Write Blockout Count - ***************************************************************************/ -/* MISC2 :: WRITE_BLOCKOUT_COUNT :: reserved0 [31:16] */ -#define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_reserved0_MASK 0xffff0000 -#define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_reserved0_SHIFT 16 - -/* MISC2 :: WRITE_BLOCKOUT_COUNT :: BLOCKOUT_COUNT [15:00] */ -#define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_BLOCKOUT_COUNT_MASK 0x0000ffff -#define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_BLOCKOUT_COUNT_SHIFT 0 - -/*************************************************************************** - *META_DATA_BASE_ADDR - Meta Data Base DRAM Address - ***************************************************************************/ -/* MISC2 :: META_DATA_BASE_ADDR :: META_DATA_BASE_ADDR [31:00] */ -#define BCHP_MISC2_META_DATA_BASE_ADDR_META_DATA_BASE_ADDR_MASK 0xffffffff -#define BCHP_MISC2_META_DATA_BASE_ADDR_META_DATA_BASE_ADDR_SHIFT 0 - -/*************************************************************************** - *META_DATA_LENGTH - Meta Data Length - ***************************************************************************/ -/* MISC2 :: META_DATA_LENGTH :: reserved0 [31:24] */ -#define BCHP_MISC2_META_DATA_LENGTH_reserved0_MASK 0xff000000 -#define BCHP_MISC2_META_DATA_LENGTH_reserved0_SHIFT 24 - -/* MISC2 :: META_DATA_LENGTH :: META_DATA_LENGTH [23:00] */ -#define BCHP_MISC2_META_DATA_LENGTH_META_DATA_LENGTH_MASK 0x00ffffff -#define BCHP_MISC2_META_DATA_LENGTH_META_DATA_LENGTH_SHIFT 0 - -/*************************************************************************** - *DIRECT_WINDOW_STATUS - Direct DRAM Access Window Status - ***************************************************************************/ -/* MISC2 :: DIRECT_WINDOW_STATUS :: reserved0 [31:01] */ -#define BCHP_MISC2_DIRECT_WINDOW_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_MISC2_DIRECT_WINDOW_STATUS_reserved0_SHIFT 1 - -/* MISC2 :: DIRECT_WINDOW_STATUS :: DIRECT_BUSY [00:00] */ -#define BCHP_MISC2_DIRECT_WINDOW_STATUS_DIRECT_BUSY_MASK 0x00000001 -#define BCHP_MISC2_DIRECT_WINDOW_STATUS_DIRECT_BUSY_SHIFT 0 - -/*************************************************************************** - *DIRECT_WINDOW_CONTROL - Direct DRAM Access Window Control - ***************************************************************************/ -/* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_BASE_ADDR [31:16] */ -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK 0xffff0000 -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_SHIFT 16 - -/* MISC2 :: DIRECT_WINDOW_CONTROL :: reserved0 [15:02] */ -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_reserved0_MASK 0x0000fffc -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_reserved0_SHIFT 2 - -/* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_POST_WRITES [01:01] */ -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_POST_WRITES_MASK 0x00000002 -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_POST_WRITES_SHIFT 1 - -/* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_ENABLE [00:00] */ -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK 0x00000001 -#define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_SHIFT 0 - -#endif /* #ifndef BCHP_MISC2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,214 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_misc3.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:11p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:19 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:11p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MISC3_H__ -#define BCHP_MISC3_H__ - -/*************************************************************************** - *MISC3 - Registers for Reset, Options, DMA Checksums - ***************************************************************************/ -#define BCHP_MISC3_RESET_CTRL 0x00502200 /* Reset Control Register */ -#define BCHP_MISC3_RX_CHECKSUM 0x0050220c /* Pixel Receive Checksum */ -#define BCHP_MISC3_TX_CHECKSUM 0x00502210 /* Transmit Checksum */ -#define BCHP_MISC3_ECO_CTRL_CORE 0x00502214 /* ECO Core Reset Control Register */ -#define BCHP_MISC3_OPTIONS_CTRL 0x00502218 /* PCIe Options Control Register */ -#define BCHP_MISC3_SW_ARB_CTRL 0x00502220 /* Software Arbitration Register */ -#define BCHP_MISC3_HIF_RX_CHECKSUM 0x00502224 /* HIF Receive Checksum */ -#define BCHP_MISC3_META_CHECKSUM 0x00502228 /* Meta Data Checksum */ -#define BCHP_MISC3_MEMORY_CTRL 0x0050222c /* Memory Control Register */ - -/*************************************************************************** - *RESET_CTRL - Reset Control Register - ***************************************************************************/ -/* MISC3 :: RESET_CTRL :: reserved0 [31:09] */ -#define BCHP_MISC3_RESET_CTRL_reserved0_MASK 0xfffffe00 -#define BCHP_MISC3_RESET_CTRL_reserved0_SHIFT 9 - -/* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */ -#define BCHP_MISC3_RESET_CTRL_PLL_RESET_MASK 0x00000100 -#define BCHP_MISC3_RESET_CTRL_PLL_RESET_SHIFT 8 - -/* MISC3 :: RESET_CTRL :: reserved1 [07:03] */ -#define BCHP_MISC3_RESET_CTRL_reserved1_MASK 0x000000f8 -#define BCHP_MISC3_RESET_CTRL_reserved1_SHIFT 3 - -/* MISC3 :: RESET_CTRL :: LOW_POWER [02:02] */ -#define BCHP_MISC3_RESET_CTRL_LOW_POWER_MASK 0x00000004 -#define BCHP_MISC3_RESET_CTRL_LOW_POWER_SHIFT 2 - -/* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */ -#define BCHP_MISC3_RESET_CTRL_POR_RESET_MASK 0x00000002 -#define BCHP_MISC3_RESET_CTRL_POR_RESET_SHIFT 1 - -/* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */ -#define BCHP_MISC3_RESET_CTRL_CORE_RESET_MASK 0x00000001 -#define BCHP_MISC3_RESET_CTRL_CORE_RESET_SHIFT 0 - -/*************************************************************************** - *RX_CHECKSUM - Pixel Receive Checksum - ***************************************************************************/ -/* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */ -#define BCHP_MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK 0xffffffff -#define BCHP_MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT 0 - -/*************************************************************************** - *TX_CHECKSUM - Transmit Checksum - ***************************************************************************/ -/* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */ -#define BCHP_MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK 0xffffffff -#define BCHP_MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT 0 - -/*************************************************************************** - *ECO_CTRL_CORE - ECO Core Reset Control Register - ***************************************************************************/ -/* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */ -#define BCHP_MISC3_ECO_CTRL_CORE_reserved0_MASK 0xffff0000 -#define BCHP_MISC3_ECO_CTRL_CORE_reserved0_SHIFT 16 - -/* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */ -#define BCHP_MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff -#define BCHP_MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0 - -/*************************************************************************** - *OPTIONS_CTRL - PCIe Options Control Register - ***************************************************************************/ -/* MISC3 :: OPTIONS_CTRL :: reserved0 [31:05] */ -#define BCHP_MISC3_OPTIONS_CTRL_reserved0_MASK 0xffffffe0 -#define BCHP_MISC3_OPTIONS_CTRL_reserved0_SHIFT 5 - -/* MISC3 :: OPTIONS_CTRL :: CQ39842_FIX_DISABLE [04:04] */ -#define BCHP_MISC3_OPTIONS_CTRL_CQ39842_FIX_DISABLE_MASK 0x00000010 -#define BCHP_MISC3_OPTIONS_CTRL_CQ39842_FIX_DISABLE_SHIFT 4 - -/* MISC3 :: OPTIONS_CTRL :: CQ35254_DISABLE [03:03] */ -#define BCHP_MISC3_OPTIONS_CTRL_CQ35254_DISABLE_MASK 0x00000008 -#define BCHP_MISC3_OPTIONS_CTRL_CQ35254_DISABLE_SHIFT 3 - -/* MISC3 :: OPTIONS_CTRL :: CQ31984_ENABLE_OPT2 [02:02] */ -#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT2_MASK 0x00000004 -#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT2_SHIFT 2 - -/* MISC3 :: OPTIONS_CTRL :: CQ31984_ENABLE_OPT1 [01:01] */ -#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT1_MASK 0x00000002 -#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT1_SHIFT 1 - -/* MISC3 :: OPTIONS_CTRL :: CQ30674_DISABLE [00:00] */ -#define BCHP_MISC3_OPTIONS_CTRL_CQ30674_DISABLE_MASK 0x00000001 -#define BCHP_MISC3_OPTIONS_CTRL_CQ30674_DISABLE_SHIFT 0 - -/*************************************************************************** - *SW_ARB_CTRL - Software Arbitration Register - ***************************************************************************/ -/* MISC3 :: SW_ARB_CTRL :: reserved0 [31:08] */ -#define BCHP_MISC3_SW_ARB_CTRL_reserved0_MASK 0xffffff00 -#define BCHP_MISC3_SW_ARB_CTRL_reserved0_SHIFT 8 - -/* MISC3 :: SW_ARB_CTRL :: req1 [07:07] */ -#define BCHP_MISC3_SW_ARB_CTRL_req1_MASK 0x00000080 -#define BCHP_MISC3_SW_ARB_CTRL_req1_SHIFT 7 - -/* MISC3 :: SW_ARB_CTRL :: arb_won1 [06:06] */ -#define BCHP_MISC3_SW_ARB_CTRL_arb_won1_MASK 0x00000040 -#define BCHP_MISC3_SW_ARB_CTRL_arb_won1_SHIFT 6 - -/* MISC3 :: SW_ARB_CTRL :: reserved1 [05:04] */ -#define BCHP_MISC3_SW_ARB_CTRL_reserved1_MASK 0x00000030 -#define BCHP_MISC3_SW_ARB_CTRL_reserved1_SHIFT 4 - -/* MISC3 :: SW_ARB_CTRL :: req0 [03:03] */ -#define BCHP_MISC3_SW_ARB_CTRL_req0_MASK 0x00000008 -#define BCHP_MISC3_SW_ARB_CTRL_req0_SHIFT 3 - -/* MISC3 :: SW_ARB_CTRL :: arb_won0 [02:02] */ -#define BCHP_MISC3_SW_ARB_CTRL_arb_won0_MASK 0x00000004 -#define BCHP_MISC3_SW_ARB_CTRL_arb_won0_SHIFT 2 - -/* MISC3 :: SW_ARB_CTRL :: req_clr0 [01:01] */ -#define BCHP_MISC3_SW_ARB_CTRL_req_clr0_MASK 0x00000002 -#define BCHP_MISC3_SW_ARB_CTRL_req_clr0_SHIFT 1 - -/* MISC3 :: SW_ARB_CTRL :: req_set0 [00:00] */ -#define BCHP_MISC3_SW_ARB_CTRL_req_set0_MASK 0x00000001 -#define BCHP_MISC3_SW_ARB_CTRL_req_set0_SHIFT 0 - -/*************************************************************************** - *HIF_RX_CHECKSUM - HIF Receive Checksum - ***************************************************************************/ -/* MISC3 :: HIF_RX_CHECKSUM :: HIF_RX_CHECKSUM [31:00] */ -#define BCHP_MISC3_HIF_RX_CHECKSUM_HIF_RX_CHECKSUM_MASK 0xffffffff -#define BCHP_MISC3_HIF_RX_CHECKSUM_HIF_RX_CHECKSUM_SHIFT 0 - -/*************************************************************************** - *META_CHECKSUM - Meta Data Checksum - ***************************************************************************/ -/* MISC3 :: META_CHECKSUM :: META_CHECKSUM [31:00] */ -#define BCHP_MISC3_META_CHECKSUM_META_CHECKSUM_MASK 0xffffffff -#define BCHP_MISC3_META_CHECKSUM_META_CHECKSUM_SHIFT 0 - -/*************************************************************************** - *MEMORY_CTRL - Memory Control Register - ***************************************************************************/ -/* MISC3 :: MEMORY_CTRL :: reserved0 [31:06] */ -#define BCHP_MISC3_MEMORY_CTRL_reserved0_MASK 0xffffffc0 -#define BCHP_MISC3_MEMORY_CTRL_reserved0_SHIFT 6 - -/* MISC3 :: MEMORY_CTRL :: TM_DLL_RETRY [05:04] */ -#define BCHP_MISC3_MEMORY_CTRL_TM_DLL_RETRY_MASK 0x00000030 -#define BCHP_MISC3_MEMORY_CTRL_TM_DLL_RETRY_SHIFT 4 - -/* MISC3 :: MEMORY_CTRL :: TM_TXDMA_BUFFER [03:02] */ -#define BCHP_MISC3_MEMORY_CTRL_TM_TXDMA_BUFFER_MASK 0x0000000c -#define BCHP_MISC3_MEMORY_CTRL_TM_TXDMA_BUFFER_SHIFT 2 - -/* MISC3 :: MEMORY_CTRL :: TM_BC_FIFO [01:00] */ -#define BCHP_MISC3_MEMORY_CTRL_TM_BC_FIFO_MASK 0x00000003 -#define BCHP_MISC3_MEMORY_CTRL_TM_BC_FIFO_SHIFT 0 - -#endif /* #ifndef BCHP_MISC3_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_gr_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_gr_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_gr_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_gr_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,116 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_misc_gr_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:12p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:46 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc_gr_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:12p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MISC_GR_BRIDGE_H__ -#define BCHP_MISC_GR_BRIDGE_H__ - -/*************************************************************************** - *MISC_GR_BRIDGE - MISC's GR-Bridge related registers - ***************************************************************************/ -#define BCHP_MISC_GR_BRIDGE_REVISION 0x005023e0 /* GR Bridge Revision */ -#define BCHP_MISC_GR_BRIDGE_CTRL 0x005023e4 /* GR Bridge Control Register */ -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x005023e8 /* GR Bridge Software Reset 0 Register */ -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x005023ec /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define BCHP_MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define BCHP_MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define BCHP_MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define BCHP_MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define BCHP_MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - -/*************************************************************************** - *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - -#endif /* #ifndef BCHP_MISC_GR_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,230 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_misc_perst.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:12p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:23 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:12p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MISC_PERST_H__ -#define BCHP_MISC_PERST_H__ - -/*************************************************************************** - *MISC_PERST - Registers for Link reset on PERST_N - ***************************************************************************/ -#define BCHP_MISC_PERST_ECO_CTRL_PERST 0x00502280 /* ECO PCIE Reset Control Register */ -#define BCHP_MISC_PERST_DECODER_CTRL 0x00502284 /* Decoder Control Register */ -#define BCHP_MISC_PERST_CCE_STATUS 0x00502288 /* Config Copy Engine Status */ -#define BCHP_MISC_PERST_PCIE_DEBUG 0x0050228c /* PCIE Debug Control Register */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS 0x00502290 /* PCIE Debug Status Register */ -#define BCHP_MISC_PERST_PCIE_LTSSM_STATUS 0x00502294 /* PCIE LTSSM Status Register */ -#define BCHP_MISC_PERST_CLOCK_CTRL 0x0050229c /* Clock Control Register */ - -/*************************************************************************** - *ECO_CTRL_PERST - ECO PCIE Reset Control Register - ***************************************************************************/ -/* MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */ -#define BCHP_MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000 -#define BCHP_MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16 - -/* MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */ -#define BCHP_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff -#define BCHP_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0 - -/*************************************************************************** - *DECODER_CTRL - Decoder Control Register - ***************************************************************************/ -/* MISC_PERST :: DECODER_CTRL :: reserved0 [31:05] */ -#define BCHP_MISC_PERST_DECODER_CTRL_reserved0_MASK 0xffffffe0 -#define BCHP_MISC_PERST_DECODER_CTRL_reserved0_SHIFT 5 - -/* MISC_PERST :: DECODER_CTRL :: STOP_CLK_OUT [04:04] */ -#define BCHP_MISC_PERST_DECODER_CTRL_STOP_CLK_OUT_MASK 0x00000010 -#define BCHP_MISC_PERST_DECODER_CTRL_STOP_CLK_OUT_SHIFT 4 - -/* MISC_PERST :: DECODER_CTRL :: reserved1 [03:01] */ -#define BCHP_MISC_PERST_DECODER_CTRL_reserved1_MASK 0x0000000e -#define BCHP_MISC_PERST_DECODER_CTRL_reserved1_SHIFT 1 - -/* MISC_PERST :: DECODER_CTRL :: BCM2727_RUN [00:00] */ -#define BCHP_MISC_PERST_DECODER_CTRL_BCM2727_RUN_MASK 0x00000001 -#define BCHP_MISC_PERST_DECODER_CTRL_BCM2727_RUN_SHIFT 0 - -/*************************************************************************** - *CCE_STATUS - Config Copy Engine Status - ***************************************************************************/ -/* MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */ -#define BCHP_MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000 -#define BCHP_MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31 - -/* MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */ -#define BCHP_MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8 -#define BCHP_MISC_PERST_CCE_STATUS_reserved0_SHIFT 3 - -/* MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */ -#define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004 -#define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2 - -/* MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */ -#define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002 -#define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1 - -/* MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */ -#define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001 -#define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0 - -/*************************************************************************** - *PCIE_DEBUG - PCIE Debug Control Register - ***************************************************************************/ -/* MISC_PERST :: PCIE_DEBUG :: SERDES_TERM_CNT [31:16] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_MASK 0xffff0000 -#define BCHP_MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_SHIFT 16 - -/* MISC_PERST :: PCIE_DEBUG :: reserved0 [15:13] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_reserved0_MASK 0x0000e000 -#define BCHP_MISC_PERST_PCIE_DEBUG_reserved0_SHIFT 13 - -/* MISC_PERST :: PCIE_DEBUG :: FORCE_CLOCK_SWITCH [12:12] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_FORCE_CLOCK_SWITCH_MASK 0x00001000 -#define BCHP_MISC_PERST_PCIE_DEBUG_FORCE_CLOCK_SWITCH_SHIFT 12 - -/* MISC_PERST :: PCIE_DEBUG :: CLKREQ_PLLPD_EXTEND_DISABLE [11:11] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_CLKREQ_PLLPD_EXTEND_DISABLE_MASK 0x00000800 -#define BCHP_MISC_PERST_PCIE_DEBUG_CLKREQ_PLLPD_EXTEND_DISABLE_SHIFT 11 - -/* MISC_PERST :: PCIE_DEBUG :: PLL_VCO_RESCUE [10:10] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_MASK 0x00000400 -#define BCHP_MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_SHIFT 10 - -/* MISC_PERST :: PCIE_DEBUG :: PLL_PDN_OVERRIDE [09:09] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_MASK 0x00000200 -#define BCHP_MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_SHIFT 9 - -/* MISC_PERST :: PCIE_DEBUG :: CORE_CLOCK_OVR [08:08] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_MASK 0x00000100 -#define BCHP_MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_SHIFT 8 - -/* MISC_PERST :: PCIE_DEBUG :: reserved1 [07:04] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_reserved1_MASK 0x000000f0 -#define BCHP_MISC_PERST_PCIE_DEBUG_reserved1_SHIFT 4 - -/* MISC_PERST :: PCIE_DEBUG :: PCIE_TMUX_SEL [03:00] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_MASK 0x0000000f -#define BCHP_MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_SHIFT 0 - -/*************************************************************************** - *PCIE_DEBUG_STATUS - PCIE Debug Status Register - ***************************************************************************/ -/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved0 [31:20] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved0_MASK 0xfff00000 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved0_SHIFT 20 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PCS_LINK_IN_L2 [19:19] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L2_MASK 0x00080000 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L2_SHIFT 19 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PCS_LINK_IN_L1 [18:18] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L1_MASK 0x00040000 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L1_SHIFT 18 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PCS_LINK_IN_L0S [17:17] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L0S_MASK 0x00020000 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L0S_SHIFT 17 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PCIE_IDLE [16:16] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCIE_IDLE_MASK 0x00010000 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCIE_IDLE_SHIFT 16 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved1 [15:06] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved1_MASK 0x0000ffc0 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved1_SHIFT 6 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATALINKATTN [05:05] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_MASK 0x00000020 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_SHIFT 5 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHYLINKATTN [04:04] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_MASK 0x00000010 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_SHIFT 4 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved2 [03:02] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved2_MASK 0x0000000c -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved2_SHIFT 2 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATA_LINKUP [01:01] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_MASK 0x00000002 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_SHIFT 1 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHY_LINKUP [00:00] */ -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_MASK 0x00000001 -#define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_SHIFT 0 - -/*************************************************************************** - *PCIE_LTSSM_STATUS - PCIE LTSSM Status Register - ***************************************************************************/ -/* MISC_PERST :: PCIE_LTSSM_STATUS :: LTSSM_VECTOR [31:00] */ -#define BCHP_MISC_PERST_PCIE_LTSSM_STATUS_LTSSM_VECTOR_MASK 0xffffffff -#define BCHP_MISC_PERST_PCIE_LTSSM_STATUS_LTSSM_VECTOR_SHIFT 0 - -/*************************************************************************** - *CLOCK_CTRL - Clock Control Register - ***************************************************************************/ -/* MISC_PERST :: CLOCK_CTRL :: reserved0 [31:03] */ -#define BCHP_MISC_PERST_CLOCK_CTRL_reserved0_MASK 0xfffffff8 -#define BCHP_MISC_PERST_CLOCK_CTRL_reserved0_SHIFT 3 - -/* MISC_PERST :: CLOCK_CTRL :: EARLY_L1_EXIT [02:02] */ -#define BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_MASK 0x00000004 -#define BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_SHIFT 2 - -/* MISC_PERST :: CLOCK_CTRL :: STOP_CORE_CLK [01:01] */ -#define BCHP_MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_MASK 0x00000002 -#define BCHP_MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_SHIFT 1 - -/* MISC_PERST :: CLOCK_CTRL :: SEL_ALT_CLK [00:00] */ -#define BCHP_MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_MASK 0x00000001 -#define BCHP_MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_SHIFT 0 - -#endif /* #ifndef BCHP_MISC_PERST_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mmscram.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mmscram.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mmscram.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mmscram.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_mmscram.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:12p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:09 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mmscram.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:12p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_MMSCRAM_H__ -#define BCHP_MMSCRAM_H__ - -/*************************************************************************** - *MMSCRAM - MMSCRAM Registers - ***************************************************************************/ -#define BCHP_MMSCRAM_RSV_S 0x000fd000 /* RESERVED */ -#define BCHP_MMSCRAM_RSV_E 0x000feffc /* RESERVED */ - -/*************************************************************************** - *RSV_S - RESERVED - ***************************************************************************/ -/* MMSCRAM :: RSV_S :: reserved0 [31:00] */ -#define BCHP_MMSCRAM_RSV_S_reserved0_MASK 0xffffffff -#define BCHP_MMSCRAM_RSV_S_reserved0_SHIFT 0 - -/*************************************************************************** - *RSV_E - RESERVED - ***************************************************************************/ -/* MMSCRAM :: RSV_E :: reserved0 [31:00] */ -#define BCHP_MMSCRAM_RSV_E_reserved0_MASK 0xffffffff -#define BCHP_MMSCRAM_RSV_E_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_MMSCRAM_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_cfg.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_cfg.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_cfg.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_cfg.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,2130 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pcie_cfg.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:12p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:54 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_cfg.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:12p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PCIE_CFG_H__ -#define BCHP_PCIE_CFG_H__ - -/*************************************************************************** - *PCIE_CFG - PCIE Config related registers - ***************************************************************************/ -#define BCHP_PCIE_CFG_DEVICE_VENDOR_ID 0x00500000 /* DEVICE_VENDOR_ID Register */ -#define BCHP_PCIE_CFG_STATUS_COMMAND 0x00500004 /* STATUS_COMMAND Register */ -#define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID 0x00500008 /* PCI_CLASSCODE_AND_REVISION_ID Register */ -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE 0x0050000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_1 0x00500010 /* BASE_ADDRESS_1 Register */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_2 0x00500014 /* BASE_ADDRESS_2 Register */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_3 0x00500018 /* BASE_ADDRESS_3 Register */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_4 0x0050001c /* BASE_ADDRESS_4 Register */ -#define BCHP_PCIE_CFG_CARDBUS_CIS_POINTER 0x00500028 /* CARDBUS_CIS_POINTER Register */ -#define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID 0x0050002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS 0x00500030 /* EXPANSION_ROM_BASE_ADDRESS Register */ -#define BCHP_PCIE_CFG_CAPABILITIES_POINTER 0x00500034 /* CAPABILITIES_POINTER Register */ -#define BCHP_PCIE_CFG_INTERRUPT 0x0050003c /* INTERRUPT Register */ -#define BCHP_PCIE_CFG_VPD_CAPABILITIES 0x00500040 /* VPD_CAPABILITIES Register */ -#define BCHP_PCIE_CFG_VPD_DATA 0x00500044 /* VPD_DATA Register */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY 0x00500048 /* POWER_MANAGEMENT_CAPABILITY Register */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS 0x0050004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER 0x00500050 /* MSI_CAPABILITY_HEADER Register */ -#define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS 0x00500054 /* MSI_LOWER_ADDRESS Register */ -#define BCHP_PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER 0x00500058 /* MSI_UPPER_ADDRESS_REGISTER Register */ -#define BCHP_PCIE_CFG_MSI_DATA 0x0050005c /* MSI_DATA Register */ -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER 0x00500060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */ -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES 0x00500064 /* RESET_COUNTERS_INITIAL_VALUES Register */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL 0x00500068 /* MISCELLANEOUS_HOST_CONTROL Register */ -#define BCHP_PCIE_CFG_SPARE 0x0050006c /* SPARE Register */ -#define BCHP_PCIE_CFG_PCI_STATE 0x00500070 /* PCI_STATE Register */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL 0x00500074 /* CLOCK_CONTROL Register */ -#define BCHP_PCIE_CFG_REGISTER_BASE 0x00500078 /* REGISTER_BASE Register */ -#define BCHP_PCIE_CFG_MEMORY_BASE 0x0050007c /* MEMORY_BASE Register */ -#define BCHP_PCIE_CFG_REGISTER_DATA 0x00500080 /* REGISTER_DATA Register */ -#define BCHP_PCIE_CFG_MEMORY_DATA 0x00500084 /* MEMORY_DATA Register */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE 0x00500088 /* EXPANSION_ROM_BAR_SIZE Register */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_ADDRESS 0x0050008c /* EXPANSION_ROM_ADDRESS Register */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_DATA 0x00500090 /* EXPANSION_ROM_DATA Register */ -#define BCHP_PCIE_CFG_VPD_INTERFACE 0x00500094 /* VPD_INTERFACE Register */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER 0x00500098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER 0x0050009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER 0x005000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER 0x005000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */ -#define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER 0x005000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */ -#define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER 0x005000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */ -#define BCHP_PCIE_CFG_INT_MAILBOX_UPPER 0x005000b0 /* INT_MAILBOX_UPPER Register */ -#define BCHP_PCIE_CFG_INT_MAILBOX_LOWER 0x005000b4 /* INT_MAILBOX_LOWER Register */ -#define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION 0x005000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT 0x005000c0 /* FUNCTION_EVENT Register */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK 0x005000c4 /* FUNCTION_EVENT_MASK Register */ -#define BCHP_PCIE_CFG_FUNCTION_PRESENT 0x005000c8 /* FUNCTION_PRESENT Register */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES 0x005000cc /* PCIE_CAPABILITIES Register */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES 0x005000d0 /* DEVICE_CAPABILITIES Register */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL 0x005000d4 /* DEVICE_STATUS_CONTROL Register */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY 0x005000d8 /* LINK_CAPABILITY Register */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL 0x005000dc /* LINK_STATUS_CONTROL Register */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2 0x005000f0 /* DEVICE_CAPABILITIES_2 Register */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2 0x005000f4 /* DEVICE_STATUS_CONTROL_2 Register */ -#define BCHP_PCIE_CFG_LINK_CAPABILITIES_2 0x005000f8 /* LINK_CAPABILITIES_2 Register */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_2 0x005000fc /* LINK_STATUS_CONTROL_2 Register */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER 0x00500100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS 0x00500104 /* UNCORRECTABLE_ERROR_STATUS Register */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK 0x00500108 /* UNCORRECTABLE_ERROR_MASK Register */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY 0x0050010c /* UNCORRECTABLE_ERROR_SEVERITY Register */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS 0x00500110 /* CORRECTABLE_ERROR_STATUS Register */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK 0x00500114 /* CORRECTABLE_ERROR_MASK Register */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL 0x00500118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */ -#define BCHP_PCIE_CFG_HEADER_LOG_1 0x0050011c /* HEADER_LOG_1 Register */ -#define BCHP_PCIE_CFG_HEADER_LOG_2 0x00500120 /* HEADER_LOG_2 Register */ -#define BCHP_PCIE_CFG_HEADER_LOG_3 0x00500124 /* HEADER_LOG_3 Register */ -#define BCHP_PCIE_CFG_HEADER_LOG_4 0x00500128 /* HEADER_LOG_4 Register */ -#define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER 0x0050013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY 0x00500140 /* PORT_VC_CAPABILITY Register */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2 0x00500144 /* PORT_VC_CAPABILITY_2 Register */ -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL 0x00500148 /* PORT_VC_STATUS_CONTROL Register */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY 0x0050014c /* VC_RESOURCE_CAPABILITY Register */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL 0x00500150 /* VC_RESOURCE_CONTROL Register */ -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS 0x00500154 /* VC_RESOURCE_STATUS Register */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER 0x00500160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW 0x00500164 /* DEVICE_SERIAL_NO_LOWER_DW Register */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW 0x00500168 /* DEVICE_SERIAL_NO_UPPER_DW Register */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER 0x0050016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT 0x00500170 /* POWER_BUDGETING_DATA_SELECT Register */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA 0x00500174 /* POWER_BUDGETING_DATA Register */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY 0x00500178 /* POWER_BUDGETING_CAPABILITY Register */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1 0x0050017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3 0x00500180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5 0x00500184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7 0x00500188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING 0x0050018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */ - -/*************************************************************************** - *DEVICE_VENDOR_ID - DEVICE_VENDOR_ID Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ -#define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 -#define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 - -/* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ -#define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff -#define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 - -/*************************************************************************** - *STATUS_COMMAND - STATUS_COMMAND Register - ***************************************************************************/ -/* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 - -/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 - -/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 - -/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 - -/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 - -/* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 - -/* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 - -/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 - -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 - -/* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 - -/* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 - -/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 - -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 -#define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 - -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 -#define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 - -/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 -#define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 - -/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 -#define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 - -/* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 -#define BCHP_PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 - -/* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 -#define BCHP_PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 - -/* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 -#define BCHP_PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 - -/* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 -#define BCHP_PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 - -/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 -#define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 - -/* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 -#define BCHP_PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 - -/* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 -#define BCHP_PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 - -/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 -#define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 - -/* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ -#define BCHP_PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 -#define BCHP_PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 - -/*************************************************************************** - *PCI_CLASSCODE_AND_REVISION_ID - PCI_CLASSCODE_AND_REVISION_ID Register - ***************************************************************************/ -/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ -#define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 -#define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 - -/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ -#define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff -#define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 - -/*************************************************************************** - *BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE - BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register - ***************************************************************************/ -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 - -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 - -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 - -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff -#define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 - -/*************************************************************************** - *BASE_ADDRESS_1 - BASE_ADDRESS_1 Register - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 -#define BCHP_PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 - -/*************************************************************************** - *BASE_ADDRESS_2 - BASE_ADDRESS_2 Register - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff -#define BCHP_PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 - -/*************************************************************************** - *BASE_ADDRESS_3 - BASE_ADDRESS_3 Register - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS [31:16] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_MASK 0xffff0000 -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_SHIFT 16 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [15:04] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x0000fff0 -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 -#define BCHP_PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 - -/*************************************************************************** - *BASE_ADDRESS_4 - BASE_ADDRESS_4 Register - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS [31:00] */ -#define BCHP_PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_MASK 0xffffffff -#define BCHP_PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_SHIFT 0 - -/*************************************************************************** - *CARDBUS_CIS_POINTER - CARDBUS_CIS_POINTER Register - ***************************************************************************/ -/* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ -#define BCHP_PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff -#define BCHP_PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 - -/*************************************************************************** - *SUBSYSTEM_DEVICE_VENDOR_ID - SUBSYSTEM_DEVICE_VENDOR_ID Register - ***************************************************************************/ -/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ -#define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 -#define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 - -/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ -#define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff -#define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 - -/*************************************************************************** - *EXPANSION_ROM_BASE_ADDRESS - EXPANSION_ROM_BASE_ADDRESS Register - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 -#define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 - -/*************************************************************************** - *CAPABILITIES_POINTER - CAPABILITIES_POINTER Register - ***************************************************************************/ -/* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ -#define BCHP_PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff -#define BCHP_PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 - -/*************************************************************************** - *INTERRUPT - INTERRUPT Register - ***************************************************************************/ -/* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ -#define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 - -/* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ -#define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff -#define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 - -/*************************************************************************** - *VPD_CAPABILITIES - VPD_CAPABILITIES Register - ***************************************************************************/ -/* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ -#define BCHP_PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff -#define BCHP_PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 - -/*************************************************************************** - *VPD_DATA - VPD_DATA Register - ***************************************************************************/ -/* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ -#define BCHP_PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff -#define BCHP_PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 - -/*************************************************************************** - *POWER_MANAGEMENT_CAPABILITY - POWER_MANAGEMENT_CAPABILITY Register - ***************************************************************************/ -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *POWER_MANAGEMENT_CONTROL_STATUS - POWER_MANAGEMENT_CONTROL_STATUS Register - ***************************************************************************/ -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 -#define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 - -/*************************************************************************** - *MSI_CAPABILITY_HEADER - MSI_CAPABILITY_HEADER Register - ***************************************************************************/ -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff -#define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *MSI_LOWER_ADDRESS - MSI_LOWER_ADDRESS Register - ***************************************************************************/ -/* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ -#define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc -#define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 - -/* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ -#define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 -#define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 - -/*************************************************************************** - *MSI_UPPER_ADDRESS_REGISTER - MSI_UPPER_ADDRESS_REGISTER Register - ***************************************************************************/ -/* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ -#define BCHP_PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff -#define BCHP_PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 - -/*************************************************************************** - *MSI_DATA - MSI_DATA Register - ***************************************************************************/ -/* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ -#define BCHP_PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff -#define BCHP_PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 - -/*************************************************************************** - *BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER - BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register - ***************************************************************************/ -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff -#define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *RESET_COUNTERS_INITIAL_VALUES - RESET_COUNTERS_INITIAL_VALUES Register - ***************************************************************************/ -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff -#define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 - -/*************************************************************************** - *MISCELLANEOUS_HOST_CONTROL - MISCELLANEOUS_HOST_CONTROL Register - ***************************************************************************/ -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BOUNDARY_CHECK [13:13] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x00002000 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BYTE_ENABLE_RULE_CHECK [12:12] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x00001000 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: INTERRUPT_CHECK [11:11] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x00000800 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: RCB_CHECK [10:10] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x00000400 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TAGGED_STATUS_MODE [09:09] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x00000200 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT_MODE [08:08] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x00000100 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_INDIRECT_ACCESS [07:07] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x00000080 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_REGISTER_WORD_SWAP [06:06] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x00000040 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY [05:05] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000020 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_SHIFT 5 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY [04:04] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000010 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_SHIFT 4 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_WORD_SWAP [03:03] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x00000008 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_BYTE_SWAP [02:02] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x00000004 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT [01:01] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x00000002 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: CLEAR_INTERRUPT [00:00] */ -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x00000001 -#define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0 - -/*************************************************************************** - *SPARE - SPARE Register - ***************************************************************************/ -/* PCIE_CFG :: SPARE :: UNUSED_0 [31:16] */ -#define BCHP_PCIE_CFG_SPARE_UNUSED_0_MASK 0xffff0000 -#define BCHP_PCIE_CFG_SPARE_UNUSED_0_SHIFT 16 - -/* PCIE_CFG :: SPARE :: RESERVED_0 [15:15] */ -#define BCHP_PCIE_CFG_SPARE_RESERVED_0_MASK 0x00008000 -#define BCHP_PCIE_CFG_SPARE_RESERVED_0_SHIFT 15 - -/* PCIE_CFG :: SPARE :: UNUSED_1 [14:02] */ -#define BCHP_PCIE_CFG_SPARE_UNUSED_1_MASK 0x00007ffc -#define BCHP_PCIE_CFG_SPARE_UNUSED_1_SHIFT 2 - -/* PCIE_CFG :: SPARE :: BAR2_TARGET_WORD_SWAP [01:01] */ -#define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_MASK 0x00000002 -#define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_SHIFT 1 - -/* PCIE_CFG :: SPARE :: BAR2_TARGET_BYTE_SWAP [00:00] */ -#define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_MASK 0x00000001 -#define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_SHIFT 0 - -/*************************************************************************** - *PCI_STATE - PCI_STATE Register - ***************************************************************************/ -/* PCIE_CFG :: PCI_STATE :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_CFG_PCI_STATE_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_CFG_PCI_STATE_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: PCI_STATE :: CONFIG_RETRY [15:15] */ -#define BCHP_PCIE_CFG_PCI_STATE_CONFIG_RETRY_MASK 0x00008000 -#define BCHP_PCIE_CFG_PCI_STATE_CONFIG_RETRY_SHIFT 15 - -/* PCIE_CFG :: PCI_STATE :: RESERVED_1 [14:12] */ -#define BCHP_PCIE_CFG_PCI_STATE_RESERVED_1_MASK 0x00007000 -#define BCHP_PCIE_CFG_PCI_STATE_RESERVED_1_SHIFT 12 - -/* PCIE_CFG :: PCI_STATE :: MAX_PCI_TARGET_RETRY [11:09] */ -#define BCHP_PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0x00000e00 -#define BCHP_PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9 - -/* PCIE_CFG :: PCI_STATE :: FLAT_VIEW [08:08] */ -#define BCHP_PCIE_CFG_PCI_STATE_FLAT_VIEW_MASK 0x00000100 -#define BCHP_PCIE_CFG_PCI_STATE_FLAT_VIEW_SHIFT 8 - -/* PCIE_CFG :: PCI_STATE :: VPD_AVAILABLE [07:07] */ -#define BCHP_PCIE_CFG_PCI_STATE_VPD_AVAILABLE_MASK 0x00000080 -#define BCHP_PCIE_CFG_PCI_STATE_VPD_AVAILABLE_SHIFT 7 - -/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_RETRY [06:06] */ -#define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x00000040 -#define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6 - -/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_DESIRED [05:05] */ -#define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x00000020 -#define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5 - -/* PCIE_CFG :: PCI_STATE :: RESERVED_2 [04:00] */ -#define BCHP_PCIE_CFG_PCI_STATE_RESERVED_2_MASK 0x0000001f -#define BCHP_PCIE_CFG_PCI_STATE_RESERVED_2_SHIFT 0 - -/*************************************************************************** - *CLOCK_CONTROL - CLOCK_CONTROL Register - ***************************************************************************/ -/* PCIE_CFG :: CLOCK_CONTROL :: PL_CLOCK_DISABLE [31:31] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_MASK 0x80000000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_SHIFT 31 - -/* PCIE_CFG :: CLOCK_CONTROL :: DLL_CLOCK_DISABLE [30:30] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_MASK 0x40000000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_SHIFT 30 - -/* PCIE_CFG :: CLOCK_CONTROL :: TL_CLOCK_DISABLE [29:29] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_MASK 0x20000000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_SHIFT 29 - -/* PCIE_CFG :: CLOCK_CONTROL :: PCI_EXPRESS_CLOCK_TO_CORE_CLOCK [28:28] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_MASK 0x10000000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_SHIFT 28 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_0 [27:21] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_0_MASK 0x0fe00000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_0_SHIFT 21 - -/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_FINAL_ALT_CLOCK_SOURCE [20:20] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_MASK 0x00100000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_SHIFT 20 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_1 [19:13] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_1_MASK 0x000fe000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_1_SHIFT 13 - -/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_ALT_CLOCK [12:12] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_MASK 0x00001000 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_SHIFT 12 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_2 [11:08] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_2_MASK 0x00000f00 -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_2_SHIFT 8 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_3 [07:00] */ -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_3_MASK 0x000000ff -#define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_3_SHIFT 0 - -/*************************************************************************** - *REGISTER_BASE - REGISTER_BASE Register - ***************************************************************************/ -/* PCIE_CFG :: REGISTER_BASE :: RESERVED_0 [31:18] */ -#define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_0_MASK 0xfffc0000 -#define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_0_SHIFT 18 - -/* PCIE_CFG :: REGISTER_BASE :: REGISTER_BASE_REGISTER [17:02] */ -#define BCHP_PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_MASK 0x0003fffc -#define BCHP_PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_SHIFT 2 - -/* PCIE_CFG :: REGISTER_BASE :: RESERVED_1 [01:00] */ -#define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_1_MASK 0x00000003 -#define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_1_SHIFT 0 - -/*************************************************************************** - *MEMORY_BASE - MEMORY_BASE Register - ***************************************************************************/ -/* PCIE_CFG :: MEMORY_BASE :: RESERVED_0 [31:24] */ -#define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_0_MASK 0xff000000 -#define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_0_SHIFT 24 - -/* PCIE_CFG :: MEMORY_BASE :: MEMORY_BASE_REGISTER [23:02] */ -#define BCHP_PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_MASK 0x00fffffc -#define BCHP_PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_SHIFT 2 - -/* PCIE_CFG :: MEMORY_BASE :: RESERVED_1 [01:00] */ -#define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_1_MASK 0x00000003 -#define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_1_SHIFT 0 - -/*************************************************************************** - *REGISTER_DATA - REGISTER_DATA Register - ***************************************************************************/ -/* PCIE_CFG :: REGISTER_DATA :: REGISTER_DATA_REGISTER [31:00] */ -#define BCHP_PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_MASK 0xffffffff -#define BCHP_PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_SHIFT 0 - -/*************************************************************************** - *MEMORY_DATA - MEMORY_DATA Register - ***************************************************************************/ -/* PCIE_CFG :: MEMORY_DATA :: MEMORY_DATA_REGISTER [31:00] */ -#define BCHP_PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_MASK 0xffffffff -#define BCHP_PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_SHIFT 0 - -/*************************************************************************** - *EXPANSION_ROM_BAR_SIZE - EXPANSION_ROM_BAR_SIZE Register - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: RESERVED_0 [31:04] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_MASK 0xfffffff0 -#define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_SHIFT 4 - -/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: BAR_SIZE [03:00] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_MASK 0x0000000f -#define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_SHIFT 0 - -/*************************************************************************** - *EXPANSION_ROM_ADDRESS - EXPANSION_ROM_ADDRESS Register - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_ADDRESS :: ROM_CTL_ADDR [31:00] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_MASK 0xffffffff -#define BCHP_PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_SHIFT 0 - -/*************************************************************************** - *EXPANSION_ROM_DATA - EXPANSION_ROM_DATA Register - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_DATA :: ROM_DATA [31:00] */ -#define BCHP_PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_MASK 0xffffffff -#define BCHP_PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_SHIFT 0 - -/*************************************************************************** - *VPD_INTERFACE - VPD_INTERFACE Register - ***************************************************************************/ -/* PCIE_CFG :: VPD_INTERFACE :: RESERVED_0 [31:01] */ -#define BCHP_PCIE_CFG_VPD_INTERFACE_RESERVED_0_MASK 0xfffffffe -#define BCHP_PCIE_CFG_VPD_INTERFACE_RESERVED_0_SHIFT 1 - -/* PCIE_CFG :: VPD_INTERFACE :: VPD_REQUEST [00:00] */ -#define BCHP_PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_MASK 0x00000001 -#define BCHP_PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_SHIFT 0 - -/*************************************************************************** - *UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER - UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff -#define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 - -/*************************************************************************** - *UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER - UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff -#define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 - -/*************************************************************************** - *UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER - UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff -#define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 - -/*************************************************************************** - *UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER - UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ -#define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff -#define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 - -/*************************************************************************** - *UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER - UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register - ***************************************************************************/ -/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ -#define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff -#define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 - -/*************************************************************************** - *UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER - UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register - ***************************************************************************/ -/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ -#define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff -#define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 - -/*************************************************************************** - *INT_MAILBOX_UPPER - INT_MAILBOX_UPPER Register - ***************************************************************************/ -/* PCIE_CFG :: INT_MAILBOX_UPPER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ -#define BCHP_PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff -#define BCHP_PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 - -/*************************************************************************** - *INT_MAILBOX_LOWER - INT_MAILBOX_LOWER Register - ***************************************************************************/ -/* PCIE_CFG :: INT_MAILBOX_LOWER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ -#define BCHP_PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff -#define BCHP_PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 - -/*************************************************************************** - *PRODUCT_ID_AND_ASIC_REVISION - PRODUCT_ID_AND_ASIC_REVISION Register - ***************************************************************************/ -/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: RESERVED_0 [31:28] */ -#define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_MASK 0xf0000000 -#define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_SHIFT 28 - -/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: PRODUCT_ID [27:08] */ -#define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_MASK 0x0fffff00 -#define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_SHIFT 8 - -/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: ASIC_REVISION_ID [07:00] */ -#define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_MASK 0x000000ff -#define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_SHIFT 0 - -/*************************************************************************** - *FUNCTION_EVENT - FUNCTION_EVENT Register - ***************************************************************************/ -/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: FUNCTION_EVENT :: INTA_EVENT [15:15] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_MASK 0x00008000 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_SHIFT 15 - -/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_1 [14:05] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_1_MASK 0x00007fe0 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: FUNCTION_EVENT :: GWAKE_EVENT [04:04] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_MASK 0x00000010 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_SHIFT 4 - -/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_2 [03:00] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_2_MASK 0x0000000f -#define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_2_SHIFT 0 - -/*************************************************************************** - *FUNCTION_EVENT_MASK - FUNCTION_EVENT_MASK Register - ***************************************************************************/ -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: INTA_MASK [15:15] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_MASK 0x00008000 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_SHIFT 15 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: WAKE_UP_MASK [14:14] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_MASK 0x00004000 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_SHIFT 14 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_1 [13:05] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_MASK 0x00003fe0 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: GWAKE_MASK [04:04] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_MASK 0x00000010 -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_SHIFT 4 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_2 [03:00] */ -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_MASK 0x0000000f -#define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_SHIFT 0 - -/*************************************************************************** - *FUNCTION_PRESENT - FUNCTION_PRESENT Register - ***************************************************************************/ -/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: FUNCTION_PRESENT :: INTA_STATUS [15:15] */ -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_MASK 0x00008000 -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_SHIFT 15 - -/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_1 [14:05] */ -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_MASK 0x00007fe0 -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: FUNCTION_PRESENT :: PME_STATUS [04:04] */ -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_MASK 0x00000010 -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_SHIFT 4 - -/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_2 [03:00] */ -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_MASK 0x0000000f -#define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_SHIFT 0 - -/*************************************************************************** - *PCIE_CAPABILITIES - PCIE_CAPABILITIES Register - ***************************************************************************/ -/* PCIE_CFG :: PCIE_CAPABILITIES :: RESERVED_0 [31:30] */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_MASK 0xc0000000 -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_SHIFT 30 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: INTERRUPT_MESSAGE_NUMBER [29:25] */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_MASK 0x3e000000 -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_SHIFT 25 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: SLOT_IMPLEMENTED [24:24] */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_MASK 0x01000000 -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_SHIFT 24 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: DEVICE_PORT_TYPE [23:20] */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_MASK 0x00f00000 -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_SHIFT 20 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_VERSION [19:16] */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_MASK 0x000f0000 -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: NEXT_POINTER [15:08] */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_ID [07:00] */ -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_MASK 0x000000ff -#define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *DEVICE_CAPABILITIES - DEVICE_CAPABILITIES Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_0 [31:28] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_MASK 0xf0000000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_SHIFT 28 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_SCALE [27:26] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_MASK 0x0c000000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_SHIFT 26 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_VALUE [25:18] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_MASK 0x03fc0000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_SHIFT 18 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_1 [17:16] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_MASK 0x00030000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_SHIFT 16 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ROLE_BASED_ERROR_SUPPORT [15:15] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_MASK 0x00008000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_SHIFT 15 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: POWER_INDICATOR_PRESENT [14:14] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_MASK 0x00004000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_SHIFT 14 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_INDICATOR_PRESENT [13:13] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_MASK 0x00002000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_SHIFT 13 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_BUTTON_PRESENT [12:12] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_MASK 0x00001000 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_SHIFT 12 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L1_ACCEPTABLE_LATENCY [11:09] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_SHIFT 9 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L0S_ACCEPTABLE_LATENCY [08:06] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_SHIFT 6 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: EXTENDED_TAG_FIELD_SUPPORTED [05:05] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_MASK 0x00000020 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_SHIFT 5 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: PHANTOM_FUNCTIONS_SUPPORTED [04:03] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_MASK 0x00000018 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_SHIFT 3 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: MAX_PAYLOAD_SIZE_SUPPORTED [02:00] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_MASK 0x00000007 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_SHIFT 0 - -/*************************************************************************** - *DEVICE_STATUS_CONTROL - DEVICE_STATUS_CONTROL Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_0 [31:22] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_MASK 0xffc00000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_SHIFT 22 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: TRANSACTION_PENDING [21:21] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_MASK 0x00200000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_SHIFT 21 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_DETECTED [20:20] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_MASK 0x00100000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_SHIFT 20 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_DETECTED [19:19] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_MASK 0x00080000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_SHIFT 19 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_DETECTED [18:18] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_MASK 0x00040000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_SHIFT 18 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_DETECTED [17:17] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_MASK 0x00020000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_SHIFT 17 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_DETECTED [16:16] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_MASK 0x00010000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_SHIFT 16 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_1 [15:15] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_MASK 0x00008000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_SHIFT 15 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_READ_REQUEST_SIZE [14:12] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_MASK 0x00007000 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_SHIFT 12 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLE_NO_SNOOP [11:11] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_MASK 0x00000800 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_SHIFT 11 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_PM_ENABLE [10:10] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_MASK 0x00000400 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_SHIFT 10 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: PHANTOM_FUNCTIONS_ENABLE [09:09] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_MASK 0x00000200 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_SHIFT 9 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_FIELD_ENABLE [08:08] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_MASK 0x00000100 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_SHIFT 8 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLED_RELAXED_ORDERING [04:04] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_MASK 0x00000010 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_SHIFT 4 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_REPORTING_ENABLE [03:03] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_MASK 0x00000008 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_SHIFT 3 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_REPORTING_ENABLED [02:02] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000004 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_SHIFT 2 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_REPORTING_ENABLED [01:01] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000002 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_SHIFT 1 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_REPORTING_ENABLED [00:00] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_MASK 0x00000001 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_SHIFT 0 - -/*************************************************************************** - *LINK_CAPABILITY - LINK_CAPABILITY Register - ***************************************************************************/ -/* PCIE_CFG :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000 -#define BCHP_PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24 - -/* PCIE_CFG :: LINK_CAPABILITY :: RESERVED_0 [23:19] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_RESERVED_0_MASK 0x00f80000 -#define BCHP_PCIE_CFG_LINK_CAPABILITY_RESERVED_0_SHIFT 19 - -/* PCIE_CFG :: LINK_CAPABILITY :: CLOCK_POWER_MANAGEMENT [18:18] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_MASK 0x00040000 -#define BCHP_PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_SHIFT 18 - -/* PCIE_CFG :: LINK_CAPABILITY :: L1_EXIT_LATENCY [17:15] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_MASK 0x00038000 -#define BCHP_PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_SHIFT 15 - -/* PCIE_CFG :: LINK_CAPABILITY :: L0S_EXIT_LATENCY [14:12] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_MASK 0x00007000 -#define BCHP_PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_SHIFT 12 - -/* PCIE_CFG :: LINK_CAPABILITY :: ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT [11:10] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_MASK 0x00000c00 -#define BCHP_PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_SHIFT 10 - -/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_WIDTH [09:04] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_MASK 0x000003f0 -#define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_SHIFT 4 - -/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_SPEED [03:00] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_MASK 0x0000000f -#define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_SHIFT 0 - -/*************************************************************************** - *LINK_STATUS_CONTROL - LINK_STATUS_CONTROL Register - ***************************************************************************/ -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_0 [31:29] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_MASK 0xe0000000 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_SHIFT 29 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: SLOT_CLOCK_CONFIGURATION [28:28] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_MASK 0x10000000 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_SHIFT 28 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_1 [27:26] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_MASK 0x0c000000 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_SHIFT 26 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: NEGOTIATED_LINK_WIDTH [25:20] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x03f00000 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: LINK_SPEED [19:16] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_MASK 0x000f0000 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_SHIFT 16 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_2 [15:09] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_MASK 0x0000fe00 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_SHIFT 9 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: CLOCK_REQUEST_ENABLE [08:08] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_MASK 0x00000100 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_SHIFT 8 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: EXTENDED_SYNCH [07:07] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_MASK 0x00000080 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_SHIFT 7 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: COMMON_CLOCK_CONFIGURATION [06:06] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_MASK 0x00000040 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_SHIFT 6 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_3 [05:05] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_MASK 0x00000020 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_SHIFT 5 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_4 [04:04] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_MASK 0x00000010 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_SHIFT 4 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: READ_COMPLETION_BOUNDARY [03:03] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_MASK 0x00000008 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_SHIFT 3 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_5 [02:02] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_MASK 0x00000004 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_SHIFT 2 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: ACTIVE_STATE_POWER_MANAGEMENT_CONTROL [01:00] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_MASK 0x00000003 -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_SHIFT 0 - -/*************************************************************************** - *DEVICE_CAPABILITIES_2 - DEVICE_CAPABILITIES_2 Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: RESERVED_0 [31:05] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_MASK 0xffffffe0 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_SHIFT 5 - -/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_DISABLE_SUPPORTED [04:04] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_MASK 0x00000010 -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_SHIFT 4 - -/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_TIMEOUT_RANGE_SUPPORTED [03:00] */ -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000f -#define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_SHIFT 0 - -/*************************************************************************** - *DEVICE_STATUS_CONTROL_2 - DEVICE_STATUS_CONTROL_2 Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: RESERVED_0 [31:05] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffe0 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_SHIFT 5 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_DISABLE [04:04] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_MASK 0x00000010 -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_SHIFT 4 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_VALUE [03:00] */ -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_MASK 0x0000000f -#define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_SHIFT 0 - -/*************************************************************************** - *LINK_CAPABILITIES_2 - LINK_CAPABILITIES_2 Register - ***************************************************************************/ -/* PCIE_CFG :: LINK_CAPABILITIES_2 :: RESERVED_0 [31:00] */ -#define BCHP_PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_MASK 0xffffffff -#define BCHP_PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_SHIFT 0 - -/*************************************************************************** - *LINK_STATUS_CONTROL_2 - LINK_STATUS_CONTROL_2 Register - ***************************************************************************/ -/* PCIE_CFG :: LINK_STATUS_CONTROL_2 :: RESERVED_0 [31:00] */ -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffff -#define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_SHIFT 0 - -/*************************************************************************** - *ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER - ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register - ***************************************************************************/ -/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *UNCORRECTABLE_ERROR_STATUS - UNCORRECTABLE_ERROR_STATUS Register - ***************************************************************************/ -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:21] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffe00000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNSUPPORTED_REQUEST_ERROR_STATUS [20:20] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_MASK 0x00100000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_SHIFT 20 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: ECRC_ERROR_STATUS [19:19] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_MASK 0x00080000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_SHIFT 19 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: MALFORMED_TLP_STATUS [18:18] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_MASK 0x00040000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_SHIFT 18 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RECEIVER_OVERFLOW_STATUS [17:17] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_MASK 0x00020000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_SHIFT 17 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNEXPECTED_COMPLETION_STATUS [16:16] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_MASK 0x00010000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_SHIFT 16 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETER_ABORT_STATUS [15:15] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_MASK 0x00008000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_SHIFT 15 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETION_TIMEOUT_STATUS [14:14] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_MASK 0x00004000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_SHIFT 14 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR_STATUS [13:13] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_MASK 0x00002000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_SHIFT 13 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: POISONED_TLP_STATUS [12:12] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_MASK 0x00001000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_SHIFT 12 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:05] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000fe0 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: DATA_LINK_PROTOCOL_ERROR_STATUS [04:04] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_MASK 0x00000010 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_SHIFT 4 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_2 [03:01] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000000e -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: TRAINING_ERROR_STATUS [00:00] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_MASK 0x00000001 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_SHIFT 0 - -/*************************************************************************** - *UNCORRECTABLE_ERROR_MASK - UNCORRECTABLE_ERROR_MASK Register - ***************************************************************************/ -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_0 [31:21] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffe00000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNSUPPORTED_REQUEST_ERROR_MASK [20:20] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_MASK 0x00100000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_SHIFT 20 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: ECRC_ERROR_MASK [19:19] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_MASK 0x00080000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_SHIFT 19 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: MALFORMED_TLP_MASK [18:18] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_MASK 0x00040000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_SHIFT 18 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RECEIVER_OVERFLOW_MASK [17:17] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_MASK 0x00020000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_SHIFT 17 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNEXPECTED_COMPLETION_MASK [16:16] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_MASK 0x00010000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_SHIFT 16 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETER_ABORT_MASK [15:15] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_MASK 0x00008000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_SHIFT 15 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETION_TIMEOUT_MASK [14:14] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_MASK 0x00004000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_SHIFT 14 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: FLOW_CONTROL_PROTOCOL_ERROR_MASK [13:13] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_MASK 0x00002000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_SHIFT 13 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: POISONED_TLP_MASK [12:12] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_MASK 0x00001000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_SHIFT 12 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_1 [11:05] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000fe0 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: DATA_LINK_PROTOCOL_ERROR_MASK [04:04] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_MASK 0x00000010 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_SHIFT 4 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_2 [03:01] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000000e -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: TRAINING_ERROR_MASK [00:00] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_MASK 0x00000001 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_SHIFT 0 - -/*************************************************************************** - *UNCORRECTABLE_ERROR_SEVERITY - UNCORRECTABLE_ERROR_SEVERITY Register - ***************************************************************************/ -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_0 [31:21] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_MASK 0xffe00000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNSUPPORTED_REQUEST_ERROR_SEVERITY [20:20] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_MASK 0x00100000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_SHIFT 20 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: ECRC_ERROR_SEVERITY [19:19] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_MASK 0x00080000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_SHIFT 19 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: MALFORMED_TLP_SEVERITY [18:18] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_MASK 0x00040000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_SHIFT 18 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RECEIVER_OVERFLOW_ERROR_SEVERITY [17:17] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_MASK 0x00020000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_SHIFT 17 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNEXPECTED_COMPLETION_ERROR_SEVERITY [16:16] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_MASK 0x00010000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_SHIFT 16 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETER_ABORT_ERROR_SEVERITY [15:15] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_MASK 0x00008000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_SHIFT 15 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETION_TIMEOUT_ERROR_SEVERITY [14:14] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_MASK 0x00004000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_SHIFT 14 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY [13:13] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_MASK 0x00002000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_SHIFT 13 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: POISONED_TLP_SEVERITY [12:12] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_MASK 0x00001000 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_SHIFT 12 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_1 [11:05] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_MASK 0x00000fe0 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: DATA_LINK_PROTOCOL_ERROR_SEVERITY [04:04] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_MASK 0x00000010 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_SHIFT 4 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_2 [03:01] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_MASK 0x0000000e -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: TRAINING_ERROR_SEVERITY [00:00] */ -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_MASK 0x00000001 -#define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_SHIFT 0 - -/*************************************************************************** - *CORRECTABLE_ERROR_STATUS - CORRECTABLE_ERROR_STATUS Register - ***************************************************************************/ -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:14] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffffc000 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 14 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: ADVISORY_NON_FATAL_ERROR_STATUS [13:13] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_MASK 0x00002000 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_SHIFT 13 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_TIMER_TIMEOUT_STATUS [12:12] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_SHIFT 12 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:09] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000e00 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 9 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_NUM_ROLLOVER_STATUS [08:08] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_SHIFT 8 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_DLLP_STATUS [07:07] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_MASK 0x00000080 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_SHIFT 7 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_TLP_STATUS [06:06] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_MASK 0x00000040 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_SHIFT 6 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_2 [05:01] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000003e -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RECEIVER_ERROR_STATUS [00:00] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_MASK 0x00000001 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_SHIFT 0 - -/*************************************************************************** - *CORRECTABLE_ERROR_MASK - CORRECTABLE_ERROR_MASK Register - ***************************************************************************/ -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_0 [31:14] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffffc000 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 14 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: ADVISORY_NON_FATAL_ERROR_MASK [13:13] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_MASK 0x00002000 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_SHIFT 13 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_TIMER_TIMEOUT_MASK [12:12] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_SHIFT 12 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_1 [11:09] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000e00 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 9 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_NUM_ROLLOVER_MASK [08:08] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_SHIFT 8 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_DLLP_MASK [07:07] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_MASK 0x00000080 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_SHIFT 7 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_TLP_MASK [06:06] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_MASK 0x00000040 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_SHIFT 6 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_2 [05:01] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000003e -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RECEIVER_ERROR_MASK [00:00] */ -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_MASK 0x00000001 -#define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_SHIFT 0 - -/*************************************************************************** - *ADVANCED_ERROR_CAPABILITIES_AND_CONTROL - ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register - ***************************************************************************/ -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: RESERVED_0 [31:09] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_MASK 0xfffffe00 -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_SHIFT 9 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_ENABLE [08:08] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_MASK 0x00000100 -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_SHIFT 8 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_CAPABLE [07:07] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_MASK 0x00000080 -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_SHIFT 7 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_ENABLE [06:06] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_MASK 0x00000040 -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_SHIFT 6 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_CAPABLE [05:05] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_MASK 0x00000020 -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_SHIFT 5 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: FIRST_ERROR_POINTER [04:00] */ -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_MASK 0x0000001f -#define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_SHIFT 0 - -/*************************************************************************** - *HEADER_LOG_1 - HEADER_LOG_1 Register - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_0 [31:24] */ -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_MASK 0xff000000 -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_1 [23:16] */ -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_2 [15:08] */ -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_3 [07:00] */ -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_MASK 0x000000ff -#define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_SHIFT 0 - -/*************************************************************************** - *HEADER_LOG_2 - HEADER_LOG_2 Register - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_4 [31:24] */ -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_MASK 0xff000000 -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_5 [23:16] */ -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_6 [15:08] */ -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_7 [07:00] */ -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_MASK 0x000000ff -#define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_SHIFT 0 - -/*************************************************************************** - *HEADER_LOG_3 - HEADER_LOG_3 Register - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_8 [31:24] */ -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_MASK 0xff000000 -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_9 [23:16] */ -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_10 [15:08] */ -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_11 [07:00] */ -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_MASK 0x000000ff -#define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_SHIFT 0 - -/*************************************************************************** - *HEADER_LOG_4 - HEADER_LOG_4 Register - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_12 [31:24] */ -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_MASK 0xff000000 -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_13 [23:16] */ -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_14 [15:08] */ -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_15 [07:00] */ -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_MASK 0x000000ff -#define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_SHIFT 0 - -/*************************************************************************** - *VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER - VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register - ***************************************************************************/ -/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *PORT_VC_CAPABILITY - PORT_VC_CAPABILITY Register - ***************************************************************************/ -/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_0 [31:12] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_MASK 0xfffff000 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_SHIFT 12 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: PORT_ARBITRATION_TABLE_ENTRY_SIZE [11:10] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_MASK 0x00000c00 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_SHIFT 10 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: REFERENCE_CLOCK [09:08] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_MASK 0x00000300 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_SHIFT 8 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_1 [07:07] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_MASK 0x00000080 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_SHIFT 7 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: LOW_PRIORITY_EXTENDED_VC_COUNT [06:04] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_MASK 0x00000070 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_SHIFT 4 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_2 [03:03] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_MASK 0x00000008 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_SHIFT 3 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: EXTENDED_VC_COUNT [02:00] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_MASK 0x00000007 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_SHIFT 0 - -/*************************************************************************** - *PORT_VC_CAPABILITY_2 - PORT_VC_CAPABILITY_2 Register - ***************************************************************************/ -/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_TABLE_OFFSET [31:24] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_SHIFT 24 - -/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: RESERVED_0 [23:08] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_MASK 0x00ffff00 -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_SHIFT 8 - -/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_CAPABILITY [07:00] */ -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_MASK 0x000000ff -#define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_SHIFT 0 - -/*************************************************************************** - *PORT_VC_STATUS_CONTROL - PORT_VC_STATUS_CONTROL Register - ***************************************************************************/ -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_0 [31:17] */ -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_MASK 0xfffe0000 -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_SHIFT 17 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_TABLE_STATUS [16:16] */ -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_MASK 0x00010000 -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_SHIFT 16 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_1 [15:04] */ -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_MASK 0x0000fff0 -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_SHIFT 4 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_SELECT [03:01] */ -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_MASK 0x0000000e -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_SHIFT 1 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: LOAD_VC_ARBITRATION_TABLE [00:00] */ -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_MASK 0x00000001 -#define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_SHIFT 0 - -/*************************************************************************** - *VC_RESOURCE_CAPABILITY - VC_RESOURCE_CAPABILITY Register - ***************************************************************************/ -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_TABLE_OFFSET [31:24] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_SHIFT 24 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_0 [23:23] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_MASK 0x00800000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_SHIFT 23 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: MAXIMUM_TIME_SLOTS [22:16] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_MASK 0x007f0000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_SHIFT 16 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: REJECT_SNOOP_TRANSACTIONS [15:15] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_MASK 0x00008000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_SHIFT 15 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: ADVANCED_PACKET_SWITCHING [14:14] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_MASK 0x00004000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_SHIFT 14 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_1 [13:08] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_MASK 0x00003f00 -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_SHIFT 8 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_CAPABILITY [07:00] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_MASK 0x000000ff -#define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_SHIFT 0 - -/*************************************************************************** - *VC_RESOURCE_CONTROL - VC_RESOURCE_CONTROL Register - ***************************************************************************/ -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ENABLE [31:31] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_MASK 0x80000000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_SHIFT 31 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_0 [30:27] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_MASK 0x78000000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_SHIFT 27 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ID [26:24] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_MASK 0x07000000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_SHIFT 24 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_1 [23:20] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_MASK 0x00f00000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_SHIFT 20 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: PORT_ARBITRATION_SELECT [19:17] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_MASK 0x000e0000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_SHIFT 17 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: LOAD_PORT_ARBITRATION_TABLE [16:16] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_MASK 0x00010000 -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_SHIFT 16 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_2 [15:08] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_MASK 0x0000ff00 -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_SHIFT 8 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: TC_VC_MAP [07:00] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_MASK 0x000000ff -#define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_SHIFT 0 - -/*************************************************************************** - *VC_RESOURCE_STATUS - VC_RESOURCE_STATUS Register - ***************************************************************************/ -/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_0 [31:18] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_MASK 0xfffc0000 -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_SHIFT 18 - -/* PCIE_CFG :: VC_RESOURCE_STATUS :: VC_NEGOTIATION_PENDING [17:17] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_MASK 0x00020000 -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_SHIFT 17 - -/* PCIE_CFG :: VC_RESOURCE_STATUS :: PORT_ARBITRATION_TABLE_STATUS [16:16] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_MASK 0x00010000 -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_SHIFT 16 - -/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_1 [15:00] */ -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_MASK 0x0000ffff -#define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_SHIFT 0 - -/*************************************************************************** - *DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER - DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *DEVICE_SERIAL_NO_LOWER_DW - DEVICE_SERIAL_NO_LOWER_DW Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW :: SERIAL_NO_LOWER [31:00] */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_MASK 0xffffffff -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_SHIFT 0 - -/*************************************************************************** - *DEVICE_SERIAL_NO_UPPER_DW - DEVICE_SERIAL_NO_UPPER_DW Register - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW :: SERIAL_NO_UPPER [31:00] */ -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_MASK 0xffffffff -#define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_SHIFT 0 - -/*************************************************************************** - *POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER - POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - -/*************************************************************************** - *POWER_BUDGETING_DATA_SELECT - POWER_BUDGETING_DATA_SELECT Register - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: RESERVED_0 [31:08] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_MASK 0xffffff00 -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_SHIFT 8 - -/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: DATA_SELECT [07:00] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_MASK 0x000000ff -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_SHIFT 0 - -/*************************************************************************** - *POWER_BUDGETING_DATA - POWER_BUDGETING_DATA Register - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_DATA :: RESERVED_0 [31:21] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_MASK 0xffe00000 -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: POWER_RAIL [20:18] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_MASK 0x001c0000 -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_SHIFT 18 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: TYPE [17:15] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_TYPE_MASK 0x00038000 -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_TYPE_SHIFT 15 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_STATE [14:13] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_MASK 0x00006000 -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_SHIFT 13 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_SUB_STATE [12:10] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_MASK 0x00001c00 -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_SHIFT 10 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: DATA_SCALE [09:08] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_MASK 0x00000300 -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_SHIFT 8 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: BASE_POWER [07:00] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_MASK 0x000000ff -#define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_SHIFT 0 - -/*************************************************************************** - *POWER_BUDGETING_CAPABILITY - POWER_BUDGETING_CAPABILITY Register - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: RESERVED_0 [31:01] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_MASK 0xfffffffe -#define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_SHIFT 1 - -/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: LOM_CONFIGURATION [00:00] */ -#define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_MASK 0x00000001 -#define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_SHIFT 0 - -/*************************************************************************** - *FIRMWARE_POWER_BUDGETING_2_1 - FIRMWARE_POWER_BUDGETING_2_1 Register - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_2 [31:29] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_MASK 0xe0000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_2 [28:26] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_MASK 0x1c000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_2 [25:24] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_MASK 0x03000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_2 [23:16] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_1 [15:13] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_MASK 0x0000e000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_1 [12:10] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_MASK 0x00001c00 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_1 [09:08] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_MASK 0x00000300 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_1 [07:00] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_MASK 0x000000ff -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_SHIFT 0 - -/*************************************************************************** - *FIRMWARE_POWER_BUDGETING_4_3 - FIRMWARE_POWER_BUDGETING_4_3 Register - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_4 [31:29] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_MASK 0xe0000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_4 [28:26] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_MASK 0x1c000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_4 [25:24] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_MASK 0x03000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_4 [23:16] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_3 [15:13] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_MASK 0x0000e000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_3 [12:10] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_MASK 0x00001c00 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_3 [09:08] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_MASK 0x00000300 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_3 [07:00] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_MASK 0x000000ff -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_SHIFT 0 - -/*************************************************************************** - *FIRMWARE_POWER_BUDGETING_6_5 - FIRMWARE_POWER_BUDGETING_6_5 Register - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_6 [31:29] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_MASK 0xe0000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_6 [28:26] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_MASK 0x1c000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_6 [25:24] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_MASK 0x03000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_6 [23:16] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_5 [15:13] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_MASK 0x0000e000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_5 [12:10] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_MASK 0x00001c00 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_5 [09:08] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_MASK 0x00000300 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_5 [07:00] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_MASK 0x000000ff -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_SHIFT 0 - -/*************************************************************************** - *FIRMWARE_POWER_BUDGETING_8_7 - FIRMWARE_POWER_BUDGETING_8_7 Register - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_8 [31:29] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_MASK 0xe0000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_8 [28:26] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_MASK 0x1c000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_8 [25:24] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_MASK 0x03000000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_8 [23:16] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_MASK 0x00ff0000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_7 [15:13] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_MASK 0x0000e000 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_7 [12:10] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_MASK 0x00001c00 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_7 [09:08] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_MASK 0x00000300 -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_7 [07:00] */ -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_MASK 0x000000ff -#define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_SHIFT 0 - -/*************************************************************************** - *PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING - PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register - ***************************************************************************/ -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNUSED_0 [31:07] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_MASK 0xffffff80 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_SHIFT 7 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: D3HOT_MEMORY_READ_ADVISORY_NON_FATAL [06:06] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_MASK 0x00000040 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_SHIFT 6 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: RETRY_POISON_ENABLE [05:05] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_MASK 0x00000020 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_SHIFT 5 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: POISON_ADVISORY_NON_FATAL_ENABLE [04:04] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000010 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_SHIFT 4 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNEXPECTED_ADVISORY_NON_FATAL_ENABLE [03:03] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000008 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_SHIFT 3 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE [02:02] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000004 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_SHIFT 2 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [01:01] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000002 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 1 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [00:00] */ -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000001 -#define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 0 - -#endif /* #ifndef BCHP_PCIE_CFG_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_dll.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_dll.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_dll.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_dll.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,674 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pcie_dll.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:13p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:21 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_dll.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:13p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PCIE_DLL_H__ -#define BCHP_PCIE_DLL_H__ - -/*************************************************************************** - *PCIE_DLL - PCIE DLL related registers - ***************************************************************************/ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL 0x00500500 /* DATA_LINK_CONTROL Register */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS 0x00500504 /* DATA_LINK_STATUS Register */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION 0x00500508 /* DATA_LINK_ATTENTION Register */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0050050c /* DATA_LINK_ATTENTION_MASK Register */ -#define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00500510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00500514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00500518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0050051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ -#define BCHP_PCIE_DLL_DATA_LINK_REPLAY 0x00500520 /* DATA_LINK_REPLAY Register */ -#define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00500524 /* DATA_LINK_ACK_TIMEOUT Register */ -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00500528 /* POWER_MANAGEMENT_THRESHOLD Register */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0050052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00500530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00500534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00500538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0050053c /* ERROR_COUNT_THRESHOLD Register */ -#define BCHP_PCIE_DLL_TL_ERROR_COUNTER 0x00500540 /* TL_ERROR_COUNTER Register */ -#define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER 0x00500544 /* DLLP_ERROR_COUNTER Register */ -#define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER 0x00500548 /* NAK_RECEIVED_COUNTER Register */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST 0x0050054c /* DATA_LINK_TEST Register */ -#define BCHP_PCIE_DLL_PACKET_BIST 0x00500550 /* PACKET_BIST Register */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00500554 /* LINK_PCIE_1_1_CONTROL Register */ - -/*************************************************************************** - *DATA_LINK_CONTROL - DATA_LINK_CONTROL Register - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_0 [31:31] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_MASK 0x80000000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_SHIFT 31 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28102_FIX_ENABLE [30:30] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28102_FIX_ENABLE_MASK 0x40000000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28102_FIX_ENABLE_SHIFT 30 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28001_FIX_ENABLE [29:29] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_MASK 0x20000000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_SHIFT 29 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ27820_FIX_ENABLE [28:28] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_MASK 0x10000000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_SHIFT 28 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: ASPM_L1_ENABLE [27:27] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_MASK 0x08000000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_SHIFT 27 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_1 [26:25] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_MASK 0x06000000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_SHIFT 25 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ11211 [24:24] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ11211_MASK 0x01000000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ11211_SHIFT 24 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_2 [23:23] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_MASK 0x00800000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_SHIFT 23 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_3 [22:22] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_MASK 0x00400000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_SHIFT 22 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_4 [21:21] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_MASK 0x00200000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_SHIFT 21 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_5 [20:20] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_MASK 0x00100000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_SHIFT 20 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_6 [19:19] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_MASK 0x00080000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_SHIFT 19 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: PLL_REFSEL_SWITCH_CONTROL_CQ11011 [18:18] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_MASK 0x00040000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_SHIFT 18 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_7 [17:17] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_MASK 0x00020000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_SHIFT 17 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL [16:16] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_MASK 0x00010000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_SHIFT 16 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_TRANSMITTER [15:15] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_MASK 0x00008000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_SHIFT 15 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_PLL [14:14] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_MASK 0x00004000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_SHIFT 14 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_RECEIVER [13:13] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_MASK 0x00002000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_SHIFT 13 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_BEACON [12:12] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_MASK 0x00001000 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_SHIFT 12 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: AUTOMATIC_TIMER_THRESHOLD_ENABLE [11:11] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_MASK 0x00000800 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_DLLP_TIMEOUT_MECHANISM [10:10] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_MASK 0x00000400 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CHECK_RECEIVE_FLOW_CONTROL_CREDITS [09:09] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_MASK 0x00000200 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_SHIFT 9 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: LINK_ENABLE [08:08] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_MASK 0x00000100 -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL_2 [07:00] */ -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_MASK 0x000000ff -#define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_SHIFT 0 - -/*************************************************************************** - *DATA_LINK_STATUS - DATA_LINK_STATUS Register - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_0 [31:26] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_MASK 0xfc000000 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_SHIFT 26 - -/* PCIE_DLL :: DATA_LINK_STATUS :: PHY_LINK_STATE [25:23] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_MASK 0x03800000 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_SHIFT 23 - -/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_STATE [22:19] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_MASK 0x00780000 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_SHIFT 19 - -/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_SUB_STATE [18:17] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_MASK 0x00060000 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_SHIFT 17 - -/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_UP [16:16] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_MASK 0x00010000 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_SHIFT 16 - -/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_1 [15:11] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_MASK 0x0000f800 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_STATUS :: PME_TURN_OFF_STATUS_IN_D0 [10:10] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_MASK 0x00000400 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_UPDATE_TIMEOUT [09:09] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_MASK 0x00000200 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_SHIFT 9 - -/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_RECEIVE_OVERFLOW [08:08] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_MASK 0x00000100 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR [07:07] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_MASK 0x00000080 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_SHIFT 7 - -/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_PROTOCOL_ERROR [06:06] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_MASK 0x00000040 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_ROLLOVER [05:05] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_MASK 0x00000020 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_TIMEOUT [04:04] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_MASK 0x00000010 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_STATUS :: NAK_RECEIVED [03:03] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_MASK 0x00000008 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_STATUS :: DLLP_ERROR [02:02] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_MASK 0x00000004 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_STATUS :: BAD_TLP_SEQUENCE_NUMBER [01:01] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_MASK 0x00000002 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_STATUS :: TLP_ERROR [00:00] */ -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_MASK 0x00000001 -#define BCHP_PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_SHIFT 0 - -/*************************************************************************** - *DATA_LINK_ATTENTION - DATA_LINK_ATTENTION Register - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_ATTENTION :: RESERVED_0 [31:06] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_MASK 0xffffffc0 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_PACKET_TEST_INDICATOR [05:05] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_MASK 0x00000020 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR [04:04] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_MASK 0x00000010 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR [03:03] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_MASK 0x00000008 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: DLLP_ERROR_COUNTER_ATTENTION_INDICATOR [02:02] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000004 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR [01:01] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_MASK 0x00000002 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_ERROR_COUNTER_ATTENTION_INDICATOR [00:00] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000001 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 0 - -/*************************************************************************** - *DATA_LINK_ATTENTION_MASK - DATA_LINK_ATTENTION_MASK Register - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: RESERVED_0 [31:08] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: UNUSED_0 [07:06] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_MASK 0x000000c0 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK [05:05] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_MASK 0x00000020 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_ERROR_ATTENTION_MASK [04:04] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_MASK 0x00000010 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: NAK_RECEIVED_COUNTER_ATTENTION_MASK [03:03] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_MASK 0x00000008 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DLLP_ERROR_COUNTER_ATTENTION_MASK [02:02] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000004 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK [01:01] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_MASK 0x00000002 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_ERROR_COUNTER_ATTENTION_MASK [00:00] */ -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000001 -#define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 0 - -/*************************************************************************** - *NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG - NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register - ***************************************************************************/ -/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: NEXT_TRANSMIT_SEQUENCE_NUMBER [11:00] */ -#define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff -#define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 - -/*************************************************************************** - *ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG - ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register - ***************************************************************************/ -/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ -#define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff -#define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 - -/*************************************************************************** - *PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG - PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register - ***************************************************************************/ -/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: PURGED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ -#define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff -#define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 - -/*************************************************************************** - *RECEIVE_SEQUENCE_NUMBER_DEBUG - RECEIVE_SEQUENCE_NUMBER_DEBUG Register - ***************************************************************************/ -/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RECEIVE_SEQUENCE_NUMBER [11:00] */ -#define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_MASK 0x00000fff -#define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_SHIFT 0 - -/*************************************************************************** - *DATA_LINK_REPLAY - DATA_LINK_REPLAY Register - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_REPLAY :: RESERVED_0 [31:23] */ -#define BCHP_PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_MASK 0xff800000 -#define BCHP_PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_SHIFT 23 - -/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_TIMEOUT_VALUE [22:10] */ -#define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_MASK 0x007ffc00 -#define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_BUFFER_SIZE [09:00] */ -#define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_MASK 0x000003ff -#define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_SHIFT 0 - -/*************************************************************************** - *DATA_LINK_ACK_TIMEOUT - DATA_LINK_ACK_TIMEOUT Register - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: RESERVED_0 [31:11] */ -#define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_MASK 0xfffff800 -#define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: ACK_LATENCY_TIMEOUT_VALUE [10:00] */ -#define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_MASK 0x000007ff -#define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_SHIFT 0 - -/*************************************************************************** - *POWER_MANAGEMENT_THRESHOLD - POWER_MANAGEMENT_THRESHOLD Register - ***************************************************************************/ -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: RESERVED_0 [31:24] */ -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_MASK 0xff000000 -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_SHIFT 24 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0_STAY_TIME [23:20] */ -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_MASK 0x00f00000 -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_SHIFT 20 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_STAY_TIME [19:16] */ -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_MASK 0x000f0000 -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_SHIFT 16 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_THRESHOLD [15:08] */ -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_MASK 0x0000ff00 -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_SHIFT 8 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0S_THRESHOLD [07:00] */ -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_MASK 0x000000ff -#define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *RETRY_BUFFER_WRITE_POINTER_DEBUG - RETRY_BUFFER_WRITE_POINTER_DEBUG Register - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RESERVED_0 [31:11] */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 -#define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RETRY_BUFFER_WRITE_POINTER [10:00] */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_MASK 0x000007ff -#define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_SHIFT 0 - -/*************************************************************************** - *RETRY_BUFFER_READ_POINTER_DEBUG - RETRY_BUFFER_READ_POINTER_DEBUG Register - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RESERVED_0 [31:11] */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RETRY_BUFFER_READ_POINTER [10:00] */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_MASK 0x000007ff -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_SHIFT 0 - -/*************************************************************************** - *RETRY_BUFFER_PURGED_POINTER_DEBUG - RETRY_BUFFER_PURGED_POINTER_DEBUG Register - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RESERVED_0 [31:11] */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 -#define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RETRY_BUFFER_PURGED_POINTER [10:00] */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_MASK 0x000007ff -#define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_SHIFT 0 - -/*************************************************************************** - *RETRY_BUFFER_READ_WRITE_DEBUG_PORT - RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT :: RETRY_BUFFER_DATA [31:00] */ -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_MASK 0xffffffff -#define BCHP_PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_SHIFT 0 - -/*************************************************************************** - *ERROR_COUNT_THRESHOLD - ERROR_COUNT_THRESHOLD Register - ***************************************************************************/ -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: RESERVED_0 [31:15] */ -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_MASK 0xffff8000 -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_SHIFT 15 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD [14:12] */ -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_MASK 0x00007000 -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_SHIFT 12 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: NAK_RECEIVED_COUNT_THRESHOLD [11:08] */ -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_MASK 0x00000f00 -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_SHIFT 8 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: DLLP_ERROR_COUNT_THRESHOLD [07:04] */ -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_MASK 0x000000f0 -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_SHIFT 4 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: TLP_ERROR_COUNT_THRESHOLD [03:00] */ -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_MASK 0x0000000f -#define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *TL_ERROR_COUNTER - TL_ERROR_COUNTER Register - ***************************************************************************/ -/* PCIE_DLL :: TL_ERROR_COUNTER :: RESERVED_0 [31:24] */ -#define BCHP_PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_MASK 0xff000000 -#define BCHP_PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_SHIFT 24 - -/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_BAD_SEQUENCE_NUMBER_COUNTER [23:16] */ -#define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_MASK 0x00ff0000 -#define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_SHIFT 16 - -/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_ERROR_COUNTER [15:00] */ -#define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_MASK 0x0000ffff -#define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_SHIFT 0 - -/*************************************************************************** - *DLLP_ERROR_COUNTER - DLLP_ERROR_COUNTER Register - ***************************************************************************/ -/* PCIE_DLL :: DLLP_ERROR_COUNTER :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_SHIFT 16 - -/* PCIE_DLL :: DLLP_ERROR_COUNTER :: DLLP_ERROR_COUNTER [15:00] */ -#define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_MASK 0x0000ffff -#define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_SHIFT 0 - -/*************************************************************************** - *NAK_RECEIVED_COUNTER - NAK_RECEIVED_COUNTER Register - ***************************************************************************/ -/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_SHIFT 16 - -/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: NAK_RECEIVED_COUNTER [15:00] */ -#define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_MASK 0x0000ffff -#define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_SHIFT 0 - -/*************************************************************************** - *DATA_LINK_TEST - DATA_LINK_TEST Register - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_TEST :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_RESERVED_0_SHIFT 16 - -/* PCIE_DLL :: DATA_LINK_TEST :: STORE_RECEIVE_TLPS [15:15] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_MASK 0x00008000 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_SHIFT 15 - -/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_TLPS [14:14] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_MASK 0x00004000 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_SHIFT 14 - -/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_DLLPS [13:13] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_MASK 0x00002000 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_SHIFT 13 - -/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PHY_LINK_UP [12:12] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_MASK 0x00001000 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_SHIFT 12 - -/* PCIE_DLL :: DATA_LINK_TEST :: BYPASS_FLOW_CONTROL [11:11] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_MASK 0x00000800 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE [10:10] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_MASK 0x00000400 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_OVERSTRESS_TEST_MODE [09:09] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_MASK 0x00000200 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_SHIFT 9 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_SLOW_CLOCK [08:08] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_MASK 0x00000100 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_COMPLETION_TIMER [07:07] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_MASK 0x00000080 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_SHIFT 7 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_REPLAY_TIMER [06:06] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_MASK 0x00000040 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_ACK_LATENCY_TIMER [05:05] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_MASK 0x00000020 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_PME_SERVICE_TIMER [04:04] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_MASK 0x00000010 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PURGE [03:03] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_MASK 0x00000008 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_RETRY [02:02] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_MASK 0x00000004 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_TEST :: INVERT_CRC [01:01] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_MASK 0x00000002 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_TEST :: SEND_BAD_CRC_BIT [00:00] */ -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_MASK 0x00000001 -#define BCHP_PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_SHIFT 0 - -/*************************************************************************** - *PACKET_BIST - PACKET_BIST Register - ***************************************************************************/ -/* PCIE_DLL :: PACKET_BIST :: RESERVED_0 [31:24] */ -#define BCHP_PCIE_DLL_PACKET_BIST_RESERVED_0_MASK 0xff000000 -#define BCHP_PCIE_DLL_PACKET_BIST_RESERVED_0_SHIFT 24 - -/* PCIE_DLL :: PACKET_BIST :: PACKET_CHECKER_LOCKED [23:23] */ -#define BCHP_PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_MASK 0x00800000 -#define BCHP_PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_SHIFT 23 - -/* PCIE_DLL :: PACKET_BIST :: RECEIVE_MISMATCH [22:22] */ -#define BCHP_PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_MASK 0x00400000 -#define BCHP_PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_SHIFT 22 - -/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_TLP_LENGTH [21:21] */ -#define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_MASK 0x00200000 -#define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_SHIFT 21 - -/* PCIE_DLL :: PACKET_BIST :: TLP_LENGTH [20:10] */ -#define BCHP_PCIE_DLL_PACKET_BIST_TLP_LENGTH_MASK 0x001ffc00 -#define BCHP_PCIE_DLL_PACKET_BIST_TLP_LENGTH_SHIFT 10 - -/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_IPG_LENGTH [09:09] */ -#define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_MASK 0x00000200 -#define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_SHIFT 9 - -/* PCIE_DLL :: PACKET_BIST :: IPG_LENGTH [08:02] */ -#define BCHP_PCIE_DLL_PACKET_BIST_IPG_LENGTH_MASK 0x000001fc -#define BCHP_PCIE_DLL_PACKET_BIST_IPG_LENGTH_SHIFT 2 - -/* PCIE_DLL :: PACKET_BIST :: TRANSMIT_START [01:01] */ -#define BCHP_PCIE_DLL_PACKET_BIST_TRANSMIT_START_MASK 0x00000002 -#define BCHP_PCIE_DLL_PACKET_BIST_TRANSMIT_START_SHIFT 1 - -/* PCIE_DLL :: PACKET_BIST :: ENABLE_PACKET_GENERATOR_TEST_MODE [00:00] */ -#define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_MASK 0x00000001 -#define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_SHIFT 0 - -/*************************************************************************** - *LINK_PCIE_1_1_CONTROL - LINK_PCIE_1_1_CONTROL Register - ***************************************************************************/ -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_CT_2_0 [31:29] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_MASK 0xe0000000 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_SHIFT 29 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_SAM_1_0 [28:27] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_MASK 0x18000000 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_SHIFT 27 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: UNUSED_0 [26:10] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_MASK 0x07fffc00 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_SHIFT 10 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: SELOCALXTAL [09:09] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_MASK 0x00000200 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_SHIFT 9 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_PLL_POWERDOWN_DISABLE [08:08] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_MASK 0x00000100 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_SHIFT 8 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_POWERDOWN_DISABLE [07:07] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_MASK 0x00000080 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_SHIFT 7 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_D3PM_CLKREQ_DISABLE [06:06] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_MASK 0x00000040 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_SHIFT 6 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_D3PM_CLKREQ_DISABLE [05:05] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_MASK 0x00000020 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_SHIFT 5 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_ASPM_CLKREQ_DISABLE [04:04] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_MASK 0x00000010 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_SHIFT 4 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_PD_W_O_CLKREQ [03:03] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_MASK 0x00000008 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_SHIFT 3 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DASPM10USTIMER [02:02] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_MASK 0x00000004 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_SHIFT 2 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFFU_EL1 [01:01] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_MASK 0x00000002 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_SHIFT 1 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFLOWCTLUPDATE1_1 [00:00] */ -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_MASK 0x00000001 -#define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_SHIFT 0 - -#endif /* #ifndef BCHP_PCIE_DLL_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_phy.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_phy.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_phy.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_phy.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,522 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pcie_phy.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:13p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:28 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_phy.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:13p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PCIE_PHY_H__ -#define BCHP_PCIE_PHY_H__ - -/*************************************************************************** - *PCIE_PHY - PCIE PHY related registers - ***************************************************************************/ -#define BCHP_PCIE_PHY_PHY_MODE 0x00500600 /* TYPE_PHY_MODE Register */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS 0x00500604 /* TYPE_PHY_LINK_STATUS Register */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00500608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0050060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00500610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00500614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ -#define BCHP_PCIE_PHY_PHY_ATTENTION 0x00500618 /* TYPE_PHY_ATTENTION Register */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK 0x0050061c /* TYPE_PHY_ATTENTION_MASK Register */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00500620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00500624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00500628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL 0x0050062c /* TYPE_PHY_TEST_CONTROL Register */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00500630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00500634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00500638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0050063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ - -/*************************************************************************** - *PHY_MODE - TYPE_PHY_MODE Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_MODE :: RESERVED_0 [31:04] */ -#define BCHP_PCIE_PHY_PHY_MODE_RESERVED_0_MASK 0xfffffff0 -#define BCHP_PCIE_PHY_PHY_MODE_RESERVED_0_SHIFT 4 - -/* PCIE_PHY :: PHY_MODE :: UPSTREAM_DEV [03:03] */ -#define BCHP_PCIE_PHY_PHY_MODE_UPSTREAM_DEV_MASK 0x00000008 -#define BCHP_PCIE_PHY_PHY_MODE_UPSTREAM_DEV_SHIFT 3 - -/* PCIE_PHY :: PHY_MODE :: SERDES_SA_MODE [02:02] */ -#define BCHP_PCIE_PHY_PHY_MODE_SERDES_SA_MODE_MASK 0x00000004 -#define BCHP_PCIE_PHY_PHY_MODE_SERDES_SA_MODE_SHIFT 2 - -/* PCIE_PHY :: PHY_MODE :: LINK_DISABLE [01:01] */ -#define BCHP_PCIE_PHY_PHY_MODE_LINK_DISABLE_MASK 0x00000002 -#define BCHP_PCIE_PHY_PHY_MODE_LINK_DISABLE_SHIFT 1 - -/* PCIE_PHY :: PHY_MODE :: SOFT_RESET [00:00] */ -#define BCHP_PCIE_PHY_PHY_MODE_SOFT_RESET_MASK 0x00000001 -#define BCHP_PCIE_PHY_PHY_MODE_SOFT_RESET_SHIFT 0 - -/*************************************************************************** - *PHY_LINK_STATUS - TYPE_PHY_LINK_STATUS Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_0 [31:10] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_MASK 0xfffffc00 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_SHIFT 10 - -/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_OVERRUN [09:09] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_MASK 0x00000200 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_SHIFT 9 - -/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_UNDERRUN [08:08] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_MASK 0x00000100 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_REQUEST_LOOPBACK [07:07] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_MASK 0x00000080 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_SHIFT 7 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_DISABLE_SCRAMBLER [06:06] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_MASK 0x00000040 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_SHIFT 6 - -/* PCIE_PHY :: PHY_LINK_STATUS :: EXTENDED_SYNCH [05:05] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_MASK 0x00000020 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_SHIFT 5 - -/* PCIE_PHY :: PHY_LINK_STATUS :: POLARITY_INVERTED [04:04] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_MASK 0x00000010 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_SHIFT 4 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_UP [03:03] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_UP_MASK 0x00000008 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_UP_SHIFT 3 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_TRAINING [02:02] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_MASK 0x00000004 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_SHIFT 2 - -/* PCIE_PHY :: PHY_LINK_STATUS :: RECEIVE_DATA_VALID [01:01] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_MASK 0x00000002 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_SHIFT 1 - -/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_1 [00:00] */ -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_MASK 0x00000001 -#define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_SHIFT 0 - -/*************************************************************************** - *PHY_LINK_LTSSM_CONTROL - TYPE_PHY_LINK_LTSSM_CONTROL Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESERVED_0 [31:08] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_MASK 0xffffff00 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESCRAMBLE [07:07] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_MASK 0x00000080 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_SHIFT 7 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DETECTSTATE [06:06] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_MASK 0x00000040 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_SHIFT 6 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: POLLINGSTATE [05:05] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_MASK 0x00000020 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_SHIFT 5 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: CONFIGSTATE [04:04] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_MASK 0x00000010 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_SHIFT 4 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RECOVSTATE [03:03] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_MASK 0x00000008 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_SHIFT 3 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: EXTLBSTATE [02:02] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_MASK 0x00000004 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_SHIFT 2 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESETSTATE [01:01] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_MASK 0x00000002 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_SHIFT 1 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESTATE [00:00] */ -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_MASK 0x00000001 -#define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_SHIFT 0 - -/*************************************************************************** - *PHY_LINK_TRAINING_LINK_NUMBER - TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: RESERVED_0 [31:08] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_MASK 0xffffff00 -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: LANE_NUMBER [07:00] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_MASK 0x000000ff -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_SHIFT 0 - -/*************************************************************************** - *PHY_LINK_TRAINING_LANE_NUMBER - TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: RESERVED_0 [31:08] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_MASK 0xffffff00 -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: LANE_NUMBER [07:00] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_MASK 0x000000ff -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_SHIFT 0 - -/*************************************************************************** - *PHY_LINK_TRAINING_N_FTS - TYPE_PHY_LINK_TRAINING_N_FTS Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RESERVED_0 [31:25] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_MASK 0xfe000000 -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_SHIFT 25 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE [24:24] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_MASK 0x01000000 -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_SHIFT 24 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE_VALUE [23:16] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_MASK 0x00ff0000 -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_SHIFT 16 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS [15:08] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_MASK 0x0000ff00 -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RECEIVER_N_FTS [07:00] */ -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_MASK 0x000000ff -#define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_SHIFT 0 - -/*************************************************************************** - *PHY_ATTENTION - TYPE_PHY_ATTENTION Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_ATTENTION :: RESERVED_0 [31:08] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_RESERVED_0_MASK 0xffffff00 -#define BCHP_PCIE_PHY_PHY_ATTENTION_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_ATTENTION :: HOT_RESET [07:07] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_HOT_RESET_MASK 0x00000080 -#define BCHP_PCIE_PHY_PHY_ATTENTION_HOT_RESET_SHIFT 7 - -/* PCIE_PHY :: PHY_ATTENTION :: LINK_DOWN [06:06] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_LINK_DOWN_MASK 0x00000040 -#define BCHP_PCIE_PHY_PHY_ATTENTION_LINK_DOWN_SHIFT 6 - -/* PCIE_PHY :: PHY_ATTENTION :: TRAINING_ERROR [05:05] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_MASK 0x00000020 -#define BCHP_PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_SHIFT 5 - -/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_OVERRUN [04:04] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_MASK 0x00000010 -#define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_SHIFT 4 - -/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_UNDERRUN [03:03] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_MASK 0x00000008 -#define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_SHIFT 3 - -/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_FRAMING_ERROR [02:02] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_MASK 0x00000004 -#define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_SHIFT 2 - -/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_DISPARITY_ERROR [01:01] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_MASK 0x00000002 -#define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_SHIFT 1 - -/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_CODE_ERROR [00:00] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_MASK 0x00000001 -#define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_SHIFT 0 - -/*************************************************************************** - *PHY_ATTENTION_MASK - TYPE_PHY_ATTENTION_MASK Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RESERVED_0 [31:08] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: HOT_RESET_MASK [07:07] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_MASK 0x00000080 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_SHIFT 7 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: LINK_DOWN_MASK [06:06] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_MASK 0x00000040 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_SHIFT 6 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: TRAINING_ERROR_MASK [05:05] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_MASK 0x00000020 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_SHIFT 5 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_OVERRUN_MASK [04:04] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_MASK 0x00000010 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_SHIFT 4 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_UNDERRUN_MASK [03:03] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_MASK 0x00000008 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_SHIFT 3 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_FRAME_ERROR_MASK [02:02] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_MASK 0x00000004 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_SHIFT 2 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_DISPARITY_ERROR_MASK [01:01] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_MASK 0x00000002 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_SHIFT 1 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_CODE_ERROR_MASK [00:00] */ -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_MASK 0x00000001 -#define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_SHIFT 0 - -/*************************************************************************** - *PHY_RECEIVE_ERROR_COUNTER - TYPE_PHY_RECEIVE_ERROR_COUNTER Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: DISPARITY_ERROR_COUNT [31:16] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_MASK 0xffff0000 -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_SHIFT 16 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: CODE_ERROR_COUNT [15:00] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_MASK 0x0000ffff -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_SHIFT 0 - -/*************************************************************************** - *PHY_RECEIVE_FRAMING_ERROR_COUNTER - TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: RESERVED_0 [31:16] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 -#define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_SHIFT 16 - -/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: FRAMING_ERROR_COUNT [15:00] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_MASK 0x0000ffff -#define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_SHIFT 0 - -/*************************************************************************** - *PHY_RECEIVE_ERROR_THRESHOLD - TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: RESERVED_0 [31:12] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_MASK 0xfffff000 -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_SHIFT 12 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: FRAME_ERROR_THRESHOLD [11:08] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_MASK 0x00000f00 -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_SHIFT 8 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: DISPARITY_ERROR_THRESHOLD [07:04] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_MASK 0x000000f0 -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_SHIFT 4 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: CODE_ERROR_THRESHOLD [03:00] */ -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_MASK 0x0000000f -#define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *PHY_TEST_CONTROL - TYPE_PHY_TEST_CONTROL Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_0 [31:31] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_MASK 0x80000000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_SHIFT 31 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DELAY_HOTRESET_ENABLE [30:30] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_MASK 0x40000000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_SHIFT 30 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_TSX_MAJORITY_CHECK [29:29] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_MASK 0x20000000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_SHIFT 29 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_MASK_OFF_BOGUS [28:28] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_MASK 0x10000000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_SHIFT 28 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_POLARITY_CHECK [27:27] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_MASK 0x08000000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_SHIFT 27 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_STICKY_POLARITY_CHECK [26:26] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_MASK 0x04000000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_SHIFT 26 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_1 [25:23] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_MASK 0x03800000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_SHIFT 23 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: TWO_OS_RULE_RELAXING [22:22] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_MASK 0x00400000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_SHIFT 22 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_HOT_RESET [21:21] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_MASK 0x00200000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_SHIFT 21 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_LINK_DOWN_RESET [20:20] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_MASK 0x00100000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_SHIFT 20 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE [19:19] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_MASK 0x00080000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_SHIFT 19 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_EXIT [18:18] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_MASK 0x00040000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_SHIFT 18 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_MASK [17:17] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_MASK 0x00020000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_SHIFT 17 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_RECOVERY [16:16] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_MASK 0x00010000 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_SHIFT 16 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: RESERVED_0 [15:08] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_MASK 0x0000ff00 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_2 [07:04] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_MASK 0x000000f0 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_SHIFT 4 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ22100_FIX_DISABLE [03:03] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_MASK 0x00000008 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_SHIFT 3 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: TRAINING_BYPASS [02:02] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_MASK 0x00000004 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_SHIFT 2 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: EXTERNAL_LOOPBACK [01:01] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_MASK 0x00000002 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_SHIFT 1 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: INTERNAL_LOOPBACK [00:00] */ -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_MASK 0x00000001 -#define BCHP_PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_SHIFT 0 - -/*************************************************************************** - *PHY_SERDES_CONTROL_OVERRIDE - TYPE_PHY_SERDES_CONTROL_OVERRIDE Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RESERVED_0 [31:18] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_MASK 0xfffc0000 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_SHIFT 18 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEVALUE [17:17] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_MASK 0x00020000 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_SHIFT 17 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEOVERRIDE [16:16] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_MASK 0x00010000 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_SHIFT 16 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPVALUE [15:15] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_MASK 0x00008000 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_SHIFT 15 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPOVERRIDE [14:14] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_MASK 0x00004000 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_SHIFT 14 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETVALUE [13:13] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_MASK 0x00002000 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_SHIFT 13 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETOVERRIDE [12:12] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_MASK 0x00001000 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_SHIFT 12 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETTIMECONTROL [11:10] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_MASK 0x00000c00 -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_SHIFT 10 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETECTIONTIME [09:00] */ -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_MASK 0x000003ff -#define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_SHIFT 0 - -/*************************************************************************** - *PHY_TIMING_PARAMETER_OVERRIDE - TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TS1NUMOVERRIDE [31:31] */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_MASK 0x80000000 -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_SHIFT 31 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINOVERRIDE [30:30] */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_MASK 0x40000000 -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_SHIFT 30 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLE2IDLEOVERRIDE [29:29] */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_MASK 0x20000000 -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_SHIFT 29 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: UNUSED_0 [28:28] */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_MASK 0x10000000 -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_SHIFT 28 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: N_TS1INPOLLINGACTIVE [27:16] */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_MASK 0x0fff0000 -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_SHIFT 16 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINTIME [15:08] */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_MASK 0x0000ff00 -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_SHIFT 8 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLESETTOIDLETIME [07:00] */ -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_MASK 0x000000ff -#define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_SHIFT 0 - -/*************************************************************************** - *PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES - TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RESERVED_0 [31:10] */ -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_MASK 0xfffffc00 -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_SHIFT 10 - -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: TRANSMIT_STATE_MACHINE_STATE [09:04] */ -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_MASK 0x000003f0 -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_SHIFT 4 - -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RECEIVE_STATE_MACHINE_STATE [03:00] */ -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_MASK 0x0000000f -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_SHIFT 0 - -/*************************************************************************** - *PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES - TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register - ***************************************************************************/ -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES :: LTSSM_STATE_MACHINE_STATE [31:00] */ -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_MASK 0xffffffff -#define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_SHIFT 0 - -#endif /* #ifndef BCHP_PCIE_PHY_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,594 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pcie_tl.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:13p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:28 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:13p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PCIE_TL_H__ -#define BCHP_PCIE_TL_H__ - -/*************************************************************************** - *PCIE_TL - PCIE TL related registers - ***************************************************************************/ -#define BCHP_PCIE_TL_TL_CONTROL 0x00500400 /* TL_CONTROL Register */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION 0x00500404 /* TRANSACTION_CONFIGURATION Register */ -#define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00500408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0050040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ -#define BCHP_PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00500410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00500414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00500418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0050041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00500420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00500424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0050043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00500458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0050045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00500460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00500464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00500468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ -#define BCHP_PCIE_TL_TL_DEBUG 0x0050046c /* TL_DEBUG Register */ - -/*************************************************************************** - *TL_CONTROL - TL_CONTROL Register - ***************************************************************************/ -/* PCIE_TL :: TL_CONTROL :: RESERVED_0 [31:31] */ -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_0_MASK 0x80000000 -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_0_SHIFT 31 - -/* PCIE_TL :: TL_CONTROL :: CQ14298_FIX_ENA_N [30:30] */ -#define BCHP_PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_MASK 0x40000000 -#define BCHP_PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_SHIFT 30 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_1 [29:29] */ -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_1_MASK 0x20000000 -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_1_SHIFT 29 - -/* PCIE_TL :: TL_CONTROL :: INTA_WAKEUP_LINK_CLKREQ_DA [28:28] */ -#define BCHP_PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_MASK 0x10000000 -#define BCHP_PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_SHIFT 28 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_2 [27:27] */ -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_2_MASK 0x08000000 -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_2_SHIFT 27 - -/* PCIE_TL :: TL_CONTROL :: CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX [26:26] */ -#define BCHP_PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_MASK 0x04000000 -#define BCHP_PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_SHIFT 26 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_3 [25:25] */ -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_3_MASK 0x02000000 -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_3_SHIFT 25 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_4 [24:24] */ -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_4_MASK 0x01000000 -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_4_SHIFT 24 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_5 [23:23] */ -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_5_MASK 0x00800000 -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_5_SHIFT 23 - -/* PCIE_TL :: TL_CONTROL :: CRC_SWAP [22:22] */ -#define BCHP_PCIE_TL_TL_CONTROL_CRC_SWAP_MASK 0x00400000 -#define BCHP_PCIE_TL_TL_CONTROL_CRC_SWAP_SHIFT 22 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_CA_ERROR [21:21] */ -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_MASK 0x00200000 -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_SHIFT 21 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_UR_ERROR [20:20] */ -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_MASK 0x00100000 -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_SHIFT 20 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_RSV_ERROR [19:19] */ -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_MASK 0x00080000 -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_SHIFT 19 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_6 [18:18] */ -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_6_MASK 0x00040000 -#define BCHP_PCIE_TL_TL_CONTROL_RESERVED_6_SHIFT 18 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_EP_ERROR [17:17] */ -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_MASK 0x00020000 -#define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_SHIFT 17 - -/* PCIE_TL :: TL_CONTROL :: ENABLE_BYTECOUNT_CHECK [16:16] */ -#define BCHP_PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_MASK 0x00010000 -#define BCHP_PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_SHIFT 16 - -/* PCIE_TL :: TL_CONTROL :: NOT_USED [15:14] */ -#define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_MASK 0x0000c000 -#define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_SHIFT 14 - -/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DR [13:11] */ -#define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_MASK 0x00003800 -#define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_SHIFT 11 - -/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DW [10:08] */ -#define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_MASK 0x00000700 -#define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_SHIFT 8 - -/* PCIE_TL :: TL_CONTROL :: NOT_USED_0 [07:06] */ -#define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_0_MASK 0x000000c0 -#define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_0_SHIFT 6 - -/* PCIE_TL :: TL_CONTROL :: NOT_USED_1 [05:00] */ -#define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_1_MASK 0x0000003f -#define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_1_SHIFT 0 - -/*************************************************************************** - *TRANSACTION_CONFIGURATION - TRANSACTION_CONFIGURATION Register - ***************************************************************************/ -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_RETRY_BUFFER_TIMING_MOD [31:31] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_MASK 0x80000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_SHIFT 31 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_0 [30:30] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_MASK 0x40000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_SHIFT 30 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_SINGLE_SHOT_ENABLE [29:29] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_MASK 0x20000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_SHIFT 29 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_1 [28:28] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_MASK 0x10000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_SHIFT 28 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: SELECT_CORE_CLOCK_OVERRIDE [27:27] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_MASK 0x08000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_SHIFT 27 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CQ9139_FIX_ENABLE [26:26] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_MASK 0x04000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_SHIFT 26 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CMPT_PWR_CHECK [25:25] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_MASK 0x02000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_SHIFT 25 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12696_FIX [24:24] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_MASK 0x01000000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_SHIFT 24 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_NO_OVERRIDE [23:23] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_MASK 0x00800000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_SHIFT 23 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12455_FIX [22:22] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_MASK 0x00400000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_SHIFT 22 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_TC_VC_FILTERING_CHECK [21:21] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_MASK 0x00200000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_SHIFT 21 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DONT_GEN_HOT_PLUG_MSG [20:20] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_MASK 0x00100000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_SHIFT 20 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: IGNORE_HOTPLUG_MSG [19:19] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_MASK 0x00080000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_SHIFT 19 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_MULTMSG_CAPABLE [18:16] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_MASK 0x00070000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_SHIFT 16 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DATA_SELECT_LIMIT [15:12] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_MASK 0x0000f000 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_SHIFT 12 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_PL [11:11] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_MASK 0x00000800 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_SHIFT 11 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_DL [10:10] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_MASK 0x00000400 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_SHIFT 10 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_TL [09:09] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_MASK 0x00000200 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_SHIFT 9 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_2 [08:08] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_MASK 0x00000100 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_SHIFT 8 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_CAP_ENABLE [07:07] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_CAP_ENABLE_MASK 0x00000080 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_CAP_ENABLE_SHIFT 7 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: PCIE_POWER_BUDGET_CAP_ENABLE [06:06] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_MASK 0x00000040 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_SHIFT 6 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: LOM_CONFIGURATION [05:05] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_MASK 0x00000020 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_SHIFT 5 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CONCATE_SELECT [04:04] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_MASK 0x00000010 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_SHIFT 4 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_3 [03:03] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_MASK 0x00000008 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_SHIFT 3 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9468_FIX [02:02] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_MASK 0x00000004 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_SHIFT 2 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: POWER_STATE_WRITE_MEM_ENABLE [01:01] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_MASK 0x00000002 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_SHIFT 1 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9709_ENABLE [00:00] */ -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_MASK 0x00000001 -#define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_SHIFT 0 - -/*************************************************************************** - *WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC - WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: RESERVED_0 [31:00] */ -#define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_MASK 0xffffffff -#define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_SHIFT 0 - -/*************************************************************************** - *WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 - WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register - ***************************************************************************/ -/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 :: RESERVED_0 [31:00] */ -#define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_MASK 0xffffffff -#define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_SHIFT 0 - -/*************************************************************************** - *DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC - DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: REG_MADDR_UPR [31:00] */ -#define BCHP_PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_MASK 0xffffffff -#define BCHP_PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_SHIFT 0 - -/*************************************************************************** - *DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 - DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 :: REG_MADDR_LWR [31:00] */ -#define BCHP_PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_MASK 0xffffffff -#define BCHP_PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_SHIFT 0 - -/*************************************************************************** - *DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC - DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: REG_MLEN_BE [31:24] */ -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_MASK 0xff000000 -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_SHIFT 24 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_FIRST_DW_BYTE_ENABLES [23:20] */ -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_MASK 0x00f00000 -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_SHIFT 20 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_LAST_DW_BYTE_ENABLES [19:16] */ -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_MASK 0x000f0000 -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_SHIFT 16 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: RESERVED_0 [15:11] */ -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_MASK 0x0000f800 -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_SHIFT 11 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_DW_LENGTH [10:00] */ -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_MASK 0x000007ff -#define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_SHIFT 0 - -/*************************************************************************** - *DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC - DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: REG_MTAG_ATTR [31:19] */ -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_MASK 0xfff80000 -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_SHIFT 19 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_FUNCTION [18:16] */ -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_MASK 0x00070000 -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_SHIFT 16 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_0 [15:13] */ -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_SHIFT 13 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_ATTRIBUTES [12:08] */ -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_MASK 0x00001f00 -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_SHIFT 8 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_1 [07:05] */ -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_SHIFT 5 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_TAG [04:00] */ -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_MASK 0x0000001f -#define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_SHIFT 0 - -/*************************************************************************** - *READ_DMA_SPLIT_IDS_DIAGNOSTIC - READ_DMA_SPLIT_IDS_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: REG_SPLIT_ID [31:16] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_MASK 0xffff0000 -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_SHIFT 16 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_0 [15:13] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_SHIFT 13 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_ATTRIBUTES [12:11] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_MASK 0x00001800 -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_SHIFT 11 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TC [10:08] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_MASK 0x00000700 -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_SHIFT 8 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_1 [07:05] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_SHIFT 5 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TAG [04:00] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_MASK 0x0000001f -#define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_SHIFT 0 - -/*************************************************************************** - *READ_DMA_SPLIT_LENGTH_DIAGNOSTIC - READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: REG_SPLIT_LEN [31:13] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_MASK 0xffffe000 -#define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_SHIFT 13 - -/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: READ_DMA_SPLIT_INITIAL_BYTE_COUNT [12:00] */ -#define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_MASK 0x00001fff -#define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_SHIFT 0 - -/*************************************************************************** - *XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC - XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: REG_SM_R0_R3 [31:31] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_MASK 0x80000000 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_SHIFT 31 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_DATA_STATE_MACHINE [30:28] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_MASK 0x70000000 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_SHIFT 28 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE [27:23] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_MASK 0x0f800000 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_SHIFT 23 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: RESERVED_0 [22:07] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_MASK 0x007fff80 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_SHIFT 7 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_RAW_REQUEST [06:06] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_MASK 0x00000040 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_SHIFT 6 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_RAW_REQUEST [05:05] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_MASK 0x00000020 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_SHIFT 5 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: INTERRUPT_MSG_GATED_REQUEST [04:04] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_MASK 0x00000010 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_SHIFT 4 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: MSI_DMA_GATED_REQUEST [03:03] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_MASK 0x00000008 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_SHIFT 3 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TARGET_COMPLETION_OR_MSG_GATED_REQUEST [02:02] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_MASK 0x00000004 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_SHIFT 2 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_GATED_REQUEST [01:01] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_MASK 0x00000002 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_SHIFT 1 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_GATED_REQUEST [00:00] */ -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_MASK 0x00000001 -#define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_SHIFT 0 - -/*************************************************************************** - *DMA_COMPLETION_MISC__DIAGNOSTIC - DMA_COMPLETION_MISC__DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: REG_DMA_CMPT_MISC2 [31:29] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_MASK 0xe0000000 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_SHIFT 29 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_BYTE_LENGTH_REMAINING [28:16] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_MASK 0x1fff0000 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_SHIFT 16 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: NOT_USED [15:15] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_MASK 0x00008000 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_SHIFT 15 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED [14:14] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_MASK 0x00004000 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_SHIFT 14 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED [13:13] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_MASK 0x00002000 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_SHIFT 13 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1 [12:12] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_MASK 0x00001000 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_SHIFT 12 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST [11:11] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_MASK 0x00000800 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_SHIFT 11 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS [10:10] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_MASK 0x00000400 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_SHIFT 10 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_FULLY [09:09] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_MASK 0x00000200 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_SHIFT 9 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_DW_DATA_VALID_ADDRESS_ACK [08:08] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_MASK 0x00000100 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_SHIFT 8 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER [07:04] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_MASK 0x000000f0 -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_SHIFT 4 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: FRAME_DEAD_TIME_ERROR_COUNTER [03:00] */ -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_MASK 0x0000000f -#define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_SHIFT 0 - -/*************************************************************************** - *SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC - SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: REG_SPLITCTL_MISC0 [31:29] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_MASK 0xe0000000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_SHIFT 29 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING [28:16] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_MASK 0x1fff0000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_SHIFT 16 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID [15:00] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_MASK 0x0000ffff -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_SHIFT 0 - -/*************************************************************************** - *SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC - SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: REG_SPLITCTL_MISC1 [31:16] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_MASK 0xffff0000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_SHIFT 16 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_0 [15:15] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_MASK 0x00008000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_SHIFT 15 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS [14:08] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_MASK 0x00007f00 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_SHIFT 8 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_1 [07:07] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_MASK 0x00000080 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_SHIFT 7 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE [06:05] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_MASK 0x00000060 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_SHIFT 5 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_TAG [04:00] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_MASK 0x0000001f -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_SHIFT 0 - -/*************************************************************************** - *SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC - SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register - ***************************************************************************/ -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: REG_SPLITCTL_MISC2 [31:31] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_MASK 0x80000000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_SHIFT 31 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS [30:30] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_MASK 0x40000000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_SHIFT 30 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_VALID_TAG [29:29] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_MASK 0x20000000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_SHIFT 29 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: UPDATED_BYTE_COUNT [28:16] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_MASK 0x1fff0000 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_SHIFT 16 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: RESERVED_0 [15:08] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_MASK 0x0000ff00 -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_SHIFT 8 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: SPLIT_TABLE_VALID_ARRAY [07:00] */ -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_MASK 0x000000ff -#define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_SHIFT 0 - -/*************************************************************************** - *TL_BUS_NO_DEV__NO__FUNC__NO - TL_BUS_NO_DEV__NO__FUNC__NO Register - ***************************************************************************/ -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: RESERVED_0 [31:17] */ -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_MASK 0xfffe0000 -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_SHIFT 17 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: CONFIG_WRITE_INDICATER [16:16] */ -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_MASK 0x00010000 -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_SHIFT 16 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: BUS_NUMBER [15:08] */ -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_MASK 0x0000ff00 -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_SHIFT 8 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: DEVICE_NUMBER [07:03] */ -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_MASK 0x000000f8 -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_SHIFT 3 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: FUNCTION_NUMBER [02:00] */ -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_MASK 0x00000007 -#define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_SHIFT 0 - -/*************************************************************************** - *TL_DEBUG - TL_DEBUG Register - ***************************************************************************/ -/* PCIE_TL :: TL_DEBUG :: A4_DEVICE_INDICATION_BIT [31:31] */ -#define BCHP_PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_MASK 0x80000000 -#define BCHP_PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_SHIFT 31 - -/* PCIE_TL :: TL_DEBUG :: B1_DEVICE_INDICATION_BIT [30:30] */ -#define BCHP_PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_MASK 0x40000000 -#define BCHP_PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_SHIFT 30 - -/* PCIE_TL :: TL_DEBUG :: RESERVED_0 [29:00] */ -#define BCHP_PCIE_TL_TL_DEBUG_RESERVED_0_MASK 0x3fffffff -#define BCHP_PCIE_TL_TL_DEBUG_RESERVED_0_SHIFT 0 - -#endif /* #ifndef BCHP_PCIE_TL_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,202 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pm_l2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:13p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:04 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:13p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PM_L2_H__ -#define BCHP_PM_L2_H__ - -/*************************************************************************** - *PM_L2 - Registers for the power management block's L2 interrupt controller - ***************************************************************************/ -#define BCHP_PM_L2_CPU_STATUS 0x00401c00 /* CPU interrupt Status Register */ -#define BCHP_PM_L2_CPU_SET 0x00401c04 /* CPU interrupt Set Register */ -#define BCHP_PM_L2_CPU_CLEAR 0x00401c08 /* CPU interrupt Clear Register */ -#define BCHP_PM_L2_CPU_MASK_STATUS 0x00401c0c /* CPU interrupt Mask Status Register */ -#define BCHP_PM_L2_CPU_MASK_SET 0x00401c10 /* CPU interrupt Mask Set Register */ -#define BCHP_PM_L2_CPU_MASK_CLEAR 0x00401c14 /* CPU interrupt Mask Clear Register */ -#define BCHP_PM_L2_PCI_STATUS 0x00401c18 /* PCI interrupt Status Register */ -#define BCHP_PM_L2_PCI_SET 0x00401c1c /* PCI interrupt Set Register */ -#define BCHP_PM_L2_PCI_CLEAR 0x00401c20 /* PCI interrupt Clear Register */ -#define BCHP_PM_L2_PCI_MASK_STATUS 0x00401c24 /* PCI interrupt Mask Status Register */ -#define BCHP_PM_L2_PCI_MASK_SET 0x00401c28 /* PCI interrupt Mask Set Register */ -#define BCHP_PM_L2_PCI_MASK_CLEAR 0x00401c2c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* PM_L2 :: CPU_STATUS :: reserved0 [31:01] */ -#define BCHP_PM_L2_CPU_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_CPU_STATUS_reserved0_SHIFT 1 - -/* PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* PM_L2 :: CPU_SET :: reserved0 [31:01] */ -#define BCHP_PM_L2_CPU_SET_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_CPU_SET_reserved0_SHIFT 1 - -/* PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* PM_L2 :: CPU_CLEAR :: reserved0 [31:01] */ -#define BCHP_PM_L2_CPU_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_CPU_CLEAR_reserved0_SHIFT 1 - -/* PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:01] */ -#define BCHP_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 1 - -/* PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* PM_L2 :: CPU_MASK_SET :: reserved0 [31:01] */ -#define BCHP_PM_L2_CPU_MASK_SET_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_CPU_MASK_SET_reserved0_SHIFT 1 - -/* PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:01] */ -#define BCHP_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 1 - -/* PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* PM_L2 :: PCI_STATUS :: reserved0 [31:01] */ -#define BCHP_PM_L2_PCI_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_PCI_STATUS_reserved0_SHIFT 1 - -/* PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* PM_L2 :: PCI_SET :: reserved0 [31:01] */ -#define BCHP_PM_L2_PCI_SET_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_PCI_SET_reserved0_SHIFT 1 - -/* PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* PM_L2 :: PCI_CLEAR :: reserved0 [31:01] */ -#define BCHP_PM_L2_PCI_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_PCI_CLEAR_reserved0_SHIFT 1 - -/* PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:01] */ -#define BCHP_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 1 - -/* PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* PM_L2 :: PCI_MASK_SET :: reserved0 [31:01] */ -#define BCHP_PM_L2_PCI_MASK_SET_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_PCI_MASK_SET_reserved0_SHIFT 1 - -/* PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:01] */ -#define BCHP_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 1 - -/* PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ -#define BCHP_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 -#define BCHP_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 - -#endif /* #ifndef BCHP_PM_L2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arch_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arch_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arch_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arch_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,333 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_arch_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:14p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:53 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arch_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:14p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_ARCH_REGS_H__ -#define BCHP_PRI_ARB_ARCH_REGS_H__ - -/*************************************************************************** - *PRI_ARB_ARCH_REGS - PRIMARY_ARB address range and alias checker registers - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG 0x0040cda0 /* Address Alias Checker control register */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_ADDR 0x0040cda4 /* Address Alias Checker violating command address. */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO 0x0040cda8 /* Address Alias Checker violating command information. */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR 0x0040cdac /* Address Alias Checker violating command status release. */ - -/*************************************************************************** - *CNTRL_REG%i - Address Range Checker (ARCH0..3) control register - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_BASE 0x0040cc00 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *CNTRL_REG%i - Address Range Checker (ARCH0..3) control register - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: reserved0 [31:06] */ -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_reserved0_MASK 0xffffffc0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_reserved0_SHIFT 6 - -/* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: READ_ABORT [05:05] */ -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_MASK 0x00000020 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_SHIFT 5 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_DISABLED 0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_ENABLED 1 - -/* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: WRITE_ABORT [04:04] */ -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_MASK 0x00000010 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_SHIFT 4 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_DISABLED 0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_ENABLED 1 - -/* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: WRITE_CHECK [03:03] */ -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_MASK 0x00000008 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_SHIFT 3 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_DISABLED 0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_ENABLED 1 - -/* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: READ_CHECK [02:02] */ -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_MASK 0x00000004 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_SHIFT 2 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_DISABLED 0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_ENABLED 1 - -/* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: MODE [01:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_MASK 0x00000003 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_SHIFT 0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_NON_EXCLUSIVE 0 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_EXCLUSIVE 1 -#define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_ULTRA_EXCLUSIVE 2 - - -/*************************************************************************** - *ADRS_RANGE_LOW%i - Address Range Checker (ARCH0..3) memory range lower address register - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_BASE 0x0040cc20 -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *ADRS_RANGE_LOW%i - Address Range Checker (ARCH0..3) memory range lower address register - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: ADRS_RANGE_LOWi :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_SHIFT 0 - - -/*************************************************************************** - *ADRS_RANGE_HIGH%i - Address Range Checker (ARCH0..3) memory range upper address register - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_BASE 0x0040cc40 -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *ADRS_RANGE_HIGH%i - Address Range Checker (ARCH0..3) memory range upper address register - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: ADRS_RANGE_HIGHi :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_SHIFT 0 - - -/*************************************************************************** - *READ_RIGHTS_0_%i - Address Range Checker (ARCH0..3) read access rights for clients #0 through #19. - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_BASE 0x0040cc60 -#define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *READ_RIGHTS_0_%i - Address Range Checker (ARCH0..3) read access rights for clients #0 through #19. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: READ_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff -#define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 - - -/*************************************************************************** - *WRITE_RIGHTS_0_%i - Address Range Checker (ARCH0..3) write access rights for clients #0 through #19. - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_BASE 0x0040ccc0 -#define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *WRITE_RIGHTS_0_%i - Address Range Checker (ARCH0..3) write access rights for clients #0 through #19. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: WRITE_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff -#define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 - - -/*************************************************************************** - *VIOL_ADDR%i - Address Range Checker (ARCH0..3) violating command address. - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_BASE 0x0040cd40 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *VIOL_ADDR%i - Address Range Checker (ARCH0..3) violating command address. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: VIOL_ADDRi :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ADDRESS_SHIFT 0 - - -/*************************************************************************** - *VIOL_INFO%i - Address Range Checker (ARCH0..3) violating command information. - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_BASE 0x0040cd60 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *VIOL_INFO%i - Address Range Checker (ARCH0..3) violating command information. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: CLIENTID [31:24] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_CLIENTID_MASK 0xff000000 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_CLIENTID_SHIFT 24 - -/* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: reserved0 [23:22] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved0_MASK 0x00c00000 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved0_SHIFT 22 - -/* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: LENGTH [21:12] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_LENGTH_MASK 0x003ff000 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_LENGTH_SHIFT 12 - -/* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: MODE [11:09] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_MODE_MASK 0x00000e00 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_MODE_SHIFT 9 - -/* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: WRITE [08:08] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_WRITE_MASK 0x00000100 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_WRITE_SHIFT 8 - -/* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: reserved1 [07:01] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved1_MASK 0x000000fe -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved1_SHIFT 1 - -/* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: STATUS [00:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_STATUS_MASK 0x00000001 -#define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_STATUS_SHIFT 0 - - -/*************************************************************************** - *STATUS_CLEAR%i - Address Range Checker (ARCH0..3) violating command status release. - ***************************************************************************/ -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_BASE 0x0040cd80 -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_START 0 -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_END 3 -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *STATUS_CLEAR%i - Address Range Checker (ARCH0..3) violating command status release. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: STATUS_CLEARi :: reserved0 [31:01] */ -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_reserved0_MASK 0xfffffffe -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_reserved0_SHIFT 1 - -/* PRI_ARB_ARCH_REGS :: STATUS_CLEARi :: CLEAR [00:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_CLEAR_MASK 0x00000001 -#define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_CLEAR_SHIFT 0 - - -/*************************************************************************** - *ALIAS_CNTRL_REG - Address Alias Checker control register - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: reserved0 [31:06] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_reserved0_MASK 0xffffffc0 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_reserved0_SHIFT 6 - -/* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: WRITE_ABORT [05:05] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_MASK 0x00000020 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_SHIFT 5 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_DISABLED 0 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_ENABLED 1 - -/* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: CHECK [04:04] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_MASK 0x00000010 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_SHIFT 4 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_DISABLED 0 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_ENABLED 1 - -/* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: DDR1_SIZE [03:02] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_MASK 0x0000000c -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SHIFT 2 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_64_MB 0 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_128_MB 1 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_256_MB 2 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_512_MB 3 - -/* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: DDR0_SIZE [01:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_MASK 0x00000003 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SHIFT 0 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_64_MB 0 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_128_MB 1 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_256_MB 2 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_512_MB 3 - -/*************************************************************************** - *ALIAS_VIOL_ADDR - Address Alias Checker violating command address. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_ADDR :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_ADDR_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_ADDR_ADDRESS_SHIFT 0 - -/*************************************************************************** - *ALIAS_VIOL_INFO - Address Alias Checker violating command information. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: CLIENTID [31:24] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_CLIENTID_MASK 0xff000000 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_CLIENTID_SHIFT 24 - -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: reserved0 [23:22] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved0_MASK 0x00c00000 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved0_SHIFT 22 - -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: LENGTH [21:12] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_LENGTH_MASK 0x003ff000 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_LENGTH_SHIFT 12 - -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: MODE [11:09] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_MODE_MASK 0x00000e00 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_MODE_SHIFT 9 - -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: WRITE [08:08] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_WRITE_MASK 0x00000100 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_WRITE_SHIFT 8 - -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: reserved1 [07:01] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved1_MASK 0x000000fe -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved1_SHIFT 1 - -/* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: STATUS [00:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_STATUS_MASK 0x00000001 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_STATUS_SHIFT 0 - -/*************************************************************************** - *ALIAS_STATUS_CLEAR - Address Alias Checker violating command status release. - ***************************************************************************/ -/* PRI_ARB_ARCH_REGS :: ALIAS_STATUS_CLEAR :: reserved0 [31:01] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_reserved0_SHIFT 1 - -/* PRI_ARB_ARCH_REGS :: ALIAS_STATUS_CLEAR :: CLEAR [00:00] */ -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_CLEAR_MASK 0x00000001 -#define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_CLEAR_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_ARB_ARCH_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,202 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_arc_l1_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:14p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:14 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:14p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_ARC_L1_REGS_H__ -#define BCHP_PRI_ARB_ARC_L1_REGS_H__ - -/*************************************************************************** - *PRI_ARB_ARC_L1_REGS - PRIMARY_ARB L1 (ARCs) Interrupt Registers - ***************************************************************************/ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS 0x0040cf00 /* Interrupt Status Register */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS 0x0040cf04 /* Interrupt Status Register */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS 0x0040cf08 /* Interrupt Mask Status Register */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS 0x0040cf0c /* Interrupt Mask Status Register */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET 0x0040cf10 /* Interrupt Mask Set Register */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET 0x0040cf14 /* Interrupt Mask Set Register */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR 0x0040cf18 /* Interrupt Mask Clear Register */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR 0x0040cf1c /* Interrupt Mask Clear Register */ - -/*************************************************************************** - *INTR_W0_STATUS - Interrupt Status Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: reserved0 [31:05] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_reserved0_MASK 0xffffffe0 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_reserved0_SHIFT 5 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ALIAS_INTR [04:04] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ALIAS_INTR_MASK 0x00000010 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ALIAS_INTR_SHIFT 4 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH3_INTR [03:03] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH3_INTR_MASK 0x00000008 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH3_INTR_SHIFT 3 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH2_INTR [02:02] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH2_INTR_MASK 0x00000004 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH2_INTR_SHIFT 2 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH1_INTR [01:01] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH1_INTR_MASK 0x00000002 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH1_INTR_SHIFT 1 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH0_INTR [00:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH0_INTR_MASK 0x00000001 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH0_INTR_SHIFT 0 - -/*************************************************************************** - *INTR_W1_STATUS - Interrupt Status Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W1_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *INTR_W0_MASK_STATUS - Interrupt Mask Status Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: reserved0 [31:05] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_reserved0_MASK 0xffffffe0 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_reserved0_SHIFT 5 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ALIAS_MASK [04:04] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ALIAS_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ALIAS_MASK_SHIFT 4 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *INTR_W1_MASK_STATUS - Interrupt Mask Status Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *INTR_W0_MASK_SET - Interrupt Mask Set Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: reserved0 [31:05] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_reserved0_MASK 0xffffffe0 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_reserved0_SHIFT 5 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ALIAS_MASK [04:04] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ALIAS_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ALIAS_MASK_SHIFT 4 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *INTR_W1_MASK_SET - Interrupt Mask Set Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_SET :: reserved0 [31:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: reserved0 [31:05] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_reserved0_MASK 0xffffffe0 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_reserved0_SHIFT 5 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ALIAS_MASK [04:04] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ALIAS_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ALIAS_MASK_SHIFT 4 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_ARB_ARC_L1_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,336 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_control_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:14p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:12 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:14p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ -#define BCHP_PRI_ARB_CONTROL_REGS_H__ - -/*************************************************************************** - *PRI_ARB_CONTROL_REGS - PRIMARY_ARB control registers - ***************************************************************************/ -#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0 0x0040cb00 /* Refresh client control for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0 0x0040cb04 /* Write timeout control for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0 0x0040cb08 /* Write timeout status for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0 0x0040cb0c /* Write timeout status clear for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC 0x0040cb10 /* Write timeout bad concentrators */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL 0x0040cb14 /* Performance Monitor Control */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR 0x0040cb18 /* Performance Monitor Clear Counts */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0 0x0040cb1c /* Performance Monitor Events for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0 0x0040cb20 /* Performance Monitor Sum of Latencies for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0 0x0040cb24 /* Performance Monitor Sum of Request Sizes for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0 0x0040cb28 /* Performance Monitor Maximum Latency for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A 0x0040cb2c /* Performance Monitor Client Access bits 19:0 for ddr interface #0 */ -#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL 0x0040cb30 /* Master Control */ - -/*************************************************************************** - *REFRESH_CTL_0 - Refresh client control for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: reserved0 [31:13] */ -#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_reserved0_MASK 0xffffe000 -#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_reserved0_SHIFT 13 - -/* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: enable [12:12] */ -#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK 0x00001000 -#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_SHIFT 12 - -/* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: period [11:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_period_MASK 0x00000fff -#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_period_SHIFT 0 - -/*************************************************************************** - *WR_TIMEOUT_CTL_0 - Write timeout control for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: reserved0 [31:13] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_reserved0_MASK 0xffffe000 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_reserved0_SHIFT 13 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: enable [12:12] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_enable_MASK 0x00001000 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_enable_SHIFT 12 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: period [11:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_period_MASK 0x00000fff -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_period_SHIFT 0 - -/*************************************************************************** - *WR_TIMEOUT_STS_0 - Write timeout status for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: reserved0 [31:10] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved0_MASK 0xfffffc00 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved0_SHIFT 10 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: long [09:09] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_long_MASK 0x00000200 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_long_SHIFT 9 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: short [08:08] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_short_MASK 0x00000100 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_short_SHIFT 8 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: reserved1 [07:07] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved1_MASK 0x00000080 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved1_SHIFT 7 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: client [06:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_client_MASK 0x0000007f -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_client_SHIFT 0 - -/*************************************************************************** - *WR_TIMEOUT_CLR_0 - Write timeout status clear for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CLR_0 :: reserved0 [31:01] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_reserved0_MASK 0xfffffffe -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_reserved0_SHIFT 1 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CLR_0 :: clear [00:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_clear_MASK 0x00000001 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_clear_SHIFT 0 - -/*************************************************************************** - *WR_TIMEOUT_BAD_CONC - Write timeout bad concentrators - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: reserved0 [31:07] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_reserved0_MASK 0xffffff80 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_reserved0_SHIFT 7 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_06 [06:06] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_06_MASK 0x00000040 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_06_SHIFT 6 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_05 [05:05] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_05_MASK 0x00000020 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_05_SHIFT 5 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_04 [04:04] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_04_MASK 0x00000010 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_04_SHIFT 4 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_03 [03:03] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_03_MASK 0x00000008 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_03_SHIFT 3 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_02 [02:02] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_02_MASK 0x00000004 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_02_SHIFT 2 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_01 [01:01] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_01_MASK 0x00000002 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_01_SHIFT 1 - -/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_00 [00:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_00_MASK 0x00000001 -#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_00_SHIFT 0 - -/*************************************************************************** - *PERF_MON_CTL - Performance Monitor Control - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: reserved0 [31:16] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved0_MASK 0xffff0000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved0_SHIFT 16 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: client_sel [15:08] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_client_sel_MASK 0x0000ff00 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_client_sel_SHIFT 8 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: reserved1 [07:03] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved1_MASK 0x000000f8 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved1_SHIFT 3 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: wr_enable [02:02] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_wr_enable_MASK 0x00000004 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_wr_enable_SHIFT 2 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: rd_enable [01:01] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_rd_enable_MASK 0x00000002 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_rd_enable_SHIFT 1 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: enable [00:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_enable_MASK 0x00000001 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_enable_SHIFT 0 - -/*************************************************************************** - *PERF_MON_CLR - Performance Monitor Clear Counts - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CLR :: reserved0 [31:01] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_reserved0_MASK 0xfffffffe -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_reserved0_SHIFT 1 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_CLR :: clear [00:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_clear_MASK 0x00000001 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_clear_SHIFT 0 - -/*************************************************************************** - *PERF_MON_EVENTS_0 - Performance Monitor Events for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: PERF_MON_EVENTS_0 :: count [31:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0_count_MASK 0xffffffff -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0_count_SHIFT 0 - -/*************************************************************************** - *PERF_MON_SUM_0 - Performance Monitor Sum of Latencies for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: PERF_MON_SUM_0 :: count [31:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0_count_MASK 0xffffffff -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0_count_SHIFT 0 - -/*************************************************************************** - *PERF_MON_SIZE_SUM_0 - Performance Monitor Sum of Request Sizes for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: PERF_MON_SIZE_SUM_0 :: count [31:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0_count_MASK 0xffffffff -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0_count_SHIFT 0 - -/*************************************************************************** - *PERF_MON_MAX_0 - Performance Monitor Maximum Latency for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: PERF_MON_MAX_0 :: count [31:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0_count_MASK 0xffffffff -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0_count_SHIFT 0 - -/*************************************************************************** - *PERF_MON_ACCESS_0A - Performance Monitor Client Access bits 19:0 for ddr interface #0 - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: reserved0 [31:20] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_reserved0_MASK 0xfff00000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_reserved0_SHIFT 20 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_19 [19:19] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_19_MASK 0x00080000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_19_SHIFT 19 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_18 [18:18] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_18_MASK 0x00040000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_18_SHIFT 18 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_17 [17:17] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_17_MASK 0x00020000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_17_SHIFT 17 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_16 [16:16] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_16_MASK 0x00010000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_16_SHIFT 16 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_15 [15:15] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_15_MASK 0x00008000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_15_SHIFT 15 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_14 [14:14] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_14_MASK 0x00004000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_14_SHIFT 14 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_13 [13:13] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_13_MASK 0x00002000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_13_SHIFT 13 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_12 [12:12] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_12_MASK 0x00001000 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_12_SHIFT 12 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_11 [11:11] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_11_MASK 0x00000800 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_11_SHIFT 11 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_10 [10:10] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_10_MASK 0x00000400 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_10_SHIFT 10 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_09 [09:09] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_09_MASK 0x00000200 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_09_SHIFT 9 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_08 [08:08] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_08_MASK 0x00000100 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_08_SHIFT 8 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_07 [07:07] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_07_MASK 0x00000080 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_07_SHIFT 7 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_06 [06:06] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_06_MASK 0x00000040 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_06_SHIFT 6 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_05 [05:05] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_05_MASK 0x00000020 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_05_SHIFT 5 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_04 [04:04] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_04_MASK 0x00000010 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_04_SHIFT 4 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_03 [03:03] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_03_MASK 0x00000008 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_03_SHIFT 3 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_02 [02:02] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_02_MASK 0x00000004 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_02_SHIFT 2 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_01 [01:01] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_01_MASK 0x00000002 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_01_SHIFT 1 - -/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_00 [00:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_00_MASK 0x00000001 -#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_00_SHIFT 0 - -/*************************************************************************** - *MASTER_CTL - Master Control - ***************************************************************************/ -/* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: reserved0 [31:01] */ -#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_reserved0_MASK 0xfffffffe -#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_reserved0_SHIFT 1 - -/* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: arb_disable [00:00] */ -#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_MASK 0x00000001 -#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_SHIFT 0 -#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable 0 -#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable 1 - -#endif /* #ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,586 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_mips_l2_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:14p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:15 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:14p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_MIPS_L2_REGS_H__ -#define BCHP_PRI_ARB_MIPS_L2_REGS_H__ - -/*************************************************************************** - *PRI_ARB_MIPS_L2_REGS - PRIMARY_ARB L2 (MIPS) Interrupt Registers - ***************************************************************************/ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS 0x0040ce00 /* CPU interrupt Status Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET 0x0040ce04 /* CPU interrupt Set Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR 0x0040ce08 /* CPU interrupt Clear Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS 0x0040ce0c /* CPU interrupt Mask Status Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET 0x0040ce10 /* CPU interrupt Mask Set Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR 0x0040ce14 /* CPU interrupt Mask Clear Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS 0x0040ce18 /* PCI interrupt Status Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET 0x0040ce1c /* PCI interrupt Set Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR 0x0040ce20 /* PCI interrupt Clear Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS 0x0040ce24 /* PCI interrupt Mask Status Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET 0x0040ce28 /* PCI interrupt Mask Set Register */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR 0x0040ce2c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ALIAS_INTR [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ALIAS_INTR_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ALIAS_INTR_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: WR_TIMEOUT_1_INTR [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_1_INTR_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_1_INTR_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: WR_TIMEOUT_0_INTR [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_0_INTR_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_0_INTR_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: TRACE_DONE_INTR [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_DONE_INTR_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_DONE_INTR_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: TRACE_TRIG_INTR [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_TRIG_INTR_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_TRIG_INTR_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH3_INTR [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH3_INTR_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH3_INTR_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH2_INTR [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH2_INTR_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH2_INTR_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH1_INTR [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH1_INTR_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH1_INTR_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH0_INTR [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH0_INTR_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH0_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ALIAS_INTR [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ALIAS_INTR_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ALIAS_INTR_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: WR_TIMEOUT_1_INTR [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_1_INTR_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_1_INTR_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: WR_TIMEOUT_0_INTR [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_0_INTR_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_0_INTR_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: TRACE_DONE_INTR [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_DONE_INTR_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_DONE_INTR_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: TRACE_TRIG_INTR [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_TRIG_INTR_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_TRIG_INTR_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH3_INTR [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH3_INTR_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH3_INTR_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH2_INTR [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH2_INTR_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH2_INTR_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH1_INTR [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH1_INTR_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH1_INTR_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH0_INTR [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH0_INTR_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH0_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ALIAS_INTR [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ALIAS_INTR_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ALIAS_INTR_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: WR_TIMEOUT_1_INTR [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_1_INTR_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_1_INTR_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: WR_TIMEOUT_0_INTR [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_0_INTR_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_0_INTR_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: TRACE_DONE_INTR [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_DONE_INTR_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_DONE_INTR_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: TRACE_TRIG_INTR [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_TRIG_INTR_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_TRIG_INTR_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH3_INTR [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH3_INTR_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH3_INTR_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH2_INTR [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH2_INTR_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH2_INTR_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH1_INTR [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH1_INTR_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH1_INTR_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH0_INTR [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH0_INTR_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH0_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ALIAS_MASK [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ALIAS_MASK_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ALIAS_MASK_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: WR_TIMEOUT_1_MASK [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_1_MASK_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_1_MASK_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: WR_TIMEOUT_0_MASK [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_0_MASK_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_0_MASK_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: TRACE_DONE_MASK [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_DONE_MASK_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_DONE_MASK_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: TRACE_TRIG_MASK [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_TRIG_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_TRIG_MASK_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ALIAS_MASK [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ALIAS_MASK_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ALIAS_MASK_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: WR_TIMEOUT_1_MASK [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_1_MASK_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_1_MASK_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: WR_TIMEOUT_0_MASK [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_0_MASK_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_0_MASK_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: TRACE_DONE_MASK [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_DONE_MASK_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_DONE_MASK_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: TRACE_TRIG_MASK [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_TRIG_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_TRIG_MASK_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ALIAS_MASK [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ALIAS_MASK_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ALIAS_MASK_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: WR_TIMEOUT_1_MASK [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_1_MASK_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_1_MASK_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: WR_TIMEOUT_0_MASK [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_0_MASK_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_0_MASK_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: TRACE_DONE_MASK [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_DONE_MASK_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_DONE_MASK_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: TRACE_TRIG_MASK [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_TRIG_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_TRIG_MASK_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ALIAS_INTR [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ALIAS_INTR_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ALIAS_INTR_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: WR_TIMEOUT_1_INTR [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_1_INTR_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_1_INTR_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: WR_TIMEOUT_0_INTR [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_0_INTR_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_0_INTR_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: TRACE_DONE_INTR [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_DONE_INTR_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_DONE_INTR_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: TRACE_TRIG_INTR [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_TRIG_INTR_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_TRIG_INTR_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH3_INTR [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH3_INTR_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH3_INTR_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH2_INTR [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH2_INTR_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH2_INTR_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH1_INTR [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH1_INTR_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH1_INTR_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH0_INTR [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH0_INTR_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH0_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ALIAS_INTR [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ALIAS_INTR_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ALIAS_INTR_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: WR_TIMEOUT_1_INTR [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_1_INTR_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_1_INTR_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: WR_TIMEOUT_0_INTR [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_0_INTR_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_0_INTR_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: TRACE_DONE_INTR [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_DONE_INTR_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_DONE_INTR_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: TRACE_TRIG_INTR [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_TRIG_INTR_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_TRIG_INTR_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH3_INTR [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH3_INTR_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH3_INTR_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH2_INTR [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH2_INTR_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH2_INTR_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH1_INTR [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH1_INTR_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH1_INTR_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH0_INTR [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH0_INTR_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH0_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ALIAS_INTR [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ALIAS_INTR_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ALIAS_INTR_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: WR_TIMEOUT_1_INTR [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_1_INTR_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_1_INTR_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: WR_TIMEOUT_0_INTR [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_0_INTR_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_0_INTR_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: TRACE_DONE_INTR [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_DONE_INTR_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_DONE_INTR_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: TRACE_TRIG_INTR [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_TRIG_INTR_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_TRIG_INTR_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH3_INTR [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH3_INTR_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH3_INTR_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH2_INTR [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH2_INTR_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH2_INTR_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH1_INTR [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH1_INTR_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH1_INTR_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH0_INTR [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH0_INTR_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH0_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ALIAS_MASK [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ALIAS_MASK_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ALIAS_MASK_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: WR_TIMEOUT_1_MASK [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_1_MASK_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_1_MASK_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: WR_TIMEOUT_0_MASK [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_0_MASK_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_0_MASK_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: TRACE_DONE_MASK [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_DONE_MASK_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_DONE_MASK_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: TRACE_TRIG_MASK [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_TRIG_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_TRIG_MASK_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ALIAS_MASK [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ALIAS_MASK_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ALIAS_MASK_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: WR_TIMEOUT_1_MASK [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_1_MASK_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_1_MASK_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: WR_TIMEOUT_0_MASK [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_0_MASK_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_0_MASK_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: TRACE_DONE_MASK [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_DONE_MASK_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_DONE_MASK_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: TRACE_TRIG_MASK [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_TRIG_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_TRIG_MASK_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH0_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_reserved0_SHIFT 9 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ALIAS_MASK [08:08] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ALIAS_MASK_MASK 0x00000100 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ALIAS_MASK_SHIFT 8 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: WR_TIMEOUT_1_MASK [07:07] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_1_MASK_MASK 0x00000080 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_1_MASK_SHIFT 7 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: WR_TIMEOUT_0_MASK [06:06] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_0_MASK_MASK 0x00000040 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_0_MASK_SHIFT 6 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: TRACE_DONE_MASK [05:05] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_DONE_MASK_MASK 0x00000020 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_DONE_MASK_SHIFT 5 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: TRACE_TRIG_MASK [04:04] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_TRIG_MASK_MASK 0x00000010 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_TRIG_MASK_SHIFT 4 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH3_MASK [03:03] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH3_MASK_MASK 0x00000008 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH3_MASK_SHIFT 3 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH2_MASK [02:02] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH2_MASK_MASK 0x00000004 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH2_MASK_SHIFT 2 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH1_MASK [01:01] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH1_MASK_MASK 0x00000002 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH1_MASK_SHIFT 1 - -/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH0_MASK [00:00] */ -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH0_MASK_MASK 0x00000001 -#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH0_MASK_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_ARB_MIPS_L2_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_msa_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_msa_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_msa_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_msa_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,142 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_msa_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:15p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:49 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_msa_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:15p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_MSA_REGS_H__ -#define BCHP_PRI_ARB_MSA_REGS_H__ - -/*************************************************************************** - *PRI_ARB_MSA_REGS - PRIMARY_ARB memory soft access client registers - ***************************************************************************/ -#define BCHP_PRI_ARB_MSA_REGS_STATUS 0x0040c800 /* Memory Controller MSA Status Register */ -#define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE 0x0040c804 /* Memory Controller SCB Command Type Register */ -#define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR 0x0040c808 /* Memory Controller SCB Address Register */ - -/*************************************************************************** - *STATUS - Memory Controller MSA Status Register - ***************************************************************************/ -/* PRI_ARB_MSA_REGS :: STATUS :: reserved0 [31:04] */ -#define BCHP_PRI_ARB_MSA_REGS_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_PRI_ARB_MSA_REGS_STATUS_reserved0_SHIFT 4 - -/* PRI_ARB_MSA_REGS :: STATUS :: FIFO_FULL [03:03] */ -#define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_FULL_MASK 0x00000008 -#define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_FULL_SHIFT 3 - -/* PRI_ARB_MSA_REGS :: STATUS :: FIFO_EMPTY [02:02] */ -#define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_EMPTY_MASK 0x00000004 -#define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_EMPTY_SHIFT 2 - -/* PRI_ARB_MSA_REGS :: STATUS :: T_LOCK [01:01] */ -#define BCHP_PRI_ARB_MSA_REGS_STATUS_T_LOCK_MASK 0x00000002 -#define BCHP_PRI_ARB_MSA_REGS_STATUS_T_LOCK_SHIFT 1 - -/* PRI_ARB_MSA_REGS :: STATUS :: BUSY [00:00] */ -#define BCHP_PRI_ARB_MSA_REGS_STATUS_BUSY_MASK 0x00000001 -#define BCHP_PRI_ARB_MSA_REGS_STATUS_BUSY_SHIFT 0 - -/*************************************************************************** - *CMD_TYPE - Memory Controller SCB Command Type Register - ***************************************************************************/ -/* PRI_ARB_MSA_REGS :: CMD_TYPE :: reserved0 [31:09] */ -#define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_reserved0_MASK 0xfffffe00 -#define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_reserved0_SHIFT 9 - -/* PRI_ARB_MSA_REGS :: CMD_TYPE :: REQ_TYPE [08:00] */ -#define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_REQ_TYPE_MASK 0x000001ff -#define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_REQ_TYPE_SHIFT 0 - -/*************************************************************************** - *CMD_ADDR - Memory Controller SCB Address Register - ***************************************************************************/ -/* PRI_ARB_MSA_REGS :: CMD_ADDR :: reserved_for_eco0 [31:29] */ -#define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_reserved_for_eco0_MASK 0xe0000000 -#define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_reserved_for_eco0_SHIFT 29 - -/* PRI_ARB_MSA_REGS :: CMD_ADDR :: ADDR [28:00] */ -#define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_ADDR_MASK 0x1fffffff -#define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_ADDR_SHIFT 0 - -/*************************************************************************** - *MSA_DATA%i - Memory Controller MSA Data Register - ***************************************************************************/ -#define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_BASE 0x0040c810 -#define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_START 0 -#define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_END 63 -#define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *MSA_DATA%i - Memory Controller MSA Data Register - ***************************************************************************/ -/* PRI_ARB_MSA_REGS :: MSA_DATAi :: Data [31:00] */ -#define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_Data_MASK 0xffffffff -#define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_Data_SHIFT 0 - - -/*************************************************************************** - *MSA_MASK%i - Memory Controller MSA Mask Data Register - ***************************************************************************/ -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_BASE 0x0040c910 -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_START 0 -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_END 63 -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *MSA_MASK%i - Memory Controller MSA Mask Data Register - ***************************************************************************/ -/* PRI_ARB_MSA_REGS :: MSA_MASKi :: reserved0 [31:04] */ -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_reserved0_MASK 0xfffffff0 -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_reserved0_SHIFT 4 - -/* PRI_ARB_MSA_REGS :: MSA_MASKi :: Mask [03:00] */ -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_Mask_MASK 0x0000000f -#define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_Mask_SHIFT 0 - - -#endif /* #ifndef BCHP_PRI_ARB_MSA_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_sarch_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_sarch_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_sarch_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_sarch_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,245 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_sarch_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:15p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:07 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_sarch_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:15p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_SARCH_REGS_H__ -#define BCHP_PRI_ARB_SARCH_REGS_H__ - -/*************************************************************************** - *PRI_ARB_SARCH_REGS - PRIMARY_ARB secure address range checker registers - ***************************************************************************/ - -/*************************************************************************** - *CNTRL_REG%i - Address Range Checker (SARCH0..7) control register - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_BASE 0x00461400 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *CNTRL_REG%i - Address Range Checker (SARCH0..7) control register - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: reserved0 [31:06] */ -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_reserved0_MASK 0xffffffc0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_reserved0_SHIFT 6 - -/* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: READ_ABORT [05:05] */ -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_MASK 0x00000020 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_SHIFT 5 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_DISABLED 0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_ENABLED 1 - -/* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: WRITE_ABORT [04:04] */ -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_MASK 0x00000010 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_SHIFT 4 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_DISABLED 0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_ENABLED 1 - -/* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: WRITE_CHECK [03:03] */ -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_MASK 0x00000008 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_SHIFT 3 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_DISABLED 0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_ENABLED 1 - -/* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: READ_CHECK [02:02] */ -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_MASK 0x00000004 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_SHIFT 2 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_DISABLED 0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_ENABLED 1 - -/* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: MODE [01:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_MASK 0x00000003 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_SHIFT 0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_NON_EXCLUSIVE 0 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_EXCLUSIVE 1 -#define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_ULTRA_EXCLUSIVE 2 - - -/*************************************************************************** - *ADRS_RANGE_LOW%i - Address Range Checker (SARCH0..7) memory range lower address register - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_BASE 0x00461420 -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *ADRS_RANGE_LOW%i - Address Range Checker (SARCH0..7) memory range lower address register - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: ADRS_RANGE_LOWi :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_SHIFT 0 - - -/*************************************************************************** - *ADRS_RANGE_HIGH%i - Address Range Checker (SARCH0..7) memory range upper address register - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_BASE 0x00461440 -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *ADRS_RANGE_HIGH%i - Address Range Checker (SARCH0..7) memory range upper address register - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: ADRS_RANGE_HIGHi :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_SHIFT 0 - - -/*************************************************************************** - *READ_RIGHTS_0_%i - Address Range Checker (SARCH0..7) read access rights for clients #0 through #19. - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_BASE 0x00461460 -#define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *READ_RIGHTS_0_%i - Address Range Checker (SARCH0..7) read access rights for clients #0 through #19. - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: READ_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff -#define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 - - -/*************************************************************************** - *WRITE_RIGHTS_0_%i - Address Range Checker (SARCH0..7) write access rights for clients #0 through #19. - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_BASE 0x004614c0 -#define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *WRITE_RIGHTS_0_%i - Address Range Checker (SARCH0..7) write access rights for clients #0 through #19. - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: WRITE_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff -#define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 - - -/*************************************************************************** - *VIOL_ADDR%i - Address Range Checker (SARCH0..7) violating command address. - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_BASE 0x00461540 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *VIOL_ADDR%i - Address Range Checker (SARCH0..7) violating command address. - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: VIOL_ADDRi :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ADDRESS_SHIFT 0 - - -/*************************************************************************** - *VIOL_INFO%i - Address Range Checker (SARCH0..7) violating command information. - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_BASE 0x00461560 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *VIOL_INFO%i - Address Range Checker (SARCH0..7) violating command information. - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: CLIENTID [31:24] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_CLIENTID_MASK 0xff000000 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_CLIENTID_SHIFT 24 - -/* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: reserved0 [23:22] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved0_MASK 0x00c00000 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved0_SHIFT 22 - -/* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: LENGTH [21:12] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_LENGTH_MASK 0x003ff000 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_LENGTH_SHIFT 12 - -/* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: MODE [11:09] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_MODE_MASK 0x00000e00 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_MODE_SHIFT 9 - -/* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: WRITE [08:08] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_WRITE_MASK 0x00000100 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_WRITE_SHIFT 8 - -/* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: reserved1 [07:01] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved1_MASK 0x000000fe -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved1_SHIFT 1 - -/* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: STATUS [00:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_STATUS_MASK 0x00000001 -#define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_STATUS_SHIFT 0 - - -/*************************************************************************** - *STATUS_CLEAR%i - Address Range Checker (SARCH0..7) violating command status release. - ***************************************************************************/ -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_BASE 0x00461580 -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_START 0 -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_END 7 -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *STATUS_CLEAR%i - Address Range Checker (SARCH0..7) violating command status release. - ***************************************************************************/ -/* PRI_ARB_SARCH_REGS :: STATUS_CLEARi :: reserved0 [31:01] */ -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_reserved0_MASK 0xfffffffe -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_reserved0_SHIFT 1 - -/* PRI_ARB_SARCH_REGS :: STATUS_CLEARi :: CLEAR [00:00] */ -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_CLEAR_MASK 0x00000001 -#define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_CLEAR_SHIFT 0 - - -#endif /* #ifndef BCHP_PRI_ARB_SARCH_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_starch_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_starch_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_starch_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_starch_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,197 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_starch_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:15p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:16 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_starch_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:15p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_STARCH_REGS_H__ -#define BCHP_PRI_ARB_STARCH_REGS_H__ - -/*************************************************************************** - *PRI_ARB_STARCH_REGS - PRIMARY_ARB secure static address range checker registers - ***************************************************************************/ -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG 0x00461200 /* Address Range Checker control register */ -#define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_LOW 0x00461220 /* Address Range Checker memory range lower address register */ -#define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_HIGH 0x00461240 /* Address Range Checker memory range upper address register */ -#define BCHP_PRI_ARB_STARCH_REGS_READ_RIGHTS_0_ 0x00461260 /* Address Range Checker read access rights for clients #0 through #19. */ -#define BCHP_PRI_ARB_STARCH_REGS_WRITE_RIGHTS_0_ 0x004612c0 /* Address Range Checker write access rights for clients #0 through #19. */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_ADDR 0x00461340 /* Address Range Checker violating command address. */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO 0x00461360 /* Address Range Checker violating command information. */ -#define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR 0x00461380 /* Address Range Checker violating command status release. */ -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE 0x004613c0 /* Memory Size register */ - -/*************************************************************************** - *CNTRL_REG - Address Range Checker control register - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: CNTRL_REG :: reserved0 [31:06] */ -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_reserved0_MASK 0xffffffc0 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_reserved0_SHIFT 6 - -/* PRI_ARB_STARCH_REGS :: CNTRL_REG :: READ_ABORT [05:05] */ -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_MASK 0x00000020 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_SHIFT 5 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_DISABLED 0 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_ENABLED 1 - -/* PRI_ARB_STARCH_REGS :: CNTRL_REG :: WRITE_ABORT [04:04] */ -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_MASK 0x00000010 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_SHIFT 4 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_DISABLED 0 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_ENABLED 1 - -/* PRI_ARB_STARCH_REGS :: CNTRL_REG :: WRITE_CHECK [03:03] */ -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_MASK 0x00000008 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_SHIFT 3 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_DISABLED 0 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_ENABLED 1 - -/* PRI_ARB_STARCH_REGS :: CNTRL_REG :: READ_CHECK [02:02] */ -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_MASK 0x00000004 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_SHIFT 2 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_DISABLED 0 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_ENABLED 1 - -/* PRI_ARB_STARCH_REGS :: CNTRL_REG :: MODE [01:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_MASK 0x00000003 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_SHIFT 0 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_NON_EXCLUSIVE 0 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_EXCLUSIVE 1 -#define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_ULTRA_EXCLUSIVE 2 - -/*************************************************************************** - *ADRS_RANGE_LOW - Address Range Checker memory range lower address register - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: ADRS_RANGE_LOW :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_LOW_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_LOW_ADDRESS_SHIFT 0 - -/*************************************************************************** - *ADRS_RANGE_HIGH - Address Range Checker memory range upper address register - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: ADRS_RANGE_HIGH :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_HIGH_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_HIGH_ADDRESS_SHIFT 0 - -/*************************************************************************** - *READ_RIGHTS_0_ - Address Range Checker read access rights for clients #0 through #19. - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: READ_RIGHTS_0_ :: ACCESS_RIGHT [31:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_READ_RIGHTS_0__ACCESS_RIGHT_MASK 0xffffffff -#define BCHP_PRI_ARB_STARCH_REGS_READ_RIGHTS_0__ACCESS_RIGHT_SHIFT 0 - -/*************************************************************************** - *WRITE_RIGHTS_0_ - Address Range Checker write access rights for clients #0 through #19. - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: WRITE_RIGHTS_0_ :: ACCESS_RIGHT [31:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_WRITE_RIGHTS_0__ACCESS_RIGHT_MASK 0xffffffff -#define BCHP_PRI_ARB_STARCH_REGS_WRITE_RIGHTS_0__ACCESS_RIGHT_SHIFT 0 - -/*************************************************************************** - *VIOL_ADDR - Address Range Checker violating command address. - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: VIOL_ADDR :: ADDRESS [31:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_ADDR_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_ADDR_ADDRESS_SHIFT 0 - -/*************************************************************************** - *VIOL_INFO - Address Range Checker violating command information. - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: VIOL_INFO :: CLIENTID [31:24] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_CLIENTID_MASK 0xff000000 -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_CLIENTID_SHIFT 24 - -/* PRI_ARB_STARCH_REGS :: VIOL_INFO :: reserved0 [23:22] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved0_MASK 0x00c00000 -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved0_SHIFT 22 - -/* PRI_ARB_STARCH_REGS :: VIOL_INFO :: LENGTH [21:12] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_LENGTH_MASK 0x003ff000 -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_LENGTH_SHIFT 12 - -/* PRI_ARB_STARCH_REGS :: VIOL_INFO :: MODE [11:09] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_MODE_MASK 0x00000e00 -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_MODE_SHIFT 9 - -/* PRI_ARB_STARCH_REGS :: VIOL_INFO :: WRITE [08:08] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_WRITE_MASK 0x00000100 -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_WRITE_SHIFT 8 - -/* PRI_ARB_STARCH_REGS :: VIOL_INFO :: reserved1 [07:01] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved1_MASK 0x000000fe -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved1_SHIFT 1 - -/* PRI_ARB_STARCH_REGS :: VIOL_INFO :: STATUS [00:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_STATUS_MASK 0x00000001 -#define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_STATUS_SHIFT 0 - -/*************************************************************************** - *STATUS_CLEAR - Address Range Checker violating command status release. - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: STATUS_CLEAR :: reserved0 [31:01] */ -#define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_reserved0_MASK 0xfffffffe -#define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_reserved0_SHIFT 1 - -/* PRI_ARB_STARCH_REGS :: STATUS_CLEAR :: CLEAR [00:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_CLEAR_MASK 0x00000001 -#define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_CLEAR_SHIFT 0 - -/*************************************************************************** - *MEMORY_SIZE - Memory Size register - ***************************************************************************/ -/* PRI_ARB_STARCH_REGS :: MEMORY_SIZE :: reserved0 [31:02] */ -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_reserved0_MASK 0xfffffffc -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_reserved0_SHIFT 2 - -/* PRI_ARB_STARCH_REGS :: MEMORY_SIZE :: DDR_SIZE [01:00] */ -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_MASK 0x00000003 -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SHIFT 0 -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_64_MB 0 -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_128_MB 1 -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_256_MB 2 -#define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_512_MB 3 - -#endif /* #ifndef BCHP_PRI_ARB_STARCH_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_trace_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_trace_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_trace_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_trace_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,914 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_trace_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:15p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:42 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_trace_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:15p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_TRACE_REGS_H__ -#define BCHP_PRI_ARB_TRACE_REGS_H__ - -/*************************************************************************** - *PRI_ARB_TRACE_REGS - PRIMARY_ARB tracelog registers - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_VERSION 0x0040c600 /* Tracelog Version */ -#define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM 0x0040c604 /* MBIST Test Mode */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR 0x0040c608 /* Beginning of buffer DRAM address in the TraceLog */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE 0x0040c60c /* Size of the buffer in DRAM */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR 0x0040c610 /* Initial location of the write pointer in DRAM */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE 0x0040c614 /* Trigger configuration */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_N_EVENTS 0x0040c618 /* N transactions */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD 0x0040c61c /* Trigger command register */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_LOWER 0x0040c620 /* Lower 32 bits of Trigger Time Interval */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER 0x0040c624 /* Upper 16 bits of Trigger Time Interval */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS 0x0040c628 /* Transaction Status Register */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER 0x0040c62c /* Upper 16 bits of elapsed time */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_LOWER 0x0040c630 /* Lower 32 bits of elapsed time */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_WR_PTR 0x0040c634 /* Buffer Write Pointer Position at the Time of Trigger */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_BEFORE_TRIGGER 0x0040c638 /* Trigger Count Before Trigger */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_AFTER_TRIGGER 0x0040c63c /* Trigger Count After Trigger */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_EVENT_COUNTER 0x0040c640 /* Trigger Event Counter */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_NUMBER 0x0040c644 /* Number of transactions captured */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER 0x0040c648 /* Upper 16 bits of timestamp at the time of Trigger */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_LOWER 0x0040c64c /* Lower 32 bits of timestamp at the time of Trigger */ - -/*************************************************************************** - *VERSION - Tracelog Version - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: VERSION :: MAJOR_REVISION_NUMBER [31:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_VERSION_MAJOR_REVISION_NUMBER_MASK 0xffff0000 -#define BCHP_PRI_ARB_TRACE_REGS_VERSION_MAJOR_REVISION_NUMBER_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: VERSION :: MINOR_REVISION_NUMBER [15:08] */ -#define BCHP_PRI_ARB_TRACE_REGS_VERSION_MINOR_REVISION_NUMBER_MASK 0x0000ff00 -#define BCHP_PRI_ARB_TRACE_REGS_VERSION_MINOR_REVISION_NUMBER_SHIFT 8 - -/* PRI_ARB_TRACE_REGS :: VERSION :: METAL_REVISION_ID [07:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_VERSION_METAL_REVISION_ID_MASK 0x000000ff -#define BCHP_PRI_ARB_TRACE_REGS_VERSION_METAL_REVISION_ID_SHIFT 0 - -/*************************************************************************** - *MBIST_TM - MBIST Test Mode - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: MBIST_TM :: reserved0 [31:02] */ -#define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_reserved0_MASK 0xfffffffc -#define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_reserved0_SHIFT 2 - -/* PRI_ARB_TRACE_REGS :: MBIST_TM :: MBIST_TESTMODE [01:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_MBIST_TESTMODE_MASK 0x00000003 -#define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_MBIST_TESTMODE_SHIFT 0 - -/*************************************************************************** - *BUFF_ADDR - Beginning of buffer DRAM address in the TraceLog - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: BUFF_ADDR :: ADDR [31:08] */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_ADDR_MASK 0xffffff00 -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_ADDR_SHIFT 8 - -/* PRI_ARB_TRACE_REGS :: BUFF_ADDR :: reserved0 [07:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_reserved0_MASK 0x000000ff -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *BUFF_SIZE - Size of the buffer in DRAM - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: BUFF_SIZE :: SIZE [31:08] */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_SIZE_MASK 0xffffff00 -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_SIZE_SHIFT 8 - -/* PRI_ARB_TRACE_REGS :: BUFF_SIZE :: reserved0 [07:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_reserved0_MASK 0x000000ff -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_reserved0_SHIFT 0 - -/*************************************************************************** - *BUFF_WR_PTR - Initial location of the write pointer in DRAM - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: BUFF_WR_PTR :: ADDR [31:08] */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_ADDR_MASK 0xffffff00 -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_ADDR_SHIFT 8 - -/* PRI_ARB_TRACE_REGS :: BUFF_WR_PTR :: reserved0 [07:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_reserved0_MASK 0x000000ff -#define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_reserved0_SHIFT 0 - -/*************************************************************************** - *TRIG_MODE - Trigger configuration - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MODE :: reserved0 [31:06] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_reserved0_MASK 0xffffffc0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_reserved0_SHIFT 6 - -/* PRI_ARB_TRACE_REGS :: TRIG_MODE :: EVENT_MODE [05:03] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_EVENT_MODE_MASK 0x00000038 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_EVENT_MODE_SHIFT 3 - -/* PRI_ARB_TRACE_REGS :: TRIG_MODE :: CAPTURE_MODE [02:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_CAPTURE_MODE_MASK 0x00000007 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_CAPTURE_MODE_SHIFT 0 - -/*************************************************************************** - *TRIG_N_EVENTS - N transactions - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_N_EVENTS :: N_EVENTS [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_N_EVENTS_N_EVENTS_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_N_EVENTS_N_EVENTS_SHIFT 0 - -/*************************************************************************** - *TRIG_CMD - Trigger command register - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_CMD :: reserved0 [31:05] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_reserved0_MASK 0xffffffe0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_reserved0_SHIFT 5 - -/* PRI_ARB_TRACE_REGS :: TRIG_CMD :: RESET [04:04] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_RESET_MASK 0x00000010 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_RESET_SHIFT 4 - -/* PRI_ARB_TRACE_REGS :: TRIG_CMD :: STOP [03:03] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_STOP_MASK 0x00000008 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_STOP_SHIFT 3 - -/* PRI_ARB_TRACE_REGS :: TRIG_CMD :: FLUSH [02:02] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_FLUSH_MASK 0x00000004 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_FLUSH_SHIFT 2 - -/* PRI_ARB_TRACE_REGS :: TRIG_CMD :: MANUAL_TRIGGER [01:01] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_MANUAL_TRIGGER_MASK 0x00000002 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_MANUAL_TRIGGER_SHIFT 1 - -/* PRI_ARB_TRACE_REGS :: TRIG_CMD :: START [00:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_START_MASK 0x00000001 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_START_SHIFT 0 - -/*************************************************************************** - *TRIG_TIME_LOWER - Lower 32 bits of Trigger Time Interval - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_TIME_LOWER :: TRANSACTION_TIME_LOWER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_LOWER_TRANSACTION_TIME_LOWER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_LOWER_TRANSACTION_TIME_LOWER_SHIFT 0 - -/*************************************************************************** - *TRIG_TIME_UPPER - Upper 16 bits of Trigger Time Interval - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_TIME_UPPER :: reserved0 [31:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_reserved0_MASK 0xffff0000 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_reserved0_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: TRIG_TIME_UPPER :: TRANSACTION_TIME_UPPER [15:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_TRANSACTION_TIME_UPPER_MASK 0x0000ffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_TRANSACTION_TIME_UPPER_SHIFT 0 - -/*************************************************************************** - *TRANSACTION_STATUS - Transaction Status Register - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: reserved0 [31:13] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_reserved0_MASK 0xffffe000 -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_reserved0_SHIFT 13 - -/* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: RESET_ACTIVE [12:12] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_RESET_ACTIVE_MASK 0x00001000 -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_RESET_ACTIVE_SHIFT 12 - -/* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: FIFO_EMPTY [11:11] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_FIFO_EMPTY_MASK 0x00000800 -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_FIFO_EMPTY_SHIFT 11 - -/* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: TRIGGER_EVENT [10:10] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_TRIGGER_EVENT_MASK 0x00000400 -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_TRIGGER_EVENT_SHIFT 10 - -/* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: LOST [09:09] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_LOST_MASK 0x00000200 -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_LOST_SHIFT 9 - -/* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: ACTIVE [08:08] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_ACTIVE_MASK 0x00000100 -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_ACTIVE_SHIFT 8 - -/* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: CONTINUITY_COUNT [07:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_CONTINUITY_COUNT_MASK 0x000000ff -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_CONTINUITY_COUNT_SHIFT 0 - -/*************************************************************************** - *TRANSACTION_TIME_UPPER - Upper 16 bits of elapsed time - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRANSACTION_TIME_UPPER :: reserved0 [31:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_reserved0_MASK 0xffff0000 -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_reserved0_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: TRANSACTION_TIME_UPPER :: TRANSACTION_TIME_UPPER [15:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_TRANSACTION_TIME_UPPER_MASK 0x0000ffff -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_TRANSACTION_TIME_UPPER_SHIFT 0 - -/*************************************************************************** - *TRANSACTION_TIME_LOWER - Lower 32 bits of elapsed time - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRANSACTION_TIME_LOWER :: TRANSACTION_TIME_LOWER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_LOWER_TRANSACTION_TIME_LOWER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_LOWER_TRANSACTION_TIME_LOWER_SHIFT 0 - -/*************************************************************************** - *TRIG_WR_PTR - Buffer Write Pointer Position at the Time of Trigger - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_WR_PTR :: TRIGGER_WRITE_POINTER_ADDRESS [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_WR_PTR_TRIGGER_WRITE_POINTER_ADDRESS_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_WR_PTR_TRIGGER_WRITE_POINTER_ADDRESS_SHIFT 0 - -/*************************************************************************** - *TRIG_COUNT_BEFORE_TRIGGER - Trigger Count Before Trigger - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_COUNT_BEFORE_TRIGGER :: EVENT_COUNT_BEFORE_TRIGGER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_BEFORE_TRIGGER_EVENT_COUNT_BEFORE_TRIGGER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_BEFORE_TRIGGER_EVENT_COUNT_BEFORE_TRIGGER_SHIFT 0 - -/*************************************************************************** - *TRIG_COUNT_AFTER_TRIGGER - Trigger Count After Trigger - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_COUNT_AFTER_TRIGGER :: EVENT_COUNT_AFTER_TRIGGER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_AFTER_TRIGGER_EVENT_COUNT_AFTER_TRIGGER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_AFTER_TRIGGER_EVENT_COUNT_AFTER_TRIGGER_SHIFT 0 - -/*************************************************************************** - *TRIG_EVENT_COUNTER - Trigger Event Counter - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_EVENT_COUNTER :: TRIGGER_EVENT_MATCH_COUNT [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_EVENT_COUNTER_TRIGGER_EVENT_MATCH_COUNT_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_EVENT_COUNTER_TRIGGER_EVENT_MATCH_COUNT_SHIFT 0 - -/*************************************************************************** - *TRANSACTION_NUMBER - Number of transactions captured - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRANSACTION_NUMBER :: TRANS_NUMBER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_NUMBER_TRANS_NUMBER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_NUMBER_TRANS_NUMBER_SHIFT 0 - -/*************************************************************************** - *TRIG_TRANS_TIME_UPPER - Upper 16 bits of timestamp at the time of Trigger - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_TRANS_TIME_UPPER :: reserved0 [31:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_reserved0_MASK 0xffff0000 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_reserved0_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: TRIG_TRANS_TIME_UPPER :: TRANSACTION_TIME_UPPER [15:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_TRANSACTION_TIME_UPPER_MASK 0x0000ffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_TRANSACTION_TIME_UPPER_SHIFT 0 - -/*************************************************************************** - *TRIG_TRANS_TIME_LOWER - Lower 32 bits of timestamp at the time of Trigger - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_TRANS_TIME_LOWER :: TRANSACTION_TIME_LOWER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_LOWER_TRANSACTION_TIME_LOWER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_LOWER_TRANSACTION_TIME_LOWER_SHIFT 0 - -/*************************************************************************** - *DATA_MEM_FILT_MODE%i - Data Memory Filter Window Mode - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_BASE 0x0040c650 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_MODE%i - Data Memory Filter Window Mode - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: reserved0 [31:12] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_reserved0_MASK 0xfffff000 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_reserved0_SHIFT 12 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: FILTER_MEMORY_EN [11:11] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_FILTER_MEMORY_EN_MASK 0x00000800 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_FILTER_MEMORY_EN_SHIFT 11 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_MCACHE_MODE [10:10] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_MASK 0x00000400 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_SHIFT 10 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_READ_MODE [09:09] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_READ_MODE_MASK 0x00000200 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_READ_MODE_SHIFT 9 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_WRITE_MODE [08:08] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_WRITE_MODE_MASK 0x00000100 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_WRITE_MODE_SHIFT 8 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_PIXEL_MODE [07:07] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_MASK 0x00000080 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_SHIFT 7 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_LINEAR_MODE [06:06] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_MASK 0x00000040 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_SHIFT 6 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_DISPLAY_MODE [05:05] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_MASK 0x00000020 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_SHIFT 5 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_CACHE_MODE [04:04] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CACHE_MODE_MASK 0x00000010 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CACHE_MODE_SHIFT 4 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_FILTER_PIXEL_MODE [03:03] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_MASK 0x00000008 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_SHIFT 3 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_CLIENT_MASK_MODE [02:02] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_MASK 0x00000004 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_SHIFT 2 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_IN_OUT [01:01] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_IN_OUT_MASK 0x00000002 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_IN_OUT_SHIFT 1 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_ADDRESS_EN [00:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_MASK 0x00000001 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_SHIFT 0 - - -/*************************************************************************** - *DATA_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_BASE 0x0040c660 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: reserved0 [31:27] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_MASK 0xf8000000 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_SHIFT 27 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: Y1_COORD [26:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_MASK 0x07ff0000 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: reserved1 [15:11] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_MASK 0x0000f800 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_SHIFT 11 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: X1_COORD [10:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_MASK 0x000007ff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_SHIFT 0 - - -/*************************************************************************** - *DATA_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_BASE 0x0040c670 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: reserved0 [31:27] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_MASK 0xf8000000 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_SHIFT 27 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: Y2_COORD [26:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_MASK 0x07ff0000 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: reserved1 [15:11] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_MASK 0x0000f800 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_SHIFT 11 - -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: X2_COORD [10:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_MASK 0x000007ff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_SHIFT 0 - - -/*************************************************************************** - *DATA_MEM_FILT_CLIENT_MASK_64_95_%i - Data Memory Filter Window Client Mask for Clients 64-95 - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_BASE 0x0040c680 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_CLIENT_MASK_64_95_%i - Data Memory Filter Window Client Mask for Clients 64-95 - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_CLIENT_MASK_64_95_i :: MEMORY_CLIENT_MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_SHIFT 0 - - -/*************************************************************************** - *DATA_MEM_FILT_CLIENT_MASK_32_63_%i - Data Memory Filter Window Client Mask for Clients 32-63 - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_BASE 0x0040c690 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_CLIENT_MASK_32_63_%i - Data Memory Filter Window Client Mask for Clients 32-63 - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_CLIENT_MASK_32_63_i :: MEMORY_CLIENT_MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_SHIFT 0 - - -/*************************************************************************** - *DATA_MEM_FILT_CLIENT_MASK_31_0_%i - Data Memory Filter Window Client Mask for Clients 0-31 - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_BASE 0x0040c6a0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_CLIENT_MASK_31_0_%i - Data Memory Filter Window Client Mask for Clients 0-31 - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_CLIENT_MASK_31_0_i :: MEMORY_CLIENT_MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_SHIFT 0 - - -/*************************************************************************** - *DATA_MEM_FILT_ADDR_UPPER%i - Data Memory Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c6b0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_ADDR_UPPER%i - Data Memory Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_ADDR_UPPERi :: UPPER_MEMORY_ADDR [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_SHIFT 0 - - -/*************************************************************************** - *DATA_MEM_FILT_ADDR_LOWER%i - Data Memory Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c6c0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_MEM_FILT_ADDR_LOWER%i - Data Memory Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_ADDR_LOWERi :: LOWER_MEMORY_ADDR [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_SHIFT 0 - - -/*************************************************************************** - *DATA_IO_FILT_MODE%i - Data I/O Filter Mode - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_BASE 0x0040c6d0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_IO_FILT_MODE%i - Data I/O Filter Mode - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: reserved0 [31:06] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_reserved0_MASK 0xffffffc0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_reserved0_SHIFT 6 - -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: FILTER_IO_EN [05:05] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_FILTER_IO_EN_MASK 0x00000020 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_FILTER_IO_EN_SHIFT 5 - -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: GISB_READ_MODE [04:04] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_READ_MODE_MASK 0x00000010 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_READ_MODE_SHIFT 4 - -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: GISB_WRITE_MODE [03:03] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_WRITE_MODE_MASK 0x00000008 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_WRITE_MODE_SHIFT 3 - -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: DATA_MODE [02:02] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_DATA_MODE_MASK 0x00000004 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_DATA_MODE_SHIFT 2 - -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: IO_IN_OUT [01:01] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_IN_OUT_MASK 0x00000002 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_IN_OUT_SHIFT 1 - -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: IO_ADDRESS_EN [00:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_ADDRESS_EN_MASK 0x00000001 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_ADDRESS_EN_SHIFT 0 - - -/*************************************************************************** - *DATA_IO_FILT_ADDR_UPPER%i - Data I/O Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c6e0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_IO_FILT_ADDR_UPPER%i - Data I/O Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_ADDR_UPPERi :: IO_ADDR_UPPER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_SHIFT 0 - - -/*************************************************************************** - *DATA_IO_FILT_ADDR_LOWER%i - Data I/O Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c6f0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_IO_FILT_ADDR_LOWER%i - Data I/O Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_ADDR_LOWERi :: IO_ADDR_LOWER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_SHIFT 0 - - -/*************************************************************************** - *DATA_IO_FILT_DATA%i - Data I/O Filter Window Data - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_BASE 0x0040c700 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_IO_FILT_DATA%i - Data I/O Filter Window Data - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_DATAi :: DATA [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_DATA_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_DATA_SHIFT 0 - - -/*************************************************************************** - *DATA_IO_FILT_DATA_MASK%i - Data I/O Filter Window Data Mask - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_BASE 0x0040c710 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DATA_IO_FILT_DATA_MASK%i - Data I/O Filter Window Data Mask - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_DATA_MASKi :: MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_MASK_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_MODE%i - Trigger Memory Filter Window Mode - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_BASE 0x0040c720 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_MODE%i - Trigger Memory Filter Window Mode - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: reserved0 [31:12] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_reserved0_MASK 0xfffff000 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_reserved0_SHIFT 12 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: FILTER_MEMORY_EN [11:11] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_FILTER_MEMORY_EN_MASK 0x00000800 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_FILTER_MEMORY_EN_SHIFT 11 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_MCACHE_MODE [10:10] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_MASK 0x00000400 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_SHIFT 10 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_READ_MODE [09:09] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_READ_MODE_MASK 0x00000200 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_READ_MODE_SHIFT 9 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_WRITE_MODE [08:08] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_WRITE_MODE_MASK 0x00000100 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_WRITE_MODE_SHIFT 8 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_PIXEL_MODE [07:07] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_MASK 0x00000080 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_SHIFT 7 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_LINEAR_MODE [06:06] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_MASK 0x00000040 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_SHIFT 6 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_DISPLAY_MODE [05:05] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_MASK 0x00000020 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_SHIFT 5 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_CACHE_MODE [04:04] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CACHE_MODE_MASK 0x00000010 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CACHE_MODE_SHIFT 4 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_FILTER_PIXEL_MODE [03:03] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_MASK 0x00000008 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_SHIFT 3 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_CLIENT_MASK_MODE [02:02] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_MASK 0x00000004 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_SHIFT 2 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_IN_OUT [01:01] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_IN_OUT_MASK 0x00000002 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_IN_OUT_SHIFT 1 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_ADDRESS_EN [00:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_MASK 0x00000001 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_BASE 0x0040c730 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: reserved0 [31:27] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_MASK 0xf8000000 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_SHIFT 27 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: Y1_COORD [26:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_MASK 0x07ff0000 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: reserved1 [15:11] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_MASK 0x0000f800 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_SHIFT 11 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: X1_COORD [10:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_MASK 0x000007ff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_BASE 0x0040c740 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: reserved0 [31:27] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_MASK 0xf8000000 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_SHIFT 27 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: Y2_COORD [26:16] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_MASK 0x07ff0000 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_SHIFT 16 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: reserved1 [15:11] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_MASK 0x0000f800 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_SHIFT 11 - -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: X2_COORD [10:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_MASK 0x000007ff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_CLIENT_MASK_64_95_%i - Trigger Memory Filter Window Client Mask for Clients 64-95 - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_BASE 0x0040c750 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_CLIENT_MASK_64_95_%i - Trigger Memory Filter Window Client Mask for Clients 64-95 - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_CLIENT_MASK_64_95_i :: MEMORY_CLIENT_MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_CLIENT_MASK_32_63_%i - Trigger Memory Filter Window Client Mask for Clients 32-63 - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_BASE 0x0040c760 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_CLIENT_MASK_32_63_%i - Trigger Memory Filter Window Client Mask for Clients 32-63 - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_CLIENT_MASK_32_63_i :: MEMORY_CLIENT_MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_CLIENT_MASK_31_0_%i - Trigger Memory Filter Window Client Mask for Clients 0-31 - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_BASE 0x0040c770 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_CLIENT_MASK_31_0_%i - Trigger Memory Filter Window Client Mask for Clients 0-31 - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_CLIENT_MASK_31_0_i :: MEMORY_CLIENT_MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_ADDR_UPPER%i - Trigger Memory Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c780 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_ADDR_UPPER%i - Trigger Memory Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_ADDR_UPPERi :: UPPER_MEMORY_ADDR [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_SHIFT 0 - - -/*************************************************************************** - *TRIG_MEM_FILT_ADDR_LOWER%i - Trigger Memory Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c790 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_MEM_FILT_ADDR_LOWER%i - Trigger Memory Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_ADDR_LOWERi :: LOWER_MEMORY_ADDR [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_SHIFT 0 - - -/*************************************************************************** - *TRIG_IO_FILT_MODE%i - Trigger I/O Filter Mode - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_BASE 0x0040c7a0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_IO_FILT_MODE%i - Trigger I/O Filter Mode - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: reserved0 [31:06] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_reserved0_MASK 0xffffffc0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_reserved0_SHIFT 6 - -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: FILTER_IO_EN [05:05] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_FILTER_IO_EN_MASK 0x00000020 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_FILTER_IO_EN_SHIFT 5 - -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: GISB_READ_MODE [04:04] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_READ_MODE_MASK 0x00000010 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_READ_MODE_SHIFT 4 - -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: GISB_WRITE_MODE [03:03] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_WRITE_MODE_MASK 0x00000008 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_WRITE_MODE_SHIFT 3 - -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: DATA_MODE [02:02] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_DATA_MODE_MASK 0x00000004 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_DATA_MODE_SHIFT 2 - -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: IO_IN_OUT [01:01] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_IN_OUT_MASK 0x00000002 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_IN_OUT_SHIFT 1 - -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: IO_ADDRESS_EN [00:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_ADDRESS_EN_MASK 0x00000001 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_ADDRESS_EN_SHIFT 0 - - -/*************************************************************************** - *TRIG_IO_FILT_ADDR_UPPER%i - Trigger I/O Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c7b0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_IO_FILT_ADDR_UPPER%i - Trigger I/O Filter Window Client Mask Upper Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_ADDR_UPPERi :: IO_ADDR_UPPER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_SHIFT 0 - - -/*************************************************************************** - *TRIG_IO_FILT_ADDR_LOWER%i - Trigger I/O Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c7c0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_IO_FILT_ADDR_LOWER%i - Trigger I/O Filter Window Client Mask Lower Bound Address - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_ADDR_LOWERi :: IO_ADDR_LOWER [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_SHIFT 0 - - -/*************************************************************************** - *TRIG_IO_FILT_DATA%i - Trigger I/O Filter Window Data - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_BASE 0x0040c7d0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_IO_FILT_DATA%i - Trigger I/O Filter Window Data - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_DATAi :: DATA [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_DATA_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_DATA_SHIFT 0 - - -/*************************************************************************** - *TRIG_IO_FILT_DATA_MASK%i - Trigger I/O Filter Window Data Mask - ***************************************************************************/ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_BASE 0x0040c7e0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_START 0 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_END 3 -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TRIG_IO_FILT_DATA_MASK%i - Trigger I/O Filter Window Data Mask - ***************************************************************************/ -/* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_DATA_MASKi :: MASK [31:00] */ -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_MASK_MASK 0xffffffff -#define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_MASK_SHIFT 0 - - -#endif /* #ifndef BCHP_PRI_ARB_TRACE_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_wrch_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_wrch_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_wrch_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_wrch_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_arb_wrch_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:15p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:44 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_wrch_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:15p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_ARB_WRCH_REGS_H__ -#define BCHP_PRI_ARB_WRCH_REGS_H__ - -/*************************************************************************** - *PRI_ARB_WRCH_REGS - PRIMARY_ARB secure wrch control registers - ***************************************************************************/ -#define BCHP_PRI_ARB_WRCH_REGS_RESERVED0 0x00461000 /* Reserved */ -#define BCHP_PRI_ARB_WRCH_REGS_RESERVED1 0x004610fc /* Reserved */ - -/*************************************************************************** - *RESERVED0 - Reserved - ***************************************************************************/ -/* PRI_ARB_WRCH_REGS :: RESERVED0 :: RESERVED [31:00] */ -#define BCHP_PRI_ARB_WRCH_REGS_RESERVED0_RESERVED_MASK 0xffffffff -#define BCHP_PRI_ARB_WRCH_REGS_RESERVED0_RESERVED_SHIFT 0 - -/*************************************************************************** - *RESERVED1 - Reserved - ***************************************************************************/ -/* PRI_ARB_WRCH_REGS :: RESERVED1 :: RESERVED [31:00] */ -#define BCHP_PRI_ARB_WRCH_REGS_RESERVED1_RESERVED_MASK 0xffffffff -#define BCHP_PRI_ARB_WRCH_REGS_RESERVED1_RESERVED_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_ARB_WRCH_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1898 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_client_regs.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:16p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:12 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:16p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_CLIENT_REGS_H__ -#define BCHP_PRI_CLIENT_REGS_H__ - -/*************************************************************************** - *PRI_CLIENT_REGS - PRIMARY_ARB_CLIENTS client configuration registers - ***************************************************************************/ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT 0x0040c000 /* Arbiter Client DEBLOCK Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL 0x0040c004 /* Arbiter Client DEBLOCK Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT 0x0040c008 /* Arbiter Client CABAC Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL 0x0040c00c /* Arbiter Client CABAC Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT 0x0040c010 /* Arbiter Client ILOOP Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL 0x0040c014 /* Arbiter Client ILOOP Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT 0x0040c018 /* Arbiter Client OLOOP Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL 0x0040c01c /* Arbiter Client OLOOP Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT 0x0040c020 /* Arbiter Client SYMB_INT Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL 0x0040c024 /* Arbiter Client SYMB_INT Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT 0x0040c028 /* Arbiter Client MOCOMP Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL 0x0040c02c /* Arbiter Client MOCOMP Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT 0x0040c030 /* Arbiter Client XPT1 Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL 0x0040c034 /* Arbiter Client XPT1 Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT 0x0040c038 /* Arbiter Client XPT2 Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL 0x0040c03c /* Arbiter Client XPT2 Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT 0x0040c040 /* Arbiter Client XPT3 Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL 0x0040c044 /* Arbiter Client XPT3 Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT 0x0040c048 /* Arbiter Client ARM Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL 0x0040c04c /* Arbiter Client ARM Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT 0x0040c050 /* Arbiter Client M2M Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL 0x0040c054 /* Arbiter Client M2M Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT 0x0040c058 /* Arbiter Client SHARF Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL 0x0040c05c /* Arbiter Client SHARF Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT 0x0040c060 /* Arbiter Client MFD0 Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL 0x0040c064 /* Arbiter Client MFD0 Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT 0x0040c068 /* Arbiter Client RXDMA Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL 0x0040c06c /* Arbiter Client RXDMA Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT 0x0040c070 /* Arbiter Client TXDMA Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL 0x0040c074 /* Arbiter Client TXDMA Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT 0x0040c078 /* Arbiter Client META Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL 0x0040c07c /* Arbiter Client META Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT 0x0040c080 /* Arbiter Client DIRECT Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL 0x0040c084 /* Arbiter Client DIRECT Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT 0x0040c088 /* Arbiter Client MSA Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL 0x0040c08c /* Arbiter Client MSA Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT 0x0040c090 /* Arbiter Client TRACE Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL 0x0040c094 /* Arbiter Client TRACE Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT 0x0040c098 /* Arbiter Client REFRESH0 Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL 0x0040c09c /* Arbiter Client REFRESH0 Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_20_COUNT 0x0040c0a0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_20_CONTROL 0x0040c0a4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_21_COUNT 0x0040c0a8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_21_CONTROL 0x0040c0ac /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_22_COUNT 0x0040c0b0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_22_CONTROL 0x0040c0b4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_23_COUNT 0x0040c0b8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_23_CONTROL 0x0040c0bc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_24_COUNT 0x0040c0c0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_24_CONTROL 0x0040c0c4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_25_COUNT 0x0040c0c8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_25_CONTROL 0x0040c0cc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_26_COUNT 0x0040c0d0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_26_CONTROL 0x0040c0d4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_27_COUNT 0x0040c0d8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_27_CONTROL 0x0040c0dc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_28_COUNT 0x0040c0e0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_28_CONTROL 0x0040c0e4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_29_COUNT 0x0040c0e8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_29_CONTROL 0x0040c0ec /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_30_COUNT 0x0040c0f0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_30_CONTROL 0x0040c0f4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_31_COUNT 0x0040c0f8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_31_CONTROL 0x0040c0fc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_32_COUNT 0x0040c100 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_32_CONTROL 0x0040c104 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_33_COUNT 0x0040c108 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_33_CONTROL 0x0040c10c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_34_COUNT 0x0040c110 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_34_CONTROL 0x0040c114 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_35_COUNT 0x0040c118 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_35_CONTROL 0x0040c11c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_36_COUNT 0x0040c120 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_36_CONTROL 0x0040c124 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_37_COUNT 0x0040c128 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_37_CONTROL 0x0040c12c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_38_COUNT 0x0040c130 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_38_CONTROL 0x0040c134 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_39_COUNT 0x0040c138 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_39_CONTROL 0x0040c13c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_40_COUNT 0x0040c140 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_40_CONTROL 0x0040c144 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_41_COUNT 0x0040c148 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_41_CONTROL 0x0040c14c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_42_COUNT 0x0040c150 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_42_CONTROL 0x0040c154 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_43_COUNT 0x0040c158 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_43_CONTROL 0x0040c15c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_44_COUNT 0x0040c160 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_44_CONTROL 0x0040c164 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_45_COUNT 0x0040c168 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_45_CONTROL 0x0040c16c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_46_COUNT 0x0040c170 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_46_CONTROL 0x0040c174 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_47_COUNT 0x0040c178 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_47_CONTROL 0x0040c17c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_48_COUNT 0x0040c180 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_48_CONTROL 0x0040c184 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_49_COUNT 0x0040c188 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_49_CONTROL 0x0040c18c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_50_COUNT 0x0040c190 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_50_CONTROL 0x0040c194 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_51_COUNT 0x0040c198 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_51_CONTROL 0x0040c19c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_52_COUNT 0x0040c1a0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_52_CONTROL 0x0040c1a4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_53_COUNT 0x0040c1a8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_53_CONTROL 0x0040c1ac /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_54_COUNT 0x0040c1b0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_54_CONTROL 0x0040c1b4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_55_COUNT 0x0040c1b8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_55_CONTROL 0x0040c1bc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_56_COUNT 0x0040c1c0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_56_CONTROL 0x0040c1c4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_57_COUNT 0x0040c1c8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_57_CONTROL 0x0040c1cc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_58_COUNT 0x0040c1d0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_58_CONTROL 0x0040c1d4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_59_COUNT 0x0040c1d8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_59_CONTROL 0x0040c1dc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_60_COUNT 0x0040c1e0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_60_CONTROL 0x0040c1e4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_61_COUNT 0x0040c1e8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_61_CONTROL 0x0040c1ec /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_62_COUNT 0x0040c1f0 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_62_CONTROL 0x0040c1f4 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_63_COUNT 0x0040c1f8 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_63_CONTROL 0x0040c1fc /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_64_COUNT 0x0040c200 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_64_CONTROL 0x0040c204 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_65_COUNT 0x0040c208 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_65_CONTROL 0x0040c20c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_66_COUNT 0x0040c210 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_66_CONTROL 0x0040c214 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_67_COUNT 0x0040c218 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_67_CONTROL 0x0040c21c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_68_COUNT 0x0040c220 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_68_CONTROL 0x0040c224 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_69_COUNT 0x0040c228 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_69_CONTROL 0x0040c22c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_70_COUNT 0x0040c230 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_70_CONTROL 0x0040c234 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_71_COUNT 0x0040c238 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_71_CONTROL 0x0040c23c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_72_COUNT 0x0040c240 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_72_CONTROL 0x0040c244 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_73_COUNT 0x0040c248 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_73_CONTROL 0x0040c24c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_74_COUNT 0x0040c250 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_74_CONTROL 0x0040c254 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_75_COUNT 0x0040c258 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_75_CONTROL 0x0040c25c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_76_COUNT 0x0040c260 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_76_CONTROL 0x0040c264 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_77_COUNT 0x0040c268 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_77_CONTROL 0x0040c26c /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_78_COUNT 0x0040c270 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_78_CONTROL 0x0040c274 /* Arbiter Client RESERVED Configuration Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_79_COUNT 0x0040c278 /* Arbiter Client RESERVED Blockout Counter Register */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_79_CONTROL 0x0040c27c /* Arbiter Client RESERVED Configuration Register */ - -/*************************************************************************** - *CLIENT_00_COUNT - Arbiter Client DEBLOCK Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_00_CONTROL - Arbiter Client DEBLOCK Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_01_COUNT - Arbiter Client CABAC Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_01_CONTROL - Arbiter Client CABAC Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_02_COUNT - Arbiter Client ILOOP Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_02_CONTROL - Arbiter Client ILOOP Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_03_COUNT - Arbiter Client OLOOP Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_03_CONTROL - Arbiter Client OLOOP Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_04_COUNT - Arbiter Client SYMB_INT Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_04_CONTROL - Arbiter Client SYMB_INT Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_05_COUNT - Arbiter Client MOCOMP Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_05_CONTROL - Arbiter Client MOCOMP Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_06_COUNT - Arbiter Client XPT1 Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_06_CONTROL - Arbiter Client XPT1 Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_07_COUNT - Arbiter Client XPT2 Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_07_CONTROL - Arbiter Client XPT2 Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_08_COUNT - Arbiter Client XPT3 Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_08_CONTROL - Arbiter Client XPT3 Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_09_COUNT - Arbiter Client ARM Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_09_CONTROL - Arbiter Client ARM Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_10_COUNT - Arbiter Client M2M Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_10_CONTROL - Arbiter Client M2M Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_11_COUNT - Arbiter Client SHARF Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_11_CONTROL - Arbiter Client SHARF Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_12_COUNT - Arbiter Client MFD0 Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_12_CONTROL - Arbiter Client MFD0 Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_13_COUNT - Arbiter Client RXDMA Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_13_CONTROL - Arbiter Client RXDMA Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_14_COUNT - Arbiter Client TXDMA Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_14_CONTROL - Arbiter Client TXDMA Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_15_COUNT - Arbiter Client META Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_15_CONTROL - Arbiter Client META Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_16_COUNT - Arbiter Client DIRECT Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_16_CONTROL - Arbiter Client DIRECT Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_17_COUNT - Arbiter Client MSA Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_17_CONTROL - Arbiter Client MSA Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_18_COUNT - Arbiter Client TRACE Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_18_CONTROL - Arbiter Client TRACE Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_19_COUNT - Arbiter Client REFRESH0 Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: reserved_for_eco0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: cr [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_cr_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_cr_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: reserved_for_eco1 [15:14] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco1_MASK 0x0000c000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco1_SHIFT 14 - -/* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: bo [13:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_bo_MASK 0x00003fff -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_bo_SHIFT 0 - -/*************************************************************************** - *CLIENT_19_CONTROL - Arbiter Client REFRESH0 Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: reserved0 [31:30] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved0_MASK 0xc0000000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved0_SHIFT 30 - -/* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: bo_count [29:16] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_bo_count_MASK 0x3fff0000 -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_bo_count_SHIFT 16 - -/* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: reserved1 [15:11] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved1_MASK 0x0000f800 -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved1_SHIFT 11 - -/* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: mode [10:08] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_mode_MASK 0x00000700 -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_mode_SHIFT 8 - -/* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: prio [07:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_prio_MASK 0x000000ff -#define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_prio_SHIFT 0 - -/*************************************************************************** - *CLIENT_20_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_20_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_20_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_20_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_20_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_20_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_20_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_20_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_21_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_21_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_21_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_21_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_21_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_21_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_21_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_21_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_22_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_22_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_22_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_22_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_22_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_22_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_22_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_22_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_23_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_23_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_23_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_23_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_23_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_23_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_23_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_23_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_24_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_24_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_24_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_24_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_24_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_24_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_24_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_24_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_25_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_25_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_25_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_25_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_25_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_25_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_25_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_25_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_26_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_26_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_26_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_26_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_26_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_26_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_26_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_26_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_27_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_27_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_27_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_27_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_27_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_27_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_27_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_27_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_28_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_28_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_28_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_28_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_28_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_28_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_28_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_28_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_29_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_29_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_29_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_29_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_29_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_29_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_29_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_29_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_30_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_30_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_30_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_30_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_30_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_30_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_30_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_30_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_31_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_31_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_31_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_31_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_31_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_31_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_31_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_31_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_32_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_32_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_32_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_32_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_32_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_32_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_32_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_32_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_33_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_33_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_33_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_33_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_33_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_33_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_33_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_33_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_34_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_34_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_34_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_34_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_34_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_34_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_34_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_34_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_35_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_35_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_35_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_35_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_35_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_35_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_35_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_35_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_36_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_36_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_36_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_36_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_36_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_36_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_36_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_36_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_37_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_37_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_37_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_37_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_37_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_37_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_37_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_37_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_38_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_38_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_38_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_38_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_38_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_38_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_38_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_38_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_39_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_39_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_39_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_39_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_39_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_39_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_39_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_39_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_40_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_40_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_40_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_40_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_40_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_40_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_40_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_40_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_41_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_41_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_41_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_41_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_41_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_41_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_41_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_41_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_42_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_42_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_42_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_42_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_42_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_42_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_42_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_42_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_43_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_43_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_43_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_43_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_43_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_43_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_43_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_43_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_44_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_44_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_44_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_44_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_44_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_44_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_44_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_44_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_45_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_45_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_45_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_45_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_45_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_45_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_45_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_45_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_46_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_46_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_46_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_46_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_46_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_46_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_46_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_46_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_47_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_47_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_47_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_47_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_47_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_47_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_47_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_47_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_48_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_48_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_48_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_48_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_48_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_48_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_48_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_48_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_49_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_49_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_49_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_49_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_49_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_49_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_49_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_49_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_50_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_50_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_50_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_50_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_50_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_50_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_50_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_50_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_51_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_51_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_51_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_51_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_51_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_51_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_51_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_51_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_52_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_52_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_52_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_52_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_52_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_52_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_52_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_52_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_53_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_53_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_53_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_53_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_53_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_53_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_53_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_53_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_54_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_54_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_54_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_54_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_54_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_54_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_54_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_54_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_55_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_55_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_55_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_55_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_55_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_55_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_55_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_55_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_56_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_56_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_56_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_56_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_56_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_56_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_56_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_56_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_57_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_57_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_57_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_57_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_57_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_57_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_57_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_57_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_58_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_58_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_58_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_58_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_58_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_58_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_58_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_58_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_59_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_59_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_59_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_59_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_59_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_59_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_59_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_59_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_60_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_60_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_60_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_60_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_60_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_60_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_60_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_60_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_61_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_61_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_61_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_61_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_61_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_61_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_61_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_61_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_62_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_62_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_62_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_62_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_62_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_62_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_62_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_62_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_63_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_63_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_63_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_63_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_63_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_63_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_63_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_63_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_64_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_64_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_64_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_64_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_64_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_64_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_64_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_64_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_65_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_65_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_65_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_65_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_65_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_65_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_65_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_65_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_66_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_66_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_66_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_66_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_66_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_66_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_66_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_66_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_67_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_67_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_67_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_67_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_67_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_67_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_67_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_67_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_68_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_68_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_68_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_68_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_68_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_68_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_68_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_68_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_69_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_69_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_69_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_69_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_69_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_69_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_69_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_69_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_70_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_70_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_70_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_70_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_70_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_70_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_70_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_70_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_71_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_71_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_71_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_71_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_71_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_71_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_71_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_71_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_72_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_72_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_72_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_72_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_72_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_72_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_72_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_72_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_73_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_73_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_73_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_73_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_73_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_73_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_73_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_73_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_74_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_74_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_74_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_74_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_74_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_74_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_74_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_74_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_75_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_75_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_75_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_75_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_75_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_75_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_75_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_75_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_76_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_76_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_76_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_76_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_76_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_76_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_76_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_76_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_77_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_77_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_77_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_77_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_77_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_77_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_77_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_77_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_78_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_78_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_78_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_78_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_78_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_78_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_78_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_78_CONTROL_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_79_COUNT - Arbiter Client RESERVED Blockout Counter Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_79_COUNT :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_79_COUNT_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_79_COUNT_RESERVED_SHIFT 0 - -/*************************************************************************** - *CLIENT_79_CONTROL - Arbiter Client RESERVED Configuration Register - ***************************************************************************/ -/* PRI_CLIENT_REGS :: CLIENT_79_CONTROL :: RESERVED [31:00] */ -#define BCHP_PRI_CLIENT_REGS_CLIENT_79_CONTROL_RESERVED_MASK 0xffffffff -#define BCHP_PRI_CLIENT_REGS_CLIENT_79_CONTROL_RESERVED_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_CLIENT_REGS_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_1.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_1.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_1.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_1.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1114 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_crit_l2_regs_1.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:16p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:24 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_1.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:16p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_CRIT_L2_REGS_1_H__ -#define BCHP_PRI_CRIT_L2_REGS_1_H__ - -/*************************************************************************** - *PRI_CRIT_L2_REGS_1 - PRIMARY_ARB_CLIENTS L2 (Mips) critical interrupt controller 1 registers - ***************************************************************************/ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS 0x0040c400 /* CPU interrupt Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET 0x0040c404 /* CPU interrupt Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR 0x0040c408 /* CPU interrupt Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS 0x0040c40c /* CPU interrupt Mask Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET 0x0040c410 /* CPU interrupt Mask Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR 0x0040c414 /* CPU interrupt Mask Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS 0x0040c418 /* PCI interrupt Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET 0x0040c41c /* PCI interrupt Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR 0x0040c420 /* PCI interrupt Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS 0x0040c424 /* PCI interrupt Mask Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET 0x0040c428 /* PCI interrupt Mask Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR 0x0040c42c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_19_INTR [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_19_INTR_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_19_INTR_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_18_INTR [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_18_INTR_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_18_INTR_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_17_INTR [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_17_INTR_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_17_INTR_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_16_INTR [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_16_INTR_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_16_INTR_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_15_INTR [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_15_INTR_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_15_INTR_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_14_INTR [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_14_INTR_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_14_INTR_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_13_INTR [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_13_INTR_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_13_INTR_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_12_INTR [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_12_INTR_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_12_INTR_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_11_INTR [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_11_INTR_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_11_INTR_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_10_INTR [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_10_INTR_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_10_INTR_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_09_INTR [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_09_INTR_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_09_INTR_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_08_INTR [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_08_INTR_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_08_INTR_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_07_INTR [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_07_INTR_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_07_INTR_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_06_INTR [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_06_INTR_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_06_INTR_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_05_INTR [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_05_INTR_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_05_INTR_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_04_INTR [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_04_INTR_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_04_INTR_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_03_INTR [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_03_INTR_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_03_INTR_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_02_INTR [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_02_INTR_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_02_INTR_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_01_INTR [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_01_INTR_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_01_INTR_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_00_INTR [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_00_INTR_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_00_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_19_INTR [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_19_INTR_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_19_INTR_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_18_INTR [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_18_INTR_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_18_INTR_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_17_INTR [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_17_INTR_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_17_INTR_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_16_INTR [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_16_INTR_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_16_INTR_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_15_INTR [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_15_INTR_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_15_INTR_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_14_INTR [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_14_INTR_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_14_INTR_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_13_INTR [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_13_INTR_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_13_INTR_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_12_INTR [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_12_INTR_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_12_INTR_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_11_INTR [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_11_INTR_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_11_INTR_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_10_INTR [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_10_INTR_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_10_INTR_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_09_INTR [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_09_INTR_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_09_INTR_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_08_INTR [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_08_INTR_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_08_INTR_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_07_INTR [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_07_INTR_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_07_INTR_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_06_INTR [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_06_INTR_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_06_INTR_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_05_INTR [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_05_INTR_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_05_INTR_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_04_INTR [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_04_INTR_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_04_INTR_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_03_INTR [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_03_INTR_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_03_INTR_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_02_INTR [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_02_INTR_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_02_INTR_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_01_INTR [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_01_INTR_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_01_INTR_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_00_INTR [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_00_INTR_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_00_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_19_INTR [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_19_INTR_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_19_INTR_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_18_INTR [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_18_INTR_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_18_INTR_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_17_INTR [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_17_INTR_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_17_INTR_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_16_INTR [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_16_INTR_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_16_INTR_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_15_INTR [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_15_INTR_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_15_INTR_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_14_INTR [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_14_INTR_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_14_INTR_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_13_INTR [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_13_INTR_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_13_INTR_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_12_INTR [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_12_INTR_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_12_INTR_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_11_INTR [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_11_INTR_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_11_INTR_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_10_INTR [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_10_INTR_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_10_INTR_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_09_INTR [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_09_INTR_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_09_INTR_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_08_INTR [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_08_INTR_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_08_INTR_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_07_INTR [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_07_INTR_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_07_INTR_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_06_INTR [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_06_INTR_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_06_INTR_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_05_INTR [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_05_INTR_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_05_INTR_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_04_INTR [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_04_INTR_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_04_INTR_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_03_INTR [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_03_INTR_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_03_INTR_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_02_INTR [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_02_INTR_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_02_INTR_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_01_INTR [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_01_INTR_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_01_INTR_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_00_INTR [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_00_INTR_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_00_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_19_MASK [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_19_MASK_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_19_MASK_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_18_MASK [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_18_MASK_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_18_MASK_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_17_MASK [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_17_MASK_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_17_MASK_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_16_MASK [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_16_MASK_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_16_MASK_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_15_MASK [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_15_MASK_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_15_MASK_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_14_MASK [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_14_MASK_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_14_MASK_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_13_MASK [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_13_MASK_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_13_MASK_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_12_MASK [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_12_MASK_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_12_MASK_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_11_MASK [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_11_MASK_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_11_MASK_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_10_MASK [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_10_MASK_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_10_MASK_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_09_MASK [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_09_MASK_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_09_MASK_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_08_MASK [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_08_MASK_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_08_MASK_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_07_MASK [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_07_MASK_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_07_MASK_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_06_MASK [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_06_MASK_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_06_MASK_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_05_MASK [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_05_MASK_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_05_MASK_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_04_MASK [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_04_MASK_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_04_MASK_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_03_MASK [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_03_MASK_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_03_MASK_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_02_MASK [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_02_MASK_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_02_MASK_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_01_MASK [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_01_MASK_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_01_MASK_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_00_MASK [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_00_MASK_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_00_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_19_MASK [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_19_MASK_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_19_MASK_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_18_MASK [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_18_MASK_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_18_MASK_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_17_MASK [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_17_MASK_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_17_MASK_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_16_MASK [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_16_MASK_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_16_MASK_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_15_MASK [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_15_MASK_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_15_MASK_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_14_MASK [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_14_MASK_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_14_MASK_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_13_MASK [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_13_MASK_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_13_MASK_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_12_MASK [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_12_MASK_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_12_MASK_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_11_MASK [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_11_MASK_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_11_MASK_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_10_MASK [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_10_MASK_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_10_MASK_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_09_MASK [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_09_MASK_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_09_MASK_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_08_MASK [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_08_MASK_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_08_MASK_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_07_MASK [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_07_MASK_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_07_MASK_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_06_MASK [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_06_MASK_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_06_MASK_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_05_MASK [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_05_MASK_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_05_MASK_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_04_MASK [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_04_MASK_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_04_MASK_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_03_MASK [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_03_MASK_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_03_MASK_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_02_MASK [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_02_MASK_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_02_MASK_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_01_MASK [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_01_MASK_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_01_MASK_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_00_MASK [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_00_MASK_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_00_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_19_MASK [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_19_MASK_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_19_MASK_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_18_MASK [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_18_MASK_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_18_MASK_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_17_MASK [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_17_MASK_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_17_MASK_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_16_MASK [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_16_MASK_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_16_MASK_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_15_MASK [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_15_MASK_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_15_MASK_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_14_MASK [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_14_MASK_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_14_MASK_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_13_MASK [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_13_MASK_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_13_MASK_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_12_MASK [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_12_MASK_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_12_MASK_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_11_MASK [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_11_MASK_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_11_MASK_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_10_MASK [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_10_MASK_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_10_MASK_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_09_MASK [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_09_MASK_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_09_MASK_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_08_MASK [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_08_MASK_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_08_MASK_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_07_MASK [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_07_MASK_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_07_MASK_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_06_MASK [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_06_MASK_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_06_MASK_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_05_MASK [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_05_MASK_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_05_MASK_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_04_MASK [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_04_MASK_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_04_MASK_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_03_MASK [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_03_MASK_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_03_MASK_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_02_MASK [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_02_MASK_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_02_MASK_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_01_MASK [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_01_MASK_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_01_MASK_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_00_MASK [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_00_MASK_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_00_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_19_INTR [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_19_INTR_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_19_INTR_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_18_INTR [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_18_INTR_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_18_INTR_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_17_INTR [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_17_INTR_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_17_INTR_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_16_INTR [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_16_INTR_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_16_INTR_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_15_INTR [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_15_INTR_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_15_INTR_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_14_INTR [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_14_INTR_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_14_INTR_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_13_INTR [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_13_INTR_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_13_INTR_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_12_INTR [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_12_INTR_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_12_INTR_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_11_INTR [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_11_INTR_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_11_INTR_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_10_INTR [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_10_INTR_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_10_INTR_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_09_INTR [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_09_INTR_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_09_INTR_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_08_INTR [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_08_INTR_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_08_INTR_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_07_INTR [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_07_INTR_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_07_INTR_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_06_INTR [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_06_INTR_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_06_INTR_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_05_INTR [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_05_INTR_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_05_INTR_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_04_INTR [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_04_INTR_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_04_INTR_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_03_INTR [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_03_INTR_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_03_INTR_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_02_INTR [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_02_INTR_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_02_INTR_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_01_INTR [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_01_INTR_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_01_INTR_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_00_INTR [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_00_INTR_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_00_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_19_INTR [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_19_INTR_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_19_INTR_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_18_INTR [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_18_INTR_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_18_INTR_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_17_INTR [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_17_INTR_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_17_INTR_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_16_INTR [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_16_INTR_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_16_INTR_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_15_INTR [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_15_INTR_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_15_INTR_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_14_INTR [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_14_INTR_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_14_INTR_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_13_INTR [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_13_INTR_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_13_INTR_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_12_INTR [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_12_INTR_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_12_INTR_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_11_INTR [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_11_INTR_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_11_INTR_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_10_INTR [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_10_INTR_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_10_INTR_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_09_INTR [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_09_INTR_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_09_INTR_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_08_INTR [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_08_INTR_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_08_INTR_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_07_INTR [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_07_INTR_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_07_INTR_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_06_INTR [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_06_INTR_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_06_INTR_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_05_INTR [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_05_INTR_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_05_INTR_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_04_INTR [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_04_INTR_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_04_INTR_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_03_INTR [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_03_INTR_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_03_INTR_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_02_INTR [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_02_INTR_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_02_INTR_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_01_INTR [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_01_INTR_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_01_INTR_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_00_INTR [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_00_INTR_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_00_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_19_INTR [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_19_INTR_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_19_INTR_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_18_INTR [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_18_INTR_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_18_INTR_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_17_INTR [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_17_INTR_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_17_INTR_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_16_INTR [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_16_INTR_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_16_INTR_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_15_INTR [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_15_INTR_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_15_INTR_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_14_INTR [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_14_INTR_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_14_INTR_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_13_INTR [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_13_INTR_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_13_INTR_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_12_INTR [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_12_INTR_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_12_INTR_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_11_INTR [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_11_INTR_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_11_INTR_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_10_INTR [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_10_INTR_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_10_INTR_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_09_INTR [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_09_INTR_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_09_INTR_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_08_INTR [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_08_INTR_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_08_INTR_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_07_INTR [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_07_INTR_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_07_INTR_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_06_INTR [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_06_INTR_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_06_INTR_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_05_INTR [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_05_INTR_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_05_INTR_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_04_INTR [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_04_INTR_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_04_INTR_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_03_INTR [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_03_INTR_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_03_INTR_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_02_INTR [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_02_INTR_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_02_INTR_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_01_INTR [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_01_INTR_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_01_INTR_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_00_INTR [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_00_INTR_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_00_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_19_MASK [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_19_MASK_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_19_MASK_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_18_MASK [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_18_MASK_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_18_MASK_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_17_MASK [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_17_MASK_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_17_MASK_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_16_MASK [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_16_MASK_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_16_MASK_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_15_MASK [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_15_MASK_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_15_MASK_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_14_MASK [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_14_MASK_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_14_MASK_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_13_MASK [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_13_MASK_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_13_MASK_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_12_MASK [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_12_MASK_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_12_MASK_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_11_MASK [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_11_MASK_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_11_MASK_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_10_MASK [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_10_MASK_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_10_MASK_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_09_MASK [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_09_MASK_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_09_MASK_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_08_MASK [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_08_MASK_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_08_MASK_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_07_MASK [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_07_MASK_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_07_MASK_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_06_MASK [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_06_MASK_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_06_MASK_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_05_MASK [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_05_MASK_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_05_MASK_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_04_MASK [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_04_MASK_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_04_MASK_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_03_MASK [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_03_MASK_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_03_MASK_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_02_MASK [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_02_MASK_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_02_MASK_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_01_MASK [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_01_MASK_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_01_MASK_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_00_MASK [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_00_MASK_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_00_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_19_MASK [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_19_MASK_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_19_MASK_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_18_MASK [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_18_MASK_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_18_MASK_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_17_MASK [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_17_MASK_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_17_MASK_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_16_MASK [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_16_MASK_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_16_MASK_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_15_MASK [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_15_MASK_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_15_MASK_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_14_MASK [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_14_MASK_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_14_MASK_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_13_MASK [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_13_MASK_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_13_MASK_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_12_MASK [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_12_MASK_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_12_MASK_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_11_MASK [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_11_MASK_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_11_MASK_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_10_MASK [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_10_MASK_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_10_MASK_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_09_MASK [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_09_MASK_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_09_MASK_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_08_MASK [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_08_MASK_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_08_MASK_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_07_MASK [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_07_MASK_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_07_MASK_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_06_MASK [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_06_MASK_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_06_MASK_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_05_MASK [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_05_MASK_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_05_MASK_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_04_MASK [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_04_MASK_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_04_MASK_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_03_MASK [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_03_MASK_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_03_MASK_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_02_MASK [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_02_MASK_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_02_MASK_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_01_MASK [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_01_MASK_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_01_MASK_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_00_MASK [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_00_MASK_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_00_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: reserved0 [31:20] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_reserved0_MASK 0xfff00000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_reserved0_SHIFT 20 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_19_MASK [19:19] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_19_MASK_MASK 0x00080000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_19_MASK_SHIFT 19 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_18_MASK [18:18] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_18_MASK_MASK 0x00040000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_18_MASK_SHIFT 18 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_17_MASK [17:17] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_17_MASK_MASK 0x00020000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_17_MASK_SHIFT 17 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_16_MASK [16:16] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_16_MASK_MASK 0x00010000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_16_MASK_SHIFT 16 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_15_MASK [15:15] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_15_MASK_MASK 0x00008000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_15_MASK_SHIFT 15 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_14_MASK [14:14] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_14_MASK_MASK 0x00004000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_14_MASK_SHIFT 14 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_13_MASK [13:13] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_13_MASK_MASK 0x00002000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_13_MASK_SHIFT 13 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_12_MASK [12:12] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_12_MASK_MASK 0x00001000 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_12_MASK_SHIFT 12 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_11_MASK [11:11] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_11_MASK_MASK 0x00000800 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_11_MASK_SHIFT 11 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_10_MASK [10:10] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_10_MASK_MASK 0x00000400 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_10_MASK_SHIFT 10 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_09_MASK [09:09] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_09_MASK_MASK 0x00000200 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_09_MASK_SHIFT 9 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_08_MASK [08:08] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_08_MASK_MASK 0x00000100 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_08_MASK_SHIFT 8 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_07_MASK [07:07] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_07_MASK_MASK 0x00000080 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_07_MASK_SHIFT 7 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_06_MASK [06:06] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_06_MASK_MASK 0x00000040 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_06_MASK_SHIFT 6 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_05_MASK [05:05] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_05_MASK_MASK 0x00000020 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_05_MASK_SHIFT 5 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_04_MASK [04:04] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_04_MASK_MASK 0x00000010 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_04_MASK_SHIFT 4 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_03_MASK [03:03] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_03_MASK_MASK 0x00000008 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_03_MASK_SHIFT 3 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_02_MASK [02:02] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_02_MASK_MASK 0x00000004 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_02_MASK_SHIFT 2 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_01_MASK [01:01] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_01_MASK_MASK 0x00000002 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_01_MASK_SHIFT 1 - -/* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_00_MASK [00:00] */ -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_00_MASK_MASK 0x00000001 -#define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_00_MASK_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_CRIT_L2_REGS_1_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,154 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_crit_l2_regs_2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:16p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:09 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:16p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_CRIT_L2_REGS_2_H__ -#define BCHP_PRI_CRIT_L2_REGS_2_H__ - -/*************************************************************************** - *PRI_CRIT_L2_REGS_2 - PRIMARY_ARB_CLIENTS L2 (Mips) critical interrupt controller 2 registers - ***************************************************************************/ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_STATUS 0x0040c440 /* CPU interrupt Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_SET 0x0040c444 /* CPU interrupt Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_CLEAR 0x0040c448 /* CPU interrupt Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_STATUS 0x0040c44c /* CPU interrupt Mask Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_SET 0x0040c450 /* CPU interrupt Mask Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_CLEAR 0x0040c454 /* CPU interrupt Mask Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_STATUS 0x0040c458 /* PCI interrupt Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_SET 0x0040c45c /* PCI interrupt Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_CLEAR 0x0040c460 /* PCI interrupt Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_STATUS 0x0040c464 /* PCI interrupt Mask Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_SET 0x0040c468 /* PCI interrupt Mask Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_CLEAR 0x0040c46c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: CPU_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: CPU_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: CPU_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_CLEAR_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: CPU_MASK_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: CPU_MASK_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: CPU_MASK_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_CLEAR_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: PCI_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: PCI_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: PCI_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_CLEAR_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: PCI_MASK_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: PCI_MASK_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_2 :: PCI_MASK_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_CLEAR_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_CRIT_L2_REGS_2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,154 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_crit_l2_regs_3.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:16p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:45 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:16p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_CRIT_L2_REGS_3_H__ -#define BCHP_PRI_CRIT_L2_REGS_3_H__ - -/*************************************************************************** - *PRI_CRIT_L2_REGS_3 - PRIMARY_ARB_CLIENTS L2 (Mips) critical interrupt controller 3 registers - ***************************************************************************/ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS 0x0040c480 /* CPU interrupt Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET 0x0040c484 /* CPU interrupt Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR 0x0040c488 /* CPU interrupt Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS 0x0040c48c /* CPU interrupt Mask Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET 0x0040c490 /* CPU interrupt Mask Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR 0x0040c494 /* CPU interrupt Mask Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS 0x0040c498 /* PCI interrupt Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET 0x0040c49c /* PCI interrupt Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR 0x0040c4a0 /* PCI interrupt Clear Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS 0x0040c4a4 /* PCI interrupt Mask Status Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET 0x0040c4a8 /* PCI interrupt Mask Set Register */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR 0x0040c4ac /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: CPU_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: CPU_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: CPU_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: CPU_MASK_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: CPU_MASK_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: CPU_MASK_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: PCI_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: PCI_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: PCI_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: PCI_MASK_STATUS :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: PCI_MASK_SET :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET_reserved0_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* PRI_CRIT_L2_REGS_3 :: PCI_MASK_CLEAR :: reserved0 [31:00] */ -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR_reserved0_MASK 0xffffffff -#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_PRI_CRIT_L2_REGS_3_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_rts_l2_regs_1.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:17p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:23 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:17p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_RTS_L2_REGS_1_H__ -#define BCHP_PRI_RTS_L2_REGS_1_H__ - -/*************************************************************************** - *PRI_RTS_L2_REGS_1 - PRIMARY_ARB_CLIENTS L2 (Mips) rts interrupt controller 1 registers - ***************************************************************************/ -#define BCHP_PRI_RTS_L2_REGS_1_CPU_STATUS 0x0040c4c0 /* CPU interrupt Status Register */ -#define BCHP_PRI_RTS_L2_REGS_1_CPU_SET 0x0040c4c4 /* CPU interrupt Set Register */ -#define BCHP_PRI_RTS_L2_REGS_1_CPU_CLEAR 0x0040c4c8 /* CPU interrupt Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_STATUS 0x0040c4cc /* CPU interrupt Mask Status Register */ -#define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_SET 0x0040c4d0 /* CPU interrupt Mask Set Register */ -#define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_CLEAR 0x0040c4d4 /* CPU interrupt Mask Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_1_PCI_STATUS 0x0040c4d8 /* PCI interrupt Status Register */ -#define BCHP_PRI_RTS_L2_REGS_1_PCI_SET 0x0040c4dc /* PCI interrupt Set Register */ -#define BCHP_PRI_RTS_L2_REGS_1_PCI_CLEAR 0x0040c4e0 /* PCI interrupt Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_STATUS 0x0040c4e4 /* PCI interrupt Mask Status Register */ -#define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_SET 0x0040c4e8 /* PCI interrupt Mask Set Register */ -#define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_CLEAR 0x0040c4ec /* PCI interrupt Mask Clear Register */ - -#endif /* #ifndef BCHP_PRI_RTS_L2_REGS_1_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_rts_l2_regs_2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:17p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:20 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:17p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_RTS_L2_REGS_2_H__ -#define BCHP_PRI_RTS_L2_REGS_2_H__ - -/*************************************************************************** - *PRI_RTS_L2_REGS_2 - PRIMARY_ARB_CLIENTS L2 (Mips) rts interrupt controller 2 registers - ***************************************************************************/ -#define BCHP_PRI_RTS_L2_REGS_2_CPU_STATUS 0x0040c500 /* CPU interrupt Status Register */ -#define BCHP_PRI_RTS_L2_REGS_2_CPU_SET 0x0040c504 /* CPU interrupt Set Register */ -#define BCHP_PRI_RTS_L2_REGS_2_CPU_CLEAR 0x0040c508 /* CPU interrupt Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_2_CPU_MASK_STATUS 0x0040c50c /* CPU interrupt Mask Status Register */ -#define BCHP_PRI_RTS_L2_REGS_2_CPU_MASK_SET 0x0040c510 /* CPU interrupt Mask Set Register */ -#define BCHP_PRI_RTS_L2_REGS_2_CPU_MASK_CLEAR 0x0040c514 /* CPU interrupt Mask Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_2_PCI_STATUS 0x0040c518 /* PCI interrupt Status Register */ -#define BCHP_PRI_RTS_L2_REGS_2_PCI_SET 0x0040c51c /* PCI interrupt Set Register */ -#define BCHP_PRI_RTS_L2_REGS_2_PCI_CLEAR 0x0040c520 /* PCI interrupt Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_2_PCI_MASK_STATUS 0x0040c524 /* PCI interrupt Mask Status Register */ -#define BCHP_PRI_RTS_L2_REGS_2_PCI_MASK_SET 0x0040c528 /* PCI interrupt Mask Set Register */ -#define BCHP_PRI_RTS_L2_REGS_2_PCI_MASK_CLEAR 0x0040c52c /* PCI interrupt Mask Clear Register */ - -#endif /* #ifndef BCHP_PRI_RTS_L2_REGS_2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_3.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_3.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_3.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_3.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_pri_rts_l2_regs_3.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:17p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:26 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_3.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:17p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_PRI_RTS_L2_REGS_3_H__ -#define BCHP_PRI_RTS_L2_REGS_3_H__ - -/*************************************************************************** - *PRI_RTS_L2_REGS_3 - PRIMARY_ARB_CLIENTS L2 (Mips) rts interrupt controller 3 registers - ***************************************************************************/ -#define BCHP_PRI_RTS_L2_REGS_3_CPU_STATUS 0x0040c540 /* CPU interrupt Status Register */ -#define BCHP_PRI_RTS_L2_REGS_3_CPU_SET 0x0040c544 /* CPU interrupt Set Register */ -#define BCHP_PRI_RTS_L2_REGS_3_CPU_CLEAR 0x0040c548 /* CPU interrupt Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_3_CPU_MASK_STATUS 0x0040c54c /* CPU interrupt Mask Status Register */ -#define BCHP_PRI_RTS_L2_REGS_3_CPU_MASK_SET 0x0040c550 /* CPU interrupt Mask Set Register */ -#define BCHP_PRI_RTS_L2_REGS_3_CPU_MASK_CLEAR 0x0040c554 /* CPU interrupt Mask Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_3_PCI_STATUS 0x0040c558 /* PCI interrupt Status Register */ -#define BCHP_PRI_RTS_L2_REGS_3_PCI_SET 0x0040c55c /* PCI interrupt Set Register */ -#define BCHP_PRI_RTS_L2_REGS_3_PCI_CLEAR 0x0040c560 /* PCI interrupt Clear Register */ -#define BCHP_PRI_RTS_L2_REGS_3_PCI_MASK_STATUS 0x0040c564 /* PCI interrupt Mask Status Register */ -#define BCHP_PRI_RTS_L2_REGS_3_PCI_MASK_SET 0x0040c568 /* PCI interrupt Mask Set Register */ -#define BCHP_PRI_RTS_L2_REGS_3_PCI_MASK_CLEAR 0x0040c56c /* PCI interrupt Mask Clear Register */ - -#endif /* #ifndef BCHP_PRI_RTS_L2_REGS_3_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,90 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_reg_cabac2bins_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:18p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:54 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:18p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_REG_CABAC2BINS_0_H__ -#define BCHP_REG_CABAC2BINS_0_H__ - -/*************************************************************************** - *REG_CABAC2BINS_0 - ***************************************************************************/ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST 0x00800bbc /* REG_CABAC2BINS_IMG__CTX_LAST */ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR 0x00800bd0 /* REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR */ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_END_END 0x00800bfc /* REG_CABAC2BINS_END_END */ - -/*************************************************************************** - *REG_CABAC2BINS_IMG__CTX_LAST - REG_CABAC2BINS_IMG__CTX_LAST - ***************************************************************************/ -/* REG_CABAC2BINS_0 :: REG_CABAC2BINS_IMG__CTX_LAST :: reserved0 [31:09] */ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_reserved0_MASK 0xfffffe00 -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_reserved0_SHIFT 9 - -/* REG_CABAC2BINS_0 :: REG_CABAC2BINS_IMG__CTX_LAST :: CtxLast [08:00] */ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_CtxLast_MASK 0x000001ff -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_CtxLast_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR - REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS_0 :: REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR :: Addr [31:04] */ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_Addr_MASK 0xfffffff0 -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_Addr_SHIFT 4 - -/* REG_CABAC2BINS_0 :: REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR :: reserved0 [03:00] */ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_reserved0_MASK 0x0000000f -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_END_END - REG_CABAC2BINS_END_END - ***************************************************************************/ -/* REG_CABAC2BINS_0 :: REG_CABAC2BINS_END_END :: reserved0 [31:00] */ -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_END_END_reserved0_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_END_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_REG_CABAC2BINS_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins2_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins2_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins2_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins2_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,386 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_reg_cabac2bins2_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:17p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:59 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins2_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:17p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_REG_CABAC2BINS2_0_H__ -#define BCHP_REG_CABAC2BINS2_0_H__ - -/*************************************************************************** - *REG_CABAC2BINS2_0 - ***************************************************************************/ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_ADDR 0x00802588 /* REG_CABAC2BINS_RD_BUFF_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL 0x0080258c /* REG_CABAC2BINS_RD_BUFF_CTL */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR 0x00802594 /* REG_CABAC2BINS_RD_BUFF_START_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_END_ADDR 0x00802598 /* REG_CABAC2BINS_RD_BUFF_END_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_STALL_CNT 0x0080259c /* REG_CABAC2BINS_RD_BUFF_STALL_CNT */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR 0x008025a8 /* REG_CABAC2BINS_WR_BUFF_START_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL 0x008025ac /* REG_CABAC2BINS_WR_BUFF_CTL */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR 0x008025b0 /* REG_CABAC2BINS_WR_BUFF_END_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR 0x008025b4 /* REG_CABAC2BINS_WR_BUFF_MARK_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_STALL_CNT 0x008025b8 /* REG_CABAC2BINS_WR_BUFF_STALL_CNT */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_ADDR 0x008025bc /* REG_CABAC2BINS_WR_BUFF_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID 0x008025c0 /* REG_CABAC2BINS_CHANNEL_ID */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_NOT_IDLE_CYCLES 0x00802620 /* REG_CABAC2BINS_NOT_IDLE_CYCLES */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0 0x00802630 /* REG_CABAC2BINS_STATE0 */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1 0x00802634 /* REG_CABAC2BINS_STATE1 */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL 0x00802640 /* REG_CABAC2BINS_INIT_TBL_CTL */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR 0x00802710 /* REG_CABAC2BINS_PICTURE_COMMAND_ADDR */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN 0x00802714 /* REG_CABAC2BINS_LITTLE_ENDIAN */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS 0x00802718 /* REG_CABAC2BINS_PICTURE_STATUS */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL 0x0080272c /* REG_CABAC2BINS_CTL */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_END_END_1 0x008027fc /* REG_CABAC2BINS_END_END_1 */ - -/*************************************************************************** - *REG_CABAC2BINS_CHANNEL_WR_POSITION_%i - REG_CABAC2BINS_CHANNEL_WR_POSITION_0..31 - ***************************************************************************/ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_BASE 0x00802400 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_START 0 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_END 31 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *REG_CABAC2BINS_CHANNEL_WR_POSITION_%i - REG_CABAC2BINS_CHANNEL_WR_POSITION_0..31 - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CHANNEL_WR_POSITION_i :: Addr [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_Addr_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_Addr_SHIFT 0 - - -/*************************************************************************** - *REG_CABAC2BINS_RD_BUFF_ADDR - REG_CABAC2BINS_RD_BUFF_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_ADDR :: Addr [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_ADDR_Addr_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_ADDR_Addr_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_RD_BUFF_CTL - REG_CABAC2BINS_RD_BUFF_CTL - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: reserved0 [31:05] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_reserved0_MASK 0xffffffe0 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_reserved0_SHIFT 5 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: At_mark [04:04] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_At_mark_MASK 0x00000010 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_At_mark_SHIFT 4 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Not_Rdy [03:03] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Not_Rdy_MASK 0x00000008 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Not_Rdy_SHIFT 3 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Wrap_En [02:02] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Wrap_En_MASK 0x00000004 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Wrap_En_SHIFT 2 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Init [01:01] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Init_MASK 0x00000002 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Init_SHIFT 1 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Buff_En [00:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Buff_En_MASK 0x00000001 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Buff_En_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_RD_BUFF_START_ADDR - REG_CABAC2BINS_RD_BUFF_START_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_START_ADDR :: Addr [31:07] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_Addr_MASK 0xffffff80 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_Addr_SHIFT 7 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_START_ADDR :: reserved0 [06:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_reserved0_MASK 0x0000007f -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_RD_BUFF_END_ADDR - REG_CABAC2BINS_RD_BUFF_END_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_END_ADDR :: Addr [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_END_ADDR_Addr_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_END_ADDR_Addr_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_RD_BUFF_STALL_CNT - REG_CABAC2BINS_RD_BUFF_STALL_CNT - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_STALL_CNT :: Count [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_STALL_CNT_Count_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_STALL_CNT_Count_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_WR_BUFF_START_ADDR - REG_CABAC2BINS_WR_BUFF_START_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_START_ADDR :: Addr [31:07] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_Addr_MASK 0xffffff80 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_Addr_SHIFT 7 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_START_ADDR :: reserved0 [06:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_reserved0_MASK 0x0000007f -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_WR_BUFF_CTL - REG_CABAC2BINS_WR_BUFF_CTL - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: reserved0 [31:05] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_reserved0_MASK 0xffffffe0 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_reserved0_SHIFT 5 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: At_mark [04:04] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_At_mark_MASK 0x00000010 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_At_mark_SHIFT 4 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Not_Rdy [03:03] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Not_Rdy_MASK 0x00000008 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Not_Rdy_SHIFT 3 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Buff_close [02:02] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_close_MASK 0x00000004 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_close_SHIFT 2 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Init [01:01] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Init_MASK 0x00000002 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Init_SHIFT 1 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Buff_En [00:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_En_MASK 0x00000001 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_En_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_WR_BUFF_END_ADDR - REG_CABAC2BINS_WR_BUFF_END_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_END_ADDR :: Addr [31:07] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_Addr_MASK 0xffffff80 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_Addr_SHIFT 7 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_END_ADDR :: reserved0 [06:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_reserved0_MASK 0x0000007f -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_WR_BUFF_MARK_ADDR - REG_CABAC2BINS_WR_BUFF_MARK_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_MARK_ADDR :: Addr [31:07] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_Addr_MASK 0xffffff80 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_Addr_SHIFT 7 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_MARK_ADDR :: reserved0 [06:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_reserved0_MASK 0x0000007f -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_WR_BUFF_STALL_CNT - REG_CABAC2BINS_WR_BUFF_STALL_CNT - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_STALL_CNT :: Count [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_STALL_CNT_Count_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_STALL_CNT_Count_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_WR_BUFF_ADDR - REG_CABAC2BINS_WR_BUFF_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_ADDR :: Addr [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_ADDR_Addr_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_ADDR_Addr_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_CHANNEL_ID - REG_CABAC2BINS_CHANNEL_ID - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CHANNEL_ID :: reserved0 [31:05] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_reserved0_MASK 0xffffffe0 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_reserved0_SHIFT 5 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CHANNEL_ID :: ID [04:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_ID_MASK 0x0000001f -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_ID_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_NOT_IDLE_CYCLES - REG_CABAC2BINS_NOT_IDLE_CYCLES - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_NOT_IDLE_CYCLES :: Cycle_Count [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_NOT_IDLE_CYCLES_Cycle_Count_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_NOT_IDLE_CYCLES_Cycle_Count_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_STATE0 - REG_CABAC2BINS_STATE0 - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE0 :: reserved0 [31:10] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_reserved0_MASK 0xfffffc00 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_reserved0_SHIFT 10 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE0 :: State [09:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_State_MASK 0x000003ff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_State_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_STATE1 - REG_CABAC2BINS_STATE1 - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE1 :: reserved0 [31:10] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_reserved0_MASK 0xfffffc00 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_reserved0_SHIFT 10 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE1 :: State [09:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_State_MASK 0x000003ff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_State_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_INIT_TBL_CTL - REG_CABAC2BINS_INIT_TBL_CTL - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_INIT_TBL_CTL :: reserved0 [31:13] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved0_MASK 0xffffe000 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved0_SHIFT 13 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_INIT_TBL_CTL :: Enable [12:12] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_Enable_MASK 0x00001000 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_Enable_SHIFT 12 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_INIT_TBL_CTL :: reserved1 [11:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved1_MASK 0x00000fff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved1_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_PICTURE_COMMAND_ADDR - REG_CABAC2BINS_PICTURE_COMMAND_ADDR - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_COMMAND_ADDR :: Addr [31:02] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_Addr_MASK 0xfffffffc -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_Addr_SHIFT 2 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_COMMAND_ADDR :: reserved0 [01:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_reserved0_MASK 0x00000003 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_LITTLE_ENDIAN - REG_CABAC2BINS_LITTLE_ENDIAN - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_LITTLE_ENDIAN :: reserved0 [31:01] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_reserved0_MASK 0xfffffffe -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_reserved0_SHIFT 1 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_LITTLE_ENDIAN :: Little_Endian [00:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_Little_Endian_MASK 0x00000001 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_Little_Endian_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_PICTURE_STATUS - REG_CABAC2BINS_PICTURE_STATUS - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: reserved0 [31:04] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_reserved0_SHIFT 4 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: Picture_Cmd_Count [03:02] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Picture_Cmd_Count_MASK 0x0000000c -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Picture_Cmd_Count_SHIFT 2 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: Full [01:01] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Full_MASK 0x00000002 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Full_SHIFT 1 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: Busy [00:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Busy_MASK 0x00000001 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Busy_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_CTL - REG_CABAC2BINS_CTL - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: reserved0 [31:12] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved0_MASK 0xfffff000 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved0_SHIFT 12 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: Int [11:11] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Int_MASK 0x00000800 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Int_SHIFT 11 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: Active [10:10] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Active_MASK 0x00000400 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Active_SHIFT 10 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: WrNR [09:09] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrNR_MASK 0x00000200 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrNR_SHIFT 9 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: RdNR [08:08] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdNR_MASK 0x00000100 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdNR_SHIFT 8 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: WrMk [07:07] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrMk_MASK 0x00000080 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrMk_SHIFT 7 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: RdMk [06:06] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdMk_MASK 0x00000040 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdMk_SHIFT 6 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: reserved1 [05:05] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved1_MASK 0x00000020 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved1_SHIFT 5 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdQ [04:04] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdQ_MASK 0x00000010 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdQ_SHIFT 4 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdWr [03:03] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdWr_MASK 0x00000008 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdWr_SHIFT 3 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdAct [02:02] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdAct_MASK 0x00000004 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdAct_SHIFT 2 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdReq [01:01] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdReq_MASK 0x00000002 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdReq_SHIFT 1 - -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: Reset [00:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Reset_MASK 0x00000001 -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Reset_SHIFT 0 - -/*************************************************************************** - *REG_CABAC2BINS_END_END_1 - REG_CABAC2BINS_END_END_1 - ***************************************************************************/ -/* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_END_END_1 :: reserved0 [31:00] */ -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_END_END_1_reserved0_MASK 0xffffffff -#define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_END_END_1_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_REG_CABAC2BINS2_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,5254 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_scl_hd.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:18p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:12 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:18p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SCL_HD_H__ -#define BCHP_SCL_HD_H__ - -/*************************************************************************** - *SCL_HD - Video Scaler Registers - ***************************************************************************/ -#define BCHP_SCL_HD_REVISION_ID 0x00540800 /* Scaler Revision register */ -#define BCHP_SCL_HD_TOP_CONTROL 0x00540804 /* Scaler Top Level Control register */ -#define BCHP_SCL_HD_VERT_CONTROL 0x00540808 /* Video Vertical Scaler Control register */ -#define BCHP_SCL_HD_HORIZ_CONTROL 0x0054080c /* Video Horizontal Scaler Control register */ -#define BCHP_SCL_HD_BVB_IN_SIZE 0x00540810 /* BVB Input Picture Size Information */ -#define BCHP_SCL_HD_PIC_OFFSET 0x00540814 /* BVB Input Picture OFFSET Information */ -#define BCHP_SCL_HD_SRC_PIC_SIZE 0x00540818 /* Scaler Source Picture Size Information */ -#define BCHP_SCL_HD_DEST_PIC_SIZE 0x0054081c /* Scaler Destination Picture Size Information */ -#define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN 0x00540820 /* Scaler Source Picture Vertical Pan/Scan Information */ -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET 0x00540824 /* Vertical 8 Taps Poly-Phase Filter Source Picture Offset */ -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP 0x00540828 /* Vertical 8 Taps Poly-Phase Filter Source Picture Stepping Size */ -#define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN 0x0054082c /* Scaler Source Picture Horizontal Pan/Scan Information */ -#define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET 0x00540830 /* Horizontal 16 Taps Poly-Phase Filter Source Picture Luma Offset */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET 0x00540834 /* Horizontal 16 Taps Poly-Phase Filter Source Picture Chroma Offset */ -#define BCHP_SCL_HD_HORIZ_FIR_INIT_PHASE_ACC 0x00540838 /* Horizontal 16 Taps Poly-Phase Filter Initial Phase Accumulate Value */ -#define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP 0x0054083c /* Horizontal Poly-Phase Filter Initial Stepping Size for Region 0 */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA 0x00540840 /* Horizontal Poly-Phase Filter Picture Delta Increment for Region 0 Stepping Size */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA 0x00540844 /* Horizontal Poly-Phase Filter Picture Delta Increment for Region 2 Stepping Size */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END 0x00540848 /* Horizontal Poly-Phase Filter Destination Region 0 Ending Position */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END 0x0054084c /* Horizontal Poly-Phase Filter Destination Region 1 Ending Position */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END 0x00540850 /* Horizontal Poly-Phase Filter Destination Region 2 Ending Position */ -#define BCHP_SCL_HD_ENABLE 0x00540854 /* Video Scaler Enable */ -#define BCHP_SCL_HD_TEST_PORT_CONTROL 0x00540880 /* Testportl control register */ -#define BCHP_SCL_HD_TEST_PORT_DATA 0x00540884 /* Testport data register */ -#define BCHP_SCL_HD_SCRATCH_0 0x00540888 /* Scaler Scratch register 0 */ -#define BCHP_SCL_HD_SCRATCH_1 0x0054088c /* Scaler Scratch register 1 */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR 0x005408a0 /* Scaler Broadcom Video Bus Input Status Clear */ -#define BCHP_SCL_HD_BVB_IN_STATUS 0x005408a4 /* Scaler Broadcom Video Bus Input Status */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01 0x00540900 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03 0x00540904 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05 0x00540908 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07 0x0054090c /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01 0x00540910 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03 0x00540914 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05 0x00540918 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07 0x0054091c /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01 0x00540920 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03 0x00540924 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05 0x00540928 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07 0x0054092c /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01 0x00540930 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03 0x00540934 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05 0x00540938 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07 0x0054093c /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01 0x00540940 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03 0x00540944 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05 0x00540948 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07 0x0054094c /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01 0x00540950 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03 0x00540954 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05 0x00540958 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07 0x0054095c /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01 0x00540960 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03 0x00540964 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05 0x00540968 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07 0x0054096c /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01 0x00540970 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03 0x00540974 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05 0x00540978 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07 0x0054097c /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01 0x00540980 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03 0x00540984 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05 0x00540988 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07 0x0054098c /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01 0x00540990 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03 0x00540994 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05 0x00540998 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07 0x0054099c /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01 0x005409a0 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03 0x005409a4 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05 0x005409a8 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07 0x005409ac /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01 0x005409b0 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03 0x005409b4 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05 0x005409b8 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07 0x005409bc /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01 0x005409c0 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03 0x005409c4 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05 0x005409c8 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07 0x005409cc /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01 0x005409d0 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03 0x005409d4 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05 0x005409d8 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07 0x005409dc /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01 0x005409e0 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03 0x005409e4 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05 0x005409e8 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07 0x005409ec /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01 0x005409f0 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03 0x005409f4 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05 0x005409f8 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07 0x005409fc /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01 0x00540a00 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03 0x00540a04 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05 0x00540a08 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07 0x00540a0c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09 0x00540a10 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11 0x00540a14 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13 0x00540a18 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15 0x00540a1c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01 0x00540a20 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03 0x00540a24 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05 0x00540a28 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07 0x00540a2c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09 0x00540a30 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11 0x00540a34 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13 0x00540a38 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15 0x00540a3c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01 0x00540a40 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03 0x00540a44 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05 0x00540a48 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07 0x00540a4c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09 0x00540a50 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11 0x00540a54 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13 0x00540a58 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15 0x00540a5c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01 0x00540a60 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03 0x00540a64 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05 0x00540a68 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07 0x00540a6c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09 0x00540a70 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11 0x00540a74 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13 0x00540a78 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15 0x00540a7c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01 0x00540a80 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03 0x00540a84 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05 0x00540a88 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07 0x00540a8c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09 0x00540a90 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11 0x00540a94 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13 0x00540a98 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15 0x00540a9c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01 0x00540aa0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03 0x00540aa4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05 0x00540aa8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07 0x00540aac /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09 0x00540ab0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11 0x00540ab4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13 0x00540ab8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15 0x00540abc /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01 0x00540ac0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03 0x00540ac4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05 0x00540ac8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07 0x00540acc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09 0x00540ad0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11 0x00540ad4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13 0x00540ad8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15 0x00540adc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01 0x00540ae0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03 0x00540ae4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05 0x00540ae8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07 0x00540aec /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09 0x00540af0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11 0x00540af4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13 0x00540af8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15 0x00540afc /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Luma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 0x00540b00 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 0x00540b04 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 0x00540b08 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 0x00540b0c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 0x00540b10 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 0x00540b14 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 0x00540b18 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 0x00540b1c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 0x00540b20 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 0x00540b24 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 0x00540b28 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 0x00540b2c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 0x00540b30 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 0x00540b34 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 0x00540b38 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 0x00540b3c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 0x00540b40 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 0x00540b44 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 0x00540b48 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 0x00540b4c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 0x00540b50 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 0x00540b54 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 0x00540b58 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 0x00540b5c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 0x00540b60 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 0x00540b64 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 0x00540b68 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 0x00540b6c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 0x00540b70 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 0x00540b74 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 0x00540b78 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 0x00540b7c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 0x00540b80 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 0x00540b84 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 0x00540b88 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 0x00540b8c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 0x00540b90 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 0x00540b94 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 0x00540b98 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 0x00540b9c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 0x00540ba0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 0x00540ba4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 0x00540ba8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 0x00540bac /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 0x00540bb0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 0x00540bb4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 0x00540bb8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 0x00540bbc /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 0x00540bc0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 0x00540bc4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 0x00540bc8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 0x00540bcc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 0x00540bd0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 0x00540bd4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 0x00540bd8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 0x00540bdc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 0x00540be0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 0x00540be4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 0x00540be8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 0x00540bec /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 0x00540bf0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 0x00540bf4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 0x00540bf8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Chroma Coefficients */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 0x00540bfc /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Chroma Coefficients */ - -/*************************************************************************** - *REVISION_ID - Scaler Revision register - ***************************************************************************/ -/* SCL_HD :: REVISION_ID :: reserved0 [31:16] */ -#define BCHP_SCL_HD_REVISION_ID_reserved0_MASK 0xffff0000 -#define BCHP_SCL_HD_REVISION_ID_reserved0_SHIFT 16 - -/* SCL_HD :: REVISION_ID :: MAJOR [15:08] */ -#define BCHP_SCL_HD_REVISION_ID_MAJOR_MASK 0x0000ff00 -#define BCHP_SCL_HD_REVISION_ID_MAJOR_SHIFT 8 - -/* SCL_HD :: REVISION_ID :: MINOR [07:00] */ -#define BCHP_SCL_HD_REVISION_ID_MINOR_MASK 0x000000ff -#define BCHP_SCL_HD_REVISION_ID_MINOR_SHIFT 0 - -/*************************************************************************** - *TOP_CONTROL - Scaler Top Level Control register - ***************************************************************************/ -/* SCL_HD :: TOP_CONTROL :: reserved0 [31:04] */ -#define BCHP_SCL_HD_TOP_CONTROL_reserved0_MASK 0xfffffff0 -#define BCHP_SCL_HD_TOP_CONTROL_reserved0_SHIFT 4 - -/* SCL_HD :: TOP_CONTROL :: ENABLE_CTRL [03:03] */ -#define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_MASK 0x00000008 -#define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_SHIFT 3 -#define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_ENABLE_BY_PICTURE 1 -#define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_ALWAYS_ENABLE 0 - -/* SCL_HD :: TOP_CONTROL :: UPDATE_SEL [02:02] */ -#define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_MASK 0x00000004 -#define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_SHIFT 2 -#define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_UPDATE_BY_PICTURE 1 -#define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_ALWAYS_UPDATE 0 - -/* SCL_HD :: TOP_CONTROL :: FILTER_ORDER [01:01] */ -#define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_MASK 0x00000002 -#define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_SHIFT 1 -#define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_VERT_FIRST 1 -#define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_HORIZ_FIRST 0 - -/* SCL_HD :: TOP_CONTROL :: reserved1 [00:00] */ -#define BCHP_SCL_HD_TOP_CONTROL_reserved1_MASK 0x00000001 -#define BCHP_SCL_HD_TOP_CONTROL_reserved1_SHIFT 0 - -/*************************************************************************** - *VERT_CONTROL - Video Vertical Scaler Control register - ***************************************************************************/ -/* SCL_HD :: VERT_CONTROL :: reserved0 [31:09] */ -#define BCHP_SCL_HD_VERT_CONTROL_reserved0_MASK 0xfffffe00 -#define BCHP_SCL_HD_VERT_CONTROL_reserved0_SHIFT 9 - -/* SCL_HD :: VERT_CONTROL :: BAVG_BLK_SIZE [08:04] */ -#define BCHP_SCL_HD_VERT_CONTROL_BAVG_BLK_SIZE_MASK 0x000001f0 -#define BCHP_SCL_HD_VERT_CONTROL_BAVG_BLK_SIZE_SHIFT 4 - -/* SCL_HD :: VERT_CONTROL :: reserved1 [03:03] */ -#define BCHP_SCL_HD_VERT_CONTROL_reserved1_MASK 0x00000008 -#define BCHP_SCL_HD_VERT_CONTROL_reserved1_SHIFT 3 - -/* SCL_HD :: VERT_CONTROL :: MODE [02:00] */ -#define BCHP_SCL_HD_VERT_CONTROL_MODE_MASK 0x00000007 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_SHIFT 0 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_BYPASS 0 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_TYPE_1 1 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_FIR4 2 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_TYPE_3 3 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_AV4 4 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_FIR8 5 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_AV8 6 -#define BCHP_SCL_HD_VERT_CONTROL_MODE_TYPE_7 7 - -/*************************************************************************** - *HORIZ_CONTROL - Video Horizontal Scaler Control register - ***************************************************************************/ -/* SCL_HD :: HORIZ_CONTROL :: reserved0 [31:08] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_reserved0_MASK 0xffffff00 -#define BCHP_SCL_HD_HORIZ_CONTROL_reserved0_SHIFT 8 - -/* SCL_HD :: HORIZ_CONTROL :: CHROMA_DERINGING [07:07] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_MASK 0x00000080 -#define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_SHIFT 7 -#define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_ON 1 - -/* SCL_HD :: HORIZ_CONTROL :: LUMA_DERINGING [06:06] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_MASK 0x00000040 -#define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_SHIFT 6 -#define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_ON 1 - -/* SCL_HD :: HORIZ_CONTROL :: MASK_HSCL_LONG_LINE [05:05] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_MASK 0x00000020 -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_SHIFT 5 -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_ON 1 - -/* SCL_HD :: HORIZ_CONTROL :: MASK_HSCL_SHORT_LINE [04:04] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_MASK 0x00000010 -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_SHIFT 4 -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_ON 1 - -/* SCL_HD :: HORIZ_CONTROL :: STALL_DRAIN_ENABLE [03:03] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_MASK 0x00000008 -#define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_SHIFT 3 -#define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_ON 1 - -/* SCL_HD :: HORIZ_CONTROL :: FIR_ENABLE [02:02] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_MASK 0x00000004 -#define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_SHIFT 2 -#define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_ON 1 - -/* SCL_HD :: HORIZ_CONTROL :: HWF1_ENABLE [01:01] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_MASK 0x00000002 -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_SHIFT 1 -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_ON 1 - -/* SCL_HD :: HORIZ_CONTROL :: HWF0_ENABLE [00:00] */ -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_MASK 0x00000001 -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_SHIFT 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_OFF 0 -#define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_ON 1 - -/*************************************************************************** - *BVB_IN_SIZE - BVB Input Picture Size Information - ***************************************************************************/ -/* SCL_HD :: BVB_IN_SIZE :: reserved0 [31:27] */ -#define BCHP_SCL_HD_BVB_IN_SIZE_reserved0_MASK 0xf8000000 -#define BCHP_SCL_HD_BVB_IN_SIZE_reserved0_SHIFT 27 - -/* SCL_HD :: BVB_IN_SIZE :: HSIZE [26:16] */ -#define BCHP_SCL_HD_BVB_IN_SIZE_HSIZE_MASK 0x07ff0000 -#define BCHP_SCL_HD_BVB_IN_SIZE_HSIZE_SHIFT 16 - -/* SCL_HD :: BVB_IN_SIZE :: reserved1 [15:11] */ -#define BCHP_SCL_HD_BVB_IN_SIZE_reserved1_MASK 0x0000f800 -#define BCHP_SCL_HD_BVB_IN_SIZE_reserved1_SHIFT 11 - -/* SCL_HD :: BVB_IN_SIZE :: VSIZE [10:00] */ -#define BCHP_SCL_HD_BVB_IN_SIZE_VSIZE_MASK 0x000007ff -#define BCHP_SCL_HD_BVB_IN_SIZE_VSIZE_SHIFT 0 - -/*************************************************************************** - *PIC_OFFSET - BVB Input Picture OFFSET Information - ***************************************************************************/ -/* SCL_HD :: PIC_OFFSET :: reserved0 [31:27] */ -#define BCHP_SCL_HD_PIC_OFFSET_reserved0_MASK 0xf8000000 -#define BCHP_SCL_HD_PIC_OFFSET_reserved0_SHIFT 27 - -/* SCL_HD :: PIC_OFFSET :: HSIZE [26:16] */ -#define BCHP_SCL_HD_PIC_OFFSET_HSIZE_MASK 0x07ff0000 -#define BCHP_SCL_HD_PIC_OFFSET_HSIZE_SHIFT 16 - -/* SCL_HD :: PIC_OFFSET :: reserved1 [15:11] */ -#define BCHP_SCL_HD_PIC_OFFSET_reserved1_MASK 0x0000f800 -#define BCHP_SCL_HD_PIC_OFFSET_reserved1_SHIFT 11 - -/* SCL_HD :: PIC_OFFSET :: VSIZE [10:00] */ -#define BCHP_SCL_HD_PIC_OFFSET_VSIZE_MASK 0x000007ff -#define BCHP_SCL_HD_PIC_OFFSET_VSIZE_SHIFT 0 - -/*************************************************************************** - *SRC_PIC_SIZE - Scaler Source Picture Size Information - ***************************************************************************/ -/* SCL_HD :: SRC_PIC_SIZE :: reserved0 [31:27] */ -#define BCHP_SCL_HD_SRC_PIC_SIZE_reserved0_MASK 0xf8000000 -#define BCHP_SCL_HD_SRC_PIC_SIZE_reserved0_SHIFT 27 - -/* SCL_HD :: SRC_PIC_SIZE :: HSIZE [26:16] */ -#define BCHP_SCL_HD_SRC_PIC_SIZE_HSIZE_MASK 0x07ff0000 -#define BCHP_SCL_HD_SRC_PIC_SIZE_HSIZE_SHIFT 16 - -/* SCL_HD :: SRC_PIC_SIZE :: reserved1 [15:11] */ -#define BCHP_SCL_HD_SRC_PIC_SIZE_reserved1_MASK 0x0000f800 -#define BCHP_SCL_HD_SRC_PIC_SIZE_reserved1_SHIFT 11 - -/* SCL_HD :: SRC_PIC_SIZE :: VSIZE [10:00] */ -#define BCHP_SCL_HD_SRC_PIC_SIZE_VSIZE_MASK 0x000007ff -#define BCHP_SCL_HD_SRC_PIC_SIZE_VSIZE_SHIFT 0 - -/*************************************************************************** - *DEST_PIC_SIZE - Scaler Destination Picture Size Information - ***************************************************************************/ -/* SCL_HD :: DEST_PIC_SIZE :: reserved0 [31:27] */ -#define BCHP_SCL_HD_DEST_PIC_SIZE_reserved0_MASK 0xf8000000 -#define BCHP_SCL_HD_DEST_PIC_SIZE_reserved0_SHIFT 27 - -/* SCL_HD :: DEST_PIC_SIZE :: HSIZE [26:16] */ -#define BCHP_SCL_HD_DEST_PIC_SIZE_HSIZE_MASK 0x07ff0000 -#define BCHP_SCL_HD_DEST_PIC_SIZE_HSIZE_SHIFT 16 - -/* SCL_HD :: DEST_PIC_SIZE :: reserved1 [15:11] */ -#define BCHP_SCL_HD_DEST_PIC_SIZE_reserved1_MASK 0x0000f800 -#define BCHP_SCL_HD_DEST_PIC_SIZE_reserved1_SHIFT 11 - -/* SCL_HD :: DEST_PIC_SIZE :: VSIZE [10:00] */ -#define BCHP_SCL_HD_DEST_PIC_SIZE_VSIZE_MASK 0x000007ff -#define BCHP_SCL_HD_DEST_PIC_SIZE_VSIZE_SHIFT 0 - -/*************************************************************************** - *SRC_PIC_VERT_PAN_SCAN - Scaler Source Picture Vertical Pan/Scan Information - ***************************************************************************/ -/* SCL_HD :: SRC_PIC_VERT_PAN_SCAN :: reserved0 [31:22] */ -#define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved0_MASK 0xffc00000 -#define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved0_SHIFT 22 - -/* SCL_HD :: SRC_PIC_VERT_PAN_SCAN :: OFFSET [21:16] */ -#define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_OFFSET_MASK 0x003f0000 -#define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_OFFSET_SHIFT 16 - -/* SCL_HD :: SRC_PIC_VERT_PAN_SCAN :: reserved1 [15:00] */ -#define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved1_MASK 0x0000ffff -#define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved1_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_SRC_PIC_OFFSET - Vertical 8 Taps Poly-Phase Filter Source Picture Offset - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_SRC_PIC_OFFSET :: VALUE [31:03] */ -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_VALUE_MASK 0xfffffff8 -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_VALUE_SHIFT 3 - -/* SCL_HD :: VERT_FIR_SRC_PIC_OFFSET :: reserved0 [02:00] */ -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_reserved0_MASK 0x00000007 -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_reserved0_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_SRC_PIC_STEP - Vertical 8 Taps Poly-Phase Filter Source Picture Stepping Size - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_SRC_PIC_STEP :: reserved0 [31:26] */ -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved0_MASK 0xfc000000 -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved0_SHIFT 26 - -/* SCL_HD :: VERT_FIR_SRC_PIC_STEP :: SIZE [25:03] */ -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_SIZE_MASK 0x03fffff8 -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_SIZE_SHIFT 3 - -/* SCL_HD :: VERT_FIR_SRC_PIC_STEP :: reserved1 [02:00] */ -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved1_MASK 0x00000007 -#define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved1_SHIFT 0 - -/*************************************************************************** - *SRC_PIC_HORIZ_PAN_SCAN - Scaler Source Picture Horizontal Pan/Scan Information - ***************************************************************************/ -/* SCL_HD :: SRC_PIC_HORIZ_PAN_SCAN :: reserved0 [31:21] */ -#define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved0_MASK 0xffe00000 -#define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved0_SHIFT 21 - -/* SCL_HD :: SRC_PIC_HORIZ_PAN_SCAN :: OFFSET [20:14] */ -#define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_OFFSET_MASK 0x001fc000 -#define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_OFFSET_SHIFT 14 - -/* SCL_HD :: SRC_PIC_HORIZ_PAN_SCAN :: reserved1 [13:00] */ -#define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved1_MASK 0x00003fff -#define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved1_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_LUMA_SRC_PIC_OFFSET - Horizontal 16 Taps Poly-Phase Filter Source Picture Luma Offset - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_LUMA_SRC_PIC_OFFSET :: VALUE [31:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_VALUE_MASK 0xffffc000 -#define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_VALUE_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_LUMA_SRC_PIC_OFFSET :: reserved0 [13:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_reserved0_MASK 0x00003fff -#define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_reserved0_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_SRC_PIC_OFFSET - Horizontal 16 Taps Poly-Phase Filter Source Picture Chroma Offset - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_SRC_PIC_OFFSET :: VALUE [31:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_VALUE_MASK 0xffffc000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_VALUE_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_SRC_PIC_OFFSET :: reserved0 [13:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_reserved0_MASK 0x00003fff -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_reserved0_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_INIT_PHASE_ACC - Horizontal 16 Taps Poly-Phase Filter Initial Phase Accumulate Value - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_INIT_PHASE_ACC :: SIZE [31:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_INIT_PHASE_ACC_SIZE_MASK 0xffffffff -#define BCHP_SCL_HD_HORIZ_FIR_INIT_PHASE_ACC_SIZE_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_INIT_STEP - Horizontal Poly-Phase Filter Initial Stepping Size for Region 0 - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_INIT_STEP :: reserved0 [31:31] */ -#define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_reserved0_MASK 0x80000000 -#define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_reserved0_SHIFT 31 - -/* SCL_HD :: HORIZ_FIR_INIT_STEP :: SIZE [30:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_SIZE_MASK 0x7fffffff -#define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_SIZE_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA - Horizontal Poly-Phase Filter Picture Delta Increment for Region 0 Stepping Size - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA :: SIZE [29:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_SIZE_MASK 0x3ffffffc -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_SIZE_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA :: reserved1 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved1_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved1_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA - Horizontal Poly-Phase Filter Picture Delta Increment for Region 2 Stepping Size - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA :: SIZE [29:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_SIZE_MASK 0x3ffffffc -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_SIZE_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA :: reserved1 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved1_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved1_SHIFT 0 - -/*************************************************************************** - *HORIZ_DEST_PIC_REGION_0_END - Horizontal Poly-Phase Filter Destination Region 0 Ending Position - ***************************************************************************/ -/* SCL_HD :: HORIZ_DEST_PIC_REGION_0_END :: reserved0 [31:27] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved0_MASK 0xf8000000 -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved0_SHIFT 27 - -/* SCL_HD :: HORIZ_DEST_PIC_REGION_0_END :: POSITION [26:16] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_POSITION_MASK 0x07ff0000 -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_POSITION_SHIFT 16 - -/* SCL_HD :: HORIZ_DEST_PIC_REGION_0_END :: reserved1 [15:00] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved1_MASK 0x0000ffff -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved1_SHIFT 0 - -/*************************************************************************** - *HORIZ_DEST_PIC_REGION_1_END - Horizontal Poly-Phase Filter Destination Region 1 Ending Position - ***************************************************************************/ -/* SCL_HD :: HORIZ_DEST_PIC_REGION_1_END :: reserved0 [31:27] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved0_MASK 0xf8000000 -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved0_SHIFT 27 - -/* SCL_HD :: HORIZ_DEST_PIC_REGION_1_END :: POSITION [26:16] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_POSITION_MASK 0x07ff0000 -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_POSITION_SHIFT 16 - -/* SCL_HD :: HORIZ_DEST_PIC_REGION_1_END :: reserved1 [15:00] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved1_MASK 0x0000ffff -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved1_SHIFT 0 - -/*************************************************************************** - *HORIZ_DEST_PIC_REGION_2_END - Horizontal Poly-Phase Filter Destination Region 2 Ending Position - ***************************************************************************/ -/* SCL_HD :: HORIZ_DEST_PIC_REGION_2_END :: reserved0 [31:27] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved0_MASK 0xf8000000 -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved0_SHIFT 27 - -/* SCL_HD :: HORIZ_DEST_PIC_REGION_2_END :: POSITION [26:16] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_POSITION_MASK 0x07ff0000 -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_POSITION_SHIFT 16 - -/* SCL_HD :: HORIZ_DEST_PIC_REGION_2_END :: reserved1 [15:00] */ -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved1_MASK 0x0000ffff -#define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved1_SHIFT 0 - -/*************************************************************************** - *ENABLE - Video Scaler Enable - ***************************************************************************/ -/* SCL_HD :: ENABLE :: reserved0 [31:01] */ -#define BCHP_SCL_HD_ENABLE_reserved0_MASK 0xfffffffe -#define BCHP_SCL_HD_ENABLE_reserved0_SHIFT 1 - -/* SCL_HD :: ENABLE :: SCALER_ENABLE [00:00] */ -#define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_MASK 0x00000001 -#define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_SHIFT 0 -#define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_OFF 0 -#define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_ON 1 - -/*************************************************************************** - *TEST_PORT_CONTROL - Testportl control register - ***************************************************************************/ -/* SCL_HD :: TEST_PORT_CONTROL :: reserved0 [31:02] */ -#define BCHP_SCL_HD_TEST_PORT_CONTROL_reserved0_MASK 0xfffffffc -#define BCHP_SCL_HD_TEST_PORT_CONTROL_reserved0_SHIFT 2 - -/* SCL_HD :: TEST_PORT_CONTROL :: TP_ADDR [01:00] */ -#define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_MASK 0x00000003 -#define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SHIFT 0 -#define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_0 0 -#define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_1 1 -#define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_2 2 -#define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_3 3 - -/*************************************************************************** - *TEST_PORT_DATA - Testport data register - ***************************************************************************/ -/* union - case SCL_0 [31:00] */ -/* SCL_HD :: TEST_PORT_DATA :: SCL_0 :: PPF_DBG [31:10] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_PPF_DBG_MASK 0xfffffc00 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_PPF_DBG_SHIFT 10 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_0 :: HWF_DBG [09:00] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_HWF_DBG_MASK 0x000003ff -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_HWF_DBG_SHIFT 0 - -/* union - case SCL_1 [31:00] */ -/* SCL_HD :: TEST_PORT_DATA :: SCL_1 :: RE_ORDER_LINE_ADDR [31:20] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_RE_ORDER_LINE_ADDR_MASK 0xfff00000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_RE_ORDER_LINE_ADDR_SHIFT 20 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_1 :: LB_RD_STATUS [19:12] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_STATUS_MASK 0x000ff000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_STATUS_SHIFT 12 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_1 :: LB_RD_LINE_ADDR [11:00] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_LINE_ADDR_MASK 0x00000fff -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_LINE_ADDR_SHIFT 0 - -/* union - case SCL_2 [31:00] */ -/* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_WR_STATUS_1 [31:27] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_1_MASK 0xf8000000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_1_SHIFT 27 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_WR_LINE_ADDR [26:16] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_LINE_ADDR_MASK 0x07ff0000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_LINE_ADDR_SHIFT 16 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_WR_STATUS_0 [15:12] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_0_MASK 0x0000f000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_0_SHIFT 12 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_RD_LINE_ADDR [11:00] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_RD_LINE_ADDR_MASK 0x00000fff -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_RD_LINE_ADDR_SHIFT 0 - -/* union - case SCL_3 [31:00] */ -/* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: HSCL_BVB_IN_STATUS [31:26] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_HSCL_BVB_IN_STATUS_MASK 0xfc000000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_HSCL_BVB_IN_STATUS_SHIFT 26 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: VSCL_BVB_IN_STATUS [25:20] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_VSCL_BVB_IN_STATUS_MASK 0x03f00000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_VSCL_BVB_IN_STATUS_SHIFT 20 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: TOP_CTRL_STATUS [19:17] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TOP_CTRL_STATUS_MASK 0x000e0000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TOP_CTRL_STATUS_SHIFT 17 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: OB_RD_STATUS [16:15] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_OB_RD_STATUS_MASK 0x00018000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_OB_RD_STATUS_SHIFT 15 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: TIME_CTRL_STATUS [14:12] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TIME_CTRL_STATUS_MASK 0x00007000 -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TIME_CTRL_STATUS_SHIFT 12 - -/* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: FIR_LINE_ADDR [11:00] */ -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_FIR_LINE_ADDR_MASK 0x00000fff -#define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_FIR_LINE_ADDR_SHIFT 0 - -/*************************************************************************** - *SCRATCH_0 - Scaler Scratch register 0 - ***************************************************************************/ -/* SCL_HD :: SCRATCH_0 :: VALUE [31:00] */ -#define BCHP_SCL_HD_SCRATCH_0_VALUE_MASK 0xffffffff -#define BCHP_SCL_HD_SCRATCH_0_VALUE_SHIFT 0 - -/*************************************************************************** - *SCRATCH_1 - Scaler Scratch register 1 - ***************************************************************************/ -/* SCL_HD :: SCRATCH_1 :: VALUE [31:00] */ -#define BCHP_SCL_HD_SCRATCH_1_VALUE_MASK 0xffffffff -#define BCHP_SCL_HD_SCRATCH_1_VALUE_SHIFT 0 - -/*************************************************************************** - *BVB_IN_STATUS_CLEAR - Scaler Broadcom Video Bus Input Status Clear - ***************************************************************************/ -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: reserved0 [31:08] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_reserved0_MASK 0xffffff00 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_reserved0_SHIFT 8 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: ENABLE_ERROR [07:07] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_ENABLE_ERROR_MASK 0x00000080 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_ENABLE_ERROR_SHIFT 7 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: HSCL_LONG_LINE [06:06] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_LONG_LINE_MASK 0x00000040 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_LONG_LINE_SHIFT 6 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: HSCL_SHORT_LINE [05:05] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_SHORT_LINE_MASK 0x00000020 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_SHORT_LINE_SHIFT 5 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: MISSING_SYNC [04:04] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_MISSING_SYNC_MASK 0x00000010 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_MISSING_SYNC_SHIFT 4 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: LONG_SOURCE [03:03] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_SOURCE_MASK 0x00000008 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_SOURCE_SHIFT 3 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: SHORT_SOURCE [02:02] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_MASK 0x00000004 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_SHIFT 2 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: LONG_LINE [01:01] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_LINE_MASK 0x00000002 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_LINE_SHIFT 1 - -/* SCL_HD :: BVB_IN_STATUS_CLEAR :: SHORT_LINE [00:00] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_LINE_MASK 0x00000001 -#define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_LINE_SHIFT 0 - -/*************************************************************************** - *BVB_IN_STATUS - Scaler Broadcom Video Bus Input Status - ***************************************************************************/ -/* SCL_HD :: BVB_IN_STATUS :: reserved0 [31:08] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_SCL_HD_BVB_IN_STATUS_reserved0_SHIFT 8 - -/* SCL_HD :: BVB_IN_STATUS :: ENABLE_ERROR [07:07] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_ENABLE_ERROR_MASK 0x00000080 -#define BCHP_SCL_HD_BVB_IN_STATUS_ENABLE_ERROR_SHIFT 7 - -/* SCL_HD :: BVB_IN_STATUS :: HSCL_LONG_LINE [06:06] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_LONG_LINE_MASK 0x00000040 -#define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_LONG_LINE_SHIFT 6 - -/* SCL_HD :: BVB_IN_STATUS :: HSCL_SHORT_LINE [05:05] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_SHORT_LINE_MASK 0x00000020 -#define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_SHORT_LINE_SHIFT 5 - -/* SCL_HD :: BVB_IN_STATUS :: MISSING_SYNC [04:04] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_MISSING_SYNC_MASK 0x00000010 -#define BCHP_SCL_HD_BVB_IN_STATUS_MISSING_SYNC_SHIFT 4 - -/* SCL_HD :: BVB_IN_STATUS :: LONG_SOURCE [03:03] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_LONG_SOURCE_MASK 0x00000008 -#define BCHP_SCL_HD_BVB_IN_STATUS_LONG_SOURCE_SHIFT 3 - -/* SCL_HD :: BVB_IN_STATUS :: SHORT_SOURCE [02:02] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_SOURCE_MASK 0x00000004 -#define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_SOURCE_SHIFT 2 - -/* SCL_HD :: BVB_IN_STATUS :: LONG_LINE [01:01] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_LONG_LINE_MASK 0x00000002 -#define BCHP_SCL_HD_BVB_IN_STATUS_LONG_LINE_SHIFT 1 - -/* SCL_HD :: BVB_IN_STATUS :: SHORT_LINE [00:00] */ -#define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_LINE_MASK 0x00000001 -#define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_LINE_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE0_00_01 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE0_02_03 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE0_04_05 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE0_06_07 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE1_00_01 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE1_02_03 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE1_04_05 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE1_06_07 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE2_00_01 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE2_02_03 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE2_04_05 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE2_06_07 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE3_00_01 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE3_02_03 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE3_04_05 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE3_06_07 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE4_00_01 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE4_02_03 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE4_04_05 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE4_06_07 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE5_00_01 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE5_02_03 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE5_04_05 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE5_06_07 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE6_00_01 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE6_02_03 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE6_04_05 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE6_06_07 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE7_00_01 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE7_02_03 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE7_04_05 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_COEFF_PHASE7_06_07 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE0_00_01 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE0_02_03 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE0_04_05 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE0_06_07 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE1_00_01 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE1_02_03 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE1_04_05 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE1_06_07 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE2_00_01 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE2_02_03 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE2_04_05 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE2_06_07 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE3_00_01 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE3_02_03 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE3_04_05 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE3_06_07 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE4_00_01 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE4_02_03 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE4_04_05 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE4_06_07 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE5_00_01 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE5_02_03 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE5_04_05 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE5_06_07 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE6_00_01 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE6_02_03 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE6_04_05 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE6_06_07 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE7_00_01 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE7_02_03 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE7_04_05 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *VERT_FIR_CHROMA_COEFF_PHASE7_06_07 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_00_01 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_02_03 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_04_05 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_06_07 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_08_09 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_10_11 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_12_13 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE0_14_15 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_00_01 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_02_03 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_04_05 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_06_07 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_08_09 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_10_11 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_12_13 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE1_14_15 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_00_01 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_02_03 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_04_05 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_06_07 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_08_09 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_10_11 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_12_13 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE2_14_15 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_00_01 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_02_03 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_04_05 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_06_07 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_08_09 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_10_11 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_12_13 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE3_14_15 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_00_01 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_02_03 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_04_05 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_06_07 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_08_09 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_10_11 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_12_13 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE4_14_15 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_00_01 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_02_03 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_04_05 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_06_07 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_08_09 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_10_11 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_12_13 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE5_14_15 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_00_01 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_02_03 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_04_05 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_06_07 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_08_09 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_10_11 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_12_13 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE6_14_15 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_00_01 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_02_03 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_04_05 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_06_07 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_08_09 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_10_11 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_12_13 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_COEFF_PHASE7_14_15 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Luma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: COEFF_8 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_8_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_8_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: COEFF_9 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_9_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_9_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: COEFF_10 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_10_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_10_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: COEFF_11 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_11_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_11_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: COEFF_12 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_12_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_12_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: COEFF_13 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_13_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_13_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved2_SHIFT 0 - -/*************************************************************************** - *HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Chroma Coefficients - ***************************************************************************/ -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: reserved0 [31:30] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved0_MASK 0xc0000000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved0_SHIFT 30 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: COEFF_14 [29:18] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_14_MASK 0x3ffc0000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_14_SHIFT 18 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: reserved1 [17:14] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved1_MASK 0x0003c000 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved1_SHIFT 14 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: COEFF_15 [13:02] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_15_MASK 0x00003ffc -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_15_SHIFT 2 - -/* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: reserved2 [01:00] */ -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved2_MASK 0x00000003 -#define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved2_SHIFT 0 - -#endif /* #ifndef BCHP_SCL_HD_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,314 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_scrub_ctrl.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:18p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:19 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:18p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SCRUB_CTRL_H__ -#define BCHP_SCRUB_CTRL_H__ - -/*************************************************************************** - *SCRUB_CTRL - Scrub Control Registers - ***************************************************************************/ -#define BCHP_SCRUB_CTRL_SCRUB_ENABLE 0x000f6000 /* Secure Sequencer Enable */ -#define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS 0x000f6004 /* ARM Bridge Out-of-Range Checker End Address */ -#define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS 0x000f6008 /* Static ARCH End Address */ -#define BCHP_SCRUB_CTRL_BI_CMAC_31_0 0x000f600c /* Boot Image CMAC value[31:0] */ -#define BCHP_SCRUB_CTRL_BI_CMAC_63_32 0x000f6010 /* Boot Image CMAC value[63:32] */ -#define BCHP_SCRUB_CTRL_BI_CMAC_95_64 0x000f6014 /* Boot Image CMAC value[95:64] */ -#define BCHP_SCRUB_CTRL_BI_CMAC_127_96 0x000f6018 /* Boot Image CMAC value[127:96] */ -#define BCHP_SCRUB_CTRL_SCRUB_STATUS 0x000f601c /* Secure Data Scrubber Status Register */ -#define BCHP_SCRUB_CTRL_CR 0x000f6024 /* CR Word Register */ -#define BCHP_SCRUB_CTRL_ECC_DONE 0x000f6030 /* OTP ECC Done Register */ -#define BCHP_SCRUB_CTRL_ECC_FAULT 0x000f6034 /* OTP ECC Fault Register */ -#define BCHP_SCRUB_CTRL_ECC_FAIL 0x000f6038 /* OTP ECC Fail Register */ -#define BCHP_SCRUB_CTRL_KEY0_31_0 0x000f603c /* Key0 [31:0] */ -#define BCHP_SCRUB_CTRL_KEY0_63_32 0x000f6040 /* Key0 [63:32] */ -#define BCHP_SCRUB_CTRL_KEY0_95_64 0x000f6044 /* Key0 [95:64] */ -#define BCHP_SCRUB_CTRL_KEY0_127_96 0x000f6048 /* Key0 [127:96] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_31_0 0x000f604c /* Key0 Post scramble [31:0] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_63_32 0x000f6050 /* Key0 Post scramble [63:32] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_95_64 0x000f6054 /* Key0 Post scramble [95:64] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_127_96 0x000f6058 /* Key0 Post scramble [127:96] */ -#define BCHP_SCRUB_CTRL_KEY1_31_0 0x000f605c /* Key1 [31:0] */ -#define BCHP_SCRUB_CTRL_KEY1_63_32 0x000f6060 /* Key1 [63:32] */ -#define BCHP_SCRUB_CTRL_KEY1_95_64 0x000f6064 /* Key1 [95:64] */ -#define BCHP_SCRUB_CTRL_KEY1_127_96 0x000f6068 /* Key1 [127:96] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_31_0 0x000f606c /* Key1 Post scramble [31:0] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_63_32 0x000f6070 /* Key1 Post scramble [63:32] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_95_64 0x000f6074 /* Key1 Post scramble [95:64] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_127_96 0x000f6078 /* Key1 Post scramble [127:96] */ - -/*************************************************************************** - *SCRUB_ENABLE - Secure Sequencer Enable - ***************************************************************************/ -/* SCRUB_CTRL :: SCRUB_ENABLE :: reserved0 [31:02] */ -#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_reserved0_MASK 0xfffffffc -#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_reserved0_SHIFT 2 - -/* SCRUB_CTRL :: SCRUB_ENABLE :: DSCRAM_EN [01:01] */ -#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_MASK 0x00000002 -#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_SHIFT 1 - -/* SCRUB_CTRL :: SCRUB_ENABLE :: SCRUB_EN [00:00] */ -#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_MASK 0x00000001 -#define BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_SHIFT 0 - -/*************************************************************************** - *BORCH_END_ADDRESS - ARM Bridge Out-of-Range Checker End Address - ***************************************************************************/ -/* SCRUB_CTRL :: BORCH_END_ADDRESS :: reserved0 [31:27] */ -#define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_reserved0_MASK 0xf8000000 -#define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_reserved0_SHIFT 27 - -/* SCRUB_CTRL :: BORCH_END_ADDRESS :: BORCH_END_ADDR [26:00] */ -#define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK 0x07ffffff -#define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_SHIFT 0 - -/*************************************************************************** - *STARCH_END_ADDRESS - Static ARCH End Address - ***************************************************************************/ -/* SCRUB_CTRL :: STARCH_END_ADDRESS :: reserved0 [31:27] */ -#define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_reserved0_MASK 0xf8000000 -#define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_reserved0_SHIFT 27 - -/* SCRUB_CTRL :: STARCH_END_ADDRESS :: STARCH_END_ADDR [26:00] */ -#define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_STARCH_END_ADDR_MASK 0x07ffffff -#define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_STARCH_END_ADDR_SHIFT 0 - -/*************************************************************************** - *BI_CMAC_31_0 - Boot Image CMAC value[31:0] - ***************************************************************************/ -/* SCRUB_CTRL :: BI_CMAC_31_0 :: CMAC_WORD [31:00] */ -#define BCHP_SCRUB_CTRL_BI_CMAC_31_0_CMAC_WORD_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_BI_CMAC_31_0_CMAC_WORD_SHIFT 0 - -/*************************************************************************** - *BI_CMAC_63_32 - Boot Image CMAC value[63:32] - ***************************************************************************/ -/* SCRUB_CTRL :: BI_CMAC_63_32 :: CMAC_WORD [31:00] */ -#define BCHP_SCRUB_CTRL_BI_CMAC_63_32_CMAC_WORD_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_BI_CMAC_63_32_CMAC_WORD_SHIFT 0 - -/*************************************************************************** - *BI_CMAC_95_64 - Boot Image CMAC value[95:64] - ***************************************************************************/ -/* SCRUB_CTRL :: BI_CMAC_95_64 :: CMAC_WORD [31:00] */ -#define BCHP_SCRUB_CTRL_BI_CMAC_95_64_CMAC_WORD_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_BI_CMAC_95_64_CMAC_WORD_SHIFT 0 - -/*************************************************************************** - *BI_CMAC_127_96 - Boot Image CMAC value[127:96] - ***************************************************************************/ -/* SCRUB_CTRL :: BI_CMAC_127_96 :: CMAC_WORD [31:00] */ -#define BCHP_SCRUB_CTRL_BI_CMAC_127_96_CMAC_WORD_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_BI_CMAC_127_96_CMAC_WORD_SHIFT 0 - -/*************************************************************************** - *SCRUB_STATUS - Secure Data Scrubber Status Register - ***************************************************************************/ -/* SCRUB_CTRL :: SCRUB_STATUS :: reserved0 [31:04] */ -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_reserved0_SHIFT 4 - -/* SCRUB_CTRL :: SCRUB_STATUS :: CMAC_WORDS_SWAPPED [03:03] */ -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_CMAC_WORDS_SWAPPED_MASK 0x00000008 -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_CMAC_WORDS_SWAPPED_SHIFT 3 - -/* SCRUB_CTRL :: SCRUB_STATUS :: SHARF_REG_RD_FAIL [02:02] */ -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_SHARF_REG_RD_FAIL_MASK 0x00000004 -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_SHARF_REG_RD_FAIL_SHIFT 2 - -/* SCRUB_CTRL :: SCRUB_STATUS :: SCRUB_BUSY [01:01] */ -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRUB_BUSY_MASK 0x00000002 -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRUB_BUSY_SHIFT 1 - -/* SCRUB_CTRL :: SCRUB_STATUS :: SCRAM_KEY_BUSY [00:00] */ -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRAM_KEY_BUSY_MASK 0x00000001 -#define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRAM_KEY_BUSY_SHIFT 0 - -/*************************************************************************** - *CR - CR Word Register - ***************************************************************************/ -/* SCRUB_CTRL :: CR :: CR_WORD [31:00] */ -#define BCHP_SCRUB_CTRL_CR_CR_WORD_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_CR_CR_WORD_SHIFT 0 - -/*************************************************************************** - *ECC_DONE - OTP ECC Done Register - ***************************************************************************/ -/* SCRUB_CTRL :: ECC_DONE :: ECC_STATUS [31:00] */ -#define BCHP_SCRUB_CTRL_ECC_DONE_ECC_STATUS_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_ECC_DONE_ECC_STATUS_SHIFT 0 - -/*************************************************************************** - *ECC_FAULT - OTP ECC Fault Register - ***************************************************************************/ -/* SCRUB_CTRL :: ECC_FAULT :: ECC_STATUS [31:00] */ -#define BCHP_SCRUB_CTRL_ECC_FAULT_ECC_STATUS_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_ECC_FAULT_ECC_STATUS_SHIFT 0 - -/*************************************************************************** - *ECC_FAIL - OTP ECC Fail Register - ***************************************************************************/ -/* SCRUB_CTRL :: ECC_FAIL :: ECC_STATUS [31:00] */ -#define BCHP_SCRUB_CTRL_ECC_FAIL_ECC_STATUS_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_ECC_FAIL_ECC_STATUS_SHIFT 0 - -/*************************************************************************** - *KEY0_31_0 - Key0 [31:0] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_31_0 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_31_0_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_31_0_KEY_SHIFT 0 - -/*************************************************************************** - *KEY0_63_32 - Key0 [63:32] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_63_32 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_63_32_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_63_32_KEY_SHIFT 0 - -/*************************************************************************** - *KEY0_95_64 - Key0 [95:64] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_95_64 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_95_64_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_95_64_KEY_SHIFT 0 - -/*************************************************************************** - *KEY0_127_96 - Key0 [127:96] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_127_96 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_127_96_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_127_96_KEY_SHIFT 0 - -/*************************************************************************** - *KEY0_PS_31_0 - Key0 Post scramble [31:0] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_PS_31_0 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_31_0_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_PS_31_0_KEY_SHIFT 0 - -/*************************************************************************** - *KEY0_PS_63_32 - Key0 Post scramble [63:32] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_PS_63_32 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_63_32_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_PS_63_32_KEY_SHIFT 0 - -/*************************************************************************** - *KEY0_PS_95_64 - Key0 Post scramble [95:64] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_PS_95_64 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_95_64_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_PS_95_64_KEY_SHIFT 0 - -/*************************************************************************** - *KEY0_PS_127_96 - Key0 Post scramble [127:96] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY0_PS_127_96 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY0_PS_127_96_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY0_PS_127_96_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_31_0 - Key1 [31:0] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_31_0 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_31_0_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_31_0_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_63_32 - Key1 [63:32] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_63_32 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_63_32_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_63_32_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_95_64 - Key1 [95:64] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_95_64 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_95_64_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_95_64_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_127_96 - Key1 [127:96] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_127_96 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_127_96_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_127_96_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_PS_31_0 - Key1 Post scramble [31:0] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_PS_31_0 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_31_0_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_PS_31_0_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_PS_63_32 - Key1 Post scramble [63:32] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_PS_63_32 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_63_32_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_PS_63_32_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_PS_95_64 - Key1 Post scramble [95:64] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_PS_95_64 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_95_64_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_PS_95_64_KEY_SHIFT 0 - -/*************************************************************************** - *KEY1_PS_127_96 - Key1 Post scramble [127:96] - ***************************************************************************/ -/* SCRUB_CTRL :: KEY1_PS_127_96 :: KEY [31:00] */ -#define BCHP_SCRUB_CTRL_KEY1_PS_127_96_KEY_MASK 0xffffffff -#define BCHP_SCRUB_CTRL_KEY1_PS_127_96_KEY_SHIFT 0 - -#endif /* #ifndef BCHP_SCRUB_CTRL_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sentinel.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sentinel.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sentinel.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sentinel.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sentinel.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:18p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:38 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sentinel.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:18p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SENTINEL_H__ -#define BCHP_SENTINEL_H__ - -/*************************************************************************** - *SENTINEL - Sentinal - ***************************************************************************/ -#define BCHP_SENTINEL_SENTINEL_ADDR_START 0x00410000 /* Sentinel Start Address */ -#define BCHP_SENTINEL_SENTINEL_ADDR_END 0x00413ffc /* Sentinel Start Address */ - -/*************************************************************************** - *SENTINEL_ADDR_START - Sentinel Start Address - ***************************************************************************/ -/* SENTINEL :: SENTINEL_ADDR_START :: ADDRESS [31:00] */ -#define BCHP_SENTINEL_SENTINEL_ADDR_START_ADDRESS_MASK 0xffffffff -#define BCHP_SENTINEL_SENTINEL_ADDR_START_ADDRESS_SHIFT 0 - -/*************************************************************************** - *SENTINEL_ADDR_END - Sentinel Start Address - ***************************************************************************/ -/* SENTINEL :: SENTINEL_ADDR_END :: ADDRESS [31:00] */ -#define BCHP_SENTINEL_SENTINEL_ADDR_END_ADDRESS_MASK 0xffffffff -#define BCHP_SENTINEL_SENTINEL_ADDR_END_ADDRESS_SHIFT 0 - -#endif /* #ifndef BCHP_SENTINEL_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_mem_dma0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_mem_dma0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_mem_dma0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_mem_dma0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,138 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sharf_mem_dma0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:19p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:19 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_mem_dma0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:19p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SHARF_MEM_DMA0_H__ -#define BCHP_SHARF_MEM_DMA0_H__ - -/*************************************************************************** - *SHARF_MEM_DMA0 - SHARF_MEM_DMA Channel 0 Registers - ***************************************************************************/ -#define BCHP_SHARF_MEM_DMA0_FIRST_DESC 0x000f4100 /* SHARF_MEM_DMA First Descriptor Address Register */ -#define BCHP_SHARF_MEM_DMA0_CTRL 0x000f4104 /* SHARF_MEM_DMA Control Register */ -#define BCHP_SHARF_MEM_DMA0_WAKE_CTRL 0x000f4108 /* SHARF_MEM_DMA Wake Control Register */ -#define BCHP_SHARF_MEM_DMA0_STATUS 0x000f4110 /* SHARF_MEM_DMA Status Register */ -#define BCHP_SHARF_MEM_DMA0_CUR_DESC 0x000f4114 /* SHARF_MEM_DMA Current Descriptor Address Register */ -#define BCHP_SHARF_MEM_DMA0_CUR_BYTE 0x000f4118 /* SHARF_MEM_DMA Current Byte Count Register */ -#define BCHP_SHARF_MEM_DMA0_SCRATCH 0x000f411c /* SHARF_MEM_DMA Scratch Register */ - -/*************************************************************************** - *FIRST_DESC - SHARF_MEM_DMA First Descriptor Address Register - ***************************************************************************/ -/* SHARF_MEM_DMA0 :: FIRST_DESC :: ADDR [31:00] */ -#define BCHP_SHARF_MEM_DMA0_FIRST_DESC_ADDR_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA0_FIRST_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *CTRL - SHARF_MEM_DMA Control Register - ***************************************************************************/ -/* SHARF_MEM_DMA0 :: CTRL :: reserved0 [31:01] */ -#define BCHP_SHARF_MEM_DMA0_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_SHARF_MEM_DMA0_CTRL_reserved0_SHIFT 1 - -/* SHARF_MEM_DMA0 :: CTRL :: RUN [00:00] */ -#define BCHP_SHARF_MEM_DMA0_CTRL_RUN_MASK 0x00000001 -#define BCHP_SHARF_MEM_DMA0_CTRL_RUN_SHIFT 0 - -/*************************************************************************** - *WAKE_CTRL - SHARF_MEM_DMA Wake Control Register - ***************************************************************************/ -/* SHARF_MEM_DMA0 :: WAKE_CTRL :: reserved0 [31:02] */ -#define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_reserved0_SHIFT 2 - -/* SHARF_MEM_DMA0 :: WAKE_CTRL :: WAKE_MODE [01:01] */ -#define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_MODE_MASK 0x00000002 -#define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_MODE_SHIFT 1 - -/* SHARF_MEM_DMA0 :: WAKE_CTRL :: WAKE [00:00] */ -#define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_MASK 0x00000001 -#define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_SHIFT 0 - -/*************************************************************************** - *STATUS - SHARF_MEM_DMA Status Register - ***************************************************************************/ -/* SHARF_MEM_DMA0 :: STATUS :: reserved0 [31:02] */ -#define BCHP_SHARF_MEM_DMA0_STATUS_reserved0_MASK 0xfffffffc -#define BCHP_SHARF_MEM_DMA0_STATUS_reserved0_SHIFT 2 - -/* SHARF_MEM_DMA0 :: STATUS :: DMA_STATUS [01:00] */ -#define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_MASK 0x00000003 -#define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_SHIFT 0 -#define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Idle 0 -#define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Busy 1 -#define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Sleep 2 -#define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Reserved 3 - -/*************************************************************************** - *CUR_DESC - SHARF_MEM_DMA Current Descriptor Address Register - ***************************************************************************/ -/* SHARF_MEM_DMA0 :: CUR_DESC :: ADDR [31:00] */ -#define BCHP_SHARF_MEM_DMA0_CUR_DESC_ADDR_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA0_CUR_DESC_ADDR_SHIFT 0 - -/*************************************************************************** - *CUR_BYTE - SHARF_MEM_DMA Current Byte Count Register - ***************************************************************************/ -/* SHARF_MEM_DMA0 :: CUR_BYTE :: reserved0 [31:25] */ -#define BCHP_SHARF_MEM_DMA0_CUR_BYTE_reserved0_MASK 0xfe000000 -#define BCHP_SHARF_MEM_DMA0_CUR_BYTE_reserved0_SHIFT 25 - -/* SHARF_MEM_DMA0 :: CUR_BYTE :: COUNT [24:00] */ -#define BCHP_SHARF_MEM_DMA0_CUR_BYTE_COUNT_MASK 0x01ffffff -#define BCHP_SHARF_MEM_DMA0_CUR_BYTE_COUNT_SHIFT 0 - -/*************************************************************************** - *SCRATCH - SHARF_MEM_DMA Scratch Register - ***************************************************************************/ -/* SHARF_MEM_DMA0 :: SCRATCH :: SCRATCH_BIT [31:00] */ -#define BCHP_SHARF_MEM_DMA0_SCRATCH_SCRATCH_BIT_MASK 0xffffffff -#define BCHP_SHARF_MEM_DMA0_SCRATCH_SCRATCH_BIT_SHIFT 0 - -#endif /* #ifndef BCHP_SHARF_MEM_DMA0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_top.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_top.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_top.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_top.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,418 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sharf_top.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:19p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:02 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_top.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:19p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SHARF_TOP_H__ -#define BCHP_SHARF_TOP_H__ - -/*************************************************************************** - *SHARF_TOP - SHARF Control Registers - ***************************************************************************/ -#define BCHP_SHARF_TOP_REVISION 0x000f4000 /* SHARF REVISION */ -#define BCHP_SHARF_TOP_STATUS 0x000f4004 /* SHARF Status */ -#define BCHP_SHARF_TOP_SHA0_31_00 0x000f4008 /* SHA Context0 State[31:0] */ -#define BCHP_SHARF_TOP_SHA0_63_32 0x000f400c /* SHA Context0 State[63:32] */ -#define BCHP_SHARF_TOP_SHA0_95_64 0x000f4010 /* SHA Context0 State[95:64] */ -#define BCHP_SHARF_TOP_SHA0_127_96 0x000f4014 /* SHA Context0 State[127:96] */ -#define BCHP_SHARF_TOP_SHA0_159_128 0x000f4018 /* SHA Context0 State[159:128] */ -#define BCHP_SHARF_TOP_SHA0_191_160 0x000f401c /* SHA Context0 State[191:160] */ -#define BCHP_SHARF_TOP_SHA0_223_192 0x000f4020 /* SHA Context0 State[223:192] */ -#define BCHP_SHARF_TOP_SHA0_255_224 0x000f4024 /* SHA Context0 State[255:224] */ -#define BCHP_SHARF_TOP_SHA1_31_00 0x000f4028 /* SHA Context1 State[31:0] */ -#define BCHP_SHARF_TOP_SHA1_63_32 0x000f402c /* SHA Context1 State[63:32] */ -#define BCHP_SHARF_TOP_SHA1_95_64 0x000f4030 /* SHA Context1 State[95:64] */ -#define BCHP_SHARF_TOP_SHA1_127_96 0x000f4034 /* SHA Context1 State[127:96] */ -#define BCHP_SHARF_TOP_SHA1_159_128 0x000f4038 /* SHA Context1 State[159:128] */ -#define BCHP_SHARF_TOP_SHA1_191_160 0x000f403c /* SHA Context1 State[191:160] */ -#define BCHP_SHARF_TOP_SHA1_223_192 0x000f4040 /* SHA Context1 State[223:192] */ -#define BCHP_SHARF_TOP_SHA1_255_224 0x000f4044 /* SHA Context1 State[255:224] */ -#define BCHP_SHARF_TOP_SHA2_31_00 0x000f4048 /* SHA Context2 State[31:0] */ -#define BCHP_SHARF_TOP_SHA2_63_32 0x000f404c /* SHA Context2 State[63:32] */ -#define BCHP_SHARF_TOP_SHA2_95_64 0x000f4050 /* SHA Context2 State[95:64] */ -#define BCHP_SHARF_TOP_SHA2_127_96 0x000f4054 /* SHA Context2 State[127:96] */ -#define BCHP_SHARF_TOP_SHA2_159_128 0x000f4058 /* SHA Context2 State[159:128] */ -#define BCHP_SHARF_TOP_SHA2_191_160 0x000f405c /* SHA Context2 State[191:160] */ -#define BCHP_SHARF_TOP_SHA2_223_192 0x000f4060 /* SHA Context2 State[223:192] */ -#define BCHP_SHARF_TOP_SHA2_255_224 0x000f4064 /* SHA Context2 State[255:224] */ -#define BCHP_SHARF_TOP_CMAC0_31_00 0x000f4068 /* CMAC Context0 State[31:0] */ -#define BCHP_SHARF_TOP_CMAC0_63_32 0x000f406c /* CMAC Context0 State[63:32] */ -#define BCHP_SHARF_TOP_CMAC0_95_64 0x000f4070 /* CMAC Context0 State[95:64] */ -#define BCHP_SHARF_TOP_CMAC0_127_96 0x000f4074 /* CMAC Context0 State[127:96] */ -#define BCHP_SHARF_TOP_CMAC1_31_00 0x000f4078 /* CMAC Context1 State[31:0] */ -#define BCHP_SHARF_TOP_CMAC1_63_32 0x000f407c /* CMAC Context1 State[63:32] */ -#define BCHP_SHARF_TOP_CMAC1_95_64 0x000f4080 /* CMAC Context1 State[95:64] */ -#define BCHP_SHARF_TOP_CMAC1_127_96 0x000f4084 /* CMAC Context1 State[127:96] */ -#define BCHP_SHARF_TOP_CTXT0_FAIL_ID 0x000f4088 /* Context 0 Fail ID register */ -#define BCHP_SHARF_TOP_CTXT1_FAIL_ID 0x000f408c /* Context 1 Fail ID register */ -#define BCHP_SHARF_TOP_CTXT2_FAIL_ID 0x000f4090 /* Context 2 Fail ID register (SHA only) */ -#define BCHP_SHARF_TOP_ERR_STATUS 0x000f4094 /* SHARF Error Status */ - -/*************************************************************************** - *REVISION - SHARF REVISION - ***************************************************************************/ -/* SHARF_TOP :: REVISION :: reserved0 [31:16] */ -#define BCHP_SHARF_TOP_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_SHARF_TOP_REVISION_reserved0_SHIFT 16 - -/* SHARF_TOP :: REVISION :: MAJOR [15:08] */ -#define BCHP_SHARF_TOP_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_SHARF_TOP_REVISION_MAJOR_SHIFT 8 - -/* SHARF_TOP :: REVISION :: MINOR [07:00] */ -#define BCHP_SHARF_TOP_REVISION_MINOR_MASK 0x000000ff -#define BCHP_SHARF_TOP_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *STATUS - SHARF Status - ***************************************************************************/ -/* SHARF_TOP :: STATUS :: reserved0 [31:04] */ -#define BCHP_SHARF_TOP_STATUS_reserved0_MASK 0xfffffff0 -#define BCHP_SHARF_TOP_STATUS_reserved0_SHIFT 4 - -/* SHARF_TOP :: STATUS :: FAIL2 [03:03] */ -#define BCHP_SHARF_TOP_STATUS_FAIL2_MASK 0x00000008 -#define BCHP_SHARF_TOP_STATUS_FAIL2_SHIFT 3 - -/* SHARF_TOP :: STATUS :: FAIL1 [02:02] */ -#define BCHP_SHARF_TOP_STATUS_FAIL1_MASK 0x00000004 -#define BCHP_SHARF_TOP_STATUS_FAIL1_SHIFT 2 - -/* SHARF_TOP :: STATUS :: FAIL0 [01:01] */ -#define BCHP_SHARF_TOP_STATUS_FAIL0_MASK 0x00000002 -#define BCHP_SHARF_TOP_STATUS_FAIL0_SHIFT 1 - -/* SHARF_TOP :: STATUS :: ACTIVE [00:00] */ -#define BCHP_SHARF_TOP_STATUS_ACTIVE_MASK 0x00000001 -#define BCHP_SHARF_TOP_STATUS_ACTIVE_SHIFT 0 - -/*************************************************************************** - *SHA0_31_00 - SHA Context0 State[31:0] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_31_00 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_31_00_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_31_00_STATE_SHIFT 0 - -/*************************************************************************** - *SHA0_63_32 - SHA Context0 State[63:32] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_63_32 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_63_32_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_63_32_STATE_SHIFT 0 - -/*************************************************************************** - *SHA0_95_64 - SHA Context0 State[95:64] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_95_64 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_95_64_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_95_64_STATE_SHIFT 0 - -/*************************************************************************** - *SHA0_127_96 - SHA Context0 State[127:96] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_127_96 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_127_96_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_127_96_STATE_SHIFT 0 - -/*************************************************************************** - *SHA0_159_128 - SHA Context0 State[159:128] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_159_128 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_159_128_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_159_128_STATE_SHIFT 0 - -/*************************************************************************** - *SHA0_191_160 - SHA Context0 State[191:160] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_191_160 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_191_160_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_191_160_STATE_SHIFT 0 - -/*************************************************************************** - *SHA0_223_192 - SHA Context0 State[223:192] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_223_192 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_223_192_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_223_192_STATE_SHIFT 0 - -/*************************************************************************** - *SHA0_255_224 - SHA Context0 State[255:224] - ***************************************************************************/ -/* SHARF_TOP :: SHA0_255_224 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA0_255_224_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA0_255_224_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_31_00 - SHA Context1 State[31:0] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_31_00 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_31_00_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_31_00_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_63_32 - SHA Context1 State[63:32] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_63_32 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_63_32_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_63_32_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_95_64 - SHA Context1 State[95:64] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_95_64 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_95_64_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_95_64_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_127_96 - SHA Context1 State[127:96] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_127_96 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_127_96_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_127_96_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_159_128 - SHA Context1 State[159:128] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_159_128 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_159_128_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_159_128_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_191_160 - SHA Context1 State[191:160] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_191_160 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_191_160_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_191_160_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_223_192 - SHA Context1 State[223:192] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_223_192 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_223_192_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_223_192_STATE_SHIFT 0 - -/*************************************************************************** - *SHA1_255_224 - SHA Context1 State[255:224] - ***************************************************************************/ -/* SHARF_TOP :: SHA1_255_224 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA1_255_224_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA1_255_224_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_31_00 - SHA Context2 State[31:0] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_31_00 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_31_00_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_31_00_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_63_32 - SHA Context2 State[63:32] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_63_32 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_63_32_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_63_32_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_95_64 - SHA Context2 State[95:64] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_95_64 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_95_64_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_95_64_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_127_96 - SHA Context2 State[127:96] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_127_96 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_127_96_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_127_96_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_159_128 - SHA Context2 State[159:128] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_159_128 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_159_128_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_159_128_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_191_160 - SHA Context2 State[191:160] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_191_160 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_191_160_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_191_160_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_223_192 - SHA Context2 State[223:192] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_223_192 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_223_192_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_223_192_STATE_SHIFT 0 - -/*************************************************************************** - *SHA2_255_224 - SHA Context2 State[255:224] - ***************************************************************************/ -/* SHARF_TOP :: SHA2_255_224 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_SHA2_255_224_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_SHA2_255_224_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC0_31_00 - CMAC Context0 State[31:0] - ***************************************************************************/ -/* SHARF_TOP :: CMAC0_31_00 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC0_31_00_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC0_31_00_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC0_63_32 - CMAC Context0 State[63:32] - ***************************************************************************/ -/* SHARF_TOP :: CMAC0_63_32 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC0_63_32_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC0_63_32_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC0_95_64 - CMAC Context0 State[95:64] - ***************************************************************************/ -/* SHARF_TOP :: CMAC0_95_64 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC0_95_64_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC0_95_64_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC0_127_96 - CMAC Context0 State[127:96] - ***************************************************************************/ -/* SHARF_TOP :: CMAC0_127_96 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC0_127_96_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC0_127_96_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC1_31_00 - CMAC Context1 State[31:0] - ***************************************************************************/ -/* SHARF_TOP :: CMAC1_31_00 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC1_31_00_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC1_31_00_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC1_63_32 - CMAC Context1 State[63:32] - ***************************************************************************/ -/* SHARF_TOP :: CMAC1_63_32 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC1_63_32_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC1_63_32_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC1_95_64 - CMAC Context1 State[95:64] - ***************************************************************************/ -/* SHARF_TOP :: CMAC1_95_64 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC1_95_64_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC1_95_64_STATE_SHIFT 0 - -/*************************************************************************** - *CMAC1_127_96 - CMAC Context1 State[127:96] - ***************************************************************************/ -/* SHARF_TOP :: CMAC1_127_96 :: STATE [31:00] */ -#define BCHP_SHARF_TOP_CMAC1_127_96_STATE_MASK 0xffffffff -#define BCHP_SHARF_TOP_CMAC1_127_96_STATE_SHIFT 0 - -/*************************************************************************** - *CTXT0_FAIL_ID - Context 0 Fail ID register - ***************************************************************************/ -/* SHARF_TOP :: CTXT0_FAIL_ID :: ID [31:00] */ -#define BCHP_SHARF_TOP_CTXT0_FAIL_ID_ID_MASK 0xffffffff -#define BCHP_SHARF_TOP_CTXT0_FAIL_ID_ID_SHIFT 0 - -/*************************************************************************** - *CTXT1_FAIL_ID - Context 1 Fail ID register - ***************************************************************************/ -/* SHARF_TOP :: CTXT1_FAIL_ID :: ID [31:00] */ -#define BCHP_SHARF_TOP_CTXT1_FAIL_ID_ID_MASK 0xffffffff -#define BCHP_SHARF_TOP_CTXT1_FAIL_ID_ID_SHIFT 0 - -/*************************************************************************** - *CTXT2_FAIL_ID - Context 2 Fail ID register (SHA only) - ***************************************************************************/ -/* SHARF_TOP :: CTXT2_FAIL_ID :: ID [31:00] */ -#define BCHP_SHARF_TOP_CTXT2_FAIL_ID_ID_MASK 0xffffffff -#define BCHP_SHARF_TOP_CTXT2_FAIL_ID_ID_SHIFT 0 - -/*************************************************************************** - *ERR_STATUS - SHARF Error Status - ***************************************************************************/ -/* SHARF_TOP :: ERR_STATUS :: reserved0 [31:08] */ -#define BCHP_SHARF_TOP_ERR_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_SHARF_TOP_ERR_STATUS_reserved0_SHIFT 8 - -/* SHARF_TOP :: ERR_STATUS :: FRAME_ERR1 [07:07] */ -#define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR1_MASK 0x00000080 -#define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR1_SHIFT 7 - -/* SHARF_TOP :: ERR_STATUS :: FRAME_ERR0 [06:06] */ -#define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR0_MASK 0x00000040 -#define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR0_SHIFT 6 - -/* SHARF_TOP :: ERR_STATUS :: AES_ALIGN_ERR1 [05:05] */ -#define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR1_MASK 0x00000020 -#define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR1_SHIFT 5 - -/* SHARF_TOP :: ERR_STATUS :: AES_ALIGN_ERR0 [04:04] */ -#define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR0_MASK 0x00000010 -#define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR0_SHIFT 4 - -/* SHARF_TOP :: ERR_STATUS :: SIZE_ERR1 [03:03] */ -#define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR1_MASK 0x00000008 -#define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR1_SHIFT 3 - -/* SHARF_TOP :: ERR_STATUS :: SIZE_ERR0 [02:02] */ -#define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR0_MASK 0x00000004 -#define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR0_SHIFT 2 - -/* SHARF_TOP :: ERR_STATUS :: AES_BSP_KEY_ERR1 [01:01] */ -#define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR1_MASK 0x00000002 -#define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR1_SHIFT 1 - -/* SHARF_TOP :: ERR_STATUS :: AES_BSP_KEY_ERR0 [00:00] */ -#define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR0_MASK 0x00000001 -#define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR0_SHIFT 0 - -#endif /* #ifndef BCHP_SHARF_TOP_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1734 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sun_gisb_arb.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:19p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:30 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:19p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SUN_GISB_ARB_H__ -#define BCHP_SUN_GISB_ARB_H__ - -/*************************************************************************** - *SUN_GISB_ARB - GISB Arbiter registers - ***************************************************************************/ -#define BCHP_SUN_GISB_ARB_REVISION 0x00400000 /* GISB ARBITER REVISION */ -#define BCHP_SUN_GISB_ARB_SCRATCH 0x00400004 /* GISB ARBITER Scratch Register */ -#define BCHP_SUN_GISB_ARB_REQ_MASK 0x00400008 /* GISB ARBITER Master Request Mask Register */ -#define BCHP_SUN_GISB_ARB_TIMER 0x0040000c /* GISB ARBITER Timer Value Register */ -#define BCHP_SUN_GISB_ARB_BP_CTRL 0x00400010 /* GISB ARBITER Breakpoint Control Register */ -#define BCHP_SUN_GISB_ARB_BP_CAP_CLR 0x00400014 /* GISB ARBITER Breakpoint Capture Clear Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_0 0x00400018 /* GISB ARBITER Breakpoint Start Address 0 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_0 0x0040001c /* GISB ARBITER Breakpoint End Address 0 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_0 0x00400020 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0 0x00400024 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0 0x00400028 /* GISB ARBITER Breakpoint Enable 0 Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_1 0x0040002c /* GISB ARBITER Breakpoint Start Address 1 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_1 0x00400030 /* GISB ARBITER Breakpoint End Address 1 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_1 0x00400034 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1 0x00400038 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1 0x0040003c /* GISB ARBITER Breakpoint Enable 1 Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_2 0x00400040 /* GISB ARBITER Breakpoint Start Address 2 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_2 0x00400044 /* GISB ARBITER Breakpoint End Address 2 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_2 0x00400048 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2 0x0040004c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2 0x00400050 /* GISB ARBITER Breakpoint Enable 2 Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_3 0x00400054 /* GISB ARBITER Breakpoint Start Address 3 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_3 0x00400058 /* GISB ARBITER Breakpoint End Address 3 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_3 0x0040005c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3 0x00400060 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3 0x00400064 /* GISB ARBITER Breakpoint Enable 3 Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_4 0x00400068 /* GISB ARBITER Breakpoint Start Address 4 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_4 0x0040006c /* GISB ARBITER Breakpoint End Address 4 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_4 0x00400070 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4 0x00400074 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4 0x00400078 /* GISB ARBITER Breakpoint Enable 4 Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_5 0x0040007c /* GISB ARBITER Breakpoint Start Address 5 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_5 0x00400080 /* GISB ARBITER Breakpoint End Address 5 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_5 0x00400084 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5 0x00400088 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5 0x0040008c /* GISB ARBITER Breakpoint Enable 5 Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_6 0x00400090 /* GISB ARBITER Breakpoint Start Address 6 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_6 0x00400094 /* GISB ARBITER Breakpoint End Address 6 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_6 0x00400098 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6 0x0040009c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6 0x004000a0 /* GISB ARBITER Breakpoint Enable 6 Register */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_7 0x004000a4 /* GISB ARBITER Breakpoint Start Address 7 Register */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_7 0x004000a8 /* GISB ARBITER Breakpoint End Address 7 Register */ -#define BCHP_SUN_GISB_ARB_BP_READ_7 0x004000ac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7 0x004000b0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7 0x004000b4 /* GISB ARBITER Breakpoint Enable 7 Register */ -#define BCHP_SUN_GISB_ARB_BP_CAP_ADDR 0x004000b8 /* GISB ARBITER Breakpoint Capture Address Register */ -#define BCHP_SUN_GISB_ARB_BP_CAP_DATA 0x004000bc /* GISB ARBITER Breakpoint Capture Data Register */ -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS 0x004000c0 /* GISB ARBITER Breakpoint Capture Status Register */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER 0x004000c4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_CLR 0x004000c8 /* GISB ARBITER Error Capture Clear Register */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_ADDR 0x004000cc /* GISB ARBITER Error Capture Address Register */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_DATA 0x004000d0 /* GISB ARBITER Error Capture Data Register */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS 0x004000d4 /* GISB ARBITER Error Capture Status Register */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER 0x004000d8 /* GISB ARBITER Error Capture GISB MASTER Register */ - -/*************************************************************************** - *REVISION - GISB ARBITER REVISION - ***************************************************************************/ -/* SUN_GISB_ARB :: REVISION :: reserved0 [31:16] */ -#define BCHP_SUN_GISB_ARB_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_SUN_GISB_ARB_REVISION_reserved0_SHIFT 16 - -/* SUN_GISB_ARB :: REVISION :: MAJOR [15:08] */ -#define BCHP_SUN_GISB_ARB_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_SUN_GISB_ARB_REVISION_MAJOR_SHIFT 8 - -/* SUN_GISB_ARB :: REVISION :: MINOR [07:00] */ -#define BCHP_SUN_GISB_ARB_REVISION_MINOR_MASK 0x000000ff -#define BCHP_SUN_GISB_ARB_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *SCRATCH - GISB ARBITER Scratch Register - ***************************************************************************/ -/* SUN_GISB_ARB :: SCRATCH :: scratch_bit [31:00] */ -#define BCHP_SUN_GISB_ARB_SCRATCH_scratch_bit_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_SCRATCH_scratch_bit_SHIFT 0 - -/*************************************************************************** - *REQ_MASK - GISB ARBITER Master Request Mask Register - ***************************************************************************/ -/* SUN_GISB_ARB :: REQ_MASK :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_REQ_MASK_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: REQ_MASK :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_REQ_MASK_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_REQ_MASK_trb_UNMASK 0 - -/* SUN_GISB_ARB :: REQ_MASK :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_REQ_MASK_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_REQ_MASK_jtag_UNMASK 0 - -/* SUN_GISB_ARB :: REQ_MASK :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_REQ_MASK_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: REQ_MASK :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_REQ_MASK_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_REQ_MASK_avd0_UNMASK 0 - -/* SUN_GISB_ARB :: REQ_MASK :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_REQ_MASK_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: REQ_MASK :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_REQ_MASK_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_REQ_MASK_bsp_UNMASK 0 - -/* SUN_GISB_ARB :: REQ_MASK :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_REQ_MASK_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_REQ_MASK_cce_UNMASK 0 - -/* SUN_GISB_ARB :: REQ_MASK :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_REQ_MASK_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_REQ_MASK_pcie_UNMASK 0 - -/* SUN_GISB_ARB :: REQ_MASK :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_REQ_MASK_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_REQ_MASK_arm_UNMASK 0 - -/* SUN_GISB_ARB :: REQ_MASK :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_REQ_MASK_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_REQ_MASK_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_REQ_MASK_ssp_UNMASK 0 - -/*************************************************************************** - *TIMER - GISB ARBITER Timer Value Register - ***************************************************************************/ -/* SUN_GISB_ARB :: TIMER :: hi_count [31:16] */ -#define BCHP_SUN_GISB_ARB_TIMER_hi_count_MASK 0xffff0000 -#define BCHP_SUN_GISB_ARB_TIMER_hi_count_SHIFT 16 - -/* SUN_GISB_ARB :: TIMER :: lo_count [15:00] */ -#define BCHP_SUN_GISB_ARB_TIMER_lo_count_MASK 0x0000ffff -#define BCHP_SUN_GISB_ARB_TIMER_lo_count_SHIFT 0 - -/*************************************************************************** - *BP_CTRL - GISB ARBITER Breakpoint Control Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_CTRL :: reserved0 [31:02] */ -#define BCHP_SUN_GISB_ARB_BP_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_SUN_GISB_ARB_BP_CTRL_reserved0_SHIFT 2 - -/* SUN_GISB_ARB :: BP_CTRL :: breakpoint_tea [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_ENABLE 1 - -/* SUN_GISB_ARB :: BP_CTRL :: repeat_capture [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_ENABLE 1 - -/*************************************************************************** - *BP_CAP_CLR - GISB ARBITER Breakpoint Capture Clear Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_CAP_CLR :: reserved0 [31:01] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_CLR_reserved0_MASK 0xfffffffe -#define BCHP_SUN_GISB_ARB_BP_CAP_CLR_reserved0_SHIFT 1 - -/* SUN_GISB_ARB :: BP_CAP_CLR :: clear [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_CLR_clear_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_CAP_CLR_clear_SHIFT 0 - -/*************************************************************************** - *BP_START_ADDR_0 - GISB ARBITER Breakpoint Start Address 0 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_0 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_0_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_0_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_0 - GISB ARBITER Breakpoint End Address 0 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_0 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_0_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_0_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_0 - GISB ARBITER Breakpoint Master Read Control 0 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_0 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_0_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_0 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_0_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_0_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_0 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_0 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_0_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_0 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_0 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_0_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_0 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_0 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_0_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_0_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_0 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_0 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_0_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_0_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_0 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_0 - GISB ARBITER Breakpoint Master Write Control 0 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_0 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_0 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_0 - GISB ARBITER Breakpoint Enable 0 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_0 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_0 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_0 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_0 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_ENABLE 1 - -/*************************************************************************** - *BP_START_ADDR_1 - GISB ARBITER Breakpoint Start Address 1 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_1 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_1_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_1_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_1 - GISB ARBITER Breakpoint End Address 1 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_1 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_1_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_1_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_1 - GISB ARBITER Breakpoint Master Read Control 1 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_1 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_1_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_1 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_1_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_1_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_1 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_1 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_1_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_1 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_1 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_1_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_1 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_1 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_1_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_1_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_1 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_1 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_1_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_1_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_1 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_1 - GISB ARBITER Breakpoint Master Write Control 1 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_1 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_1 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_1 - GISB ARBITER Breakpoint Enable 1 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_1 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_1 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_1 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_1 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_ENABLE 1 - -/*************************************************************************** - *BP_START_ADDR_2 - GISB ARBITER Breakpoint Start Address 2 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_2 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_2_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_2_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_2 - GISB ARBITER Breakpoint End Address 2 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_2 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_2_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_2_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_2 - GISB ARBITER Breakpoint Master Read Control 2 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_2 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_2_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_2 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_2_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_2_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_2 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_2 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_2_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_2 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_2 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_2_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_2 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_2 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_2_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_2_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_2 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_2 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_2_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_2_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_2 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_2 - GISB ARBITER Breakpoint Master Write Control 2 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_2 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_2 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_2 - GISB ARBITER Breakpoint Enable 2 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_2 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_2 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_2 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_2 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_ENABLE 1 - -/*************************************************************************** - *BP_START_ADDR_3 - GISB ARBITER Breakpoint Start Address 3 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_3 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_3_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_3_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_3 - GISB ARBITER Breakpoint End Address 3 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_3 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_3_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_3_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_3 - GISB ARBITER Breakpoint Master Read Control 3 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_3 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_3_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_3 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_3_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_3_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_3 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_3 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_3_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_3 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_3 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_3_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_3 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_3 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_3_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_3_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_3 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_3 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_3_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_3_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_3 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_3 - GISB ARBITER Breakpoint Master Write Control 3 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_3 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_3 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_3 - GISB ARBITER Breakpoint Enable 3 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_3 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_3 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_3 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_3 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_ENABLE 1 - -/*************************************************************************** - *BP_START_ADDR_4 - GISB ARBITER Breakpoint Start Address 4 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_4 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_4_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_4_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_4 - GISB ARBITER Breakpoint End Address 4 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_4 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_4_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_4_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_4 - GISB ARBITER Breakpoint Master Read Control 4 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_4 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_4_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_4 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_4_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_4_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_4 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_4 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_4_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_4 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_4 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_4_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_4 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_4 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_4_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_4_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_4 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_4 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_4_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_4_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_4 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_4 - GISB ARBITER Breakpoint Master Write Control 4 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_4 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_4 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_4 - GISB ARBITER Breakpoint Enable 4 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_4 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_4 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_4 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_4 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_ENABLE 1 - -/*************************************************************************** - *BP_START_ADDR_5 - GISB ARBITER Breakpoint Start Address 5 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_5 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_5_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_5_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_5 - GISB ARBITER Breakpoint End Address 5 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_5 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_5_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_5_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_5 - GISB ARBITER Breakpoint Master Read Control 5 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_5 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_5_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_5 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_5_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_5_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_5 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_5 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_5_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_5 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_5 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_5_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_5 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_5 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_5_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_5_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_5 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_5 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_5_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_5_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_5 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_5 - GISB ARBITER Breakpoint Master Write Control 5 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_5 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_5 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_5 - GISB ARBITER Breakpoint Enable 5 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_5 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_5 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_5 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_5 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_ENABLE 1 - -/*************************************************************************** - *BP_START_ADDR_6 - GISB ARBITER Breakpoint Start Address 6 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_6 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_6_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_6_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_6 - GISB ARBITER Breakpoint End Address 6 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_6 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_6_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_6_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_6 - GISB ARBITER Breakpoint Master Read Control 6 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_6 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_6_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_6 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_6_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_6_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_6 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_6 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_6_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_6 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_6 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_6_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_6 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_6 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_6_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_6_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_6 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_6 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_6_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_6_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_6 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_6 - GISB ARBITER Breakpoint Master Write Control 6 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_6 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_6 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_6 - GISB ARBITER Breakpoint Enable 6 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_6 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_6 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_6 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_6 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_ENABLE 1 - -/*************************************************************************** - *BP_START_ADDR_7 - GISB ARBITER Breakpoint Start Address 7 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_START_ADDR_7 :: start [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_7_start_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_START_ADDR_7_start_SHIFT 0 - -/*************************************************************************** - *BP_END_ADDR_7 - GISB ARBITER Breakpoint End Address 7 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_END_ADDR_7 :: end [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_7_end_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_END_ADDR_7_end_SHIFT 0 - -/*************************************************************************** - *BP_READ_7 - GISB ARBITER Breakpoint Master Read Control 7 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_READ_7 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_READ_7_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_READ_7 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_READ_7_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_READ_7_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_7 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_7 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_READ_7_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_READ_7 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_7 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_READ_7_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_READ_7 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_7 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_READ_7_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_READ_7_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_7 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_7 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_READ_7_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_READ_7_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_READ_7 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_ENABLE 1 - -/*************************************************************************** - *BP_WRITE_7 - GISB ARBITER Breakpoint Master Write Control 7 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_WRITE_7 :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_SHIFT 11 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_SHIFT 10 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_SHIFT 7 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_SHIFT 4 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_SHIFT 3 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_ENABLE 1 - -/* SUN_GISB_ARB :: BP_WRITE_7 :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_ENABLE 1 - -/*************************************************************************** - *BP_ENABLE_7 - GISB ARBITER Breakpoint Enable 7 Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_ENABLE_7 :: reserved0 [31:03] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_reserved0_SHIFT 3 - -/* SUN_GISB_ARB :: BP_ENABLE_7 :: block [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_SHIFT 2 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_7 :: address [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_SHIFT 1 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_ENABLE 1 - -/* SUN_GISB_ARB :: BP_ENABLE_7 :: access [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_SHIFT 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_DISABLE 0 -#define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_ENABLE 1 - -/*************************************************************************** - *BP_CAP_ADDR - GISB ARBITER Breakpoint Capture Address Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_CAP_ADDR :: address [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_ADDR_address_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_CAP_ADDR_address_SHIFT 0 - -/*************************************************************************** - *BP_CAP_DATA - GISB ARBITER Breakpoint Capture Data Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_CAP_DATA :: data [31:00] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_DATA_data_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_BP_CAP_DATA_data_SHIFT 0 - -/*************************************************************************** - *BP_CAP_STATUS - GISB ARBITER Breakpoint Capture Status Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_CAP_STATUS :: reserved0 [31:06] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_reserved0_MASK 0xffffffc0 -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_reserved0_SHIFT 6 - -/* SUN_GISB_ARB :: BP_CAP_STATUS :: bs_b [05:02] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_bs_b_MASK 0x0000003c -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_bs_b_SHIFT 2 - -/* SUN_GISB_ARB :: BP_CAP_STATUS :: write [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_write_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_write_SHIFT 1 - -/* SUN_GISB_ARB :: BP_CAP_STATUS :: valid [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_valid_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_valid_SHIFT 0 - -/*************************************************************************** - *BP_CAP_MASTER - GISB ARBITER Breakpoint Capture GISB MASTER Register - ***************************************************************************/ -/* SUN_GISB_ARB :: BP_CAP_MASTER :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_trb_SHIFT 11 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_jtag_SHIFT 10 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_avd0_SHIFT 7 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_bsp_SHIFT 4 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_cce_SHIFT 3 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_pcie_SHIFT 2 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_arm_SHIFT 1 - -/* SUN_GISB_ARB :: BP_CAP_MASTER :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_ssp_SHIFT 0 - -/*************************************************************************** - *ERR_CAP_CLR - GISB ARBITER Error Capture Clear Register - ***************************************************************************/ -/* SUN_GISB_ARB :: ERR_CAP_CLR :: reserved0 [31:01] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_reserved0_MASK 0xfffffffe -#define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_reserved0_SHIFT 1 - -/* SUN_GISB_ARB :: ERR_CAP_CLR :: clear [00:00] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_clear_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_clear_SHIFT 0 - -/*************************************************************************** - *ERR_CAP_ADDR - GISB ARBITER Error Capture Address Register - ***************************************************************************/ -/* SUN_GISB_ARB :: ERR_CAP_ADDR :: address [31:00] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_ADDR_address_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_ERR_CAP_ADDR_address_SHIFT 0 - -/*************************************************************************** - *ERR_CAP_DATA - GISB ARBITER Error Capture Data Register - ***************************************************************************/ -/* SUN_GISB_ARB :: ERR_CAP_DATA :: data [31:00] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_DATA_data_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_ERR_CAP_DATA_data_SHIFT 0 - -/*************************************************************************** - *ERR_CAP_STATUS - GISB ARBITER Error Capture Status Register - ***************************************************************************/ -/* SUN_GISB_ARB :: ERR_CAP_STATUS :: reserved0 [31:13] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved0_MASK 0xffffe000 -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved0_SHIFT 13 - -/* SUN_GISB_ARB :: ERR_CAP_STATUS :: timeout [12:12] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_timeout_MASK 0x00001000 -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_timeout_SHIFT 12 - -/* SUN_GISB_ARB :: ERR_CAP_STATUS :: tea [11:11] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_tea_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_tea_SHIFT 11 - -/* SUN_GISB_ARB :: ERR_CAP_STATUS :: reserved1 [10:06] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved1_MASK 0x000007c0 -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved1_SHIFT 6 - -/* SUN_GISB_ARB :: ERR_CAP_STATUS :: bs_b [05:02] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_bs_b_MASK 0x0000003c -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_bs_b_SHIFT 2 - -/* SUN_GISB_ARB :: ERR_CAP_STATUS :: write [01:01] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_write_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_write_SHIFT 1 - -/* SUN_GISB_ARB :: ERR_CAP_STATUS :: valid [00:00] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_valid_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_valid_SHIFT 0 - -/*************************************************************************** - *ERR_CAP_MASTER - GISB ARBITER Error Capture GISB MASTER Register - ***************************************************************************/ -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: reserved0 [31:12] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved0_MASK 0xfffff000 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved0_SHIFT 12 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: trb [11:11] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_trb_MASK 0x00000800 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_trb_SHIFT 11 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: jtag [10:10] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_jtag_MASK 0x00000400 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_jtag_SHIFT 10 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: reserved1 [09:08] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved1_MASK 0x00000300 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved1_SHIFT 8 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: avd0 [07:07] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_avd0_MASK 0x00000080 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_avd0_SHIFT 7 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: reserved2 [06:05] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved2_MASK 0x00000060 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved2_SHIFT 5 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: bsp [04:04] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_bsp_MASK 0x00000010 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_bsp_SHIFT 4 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: cce [03:03] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_cce_MASK 0x00000008 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_cce_SHIFT 3 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: pcie [02:02] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_pcie_MASK 0x00000004 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_pcie_SHIFT 2 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: arm [01:01] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_arm_MASK 0x00000002 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_arm_SHIFT 1 - -/* SUN_GISB_ARB :: ERR_CAP_MASTER :: ssp [00:00] */ -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_ssp_MASK 0x00000001 -#define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_ssp_SHIFT 0 - -#endif /* #ifndef BCHP_SUN_GISB_ARB_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb_sec.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb_sec.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb_sec.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb_sec.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sun_gisb_arb_sec.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:19p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:22 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb_sec.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:19p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SUN_GISB_ARB_SEC_H__ -#define BCHP_SUN_GISB_ARB_SEC_H__ - -/*************************************************************************** - *SUN_GISB_ARB_SEC - GISB Arbiter secure registers - ***************************************************************************/ -#define BCHP_SUN_GISB_ARB_SEC_RSV_S 0x00460000 /* RESERVED */ -#define BCHP_SUN_GISB_ARB_SEC_RSV_E 0x00460064 /* RESERVED */ - -/*************************************************************************** - *RSV_S - RESERVED - ***************************************************************************/ -/* SUN_GISB_ARB_SEC :: RSV_S :: reserved0 [31:00] */ -#define BCHP_SUN_GISB_ARB_SEC_RSV_S_reserved0_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_SEC_RSV_S_reserved0_SHIFT 0 - -/*************************************************************************** - *RSV_E - RESERVED - ***************************************************************************/ -/* SUN_GISB_ARB_SEC :: RSV_E :: reserved0 [31:00] */ -#define BCHP_SUN_GISB_ARB_SEC_RSV_E_reserved0_MASK 0xffffffff -#define BCHP_SUN_GISB_ARB_SEC_RSV_E_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_SUN_GISB_ARB_SEC_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1858 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sun_l2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:20p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:43 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:20p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SUN_L2_H__ -#define BCHP_SUN_L2_H__ - -/*************************************************************************** - *SUN_L2 - Registers for the Sundry block's L2 interrupt controller - ***************************************************************************/ -#define BCHP_SUN_L2_CPU_STATUS 0x00401800 /* CPU interrupt Status Register */ -#define BCHP_SUN_L2_CPU_SET 0x00401804 /* CPU interrupt Set Register */ -#define BCHP_SUN_L2_CPU_CLEAR 0x00401808 /* CPU interrupt Clear Register */ -#define BCHP_SUN_L2_CPU_MASK_STATUS 0x0040180c /* CPU interrupt Mask Status Register */ -#define BCHP_SUN_L2_CPU_MASK_SET 0x00401810 /* CPU interrupt Mask Set Register */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR 0x00401814 /* CPU interrupt Mask Clear Register */ -#define BCHP_SUN_L2_PCI_STATUS 0x00401818 /* PCI interrupt Status Register */ -#define BCHP_SUN_L2_PCI_SET 0x0040181c /* PCI interrupt Set Register */ -#define BCHP_SUN_L2_PCI_CLEAR 0x00401820 /* PCI interrupt Clear Register */ -#define BCHP_SUN_L2_PCI_MASK_STATUS 0x00401824 /* PCI interrupt Mask Status Register */ -#define BCHP_SUN_L2_PCI_MASK_SET 0x00401828 /* PCI interrupt Mask Set Register */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR 0x0040182c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: CPU_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_CPU_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_CPU_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: CPU_STATUS :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_CPU_STATUS_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_CPU_STATUS_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: CPU_STATUS :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_CPU_STATUS_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_CPU_STATUS_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: CPU_STATUS :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_CPU_STATUS_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_CPU_STATUS_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: CPU_STATUS :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_CPU_STATUS_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_CPU_STATUS_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: CPU_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_CPU_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_CPU_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: CPU_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_CPU_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_CPU_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: CPU_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_CPU_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_CPU_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: CPU_STATUS :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_CPU_STATUS_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_CPU_STATUS_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: CPU_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_CPU_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_CPU_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: CPU_STATUS :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_CPU_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_CPU_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* SUN_L2 :: CPU_SET :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: CPU_SET :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: CPU_SET :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_CPU_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_CPU_SET_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: CPU_SET :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_CPU_SET_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_CPU_SET_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: CPU_SET :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_CPU_SET_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_CPU_SET_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: CPU_SET :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_CPU_SET_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_CPU_SET_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: CPU_SET :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_CPU_SET_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_CPU_SET_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: CPU_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: CPU_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: CPU_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: CPU_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: CPU_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: CPU_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: CPU_SET :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_CPU_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_CPU_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: CPU_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_CPU_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_CPU_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: CPU_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_CPU_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_CPU_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: CPU_SET :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_CPU_SET_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_CPU_SET_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: CPU_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_CPU_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_CPU_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: CPU_SET :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_CPU_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_CPU_SET_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: CPU_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_CPU_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_CPU_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: CPU_CLEAR :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_CPU_CLEAR_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_CPU_CLEAR_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: CPU_CLEAR :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_CPU_CLEAR_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_CPU_CLEAR_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: CPU_CLEAR :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_CPU_CLEAR_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_CPU_CLEAR_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: CPU_CLEAR :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_CPU_CLEAR_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_CPU_CLEAR_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: CPU_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_CPU_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_CPU_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: CPU_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_CPU_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_CPU_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: CPU_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_CPU_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_CPU_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: CPU_CLEAR :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_CPU_CLEAR_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_CPU_CLEAR_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: CPU_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_CPU_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_CPU_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: CPU_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_CPU_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_CPU_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: CPU_MASK_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: CPU_MASK_STATUS :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: CPU_MASK_STATUS :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: CPU_MASK_STATUS :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: CPU_MASK_STATUS :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: CPU_MASK_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_CPU_MASK_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: CPU_MASK_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_CPU_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: CPU_MASK_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_CPU_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: CPU_MASK_STATUS :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: CPU_MASK_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: CPU_MASK_STATUS :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: CPU_MASK_SET :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_CPU_MASK_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_CPU_MASK_SET_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: CPU_MASK_SET :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_CPU_MASK_SET_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_CPU_MASK_SET_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: CPU_MASK_SET :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_CPU_MASK_SET_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: CPU_MASK_SET :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_CPU_MASK_SET_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: CPU_MASK_SET :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_CPU_MASK_SET_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_CPU_MASK_SET_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: CPU_MASK_SET :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_CPU_MASK_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_CPU_MASK_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: CPU_MASK_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_CPU_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_CPU_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: CPU_MASK_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_CPU_MASK_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_CPU_MASK_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: CPU_MASK_SET :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: CPU_MASK_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_CPU_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_CPU_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: CPU_MASK_SET :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: CPU_MASK_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: CPU_MASK_CLEAR :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: CPU_MASK_CLEAR :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: CPU_MASK_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: CPU_MASK_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: CPU_MASK_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: CPU_MASK_CLEAR :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: CPU_MASK_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: CPU_MASK_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: PCI_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_PCI_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_PCI_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: PCI_STATUS :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_PCI_STATUS_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_PCI_STATUS_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: PCI_STATUS :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_PCI_STATUS_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_PCI_STATUS_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: PCI_STATUS :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_PCI_STATUS_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_PCI_STATUS_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: PCI_STATUS :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_PCI_STATUS_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_PCI_STATUS_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: PCI_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_PCI_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_PCI_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: PCI_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_PCI_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_PCI_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: PCI_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_PCI_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_PCI_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: PCI_STATUS :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_PCI_STATUS_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_PCI_STATUS_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: PCI_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_PCI_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_PCI_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: PCI_STATUS :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_PCI_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_PCI_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* SUN_L2 :: PCI_SET :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: PCI_SET :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: PCI_SET :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_PCI_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_PCI_SET_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: PCI_SET :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_PCI_SET_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_PCI_SET_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: PCI_SET :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_PCI_SET_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_PCI_SET_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: PCI_SET :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_PCI_SET_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_PCI_SET_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: PCI_SET :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_PCI_SET_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_PCI_SET_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: PCI_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: PCI_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: PCI_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: PCI_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: PCI_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: PCI_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: PCI_SET :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_PCI_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_PCI_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: PCI_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_PCI_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_PCI_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: PCI_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_PCI_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_PCI_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: PCI_SET :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_PCI_SET_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_PCI_SET_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: PCI_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_PCI_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_PCI_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: PCI_SET :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_PCI_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_PCI_SET_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: PCI_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_PCI_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_PCI_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: PCI_CLEAR :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_PCI_CLEAR_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_PCI_CLEAR_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: PCI_CLEAR :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_PCI_CLEAR_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_PCI_CLEAR_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: PCI_CLEAR :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_PCI_CLEAR_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_PCI_CLEAR_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: PCI_CLEAR :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_PCI_CLEAR_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_PCI_CLEAR_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: PCI_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_PCI_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_PCI_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: PCI_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_PCI_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_PCI_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: PCI_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_PCI_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_PCI_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: PCI_CLEAR :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_PCI_CLEAR_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_PCI_CLEAR_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: PCI_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_PCI_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_PCI_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: PCI_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_PCI_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_PCI_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: PCI_MASK_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: PCI_MASK_STATUS :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: PCI_MASK_STATUS :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: PCI_MASK_STATUS :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: PCI_MASK_STATUS :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: PCI_MASK_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_PCI_MASK_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: PCI_MASK_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_PCI_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: PCI_MASK_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_PCI_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: PCI_MASK_STATUS :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: PCI_MASK_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: PCI_MASK_STATUS :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: PCI_MASK_SET :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_PCI_MASK_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_PCI_MASK_SET_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: PCI_MASK_SET :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_PCI_MASK_SET_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_PCI_MASK_SET_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: PCI_MASK_SET :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_PCI_MASK_SET_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: PCI_MASK_SET :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_PCI_MASK_SET_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: PCI_MASK_SET :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_PCI_MASK_SET_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_PCI_MASK_SET_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: PCI_MASK_SET :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_PCI_MASK_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_PCI_MASK_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: PCI_MASK_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_PCI_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_PCI_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: PCI_MASK_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_PCI_MASK_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_PCI_MASK_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: PCI_MASK_SET :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: PCI_MASK_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_PCI_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_PCI_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: PCI_MASK_SET :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TIMEOUT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_31 [31:31] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_31_MASK 0x80000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_31_SHIFT 31 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_30 [30:30] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_30_MASK 0x40000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_30_SHIFT 30 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_29 [29:29] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_29_MASK 0x20000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_29_SHIFT 29 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_28 [28:28] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_28_MASK 0x10000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_28_SHIFT 28 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_27 [27:27] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_27_MASK 0x08000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_27_SHIFT 27 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_26 [26:26] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_26_MASK 0x04000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_26_SHIFT 26 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_25 [25:25] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_25_MASK 0x02000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_25_SHIFT 25 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_24 [24:24] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_24_MASK 0x01000000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_24_SHIFT 24 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_23 [23:23] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_23_MASK 0x00800000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_23_SHIFT 23 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_22 [22:22] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_22_MASK 0x00400000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_22_SHIFT 22 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_21 [21:21] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_21_MASK 0x00200000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_21_SHIFT 21 - -/* SUN_L2 :: PCI_MASK_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 - -/* SUN_L2 :: PCI_MASK_CLEAR :: AUX_INTR [19:19] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_AUX_INTR_MASK 0x00080000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_AUX_INTR_SHIFT 19 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SERS_PKT_ERR [18:18] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_PKT_ERR_MASK 0x00040000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_PKT_ERR_SHIFT 18 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SERS_CLK_ERR [17:17] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_CLK_ERR_MASK 0x00020000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_CLK_ERR_SHIFT 17 - -/* union - case mapped_buffer_mode [16:13] */ -/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 - -/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 - -/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 - -/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 - -/* union - case cmd_fifo_mode [16:13] */ -/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 - -/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 - -/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 - -/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 - -/* SUN_L2 :: PCI_MASK_CLEAR :: SERS_R_PKT [12:12] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_R_PKT_MASK 0x00001000 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_R_PKT_SHIFT 12 - -/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 - -/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 - -/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 - -/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 - -/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 - -/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 - -/* SUN_L2 :: PCI_MASK_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 - -/* SUN_L2 :: PCI_MASK_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 - -/* SUN_L2 :: PCI_MASK_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 - -/* SUN_L2 :: PCI_MASK_CLEAR :: GISB_TEA_INTR [02:02] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TEA_INTR_MASK 0x00000004 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TEA_INTR_SHIFT 2 - -/* SUN_L2 :: PCI_MASK_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 - -/* SUN_L2 :: PCI_MASK_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ -#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 -#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 - -#endif /* #ifndef BCHP_SUN_L2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,120 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sun_rg.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:20p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:19 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:20p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SUN_RG_H__ -#define BCHP_SUN_RG_H__ - -/*************************************************************************** - *SUN_RG - Registers for the Sundry block's RG bridge - ***************************************************************************/ -#define BCHP_SUN_RG_REVISION 0x00401000 /* RG Bridge Revision */ -#define BCHP_SUN_RG_CTRL 0x00401004 /* RG Bridge Control Register */ -#define BCHP_SUN_RG_SW_RESET_0 0x00401008 /* RG Bridge Software Reset 0 Register */ -#define BCHP_SUN_RG_SW_RESET_1 0x0040100c /* RG Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - RG Bridge Revision - ***************************************************************************/ -/* SUN_RG :: REVISION :: reserved0 [31:16] */ -#define BCHP_SUN_RG_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_SUN_RG_REVISION_reserved0_SHIFT 16 - -/* SUN_RG :: REVISION :: MAJOR [15:08] */ -#define BCHP_SUN_RG_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_SUN_RG_REVISION_MAJOR_SHIFT 8 - -/* SUN_RG :: REVISION :: MINOR [07:00] */ -#define BCHP_SUN_RG_REVISION_MINOR_MASK 0x000000ff -#define BCHP_SUN_RG_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - RG Bridge Control Register - ***************************************************************************/ -/* SUN_RG :: CTRL :: reserved0 [31:02] */ -#define BCHP_SUN_RG_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_SUN_RG_CTRL_reserved0_SHIFT 2 - -/* SUN_RG :: CTRL :: rbus_error_intr [01:01] */ -#define BCHP_SUN_RG_CTRL_rbus_error_intr_MASK 0x00000002 -#define BCHP_SUN_RG_CTRL_rbus_error_intr_SHIFT 1 -#define BCHP_SUN_RG_CTRL_rbus_error_intr_INTR_DISABLE 0 -#define BCHP_SUN_RG_CTRL_rbus_error_intr_INTR_ENABLE 1 - -/* SUN_RG :: CTRL :: reserved1 [00:00] */ -#define BCHP_SUN_RG_CTRL_reserved1_MASK 0x00000001 -#define BCHP_SUN_RG_CTRL_reserved1_SHIFT 0 - -/*************************************************************************** - *SW_RESET_0 - RG Bridge Software Reset 0 Register - ***************************************************************************/ -/* SUN_RG :: SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_SUN_RG_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_SUN_RG_SW_RESET_0_reserved0_SHIFT 1 - -/* SUN_RG :: SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - -/*************************************************************************** - *SW_RESET_1 - RG Bridge Software Reset 1 Register - ***************************************************************************/ -/* SUN_RG :: SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_SUN_RG_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_SUN_RG_SW_RESET_1_reserved0_SHIFT 1 - -/* SUN_RG :: SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - -#endif /* #ifndef BCHP_SUN_RG_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rgr.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rgr.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rgr.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rgr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,130 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sun_rgr.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:20p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:14 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rgr.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:20p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SUN_RGR_H__ -#define BCHP_SUN_RGR_H__ - -/*************************************************************************** - *SUN_RGR - Registers for the Sundry block's RGR bridge - ***************************************************************************/ -#define BCHP_SUN_RGR_REVISION 0x00400800 /* RGR Bridge Revision */ -#define BCHP_SUN_RGR_CTRL 0x00400804 /* RGR Bridge Control Register */ -#define BCHP_SUN_RGR_RBUS_TIMER 0x00400808 /* RGR Bridge RBUS Timer Register */ -#define BCHP_SUN_RGR_SW_RESET_0 0x0040080c /* RGR Bridge Software Reset 0 Register */ -#define BCHP_SUN_RGR_SW_RESET_1 0x00400810 /* RGR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - RGR Bridge Revision - ***************************************************************************/ -/* SUN_RGR :: REVISION :: reserved0 [31:16] */ -#define BCHP_SUN_RGR_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_SUN_RGR_REVISION_reserved0_SHIFT 16 - -/* SUN_RGR :: REVISION :: MAJOR [15:08] */ -#define BCHP_SUN_RGR_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_SUN_RGR_REVISION_MAJOR_SHIFT 8 - -/* SUN_RGR :: REVISION :: MINOR [07:00] */ -#define BCHP_SUN_RGR_REVISION_MINOR_MASK 0x000000ff -#define BCHP_SUN_RGR_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - RGR Bridge Control Register - ***************************************************************************/ -/* SUN_RGR :: CTRL :: reserved0 [31:02] */ -#define BCHP_SUN_RGR_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_SUN_RGR_CTRL_reserved0_SHIFT 2 - -/* SUN_RGR :: CTRL :: rbus_error_intr [01:01] */ -#define BCHP_SUN_RGR_CTRL_rbus_error_intr_MASK 0x00000002 -#define BCHP_SUN_RGR_CTRL_rbus_error_intr_SHIFT 1 -#define BCHP_SUN_RGR_CTRL_rbus_error_intr_INTR_DISABLE 0 -#define BCHP_SUN_RGR_CTRL_rbus_error_intr_INTR_ENABLE 1 - -/* SUN_RGR :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_SUN_RGR_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_SUN_RGR_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_SUN_RGR_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_SUN_RGR_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *RBUS_TIMER - RGR Bridge RBUS Timer Register - ***************************************************************************/ -/* SUN_RGR :: RBUS_TIMER :: reserved0 [31:16] */ -#define BCHP_SUN_RGR_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define BCHP_SUN_RGR_RBUS_TIMER_reserved0_SHIFT 16 - -/* SUN_RGR :: RBUS_TIMER :: timer_value [15:00] */ -#define BCHP_SUN_RGR_RBUS_TIMER_timer_value_MASK 0x0000ffff -#define BCHP_SUN_RGR_RBUS_TIMER_timer_value_SHIFT 0 - -/*************************************************************************** - *SW_RESET_0 - RGR Bridge Software Reset 0 Register - ***************************************************************************/ -/* SUN_RGR :: SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_SUN_RGR_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_SUN_RGR_SW_RESET_0_reserved0_SHIFT 1 - -/* SUN_RGR :: SW_RESET_0 :: ccb_arbiter_sw_reset [00:00] */ -#define BCHP_SUN_RGR_SW_RESET_0_ccb_arbiter_sw_reset_MASK 0x00000001 -#define BCHP_SUN_RGR_SW_RESET_0_ccb_arbiter_sw_reset_SHIFT 0 - -/*************************************************************************** - *SW_RESET_1 - RGR Bridge Software Reset 1 Register - ***************************************************************************/ -/* SUN_RGR :: SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_SUN_RGR_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_SUN_RGR_SW_RESET_1_reserved0_SHIFT 1 - -/* SUN_RGR :: SW_RESET_1 :: unused_sw_reset [00:00] */ -#define BCHP_SUN_RGR_SW_RESET_1_unused_sw_reset_MASK 0x00000001 -#define BCHP_SUN_RGR_SW_RESET_1_unused_sw_reset_SHIFT 0 - -#endif /* #ifndef BCHP_SUN_RGR_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1790 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_sun_top_ctrl.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:20p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:07 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:20p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_SUN_TOP_CTRL_H__ -#define BCHP_SUN_TOP_CTRL_H__ - -/*************************************************************************** - *SUN_TOP_CTRL - Top Control registers - ***************************************************************************/ -#define BCHP_SUN_TOP_CTRL_PROD_REVISION 0x00404000 /* Product Revision ID */ -#define BCHP_SUN_TOP_CTRL_SUN_REVISION 0x00404004 /* Sundry Revision ID */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404008 /* Reset control */ -#define BCHP_SUN_TOP_CTRL_NMI_CTRL 0x00404010 /* Control register for NMI */ -#define BCHP_SUN_TOP_CTRL_SW_RESET 0x00404014 /* Software reset register */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404018 /* Reset history */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ -#define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ -#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ -#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ -#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x004040bc /* Scratch register */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x004040c0 /* Spare control bits reserved for future use */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x00404180 /* Bypass clock unselect register 0 */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404200 /* Test port control */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404204 /* Testport peek register */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404208 /* Testport poke register */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040420c /* Testport peek register */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404210 /* Testport poke register */ -#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404214 /* EJTAG input bus enables */ -#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404218 /* EJTAG output select */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL 0x0040421c /* UART Router select */ -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404300 /* Serial Slave Port configuration register */ -#define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404320 /* SERS Revision Register */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404324 /* SERS Configuration Register */ -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404400 /* Block select for RO testmode */ -#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL 0x00404500 /* Test_mode control register */ -#define BCHP_SUN_TOP_CTRL_TEST_MODE 0x00404504 /* Register source for test_mode */ -#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE 0x00404508 /* Register source for sub_test_mode */ -#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE 0x0040450c /* Final latched testmode value */ -#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE 0x00404510 /* Final latched sub-testmode value */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL 0x00404600 /* Control register for Power Controller */ -#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS 0x00404604 /* Power Management IRQ input status */ -#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT 0x00404608 /* Power Management Wait counter in place of Wait for MIPS IRQ */ - -/*************************************************************************** - *PROD_REVISION - Product Revision ID - ***************************************************************************/ -/* SUN_TOP_CTRL :: PROD_REVISION :: product_revision [31:00] */ -#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_SHIFT 0 - -/*************************************************************************** - *SUN_REVISION - Sundry Revision ID - ***************************************************************************/ -/* SUN_TOP_CTRL :: SUN_REVISION :: reserved0 [31:16] */ -#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_SHIFT 16 - -/* SUN_TOP_CTRL :: SUN_REVISION :: sundry_revision [15:00] */ -#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_MASK 0x0000ffff -#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_SHIFT 0 - -/*************************************************************************** - *RESET_CTRL - Reset control - ***************************************************************************/ -/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_monitor [31:31] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_MASK 0x80000000 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_SHIFT 31 - -/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_monitor [30:30] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_MASK 0x40000000 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_SHIFT 30 - -/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_def_val_monitor [29:29] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_MASK 0x20000000 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_SHIFT 29 - -/* SUN_TOP_CTRL :: RESET_CTRL :: reset_ext_mode_monitor [28:28] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_MASK 0x10000000 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_SHIFT 28 - -/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_205_monitor [27:27] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_MASK 0x08000000 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_SHIFT 27 - -/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_200_monitor [26:26] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_MASK 0x04000000 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_SHIFT 26 - -/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [25:12] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0x03fff000 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 12 - -/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [11:11] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000800 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 11 - -/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable_lock [10:10] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_MASK 0x00000400 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_SHIFT 10 - -/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable [09:09] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_SHIFT 9 - -/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable_lock [08:08] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_MASK 0x00000100 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_SHIFT 8 - -/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable [07:07] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_MASK 0x00000080 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_SHIFT 7 - -/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [06:06] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000040 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 6 - -/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable [05:05] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000020 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 5 - -/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_polarity [04:04] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000010 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 4 - -/* SUN_TOP_CTRL :: RESET_CTRL :: master_reset_en [03:03] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_SHIFT 3 - -/* SUN_TOP_CTRL :: RESET_CTRL :: reserved1 [02:01] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_MASK 0x00000006 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_SHIFT 1 - -/* SUN_TOP_CTRL :: RESET_CTRL :: sc_insert_reset_en [00:00] */ -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_SHIFT 0 - -/*************************************************************************** - *NMI_CTRL - Control register for NMI - ***************************************************************************/ -/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */ -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_MASK 0x80000000 -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_SHIFT 31 - -/* SUN_TOP_CTRL :: NMI_CTRL :: reserved0 [30:03] */ -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_MASK 0x7ffffff8 -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_SHIFT 3 - -/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */ -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT 2 - -/* SUN_TOP_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */ -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT 1 - -/* SUN_TOP_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */ -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT 0 - -/*************************************************************************** - *SW_RESET - Software reset register - ***************************************************************************/ -/* SUN_TOP_CTRL :: SW_RESET :: chip_master_reset [31:31] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_MASK 0x80000000 -#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_SHIFT 31 - -/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_1shot [30:30] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_MASK 0x40000000 -#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_SHIFT 30 - -/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_1shot [29:29] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_MASK 0x20000000 -#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_SHIFT 29 - -/* SUN_TOP_CTRL :: SW_RESET :: reserved0 [28:22] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_MASK 0x1fc00000 -#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_SHIFT 22 - -/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_level [21:21] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_MASK 0x00200000 -#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_SHIFT 21 - -/* SUN_TOP_CTRL :: SW_RESET :: reserved1 [20:12] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_MASK 0x001ff000 -#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_SHIFT 12 - -/* SUN_TOP_CTRL :: SW_RESET :: xpt_sw_reset [11:11] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_MASK 0x00000800 -#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_SHIFT 11 - -/* SUN_TOP_CTRL :: SW_RESET :: bvn_sw_reset [10:10] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_MASK 0x00000400 -#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_SHIFT 10 - -/* SUN_TOP_CTRL :: SW_RESET :: sharf_sw_reset [09:09] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_sharf_sw_reset_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_SW_RESET_sharf_sw_reset_SHIFT 9 - -/* SUN_TOP_CTRL :: SW_RESET :: avd0_sw_reset [08:08] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_MASK 0x00000100 -#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_SHIFT 8 - -/* SUN_TOP_CTRL :: SW_RESET :: misc_sw_reset [07:07] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_misc_sw_reset_MASK 0x00000080 -#define BCHP_SUN_TOP_CTRL_SW_RESET_misc_sw_reset_SHIFT 7 - -/* SUN_TOP_CTRL :: SW_RESET :: ddr0_sw_reset [06:06] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_MASK 0x00000040 -#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_SHIFT 6 - -/* SUN_TOP_CTRL :: SW_RESET :: blink_sw_reset [05:05] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_blink_sw_reset_MASK 0x00000020 -#define BCHP_SUN_TOP_CTRL_SW_RESET_blink_sw_reset_SHIFT 5 - -/* SUN_TOP_CTRL :: SW_RESET :: jtag_otp_sw_reset [04:04] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_MASK 0x00000010 -#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_SHIFT 4 - -/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_level [03:03] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_SHIFT 3 - -/* SUN_TOP_CTRL :: SW_RESET :: reserved2 [02:01] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_MASK 0x00000006 -#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_SHIFT 1 - -/* SUN_TOP_CTRL :: SW_RESET :: sundry_sw_reset [00:00] */ -#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_SHIFT 0 - -/*************************************************************************** - *RESET_HISTORY - Reset history - ***************************************************************************/ -/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:12] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfffff000 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 12 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset [11:11] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_MASK 0x00000800 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_SHIFT 11 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_sft_sft_rst_b [10:10] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_MASK 0x00000400 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_SHIFT 10 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_hrd_sft_rst_b [09:09] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_SHIFT 9 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [08:08] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000100 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 8 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset [07:07] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_MASK 0x00000080 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_SHIFT 7 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: special_sw_reset [06:06] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_MASK 0x00000040 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_SHIFT 6 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved1 [05:05] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_MASK 0x00000020 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_SHIFT 5 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [04:04] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000010 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 4 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [03:03] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 3 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 - -/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 - -/*************************************************************************** - *STRAP_VALUE_0 - Strapping values - ***************************************************************************/ -/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:04] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffffff0 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 4 - -/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_test_enable [03:03] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_test_enable_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_test_enable_SHIFT 3 - -/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_config_use_default [02:02] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_default_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_default_SHIFT 2 - -/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_eeprom_16_bit [01:01] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_eeprom_16_bit_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_eeprom_16_bit_SHIFT 1 - -/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_config_use_otp [00:00] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_otp_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_otp_SHIFT 0 - -/*************************************************************************** - *STRAP_VALUE_1 - Strapping values - ***************************************************************************/ -/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:03] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xfffffff8 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 3 - -/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_2 [02:02] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_SHIFT 2 - -/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_SHIFT 1 - -/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_SHIFT 0 - -/*************************************************************************** - *BOND_STATUS - Bond option value register - ***************************************************************************/ -/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ -#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 - -/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ -#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 - -/*************************************************************************** - *OTP_OPTION_TEST_0 - OTP option test register - ***************************************************************************/ -/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [31:05] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0xffffffe0 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 5 - -/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option0_spare_1 [04:04] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_1_MASK 0x00000010 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_1_SHIFT 4 - -/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option0_spare_0 [03:03] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_0_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_0_SHIFT 3 - -/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [02:01] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000006 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 1 - -/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [00:00] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 0 - -/*************************************************************************** - *OTP_OPTION_TEST_1 - OTP option test register - ***************************************************************************/ -/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved0 [31:01] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_MASK 0xfffffffe -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_SHIFT 1 - -/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_0_SHIFT 0 - -/*************************************************************************** - *OTP_OPTION_STATUS_0 - OTP option status register - ***************************************************************************/ -/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [31:05] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0xffffffe0 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 5 - -/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option0_spare_1 [04:04] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_1_MASK 0x00000010 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_1_SHIFT 4 - -/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option0_spare_0 [03:03] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_0_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_0_SHIFT 3 - -/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [02:01] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000006 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 1 - -/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [00:00] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 0 - -/*************************************************************************** - *OTP_OPTION_STATUS_1 - OTP option status register - ***************************************************************************/ -/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved0 [31:01] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_MASK 0xfffffffe -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_SHIFT 1 - -/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_0_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_0 - Semaphore channel 0 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_1 - Semaphore channel 1 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_2 - Semaphore channel 2 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_3 - Semaphore channel 3 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_4 - Semaphore channel 4 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_5 - Semaphore channel 5 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_6 - Semaphore channel 6 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_7 - Semaphore channel 7 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_8 - Semaphore channel 8 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_9 - Semaphore channel 9 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_10 - Semaphore channel 10 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_11 - Semaphore channel 11 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_12 - Semaphore channel 12 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_13 - Semaphore channel 13 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_14 - Semaphore channel 14 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *SEMAPHORE_15 - Semaphore channel 15 - ***************************************************************************/ -/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 - -/*************************************************************************** - *GEN_WATCHDOG_0 - General watchdog timer 0 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ -#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 - -/*************************************************************************** - *GEN_WATCHDOG_1 - General watchdog timer 1 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ -#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_0 - General control register 0 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_reserved [31:25] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_MASK 0xfe000000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_SHIFT 25 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_burst_stat_sel [24:24] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_MASK 0x01000000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_SHIFT 24 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_access_mode [23:22] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_MASK 0x00c00000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_SHIFT 22 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_prog_en [21:21] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_MASK 0x00200000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_SHIFT 21 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_debug_mode [20:20] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_MASK 0x00100000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_SHIFT 20 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_continue_on_fail [19:19] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_MASK 0x00080000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_SHIFT 19 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_time_margin [18:16] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_MASK 0x00070000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_SHIFT 16 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_sadbyp [15:15] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_MASK 0x00008000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_SHIFT 15 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_unused [14:14] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_MASK 0x00004000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_SHIFT 14 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pbyp [13:13] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_MASK 0x00002000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_SHIFT 13 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pcount [12:10] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_MASK 0x00001c00 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_SHIFT 10 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_vsel [09:06] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_MASK 0x000003c0 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_SHIFT 6 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_prog_sel [05:05] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_MASK 0x00000020 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_SHIFT 5 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_command [04:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_MASK 0x0000001e -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_start [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_1 - General control register 1 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_addr [31:16] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_MASK 0xffff0000 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_SHIFT 16 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [15:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0x0000fffe -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_mode [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_2 - General control register 2 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl_2 [31:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl_2_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl_2_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_3 - General control register 3 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:04] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffff0 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 4 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_3 [03:03] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_3_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_3_SHIFT 3 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_2 [02:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_2_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_2_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_4 - General control register 4 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffe -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_5 - General control register 5 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_7 [07:07] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_7_MASK 0x00000080 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_7_SHIFT 7 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_6 [06:06] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_6_MASK 0x00000040 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_6_SHIFT 6 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_5 [05:05] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_5_MASK 0x00000020 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_5_SHIFT 5 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_4 [04:04] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_4_MASK 0x00000010 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_4_SHIFT 4 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_3 [03:03] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_3_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_3_SHIFT 3 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_2 [02:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_2_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_2_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_STATUS_0 - General status register 0 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: jtag_otp_data_out [31:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_data_out_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_data_out_SHIFT 0 - -/*************************************************************************** - *GENERAL_STATUS_1 - General status register 1 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:08] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xffffff00 -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 8 - -/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: jtag_otp_status [07:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_status_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_status_SHIFT 0 - -/*************************************************************************** - *GENERAL_STATUS_2 - General status register 2 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:04] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffff0 -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 4 - -/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_03 [03:03] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_SHIFT 3 - -/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_02 [02:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_01 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_00 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0 - -/*************************************************************************** - *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 - ***************************************************************************/ -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1 - -/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0 - -/*************************************************************************** - *UNCLEARED_SCRATCH - Scratch register - ***************************************************************************/ -/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ -#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 - -/*************************************************************************** - *SPARE_CTRL - Spare control bits reserved for future use - ***************************************************************************/ -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 - -/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 - -/*************************************************************************** - *PIN_MUX_CTRL_0 - Pinmux control register 0 - ***************************************************************************/ -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_07 [31:28] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_MASK 0xf0000000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_SHIFT 28 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_GPIO_07 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_SPARE0_ON_GPIO_07 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_TEST_OUT0 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_TP_IN7 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_TP_OUT7 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_RC_TP_OUT7 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_06 [27:24] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_MASK 0x0f000000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_SHIFT 24 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_GPIO_06 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_SPARE0_ON_GPIO_06 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_TEST_ACK 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_TP_IN6 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_TP_OUT6 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_RC_TP_OUT6 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_05 [23:20] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_MASK 0x00f00000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_SHIFT 20 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_GPIO_05 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_DBG_UART2_RX 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_TEST_REQ 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_TP_IN5 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_TP_OUT5 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_RC_TP_OUT5 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_04 [19:16] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_MASK 0x000f0000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_SHIFT 16 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_GPIO_04 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_DBG_UART2_TX 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_TEST_CLK 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_TP_IN4 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_TP_OUT4 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_RC_TP_OUT4 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_03 [15:12] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_MASK 0x0000f000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_SHIFT 12 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_GPIO_03 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_DBG_UART1_RX 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_TEST_IN3 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_TP_IN3 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_TP_OUT3 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_RC_TP_OUT3 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [11:08] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK 0x00000f00 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT 8 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DBG_UART1_TX 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_TEST_IN2 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_TP_IN2 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_TP_OUT2 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_RC_TP_OUT2 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [07:04] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK 0x000000f0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DBG_UART0_RX 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_TEST_IN1 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_TP_IN1 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_TP_OUT1 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_RC_TP_OUT1 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [03:00] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK 0x0000000f -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DBG_UART0_TX 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_TEST_IN0 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_TP_IN0 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_TP_OUT0 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_RC_TP_OUT0 5 - -/*************************************************************************** - *PIN_MUX_CTRL_1 - Pinmux control register 1 - ***************************************************************************/ -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: reserved0 [31:24] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_reserved0_MASK 0xff000000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_reserved0_SHIFT 24 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: eeprom_data [23:20] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_MASK 0x00f00000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_SHIFT 20 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_EEPROM_DATA 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_PCIE_MDIO_RST 1 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: eeprom_clk [19:16] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_MASK 0x000f0000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_SHIFT 16 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_EEPROM_CLK 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_PCIE_MDC 1 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_11 [15:12] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_MASK 0x0000f000 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_SHIFT 12 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_GPIO_11 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_PCIE_MDIO 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_SPARE0_ON_GPIO_11 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_TP_IN11 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_TP_OUT11 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_RC_TP_OUT11 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [11:08] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK 0x00000f00 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT 8 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_RO_IO_TESTOUT 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_TEST_OUT3 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_TP_IN10 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_TP_OUT10 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_RC_TP_OUT10 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [07:04] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK 0x000000f0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_RO_CORE_TESTOUT 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_TEST_OUT2 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_TP_IN9 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_TP_OUT9 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_RC_TP_OUT9 5 - -/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [03:00] */ -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK 0x0000000f -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08 0 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SPARE0_ON_GPIO_08 1 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_TEST_OUT1 2 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_TP_IN8 3 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_TP_OUT8 4 -#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_RC_TP_OUT8 5 - -/*************************************************************************** - *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 - ***************************************************************************/ -/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */ -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xfffffff0 -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 4 - -/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_low_pwr_n [03:03] */ -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_low_pwr_n_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_low_pwr_n_SHIFT 3 - -/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_eeprom_clk [02:02] */ -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_eeprom_clk_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_eeprom_clk_SHIFT 2 - -/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_bsc_s_sda [01:01] */ -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_sda_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_sda_SHIFT 1 - -/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_bsc_s_scl [00:00] */ -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_scl_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_scl_SHIFT 0 - -/*************************************************************************** - *TEST_PORT_CTRL - Test port control - ***************************************************************************/ -/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sundry_local_tp_out_sel [31:28] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MASK 0xf0000000 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SHIFT 28 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_0 0 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_1 1 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_FP_RST_CNT 2 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MISC_TEST 3 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SSP 4 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_OUT_POKE_REG 5 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_IN 6 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_0 7 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_1 8 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_2 9 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_3 10 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_STATUS 11 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_IRQ_IN 12 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_13 13 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_14 14 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TOP_AUX_TP_OUT 15 - -/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 - -/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 - -/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 - -/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD 0 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MISC 1 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BLINK 2 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DDR_IF0 3 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SUN 4 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 5 -#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UNUSED_31 31 - -/*************************************************************************** - *TEST_PORT_OUT_PEEK - Testport peek register - ***************************************************************************/ -/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 - -/*************************************************************************** - *TEST_PORT_OUT_POKE - Testport poke register - ***************************************************************************/ -/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 - -/*************************************************************************** - *TEST_PORT_IN_PEEK - Testport peek register - ***************************************************************************/ -/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 - -/*************************************************************************** - *TEST_PORT_IN_POKE - Testport poke register - ***************************************************************************/ -/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ -#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 - -/*************************************************************************** - *EJTAG_INPUT_EN - EJTAG input bus enables - ***************************************************************************/ -/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [01:00] */ -#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x00000003 -#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 -#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 -#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_ARM_CPU_ONE_HOT 2 - -/*************************************************************************** - *EJTAG_OUTPUT_SEL - EJTAG output select - ***************************************************************************/ -/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [01:00] */ -#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x00000003 -#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 -#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 -#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_ARM_CPU 1 - -/*************************************************************************** - *UART_ROUTER_SEL - UART Router select - ***************************************************************************/ -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK 0xf0000000 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT 28 - -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK 0x0f000000 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT 24 - -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK 0x00f00000 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT 20 - -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK 0x000f0000 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT 16 - -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK 0x0000f000 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT 12 - -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK 0x00000f00 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT 8 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU 0 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_ARM 1 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL 2 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL 3 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15 - -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK 0x000000f0 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT 4 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU 0 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_ARM 1 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL 2 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL 3 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15 - -/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */ -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK 0x0000000f -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT 0 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU 0 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_ARM 1 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL 2 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL 3 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14 -#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15 - -/*************************************************************************** - *SSP_CONFIG - Serial Slave Port configuration register - ***************************************************************************/ -/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 - -/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 - -/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 - -/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 - -/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 - -/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 - -/*************************************************************************** - *SERS_REV - SERS Revision Register - ***************************************************************************/ -/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ -#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 -#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 - -/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ -#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 -#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 - -/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ -#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff -#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 - -/*************************************************************************** - *SERS_CFG - SERS Configuration Register - ***************************************************************************/ -/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 - -/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 - -/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 - -/* union - case mapped_buffer_mode [26:08] */ -/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 - -/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 - -/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 - -/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 - -/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 - -/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 - -/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 - -/* union - case cmd_fifo_mode [26:08] */ -/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 - -/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 - -/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 - -/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 - -/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 - -/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 - -/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe -#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 - -/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ -#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 - -/*************************************************************************** - *SERS_CMD_BUF_%i - Host Serial Write Command Buffer - ***************************************************************************/ -#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404328 -#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 -#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 -#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *SERS_CMD_BUF_%i - Host Serial Write Command Buffer - ***************************************************************************/ -/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ -#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 - - -/*************************************************************************** - *SERS_STAT_BUF_%i - Host Serial Read Status Buffer - ***************************************************************************/ -#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404348 -#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 -#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 -#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *SERS_STAT_BUF_%i - Host Serial Read Status Buffer - ***************************************************************************/ -/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ -#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 - - -/*************************************************************************** - *RO_TEST_BLOCK_SEL - Block select for RO testmode - ***************************************************************************/ -/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */ -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xffffffe0 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 5 - -/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [04:03] */ -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000018 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 3 - -/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [02:00] */ -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000007 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SUN_RO_TEST_ID 1 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DDR_IF_RO_TEST_ID 2 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MISC_RO_TEST_ID 3 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_BLINK_RO_TEST_ID 4 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_AVD_RO_TEST_ID 5 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_RES0_RO_TEST_ID 6 -#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_CLK_GEN_RO_TEST_ID 7 - -/*************************************************************************** - *TEST_MODE_CTRL - Test_mode control register - ***************************************************************************/ -/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: reserved0 [31:01] */ -#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_SHIFT 1 - -/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: use_test_mode_reg_src [00:00] */ -#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_SHIFT 0 - -/*************************************************************************** - *TEST_MODE - Register source for test_mode - ***************************************************************************/ -/* SUN_TOP_CTRL :: TEST_MODE :: reserved0 [31:04] */ -#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_MASK 0xfffffff0 -#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_SHIFT 4 - -/* SUN_TOP_CTRL :: TEST_MODE :: test_mode [03:00] */ -#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_MASK 0x0000000f -#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_SHIFT 0 - -/*************************************************************************** - *SUB_TEST_MODE - Register source for sub_test_mode - ***************************************************************************/ -/* SUN_TOP_CTRL :: SUB_TEST_MODE :: reserved0 [31:02] */ -#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_MASK 0xfffffffc -#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_SHIFT 2 - -/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [01:01] */ -#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 1 - -/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT 0 - -/*************************************************************************** - *LATCHED_TEST_MODE - Final latched testmode value - ***************************************************************************/ -/* SUN_TOP_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */ -#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0 - -/*************************************************************************** - *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value - ***************************************************************************/ -/* SUN_TOP_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */ -#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff -#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0 - -/*************************************************************************** - *PM_CTRL - Control register for Power Controller - ***************************************************************************/ -/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_count_upper_bits [31:20] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_MASK 0xfff00000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_SHIFT 20 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_counter_active [19:19] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_MASK 0x00080000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_SHIFT 19 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_rst_clock_div [18:18] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_MASK 0x00040000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_SHIFT 18 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_pwrdn_pll_req [17:17] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_MASK 0x00020000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_SHIFT 17 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cml_clocks [16:16] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_MASK 0x00010000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_SHIFT 16 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_all_clocks [15:15] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_MASK 0x00008000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_SHIFT 15 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cpu_clock [14:14] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_MASK 0x00004000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_SHIFT 14 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_avd_rptd_clock [13:13] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_MASK 0x00002000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_SHIFT 13 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_pll_lock [12:12] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_MASK 0x00001000 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_SHIFT 12 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_dram_ready_for_pwrdn [11:11] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_MASK 0x00000800 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_SHIFT 11 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_bsp_ready_for_pwrdn [10:10] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_MASK 0x00000400 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_SHIFT 10 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_mips_ready_for_pwrdn [09:09] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_MASK 0x00000200 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_SHIFT 9 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_sec_avd_rptd_clk_disable [08:08] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_MASK 0x00000100 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_SHIFT 8 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_state [07:04] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_MASK 0x000000f0 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_SHIFT 4 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_ACTIVE 0 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_PWRDN_RDY 1 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_AVD_RPTD 2 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_CPU 3 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_STANDBY 4 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY 5 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY_WITH_PLLS_ON 6 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_RESET_216_108_CLKS 7 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_ACTIVE 8 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_power_ctrl_disable [03:03] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_MASK 0x00000008 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_SHIFT 3 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK 0x00000004 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT 2 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK 0x00000002 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT 1 - -/* SUN_TOP_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */ -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT 0 - -/*************************************************************************** - *PM_IRQ_INPUT_STATUS - Power Management IRQ input status - ***************************************************************************/ -/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: reserved0 [31:01] */ -#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_SHIFT 1 - -/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: spare_wakeup_event_0 [00:00] */ -#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_MASK 0x00000001 -#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_SHIFT 0 - -/*************************************************************************** - *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ - ***************************************************************************/ -/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */ -#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK 0xffff0000 -#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT 16 - -/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */ -#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK 0x0000ffff -#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0 - -#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rgr_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rgr_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rgr_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rgr_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,126 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_tgt_rgr_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:21p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:57 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rgr_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:21p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_TGT_RGR_BRIDGE_H__ -#define BCHP_TGT_RGR_BRIDGE_H__ - -/*************************************************************************** - *TGT_RGR_BRIDGE - TGT RGR Bridge Registers - ***************************************************************************/ -#define BCHP_TGT_RGR_BRIDGE_REVISION 0x00500780 /* PCIE RGR Bridge Revision Register */ -#define BCHP_TGT_RGR_BRIDGE_CTRL 0x00500784 /* RGR Bridge Control Register */ -#define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER 0x00500788 /* RGR Bridge RBUS Timer Register */ -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0050078c /* RGR Bridge Spare Software Reset 0 Register */ -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00500790 /* RGR Bridge Spare Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - PCIE RGR Bridge Revision Register - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define BCHP_TGT_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_TGT_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* TGT_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define BCHP_TGT_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_TGT_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* TGT_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define BCHP_TGT_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define BCHP_TGT_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - RGR Bridge Control Register - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ -#define BCHP_TGT_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc -#define BCHP_TGT_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 - -/* TGT_RGR_BRIDGE :: CTRL :: RBUS_ERROR_INTR [01:01] */ -#define BCHP_TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_MASK 0x00000002 -#define BCHP_TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_SHIFT 1 - -/* TGT_RGR_BRIDGE :: CTRL :: GISB_ERROR_INTR [00:00] */ -#define BCHP_TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_MASK 0x00000001 -#define BCHP_TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_SHIFT 0 - -/*************************************************************************** - *RBUS_TIMER - RGR Bridge RBUS Timer Register - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ -#define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 - -/* TGT_RGR_BRIDGE :: RBUS_TIMER :: RBUS_TO_RBUS_TRANS_TIMER_CNT [15:00] */ -#define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_MASK 0x0000ffff -#define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_SHIFT 0 - -/*************************************************************************** - *SPARE_SW_RESET_0 - RGR Bridge Spare Software Reset 0 Register - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 - -/*************************************************************************** - *SPARE_SW_RESET_1 - RGR Bridge Spare Software Reset 1 Register - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 - -#endif /* #ifndef BCHP_TGT_RGR_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_timer.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_timer.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_timer.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_timer.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,310 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_timer.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:21p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:31 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_timer.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:21p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_TIMER_H__ -#define BCHP_TIMER_H__ - -/*************************************************************************** - *TIMER - Watchdog & Programmable Timers - ***************************************************************************/ -#define BCHP_TIMER_TIMER_IS 0x004060c0 /* TIMER INTERRUPT STATUS REGISTER */ -#define BCHP_TIMER_TIMER_IE0 0x004060c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */ -#define BCHP_TIMER_TIMER0_CTRL 0x004060c8 /* TIMER0 CONTROL REGISTER */ -#define BCHP_TIMER_TIMER1_CTRL 0x004060cc /* TIMER1 CONTROL REGISTER */ -#define BCHP_TIMER_TIMER2_CTRL 0x004060d0 /* TIMER2 CONTROL REGISTER */ -#define BCHP_TIMER_TIMER3_CTRL 0x004060d4 /* TIMER3 CONTROL REGISTER */ -#define BCHP_TIMER_TIMER0_STAT 0x004060d8 /* TIMER0 STATUS REGISTER */ -#define BCHP_TIMER_TIMER1_STAT 0x004060dc /* TIMER1 STATUS REGISTER */ -#define BCHP_TIMER_TIMER2_STAT 0x004060e0 /* TIMER2 STATUS REGISTER */ -#define BCHP_TIMER_TIMER3_STAT 0x004060e4 /* TIMER3 STATUS REGISTER */ -#define BCHP_TIMER_WDTIMEOUT 0x004060e8 /* WATCHDOG TIMEOUT REGISTER */ -#define BCHP_TIMER_WDCMD 0x004060ec /* WATCHDOG COMMAND REGISTER */ -#define BCHP_TIMER_WDCHIPRST_CNT 0x004060f0 /* WATCHDOG CHIP RESET COUNT REGISTER */ -#define BCHP_TIMER_WDCRS 0x004060f4 /* WATCHDOG CHIP RESET STATUS REGISTER */ -#define BCHP_TIMER_TIMER_IE1 0x004060f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */ -#define BCHP_TIMER_WDCTRL 0x004060fc /* WATCHDOG CONTROL REGISTER */ - -/*************************************************************************** - *TIMER_IS - TIMER INTERRUPT STATUS REGISTER - ***************************************************************************/ -/* TIMER :: TIMER_IS :: reserved0 [31:05] */ -#define BCHP_TIMER_TIMER_IS_reserved0_MASK 0xffffffe0 -#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT 5 - -/* TIMER :: TIMER_IS :: WDINT [04:04] */ -#define BCHP_TIMER_TIMER_IS_WDINT_MASK 0x00000010 -#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT 4 - -/* TIMER :: TIMER_IS :: TMR3TO [03:03] */ -#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK 0x00000008 -#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT 3 - -/* TIMER :: TIMER_IS :: TMR2TO [02:02] */ -#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK 0x00000004 -#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT 2 - -/* TIMER :: TIMER_IS :: TMR1TO [01:01] */ -#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK 0x00000002 -#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT 1 - -/* TIMER :: TIMER_IS :: TMR0TO [00:00] */ -#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK 0x00000001 -#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT 0 - -/*************************************************************************** - *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER - ***************************************************************************/ -/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */ -#define BCHP_TIMER_TIMER_IE0_reserved0_MASK 0xffffffe0 -#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT 5 - -/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */ -#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK 0x00000010 -#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT 4 - -/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */ -#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK 0x00000008 -#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT 3 - -/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */ -#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK 0x00000004 -#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT 2 - -/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */ -#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK 0x00000002 -#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT 1 - -/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */ -#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK 0x00000001 -#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT 0 - -/*************************************************************************** - *TIMER0_CTRL - TIMER0 CONTROL REGISTER - ***************************************************************************/ -/* TIMER :: TIMER0_CTRL :: ENA [31:31] */ -#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK 0x80000000 -#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT 31 - -/* TIMER :: TIMER0_CTRL :: MODE [30:30] */ -#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK 0x40000000 -#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT 30 - -/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */ -#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *TIMER1_CTRL - TIMER1 CONTROL REGISTER - ***************************************************************************/ -/* TIMER :: TIMER1_CTRL :: ENA [31:31] */ -#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK 0x80000000 -#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT 31 - -/* TIMER :: TIMER1_CTRL :: MODE [30:30] */ -#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK 0x40000000 -#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT 30 - -/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */ -#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *TIMER2_CTRL - TIMER2 CONTROL REGISTER - ***************************************************************************/ -/* TIMER :: TIMER2_CTRL :: ENA [31:31] */ -#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK 0x80000000 -#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT 31 - -/* TIMER :: TIMER2_CTRL :: MODE [30:30] */ -#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK 0x40000000 -#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT 30 - -/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */ -#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *TIMER3_CTRL - TIMER3 CONTROL REGISTER - ***************************************************************************/ -/* TIMER :: TIMER3_CTRL :: ENA [31:31] */ -#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK 0x80000000 -#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT 31 - -/* TIMER :: TIMER3_CTRL :: MODE [30:30] */ -#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK 0x40000000 -#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT 30 - -/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */ -#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *TIMER0_STAT - TIMER0 STATUS REGISTER - ***************************************************************************/ -/* TIMER :: TIMER0_STAT :: RESERVED [31:30] */ -#define BCHP_TIMER_TIMER0_STAT_RESERVED_MASK 0xc0000000 -#define BCHP_TIMER_TIMER0_STAT_RESERVED_SHIFT 30 - -/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */ -#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT 0 - -/*************************************************************************** - *TIMER1_STAT - TIMER1 STATUS REGISTER - ***************************************************************************/ -/* TIMER :: TIMER1_STAT :: RESERVED [31:30] */ -#define BCHP_TIMER_TIMER1_STAT_RESERVED_MASK 0xc0000000 -#define BCHP_TIMER_TIMER1_STAT_RESERVED_SHIFT 30 - -/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */ -#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT 0 - -/*************************************************************************** - *TIMER2_STAT - TIMER2 STATUS REGISTER - ***************************************************************************/ -/* TIMER :: TIMER2_STAT :: RESERVED [31:30] */ -#define BCHP_TIMER_TIMER2_STAT_RESERVED_MASK 0xc0000000 -#define BCHP_TIMER_TIMER2_STAT_RESERVED_SHIFT 30 - -/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */ -#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT 0 - -/*************************************************************************** - *TIMER3_STAT - TIMER3 STATUS REGISTER - ***************************************************************************/ -/* TIMER :: TIMER3_STAT :: RESERVED [31:30] */ -#define BCHP_TIMER_TIMER3_STAT_RESERVED_MASK 0xc0000000 -#define BCHP_TIMER_TIMER3_STAT_RESERVED_SHIFT 30 - -/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */ -#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK 0x3fffffff -#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT 0 - -/*************************************************************************** - *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER - ***************************************************************************/ -/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */ -#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK 0xffffffff -#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *WDCMD - WATCHDOG COMMAND REGISTER - ***************************************************************************/ -/* TIMER :: WDCMD :: WDCMD [31:00] */ -#define BCHP_TIMER_WDCMD_WDCMD_MASK 0xffffffff -#define BCHP_TIMER_WDCMD_WDCMD_SHIFT 0 - -/*************************************************************************** - *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER - ***************************************************************************/ -/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */ -#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK 0xfc000000 -#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT 26 - -/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */ -#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK 0x03ffffff -#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT 0 - -/*************************************************************************** - *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER - ***************************************************************************/ -/* TIMER :: WDCRS :: reserved0 [31:01] */ -#define BCHP_TIMER_WDCRS_reserved0_MASK 0xfffffffe -#define BCHP_TIMER_WDCRS_reserved0_SHIFT 1 - -/* TIMER :: WDCRS :: WDCR [00:00] */ -#define BCHP_TIMER_WDCRS_WDCR_MASK 0x00000001 -#define BCHP_TIMER_WDCRS_WDCR_SHIFT 0 - -/*************************************************************************** - *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER - ***************************************************************************/ -/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */ -#define BCHP_TIMER_TIMER_IE1_reserved0_MASK 0xffffffe0 -#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT 5 - -/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */ -#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK 0x00000010 -#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT 4 - -/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */ -#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK 0x00000008 -#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT 3 - -/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */ -#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK 0x00000004 -#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT 2 - -/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */ -#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK 0x00000002 -#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT 1 - -/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */ -#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK 0x00000001 -#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT 0 - -/*************************************************************************** - *WDCTRL - WATCHDOG CONTROL REGISTER - ***************************************************************************/ -/* TIMER :: WDCTRL :: reserved0 [31:03] */ -#define BCHP_TIMER_WDCTRL_reserved0_MASK 0xfffffff8 -#define BCHP_TIMER_WDCTRL_reserved0_SHIFT 3 - -/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */ -#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK 0x00000004 -#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT 2 - -/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */ -#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK 0x00000003 -#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT 0 - -#endif /* #ifndef BCHP_TIMER_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,146 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_tmisc.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:21p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:17 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:21p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_TMISC_H__ -#define BCHP_TMISC_H__ - -/*************************************************************************** - *TMISC - BVN Top Control Registers - ***************************************************************************/ -#define BCHP_TMISC_SOFT_RESET 0x00541400 /* BVN TOP Soft Reset */ -#define BCHP_TMISC_TEST_PORT_DATA 0x00541404 /* BVN TOP Test Port Status */ -#define BCHP_TMISC_TEST_PORT_CTRL 0x00541408 /* BVN TOP Test Port Control */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD 0x00541410 /* BVN TOP MBIST TM Control for MFD */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR 0x00541414 /* BVN TOP MBIST TM Control for DNR */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL 0x00541418 /* BVN TOP MBIST TM Control for SCL */ -#define BCHP_TMISC_SCRATCH_0 0x0054143c /* Scratch Register */ - -/*************************************************************************** - *SOFT_RESET - BVN TOP Soft Reset - ***************************************************************************/ -/* TMISC :: SOFT_RESET :: reserved0 [31:04] */ -#define BCHP_TMISC_SOFT_RESET_reserved0_MASK 0xfffffff0 -#define BCHP_TMISC_SOFT_RESET_reserved0_SHIFT 4 - -/* TMISC :: SOFT_RESET :: CSC [03:03] */ -#define BCHP_TMISC_SOFT_RESET_CSC_MASK 0x00000008 -#define BCHP_TMISC_SOFT_RESET_CSC_SHIFT 3 - -/* TMISC :: SOFT_RESET :: SCL [02:02] */ -#define BCHP_TMISC_SOFT_RESET_SCL_MASK 0x00000004 -#define BCHP_TMISC_SOFT_RESET_SCL_SHIFT 2 - -/* TMISC :: SOFT_RESET :: DNR [01:01] */ -#define BCHP_TMISC_SOFT_RESET_DNR_MASK 0x00000002 -#define BCHP_TMISC_SOFT_RESET_DNR_SHIFT 1 - -/* TMISC :: SOFT_RESET :: MFD [00:00] */ -#define BCHP_TMISC_SOFT_RESET_MFD_MASK 0x00000001 -#define BCHP_TMISC_SOFT_RESET_MFD_SHIFT 0 - -/*************************************************************************** - *TEST_PORT_DATA - BVN TOP Test Port Status - ***************************************************************************/ -/* TMISC :: TEST_PORT_DATA :: TEST_PORT_DATA [31:00] */ -#define BCHP_TMISC_TEST_PORT_DATA_TEST_PORT_DATA_MASK 0xffffffff -#define BCHP_TMISC_TEST_PORT_DATA_TEST_PORT_DATA_SHIFT 0 - -/*************************************************************************** - *TEST_PORT_CTRL - BVN TOP Test Port Control - ***************************************************************************/ -/* TMISC :: TEST_PORT_CTRL :: reserved0 [31:24] */ -#define BCHP_TMISC_TEST_PORT_CTRL_reserved0_MASK 0xff000000 -#define BCHP_TMISC_TEST_PORT_CTRL_reserved0_SHIFT 24 - -/* TMISC :: TEST_PORT_CTRL :: TM_CTRL [23:00] */ -#define BCHP_TMISC_TEST_PORT_CTRL_TM_CTRL_MASK 0x00ffffff -#define BCHP_TMISC_TEST_PORT_CTRL_TM_CTRL_SHIFT 0 - -/*************************************************************************** - *BVNT_MBIST_TM_CTRL_MFD - BVN TOP MBIST TM Control for MFD - ***************************************************************************/ -/* TMISC :: BVNT_MBIST_TM_CTRL_MFD :: reserved0 [31:24] */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_reserved0_MASK 0xff000000 -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_reserved0_SHIFT 24 - -/* TMISC :: BVNT_MBIST_TM_CTRL_MFD :: TM_CTRL [23:00] */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_TM_CTRL_MASK 0x00ffffff -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_TM_CTRL_SHIFT 0 - -/*************************************************************************** - *BVNT_MBIST_TM_CTRL_DNR - BVN TOP MBIST TM Control for DNR - ***************************************************************************/ -/* TMISC :: BVNT_MBIST_TM_CTRL_DNR :: reserved0 [31:24] */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_reserved0_MASK 0xff000000 -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_reserved0_SHIFT 24 - -/* TMISC :: BVNT_MBIST_TM_CTRL_DNR :: TM_CTRL [23:00] */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_TM_CTRL_MASK 0x00ffffff -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_TM_CTRL_SHIFT 0 - -/*************************************************************************** - *BVNT_MBIST_TM_CTRL_SCL - BVN TOP MBIST TM Control for SCL - ***************************************************************************/ -/* TMISC :: BVNT_MBIST_TM_CTRL_SCL :: reserved0 [31:24] */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_reserved0_MASK 0xff000000 -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_reserved0_SHIFT 24 - -/* TMISC :: BVNT_MBIST_TM_CTRL_SCL :: TM_CTRL [23:00] */ -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_TM_CTRL_MASK 0x00ffffff -#define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_TM_CTRL_SHIFT 0 - -/*************************************************************************** - *SCRATCH_0 - Scratch Register - ***************************************************************************/ -/* TMISC :: SCRATCH_0 :: VALUE [31:00] */ -#define BCHP_TMISC_SCRATCH_0_VALUE_MASK 0xffffffff -#define BCHP_TMISC_SCRATCH_0_VALUE_SHIFT 0 - -#endif /* #ifndef BCHP_TMISC_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_trb_top.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_trb_top.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_trb_top.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_trb_top.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,102 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_trb_top.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:21p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:24 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_trb_top.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:21p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_TRB_TOP_H__ -#define BCHP_TRB_TOP_H__ - -/*************************************************************************** - *TRB_TOP - TRB Control Registers - ***************************************************************************/ -#define BCHP_TRB_TOP_CTL 0x000f0000 /* TRB Control */ -#define BCHP_TRB_TOP_STATUS 0x000f0004 /* TRB Status */ -#define BCHP_TRB_TOP_REVISION 0x000f0008 /* TRB REVISION */ - -/*************************************************************************** - *CTL - TRB Control - ***************************************************************************/ -/* TRB_TOP :: CTL :: reserved0 [31:02] */ -#define BCHP_TRB_TOP_CTL_reserved0_MASK 0xfffffffc -#define BCHP_TRB_TOP_CTL_reserved0_SHIFT 2 - -/* TRB_TOP :: CTL :: TRBOver [01:01] */ -#define BCHP_TRB_TOP_CTL_TRBOver_MASK 0x00000002 -#define BCHP_TRB_TOP_CTL_TRBOver_SHIFT 1 - -/* TRB_TOP :: CTL :: TRBEna [00:00] */ -#define BCHP_TRB_TOP_CTL_TRBEna_MASK 0x00000001 -#define BCHP_TRB_TOP_CTL_TRBEna_SHIFT 0 - -/*************************************************************************** - *STATUS - TRB Status - ***************************************************************************/ -/* TRB_TOP :: STATUS :: reserved0 [31:01] */ -#define BCHP_TRB_TOP_STATUS_reserved0_MASK 0xfffffffe -#define BCHP_TRB_TOP_STATUS_reserved0_SHIFT 1 - -/* TRB_TOP :: STATUS :: ErrSeen [00:00] */ -#define BCHP_TRB_TOP_STATUS_ErrSeen_MASK 0x00000001 -#define BCHP_TRB_TOP_STATUS_ErrSeen_SHIFT 0 - -/*************************************************************************** - *REVISION - TRB REVISION - ***************************************************************************/ -/* TRB_TOP :: REVISION :: reserved0 [31:16] */ -#define BCHP_TRB_TOP_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_TRB_TOP_REVISION_reserved0_SHIFT 16 - -/* TRB_TOP :: REVISION :: MAJOR [15:08] */ -#define BCHP_TRB_TOP_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_TRB_TOP_REVISION_MAJOR_SHIFT 8 - -/* TRB_TOP :: REVISION :: MINOR [07:00] */ -#define BCHP_TRB_TOP_REVISION_MINOR_MASK 0x000000ff -#define BCHP_TRB_TOP_REVISION_MINOR_SHIFT 0 - -#endif /* #ifndef BCHP_TRB_TOP_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_triple_sec.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_triple_sec.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_triple_sec.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_triple_sec.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_triple_sec.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:22p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:03 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_triple_sec.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:22p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_TRIPLE_SEC_H__ -#define BCHP_TRIPLE_SEC_H__ - -/*************************************************************************** - *TRIPLE_SEC - TRIPLE_SEC Registers - ***************************************************************************/ -#define BCHP_TRIPLE_SEC_RSV_S 0x000ff000 /* RESERVED */ -#define BCHP_TRIPLE_SEC_RSV_E 0x000ff4fc /* RESERVED */ - -/*************************************************************************** - *RSV_S - RESERVED - ***************************************************************************/ -/* TRIPLE_SEC :: RSV_S :: reserved0 [31:00] */ -#define BCHP_TRIPLE_SEC_RSV_S_reserved0_MASK 0xffffffff -#define BCHP_TRIPLE_SEC_RSV_S_reserved0_SHIFT 0 - -/*************************************************************************** - *RSV_E - RESERVED - ***************************************************************************/ -/* TRIPLE_SEC :: RSV_E :: reserved0 [31:00] */ -#define BCHP_TRIPLE_SEC_RSV_E_reserved0_MASK 0xffffffff -#define BCHP_TRIPLE_SEC_RSV_E_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_TRIPLE_SEC_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_vich_0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_vich_0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_vich_0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_vich_0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_vich_0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:22p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:22 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_vich_0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:22p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_VICH_0_H__ -#define BCHP_VICH_0_H__ - -/*************************************************************************** - *VICH_0 - ***************************************************************************/ -#define BCHP_VICH_0_RESERVED 0x00b00000 /* RESERVED */ -#define BCHP_VICH_0_RESERVED_END 0x00b0004c /* RESERVED_END */ - -/*************************************************************************** - *RESERVED - RESERVED - ***************************************************************************/ -/* VICH_0 :: RESERVED :: reserved0 [31:00] */ -#define BCHP_VICH_0_RESERVED_reserved0_MASK 0xffffffff -#define BCHP_VICH_0_RESERVED_reserved0_SHIFT 0 - -/*************************************************************************** - *RESERVED_END - RESERVED_END - ***************************************************************************/ -/* VICH_0 :: RESERVED_END :: reserved0 [31:00] */ -#define BCHP_VICH_0_RESERVED_END_reserved0_MASK 0xffffffff -#define BCHP_VICH_0_RESERVED_END_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_VICH_0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup_ctrl2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup_ctrl2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup_ctrl2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup_ctrl2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,250 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_wakeup_ctrl2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:22p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:03 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup_ctrl2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:22p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_WAKEUP_CTRL2_H__ -#define BCHP_WAKEUP_CTRL2_H__ - -/*************************************************************************** - *WAKEUP_CTRL2 - Wakeup Controller Registers - ***************************************************************************/ -#define BCHP_WAKEUP_CTRL2_STATUS 0x00406c00 /* Wake-Up Status Register */ -#define BCHP_WAKEUP_CTRL2_SET 0x00406c04 /* Wake-Up Set Register */ -#define BCHP_WAKEUP_CTRL2_CLEAR 0x00406c08 /* Wake-Up Clear Register */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS 0x00406c0c /* Wake-Up Mask Status Register */ -#define BCHP_WAKEUP_CTRL2_MASK_SET 0x00406c10 /* Wake-Up Mask Set Register */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR 0x00406c14 /* Wake-Up Mask Clear Register */ - -/*************************************************************************** - *STATUS - Wake-Up Status Register - ***************************************************************************/ -/* WAKEUP_CTRL2 :: STATUS :: reserved0 [31:06] */ -#define BCHP_WAKEUP_CTRL2_STATUS_reserved0_MASK 0xffffffc0 -#define BCHP_WAKEUP_CTRL2_STATUS_reserved0_SHIFT 6 - -/* WAKEUP_CTRL2 :: STATUS :: GIO [05:05] */ -#define BCHP_WAKEUP_CTRL2_STATUS_GIO_MASK 0x00000020 -#define BCHP_WAKEUP_CTRL2_STATUS_GIO_SHIFT 5 - -/* WAKEUP_CTRL2 :: STATUS :: UART2 [04:04] */ -#define BCHP_WAKEUP_CTRL2_STATUS_UART2_MASK 0x00000010 -#define BCHP_WAKEUP_CTRL2_STATUS_UART2_SHIFT 4 - -/* WAKEUP_CTRL2 :: STATUS :: UART1 [03:03] */ -#define BCHP_WAKEUP_CTRL2_STATUS_UART1_MASK 0x00000008 -#define BCHP_WAKEUP_CTRL2_STATUS_UART1_SHIFT 3 - -/* WAKEUP_CTRL2 :: STATUS :: UART0 [02:02] */ -#define BCHP_WAKEUP_CTRL2_STATUS_UART0_MASK 0x00000004 -#define BCHP_WAKEUP_CTRL2_STATUS_UART0_SHIFT 2 - -/* WAKEUP_CTRL2 :: STATUS :: WAKEUP_TIMER [01:01] */ -#define BCHP_WAKEUP_CTRL2_STATUS_WAKEUP_TIMER_MASK 0x00000002 -#define BCHP_WAKEUP_CTRL2_STATUS_WAKEUP_TIMER_SHIFT 1 - -/* WAKEUP_CTRL2 :: STATUS :: IRR [00:00] */ -#define BCHP_WAKEUP_CTRL2_STATUS_IRR_MASK 0x00000001 -#define BCHP_WAKEUP_CTRL2_STATUS_IRR_SHIFT 0 - -/*************************************************************************** - *SET - Wake-Up Set Register - ***************************************************************************/ -/* WAKEUP_CTRL2 :: SET :: reserved0 [31:06] */ -#define BCHP_WAKEUP_CTRL2_SET_reserved0_MASK 0xffffffc0 -#define BCHP_WAKEUP_CTRL2_SET_reserved0_SHIFT 6 - -/* WAKEUP_CTRL2 :: SET :: GIO [05:05] */ -#define BCHP_WAKEUP_CTRL2_SET_GIO_MASK 0x00000020 -#define BCHP_WAKEUP_CTRL2_SET_GIO_SHIFT 5 - -/* WAKEUP_CTRL2 :: SET :: UART2 [04:04] */ -#define BCHP_WAKEUP_CTRL2_SET_UART2_MASK 0x00000010 -#define BCHP_WAKEUP_CTRL2_SET_UART2_SHIFT 4 - -/* WAKEUP_CTRL2 :: SET :: UART1 [03:03] */ -#define BCHP_WAKEUP_CTRL2_SET_UART1_MASK 0x00000008 -#define BCHP_WAKEUP_CTRL2_SET_UART1_SHIFT 3 - -/* WAKEUP_CTRL2 :: SET :: UART0 [02:02] */ -#define BCHP_WAKEUP_CTRL2_SET_UART0_MASK 0x00000004 -#define BCHP_WAKEUP_CTRL2_SET_UART0_SHIFT 2 - -/* WAKEUP_CTRL2 :: SET :: WAKEUP_TIMER [01:01] */ -#define BCHP_WAKEUP_CTRL2_SET_WAKEUP_TIMER_MASK 0x00000002 -#define BCHP_WAKEUP_CTRL2_SET_WAKEUP_TIMER_SHIFT 1 - -/* WAKEUP_CTRL2 :: SET :: IRR [00:00] */ -#define BCHP_WAKEUP_CTRL2_SET_IRR_MASK 0x00000001 -#define BCHP_WAKEUP_CTRL2_SET_IRR_SHIFT 0 - -/*************************************************************************** - *CLEAR - Wake-Up Clear Register - ***************************************************************************/ -/* WAKEUP_CTRL2 :: CLEAR :: reserved0 [31:06] */ -#define BCHP_WAKEUP_CTRL2_CLEAR_reserved0_MASK 0xffffffc0 -#define BCHP_WAKEUP_CTRL2_CLEAR_reserved0_SHIFT 6 - -/* WAKEUP_CTRL2 :: CLEAR :: GIO [05:05] */ -#define BCHP_WAKEUP_CTRL2_CLEAR_GIO_MASK 0x00000020 -#define BCHP_WAKEUP_CTRL2_CLEAR_GIO_SHIFT 5 - -/* WAKEUP_CTRL2 :: CLEAR :: UART2 [04:04] */ -#define BCHP_WAKEUP_CTRL2_CLEAR_UART2_MASK 0x00000010 -#define BCHP_WAKEUP_CTRL2_CLEAR_UART2_SHIFT 4 - -/* WAKEUP_CTRL2 :: CLEAR :: UART1 [03:03] */ -#define BCHP_WAKEUP_CTRL2_CLEAR_UART1_MASK 0x00000008 -#define BCHP_WAKEUP_CTRL2_CLEAR_UART1_SHIFT 3 - -/* WAKEUP_CTRL2 :: CLEAR :: UART0 [02:02] */ -#define BCHP_WAKEUP_CTRL2_CLEAR_UART0_MASK 0x00000004 -#define BCHP_WAKEUP_CTRL2_CLEAR_UART0_SHIFT 2 - -/* WAKEUP_CTRL2 :: CLEAR :: WAKEUP_TIMER [01:01] */ -#define BCHP_WAKEUP_CTRL2_CLEAR_WAKEUP_TIMER_MASK 0x00000002 -#define BCHP_WAKEUP_CTRL2_CLEAR_WAKEUP_TIMER_SHIFT 1 - -/* WAKEUP_CTRL2 :: CLEAR :: IRR [00:00] */ -#define BCHP_WAKEUP_CTRL2_CLEAR_IRR_MASK 0x00000001 -#define BCHP_WAKEUP_CTRL2_CLEAR_IRR_SHIFT 0 - -/*************************************************************************** - *MASK_STATUS - Wake-Up Mask Status Register - ***************************************************************************/ -/* WAKEUP_CTRL2 :: MASK_STATUS :: reserved0 [31:06] */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_reserved0_MASK 0xffffffc0 -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_reserved0_SHIFT 6 - -/* WAKEUP_CTRL2 :: MASK_STATUS :: GIO [05:05] */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_GIO_MASK 0x00000020 -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_GIO_SHIFT 5 - -/* WAKEUP_CTRL2 :: MASK_STATUS :: UART2 [04:04] */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART2_MASK 0x00000010 -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART2_SHIFT 4 - -/* WAKEUP_CTRL2 :: MASK_STATUS :: UART1 [03:03] */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART1_MASK 0x00000008 -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART1_SHIFT 3 - -/* WAKEUP_CTRL2 :: MASK_STATUS :: UART0 [02:02] */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART0_MASK 0x00000004 -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART0_SHIFT 2 - -/* WAKEUP_CTRL2 :: MASK_STATUS :: WAKEUP_TIMER [01:01] */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_WAKEUP_TIMER_MASK 0x00000002 -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_WAKEUP_TIMER_SHIFT 1 - -/* WAKEUP_CTRL2 :: MASK_STATUS :: IRR [00:00] */ -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_IRR_MASK 0x00000001 -#define BCHP_WAKEUP_CTRL2_MASK_STATUS_IRR_SHIFT 0 - -/*************************************************************************** - *MASK_SET - Wake-Up Mask Set Register - ***************************************************************************/ -/* WAKEUP_CTRL2 :: MASK_SET :: reserved0 [31:06] */ -#define BCHP_WAKEUP_CTRL2_MASK_SET_reserved0_MASK 0xffffffc0 -#define BCHP_WAKEUP_CTRL2_MASK_SET_reserved0_SHIFT 6 - -/* WAKEUP_CTRL2 :: MASK_SET :: GIO [05:05] */ -#define BCHP_WAKEUP_CTRL2_MASK_SET_GIO_MASK 0x00000020 -#define BCHP_WAKEUP_CTRL2_MASK_SET_GIO_SHIFT 5 - -/* WAKEUP_CTRL2 :: MASK_SET :: UART2 [04:04] */ -#define BCHP_WAKEUP_CTRL2_MASK_SET_UART2_MASK 0x00000010 -#define BCHP_WAKEUP_CTRL2_MASK_SET_UART2_SHIFT 4 - -/* WAKEUP_CTRL2 :: MASK_SET :: UART1 [03:03] */ -#define BCHP_WAKEUP_CTRL2_MASK_SET_UART1_MASK 0x00000008 -#define BCHP_WAKEUP_CTRL2_MASK_SET_UART1_SHIFT 3 - -/* WAKEUP_CTRL2 :: MASK_SET :: UART0 [02:02] */ -#define BCHP_WAKEUP_CTRL2_MASK_SET_UART0_MASK 0x00000004 -#define BCHP_WAKEUP_CTRL2_MASK_SET_UART0_SHIFT 2 - -/* WAKEUP_CTRL2 :: MASK_SET :: WAKEUP_TIMER [01:01] */ -#define BCHP_WAKEUP_CTRL2_MASK_SET_WAKEUP_TIMER_MASK 0x00000002 -#define BCHP_WAKEUP_CTRL2_MASK_SET_WAKEUP_TIMER_SHIFT 1 - -/* WAKEUP_CTRL2 :: MASK_SET :: IRR [00:00] */ -#define BCHP_WAKEUP_CTRL2_MASK_SET_IRR_MASK 0x00000001 -#define BCHP_WAKEUP_CTRL2_MASK_SET_IRR_SHIFT 0 - -/*************************************************************************** - *MASK_CLEAR - Wake-Up Mask Clear Register - ***************************************************************************/ -/* WAKEUP_CTRL2 :: MASK_CLEAR :: reserved0 [31:06] */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_reserved0_MASK 0xffffffc0 -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_reserved0_SHIFT 6 - -/* WAKEUP_CTRL2 :: MASK_CLEAR :: GIO [05:05] */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_GIO_MASK 0x00000020 -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_GIO_SHIFT 5 - -/* WAKEUP_CTRL2 :: MASK_CLEAR :: UART2 [04:04] */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART2_MASK 0x00000010 -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART2_SHIFT 4 - -/* WAKEUP_CTRL2 :: MASK_CLEAR :: UART1 [03:03] */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART1_MASK 0x00000008 -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART1_SHIFT 3 - -/* WAKEUP_CTRL2 :: MASK_CLEAR :: UART0 [02:02] */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART0_MASK 0x00000004 -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART0_SHIFT 2 - -/* WAKEUP_CTRL2 :: MASK_CLEAR :: WAKEUP_TIMER [01:01] */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_WAKEUP_TIMER_MASK 0x00000002 -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_WAKEUP_TIMER_SHIFT 1 - -/* WAKEUP_CTRL2 :: MASK_CLEAR :: IRR [00:00] */ -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_IRR_MASK 0x00000001 -#define BCHP_WAKEUP_CTRL2_MASK_CLEAR_IRR_SHIFT 0 - -#endif /* #ifndef BCHP_WAKEUP_CTRL2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_gr_bridge.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_gr_bridge.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_gr_bridge.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_gr_bridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,110 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_wrap_misc_gr_bridge.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:22p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:38 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_gr_bridge.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:22p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_WRAP_MISC_GR_BRIDGE_H__ -#define BCHP_WRAP_MISC_GR_BRIDGE_H__ - -/*************************************************************************** - *WRAP_MISC_GR_BRIDGE - ***************************************************************************/ -#define BCHP_WRAP_MISC_GR_BRIDGE_REVISION 0x000f1000 /* GR Bridge Revision */ -#define BCHP_WRAP_MISC_GR_BRIDGE_CTRL 0x000f1004 /* GR Bridge Control Register */ -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0 0x000f1008 /* GR Bridge Software Reset 0 Register */ -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_1 0x000f100c /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* WRAP_MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* WRAP_MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* WRAP_MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* WRAP_MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* WRAP_MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* WRAP_MISC_GR_BRIDGE :: SW_RESET_0 :: reserved0 [31:01] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_reserved0_SHIFT 1 - -/* WRAP_MISC_GR_BRIDGE :: SW_RESET_0 :: SW_RESET [00:00] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_MASK 0x00000001 -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_SHIFT 0 -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_DEASSERT 0 -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_ASSERT 1 - -/*************************************************************************** - *SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* WRAP_MISC_GR_BRIDGE :: SW_RESET_1 :: reserved0 [31:00] */ -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_1_reserved0_MASK 0xffffffff -#define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_1_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_WRAP_MISC_GR_BRIDGE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1306 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_wrap_misc_intr2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:23p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:21 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:23p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_WRAP_MISC_INTR2_H__ -#define BCHP_WRAP_MISC_INTR2_H__ - -/*************************************************************************** - *WRAP_MISC_INTR2 - MISC block Level 2 Interrupt Controller - ***************************************************************************/ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS 0x000f2000 /* CPU interrupt Status Register */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET 0x000f2004 /* CPU interrupt Set Register */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR 0x000f2008 /* CPU interrupt Clear Register */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS 0x000f200c /* CPU interrupt Mask Status Register */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET 0x000f2010 /* CPU interrupt Mask Set Register */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR 0x000f2014 /* CPU interrupt Mask Clear Register */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS 0x000f2018 /* PCI interrupt Status Register */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET 0x000f201c /* PCI interrupt Set Register */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR 0x000f2020 /* PCI interrupt Clear Register */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS 0x000f2024 /* PCI interrupt Mask Status Register */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET 0x000f2028 /* PCI interrupt Mask Set Register */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR 0x000f202c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: CPU_STATUS :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_FAIL_INTR [23:23] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT 23 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_DONE_INTR [22:22] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT 22 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: PREMATURE_ARM_REQ_INTR [21:21] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PREMATURE_ARM_REQ_INTR_SHIFT 21 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: BAD_STARCH_CFG_INTR [20:20] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BAD_STARCH_CFG_INTR_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BAD_STARCH_CFG_INTR_SHIFT 20 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: SCRM_KEY_DONE_INTR [19:19] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT 19 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: BORCH_ERROR_INTR [18:18] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BORCH_ERROR_INTR_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BORCH_ERROR_INTR_SHIFT 18 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: GR_BRIDGE_ERROR_INTR [17:17] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_GR_BRIDGE_ERROR_INTR_SHIFT 17 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: MEM_DMA_INTR [16:16] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_MEM_DMA_INTR_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_MEM_DMA_INTR_SHIFT 16 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX4_INTR [15:15] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX4_INTR_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX4_INTR_SHIFT 15 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX3_INTR [14:14] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX3_INTR_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX3_INTR_SHIFT 14 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX2_INTR [13:13] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX2_INTR_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX2_INTR_SHIFT 13 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX1_INTR [12:12] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX1_INTR_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX1_INTR_SHIFT 12 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX4_INTR [11:11] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX4_INTR_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX4_INTR_SHIFT 11 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX3_INTR [10:10] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX3_INTR_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX3_INTR_SHIFT 10 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX2_INTR [09:09] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX2_INTR_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX2_INTR_SHIFT 9 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX1_INTR [08:08] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX1_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX1_INTR_SHIFT 8 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL2_INTR [07:07] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL2_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL2_INTR_SHIFT 7 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL1_INTR [06:06] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL1_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL1_INTR_SHIFT 6 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL0_INTR [05:05] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL0_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL0_INTR_SHIFT 5 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_ERR_INTR [04:04] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT 4 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_MEM_DMA0_DONE [03:03] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_MEM_DMA0_DONE_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_MEM_DMA0_DONE_SHIFT 3 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_INTR [02:02] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_INTR_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_INTR_SHIFT 2 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_RCV_INTR [01:01] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_RCV_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_RCV_INTR_SHIFT 1 - -/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_XMIT_INTR [00:00] */ -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_XMIT_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_XMIT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: CPU_SET :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: CPU_SET :: BOOT_VER_FAIL_INTR [23:23] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_FAIL_INTR_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_FAIL_INTR_SHIFT 23 - -/* WRAP_MISC_INTR2 :: CPU_SET :: BOOT_VER_DONE_INTR [22:22] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_DONE_INTR_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_DONE_INTR_SHIFT 22 - -/* WRAP_MISC_INTR2 :: CPU_SET :: PREMATURE_ARM_REQ_INTR [21:21] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PREMATURE_ARM_REQ_INTR_SHIFT 21 - -/* WRAP_MISC_INTR2 :: CPU_SET :: BAD_STARCH_CFG_INTR [20:20] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BAD_STARCH_CFG_INTR_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BAD_STARCH_CFG_INTR_SHIFT 20 - -/* WRAP_MISC_INTR2 :: CPU_SET :: SCRM_KEY_DONE_INTR [19:19] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SCRM_KEY_DONE_INTR_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SCRM_KEY_DONE_INTR_SHIFT 19 - -/* WRAP_MISC_INTR2 :: CPU_SET :: BORCH_ERROR_INTR [18:18] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BORCH_ERROR_INTR_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_BORCH_ERROR_INTR_SHIFT 18 - -/* WRAP_MISC_INTR2 :: CPU_SET :: GR_BRIDGE_ERROR_INTR [17:17] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_GR_BRIDGE_ERROR_INTR_SHIFT 17 - -/* WRAP_MISC_INTR2 :: CPU_SET :: MEM_DMA_INTR [16:16] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_MEM_DMA_INTR_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_MEM_DMA_INTR_SHIFT 16 - -/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX4_INTR [15:15] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX4_INTR_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX4_INTR_SHIFT 15 - -/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX3_INTR [14:14] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX3_INTR_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX3_INTR_SHIFT 14 - -/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX2_INTR [13:13] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX2_INTR_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX2_INTR_SHIFT 13 - -/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX1_INTR [12:12] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX1_INTR_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX1_INTR_SHIFT 12 - -/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX4_INTR [11:11] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX4_INTR_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX4_INTR_SHIFT 11 - -/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX3_INTR [10:10] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX3_INTR_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX3_INTR_SHIFT 10 - -/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX2_INTR [09:09] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX2_INTR_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX2_INTR_SHIFT 9 - -/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX1_INTR [08:08] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX1_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX1_INTR_SHIFT 8 - -/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL2_INTR [07:07] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL2_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL2_INTR_SHIFT 7 - -/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL1_INTR [06:06] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL1_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL1_INTR_SHIFT 6 - -/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL0_INTR [05:05] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL0_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL0_INTR_SHIFT 5 - -/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_ERR_INTR [04:04] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_ERR_INTR_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_ERR_INTR_SHIFT 4 - -/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_MEM_DMA0_DONE [03:03] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_MEM_DMA0_DONE_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_MEM_DMA0_DONE_SHIFT 3 - -/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_INTR [02:02] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_INTR_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_INTR_SHIFT 2 - -/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_RCV_INTR [01:01] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_RCV_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_RCV_INTR_SHIFT 1 - -/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_XMIT_INTR [00:00] */ -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_XMIT_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_XMIT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BOOT_VER_FAIL_INTR [23:23] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_FAIL_INTR_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_FAIL_INTR_SHIFT 23 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BOOT_VER_DONE_INTR [22:22] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_DONE_INTR_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_DONE_INTR_SHIFT 22 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PREMATURE_ARM_REQ_INTR [21:21] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PREMATURE_ARM_REQ_INTR_SHIFT 21 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BAD_STARCH_CFG_INTR [20:20] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BAD_STARCH_CFG_INTR_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BAD_STARCH_CFG_INTR_SHIFT 20 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SCRM_KEY_DONE_INTR [19:19] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SCRM_KEY_DONE_INTR_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SCRM_KEY_DONE_INTR_SHIFT 19 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BORCH_ERROR_INTR [18:18] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BORCH_ERROR_INTR_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BORCH_ERROR_INTR_SHIFT 18 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: GR_BRIDGE_ERROR_INTR [17:17] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_GR_BRIDGE_ERROR_INTR_SHIFT 17 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: MEM_DMA_INTR [16:16] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_MEM_DMA_INTR_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_MEM_DMA_INTR_SHIFT 16 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX4_INTR [15:15] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX4_INTR_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX4_INTR_SHIFT 15 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX3_INTR [14:14] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX3_INTR_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX3_INTR_SHIFT 14 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX2_INTR [13:13] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX2_INTR_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX2_INTR_SHIFT 13 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX1_INTR [12:12] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX1_INTR_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX1_INTR_SHIFT 12 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX4_INTR [11:11] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX4_INTR_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX4_INTR_SHIFT 11 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX3_INTR [10:10] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX3_INTR_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX3_INTR_SHIFT 10 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX2_INTR [09:09] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX2_INTR_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX2_INTR_SHIFT 9 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX1_INTR [08:08] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX1_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX1_INTR_SHIFT 8 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL2_INTR [07:07] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL2_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL2_INTR_SHIFT 7 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL1_INTR [06:06] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL1_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL1_INTR_SHIFT 6 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL0_INTR [05:05] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL0_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL0_INTR_SHIFT 5 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_ERR_INTR [04:04] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_ERR_INTR_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_ERR_INTR_SHIFT 4 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_MEM_DMA0_DONE [03:03] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_MEM_DMA0_DONE_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_MEM_DMA0_DONE_SHIFT 3 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_INTR [02:02] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_INTR_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_INTR_SHIFT 2 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_RCV_INTR [01:01] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_RCV_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_RCV_INTR_SHIFT 1 - -/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_XMIT_INTR [00:00] */ -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_XMIT_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_XMIT_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BOOT_VER_FAIL_MASK [23:23] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_FAIL_MASK_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_FAIL_MASK_SHIFT 23 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BOOT_VER_DONE_MASK [22:22] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_DONE_MASK_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_DONE_MASK_SHIFT 22 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PREMATURE_ARM_REQ_MASK [21:21] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PREMATURE_ARM_REQ_MASK_SHIFT 21 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BAD_STARCH_CFG_MASK [20:20] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BAD_STARCH_CFG_MASK_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BAD_STARCH_CFG_MASK_SHIFT 20 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SCRM_KEY_DONE_MASK [19:19] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SCRM_KEY_DONE_MASK_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SCRM_KEY_DONE_MASK_SHIFT 19 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BORCH_ERROR_MASK [18:18] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BORCH_ERROR_MASK_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BORCH_ERROR_MASK_SHIFT 18 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: GR_BRIDGE_ERROR_MASK [17:17] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_GR_BRIDGE_ERROR_MASK_SHIFT 17 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: MEM_DMA_MASK [16:16] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_MEM_DMA_MASK_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_MEM_DMA_MASK_SHIFT 16 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX4_MASK [15:15] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX4_MASK_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX4_MASK_SHIFT 15 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX3_MASK [14:14] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX3_MASK_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX3_MASK_SHIFT 14 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX2_MASK [13:13] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX2_MASK_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX2_MASK_SHIFT 13 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX1_MASK [12:12] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX1_MASK_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX1_MASK_SHIFT 12 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX4_MASK [11:11] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX4_MASK_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX4_MASK_SHIFT 11 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX3_MASK [10:10] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX3_MASK_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX3_MASK_SHIFT 10 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX2_MASK [09:09] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX2_MASK_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX2_MASK_SHIFT 9 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX1_MASK [08:08] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX1_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX1_MASK_SHIFT 8 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL2_MASK [07:07] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL2_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL2_MASK_SHIFT 7 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL1_MASK [06:06] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL1_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL1_MASK_SHIFT 6 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL0_MASK [05:05] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL0_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL0_MASK_SHIFT 5 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_ERR_MASK [04:04] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_ERR_MASK_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_ERR_MASK_SHIFT 4 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_MASK [02:02] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_MASK_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_MASK_SHIFT 2 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_RCV_MASK [01:01] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_RCV_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_RCV_MASK_SHIFT 1 - -/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_XMIT_MASK [00:00] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_XMIT_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_XMIT_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BOOT_VER_FAIL_MASK [23:23] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_FAIL_MASK_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_FAIL_MASK_SHIFT 23 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BOOT_VER_DONE_MASK [22:22] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_DONE_MASK_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_DONE_MASK_SHIFT 22 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PREMATURE_ARM_REQ_MASK [21:21] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PREMATURE_ARM_REQ_MASK_SHIFT 21 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BAD_STARCH_CFG_MASK [20:20] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BAD_STARCH_CFG_MASK_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BAD_STARCH_CFG_MASK_SHIFT 20 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SCRM_KEY_DONE_MASK [19:19] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SCRM_KEY_DONE_MASK_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SCRM_KEY_DONE_MASK_SHIFT 19 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BORCH_ERROR_MASK [18:18] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BORCH_ERROR_MASK_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BORCH_ERROR_MASK_SHIFT 18 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: GR_BRIDGE_ERROR_MASK [17:17] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_GR_BRIDGE_ERROR_MASK_SHIFT 17 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: MEM_DMA_MASK [16:16] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_MEM_DMA_MASK_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_MEM_DMA_MASK_SHIFT 16 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX4_MASK [15:15] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX4_MASK_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX4_MASK_SHIFT 15 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX3_MASK [14:14] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX3_MASK_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX3_MASK_SHIFT 14 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX2_MASK [13:13] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX2_MASK_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX2_MASK_SHIFT 13 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX1_MASK [12:12] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX1_MASK_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX1_MASK_SHIFT 12 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX4_MASK [11:11] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX4_MASK_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX4_MASK_SHIFT 11 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX3_MASK [10:10] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX3_MASK_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX3_MASK_SHIFT 10 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX2_MASK [09:09] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX2_MASK_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX2_MASK_SHIFT 9 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX1_MASK [08:08] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX1_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX1_MASK_SHIFT 8 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL2_MASK [07:07] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL2_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL2_MASK_SHIFT 7 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL1_MASK [06:06] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL1_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL1_MASK_SHIFT 6 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL0_MASK [05:05] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL0_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL0_MASK_SHIFT 5 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_ERR_MASK [04:04] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_ERR_MASK_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_ERR_MASK_SHIFT 4 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_MASK [02:02] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_MASK_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_MASK_SHIFT 2 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_RCV_MASK [01:01] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_RCV_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_RCV_MASK_SHIFT 1 - -/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_XMIT_MASK [00:00] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_XMIT_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_XMIT_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BOOT_VER_FAIL_MASK [23:23] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_FAIL_MASK_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_FAIL_MASK_SHIFT 23 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BOOT_VER_DONE_MASK [22:22] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_DONE_MASK_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_DONE_MASK_SHIFT 22 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PREMATURE_ARM_REQ_MASK [21:21] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_SHIFT 21 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BAD_STARCH_CFG_MASK [20:20] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BAD_STARCH_CFG_MASK_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BAD_STARCH_CFG_MASK_SHIFT 20 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SCRM_KEY_DONE_MASK [19:19] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SCRM_KEY_DONE_MASK_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SCRM_KEY_DONE_MASK_SHIFT 19 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BORCH_ERROR_MASK [18:18] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BORCH_ERROR_MASK_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BORCH_ERROR_MASK_SHIFT 18 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: GR_BRIDGE_ERROR_MASK [17:17] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_SHIFT 17 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: MEM_DMA_MASK [16:16] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_MEM_DMA_MASK_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_MEM_DMA_MASK_SHIFT 16 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX4_MASK [15:15] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX4_MASK_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX4_MASK_SHIFT 15 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX3_MASK [14:14] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX3_MASK_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX3_MASK_SHIFT 14 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX2_MASK [13:13] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX2_MASK_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX2_MASK_SHIFT 13 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX1_MASK [12:12] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX1_MASK_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX1_MASK_SHIFT 12 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX4_MASK [11:11] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX4_MASK_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX4_MASK_SHIFT 11 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX3_MASK [10:10] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX3_MASK_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX3_MASK_SHIFT 10 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX2_MASK [09:09] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX2_MASK_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX2_MASK_SHIFT 9 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX1_MASK [08:08] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX1_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX1_MASK_SHIFT 8 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL2_MASK [07:07] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL2_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL2_MASK_SHIFT 7 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL1_MASK [06:06] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL1_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL1_MASK_SHIFT 6 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL0_MASK [05:05] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL0_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL0_MASK_SHIFT 5 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_ERR_MASK [04:04] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_ERR_MASK_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_ERR_MASK_SHIFT 4 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_MASK [02:02] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_MASK_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_MASK_SHIFT 2 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_RCV_MASK [01:01] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_RCV_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_RCV_MASK_SHIFT 1 - -/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_XMIT_MASK [00:00] */ -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_XMIT_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_XMIT_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: PCI_STATUS :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: BOOT_VER_FAIL_INTR [23:23] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_FAIL_INTR_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_FAIL_INTR_SHIFT 23 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: BOOT_VER_DONE_INTR [22:22] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_DONE_INTR_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_DONE_INTR_SHIFT 22 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: PREMATURE_ARM_REQ_INTR [21:21] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PREMATURE_ARM_REQ_INTR_SHIFT 21 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: BAD_STARCH_CFG_INTR [20:20] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BAD_STARCH_CFG_INTR_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BAD_STARCH_CFG_INTR_SHIFT 20 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: SCRM_KEY_DONE_INTR [19:19] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SCRM_KEY_DONE_INTR_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SCRM_KEY_DONE_INTR_SHIFT 19 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: BORCH_ERROR_INTR [18:18] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BORCH_ERROR_INTR_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BORCH_ERROR_INTR_SHIFT 18 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: GR_BRIDGE_ERROR_INTR [17:17] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_GR_BRIDGE_ERROR_INTR_SHIFT 17 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: MEM_DMA_INTR [16:16] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_MEM_DMA_INTR_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_MEM_DMA_INTR_SHIFT 16 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX4_INTR [15:15] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX4_INTR_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX4_INTR_SHIFT 15 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX3_INTR [14:14] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX3_INTR_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX3_INTR_SHIFT 14 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX2_INTR [13:13] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX2_INTR_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX2_INTR_SHIFT 13 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX1_INTR [12:12] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX1_INTR_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX1_INTR_SHIFT 12 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX4_INTR [11:11] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX4_INTR_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX4_INTR_SHIFT 11 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX3_INTR [10:10] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX3_INTR_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX3_INTR_SHIFT 10 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX2_INTR [09:09] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX2_INTR_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX2_INTR_SHIFT 9 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX1_INTR [08:08] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX1_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX1_INTR_SHIFT 8 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL2_INTR [07:07] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL2_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL2_INTR_SHIFT 7 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL1_INTR [06:06] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL1_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL1_INTR_SHIFT 6 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL0_INTR [05:05] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL0_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL0_INTR_SHIFT 5 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_ERR_INTR [04:04] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_ERR_INTR_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_ERR_INTR_SHIFT 4 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_MEM_DMA0_DONE [03:03] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_MEM_DMA0_DONE_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_MEM_DMA0_DONE_SHIFT 3 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_INTR [02:02] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_INTR_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_INTR_SHIFT 2 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_RCV_INTR [01:01] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_RCV_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_RCV_INTR_SHIFT 1 - -/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_XMIT_INTR [00:00] */ -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_XMIT_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_XMIT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: PCI_SET :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: PCI_SET :: BOOT_VER_FAIL_INTR [23:23] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_FAIL_INTR_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_FAIL_INTR_SHIFT 23 - -/* WRAP_MISC_INTR2 :: PCI_SET :: BOOT_VER_DONE_INTR [22:22] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_DONE_INTR_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_DONE_INTR_SHIFT 22 - -/* WRAP_MISC_INTR2 :: PCI_SET :: PREMATURE_ARM_REQ_INTR [21:21] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PREMATURE_ARM_REQ_INTR_SHIFT 21 - -/* WRAP_MISC_INTR2 :: PCI_SET :: BAD_STARCH_CFG_INTR [20:20] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BAD_STARCH_CFG_INTR_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BAD_STARCH_CFG_INTR_SHIFT 20 - -/* WRAP_MISC_INTR2 :: PCI_SET :: SCRM_KEY_DONE_INTR [19:19] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SCRM_KEY_DONE_INTR_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SCRM_KEY_DONE_INTR_SHIFT 19 - -/* WRAP_MISC_INTR2 :: PCI_SET :: BORCH_ERROR_INTR [18:18] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BORCH_ERROR_INTR_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_BORCH_ERROR_INTR_SHIFT 18 - -/* WRAP_MISC_INTR2 :: PCI_SET :: GR_BRIDGE_ERROR_INTR [17:17] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_GR_BRIDGE_ERROR_INTR_SHIFT 17 - -/* WRAP_MISC_INTR2 :: PCI_SET :: MEM_DMA_INTR [16:16] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_MEM_DMA_INTR_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_MEM_DMA_INTR_SHIFT 16 - -/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX4_INTR [15:15] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX4_INTR_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX4_INTR_SHIFT 15 - -/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX3_INTR [14:14] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX3_INTR_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX3_INTR_SHIFT 14 - -/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX2_INTR [13:13] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX2_INTR_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX2_INTR_SHIFT 13 - -/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX1_INTR [12:12] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX1_INTR_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX1_INTR_SHIFT 12 - -/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX4_INTR [11:11] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX4_INTR_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX4_INTR_SHIFT 11 - -/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX3_INTR [10:10] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX3_INTR_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX3_INTR_SHIFT 10 - -/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX2_INTR [09:09] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX2_INTR_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX2_INTR_SHIFT 9 - -/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX1_INTR [08:08] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX1_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX1_INTR_SHIFT 8 - -/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL2_INTR [07:07] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL2_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL2_INTR_SHIFT 7 - -/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL1_INTR [06:06] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL1_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL1_INTR_SHIFT 6 - -/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL0_INTR [05:05] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL0_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL0_INTR_SHIFT 5 - -/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_ERR_INTR [04:04] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_ERR_INTR_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_ERR_INTR_SHIFT 4 - -/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_MEM_DMA0_DONE [03:03] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_MEM_DMA0_DONE_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_MEM_DMA0_DONE_SHIFT 3 - -/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_INTR [02:02] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_INTR_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_INTR_SHIFT 2 - -/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_RCV_INTR [01:01] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_RCV_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_RCV_INTR_SHIFT 1 - -/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_XMIT_INTR [00:00] */ -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_XMIT_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_XMIT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BOOT_VER_FAIL_INTR [23:23] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_FAIL_INTR_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_FAIL_INTR_SHIFT 23 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BOOT_VER_DONE_INTR [22:22] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_DONE_INTR_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_DONE_INTR_SHIFT 22 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PREMATURE_ARM_REQ_INTR [21:21] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PREMATURE_ARM_REQ_INTR_SHIFT 21 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BAD_STARCH_CFG_INTR [20:20] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BAD_STARCH_CFG_INTR_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BAD_STARCH_CFG_INTR_SHIFT 20 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SCRM_KEY_DONE_INTR [19:19] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SCRM_KEY_DONE_INTR_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SCRM_KEY_DONE_INTR_SHIFT 19 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BORCH_ERROR_INTR [18:18] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BORCH_ERROR_INTR_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BORCH_ERROR_INTR_SHIFT 18 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: GR_BRIDGE_ERROR_INTR [17:17] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_GR_BRIDGE_ERROR_INTR_SHIFT 17 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: MEM_DMA_INTR [16:16] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_MEM_DMA_INTR_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_MEM_DMA_INTR_SHIFT 16 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX4_INTR [15:15] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX4_INTR_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX4_INTR_SHIFT 15 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX3_INTR [14:14] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX3_INTR_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX3_INTR_SHIFT 14 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX2_INTR [13:13] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX2_INTR_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX2_INTR_SHIFT 13 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX1_INTR [12:12] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX1_INTR_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX1_INTR_SHIFT 12 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX4_INTR [11:11] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX4_INTR_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX4_INTR_SHIFT 11 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX3_INTR [10:10] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX3_INTR_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX3_INTR_SHIFT 10 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX2_INTR [09:09] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX2_INTR_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX2_INTR_SHIFT 9 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX1_INTR [08:08] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX1_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX1_INTR_SHIFT 8 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL2_INTR [07:07] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL2_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL2_INTR_SHIFT 7 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL1_INTR [06:06] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL1_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL1_INTR_SHIFT 6 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL0_INTR [05:05] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL0_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL0_INTR_SHIFT 5 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_ERR_INTR [04:04] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_ERR_INTR_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_ERR_INTR_SHIFT 4 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_MEM_DMA0_DONE [03:03] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_MEM_DMA0_DONE_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_MEM_DMA0_DONE_SHIFT 3 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_INTR [02:02] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_INTR_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_INTR_SHIFT 2 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_RCV_INTR [01:01] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_RCV_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_RCV_INTR_SHIFT 1 - -/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_XMIT_INTR [00:00] */ -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_XMIT_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_XMIT_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BOOT_VER_FAIL_MASK [23:23] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_FAIL_MASK_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_FAIL_MASK_SHIFT 23 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BOOT_VER_DONE_MASK [22:22] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_DONE_MASK_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_DONE_MASK_SHIFT 22 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PREMATURE_ARM_REQ_MASK [21:21] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PREMATURE_ARM_REQ_MASK_SHIFT 21 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BAD_STARCH_CFG_MASK [20:20] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BAD_STARCH_CFG_MASK_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BAD_STARCH_CFG_MASK_SHIFT 20 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SCRM_KEY_DONE_MASK [19:19] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SCRM_KEY_DONE_MASK_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SCRM_KEY_DONE_MASK_SHIFT 19 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BORCH_ERROR_MASK [18:18] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BORCH_ERROR_MASK_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BORCH_ERROR_MASK_SHIFT 18 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: GR_BRIDGE_ERROR_MASK [17:17] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_GR_BRIDGE_ERROR_MASK_SHIFT 17 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: MEM_DMA_MASK [16:16] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_MEM_DMA_MASK_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_MEM_DMA_MASK_SHIFT 16 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX4_MASK [15:15] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX4_MASK_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX4_MASK_SHIFT 15 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX3_MASK [14:14] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX3_MASK_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX3_MASK_SHIFT 14 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX2_MASK [13:13] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX2_MASK_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX2_MASK_SHIFT 13 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX1_MASK [12:12] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX1_MASK_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX1_MASK_SHIFT 12 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX4_MASK [11:11] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX4_MASK_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX4_MASK_SHIFT 11 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX3_MASK [10:10] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX3_MASK_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX3_MASK_SHIFT 10 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX2_MASK [09:09] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX2_MASK_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX2_MASK_SHIFT 9 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX1_MASK [08:08] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX1_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX1_MASK_SHIFT 8 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL2_MASK [07:07] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL2_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL2_MASK_SHIFT 7 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL1_MASK [06:06] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL1_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL1_MASK_SHIFT 6 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL0_MASK [05:05] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL0_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL0_MASK_SHIFT 5 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_ERR_MASK [04:04] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_ERR_MASK_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_ERR_MASK_SHIFT 4 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_MASK [02:02] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_MASK_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_MASK_SHIFT 2 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_RCV_MASK [01:01] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_RCV_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_RCV_MASK_SHIFT 1 - -/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_XMIT_MASK [00:00] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_XMIT_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_XMIT_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BOOT_VER_FAIL_MASK [23:23] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_FAIL_MASK_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_FAIL_MASK_SHIFT 23 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BOOT_VER_DONE_MASK [22:22] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_DONE_MASK_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_DONE_MASK_SHIFT 22 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PREMATURE_ARM_REQ_MASK [21:21] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PREMATURE_ARM_REQ_MASK_SHIFT 21 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BAD_STARCH_CFG_MASK [20:20] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BAD_STARCH_CFG_MASK_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BAD_STARCH_CFG_MASK_SHIFT 20 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SCRM_KEY_DONE_MASK [19:19] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SCRM_KEY_DONE_MASK_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SCRM_KEY_DONE_MASK_SHIFT 19 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BORCH_ERROR_MASK [18:18] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BORCH_ERROR_MASK_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BORCH_ERROR_MASK_SHIFT 18 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: GR_BRIDGE_ERROR_MASK [17:17] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_GR_BRIDGE_ERROR_MASK_SHIFT 17 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: MEM_DMA_MASK [16:16] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_MEM_DMA_MASK_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_MEM_DMA_MASK_SHIFT 16 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX4_MASK [15:15] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX4_MASK_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX4_MASK_SHIFT 15 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX3_MASK [14:14] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX3_MASK_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX3_MASK_SHIFT 14 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX2_MASK [13:13] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX2_MASK_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX2_MASK_SHIFT 13 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX1_MASK [12:12] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX1_MASK_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX1_MASK_SHIFT 12 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX4_MASK [11:11] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX4_MASK_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX4_MASK_SHIFT 11 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX3_MASK [10:10] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX3_MASK_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX3_MASK_SHIFT 10 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX2_MASK [09:09] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX2_MASK_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX2_MASK_SHIFT 9 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX1_MASK [08:08] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX1_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX1_MASK_SHIFT 8 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL2_MASK [07:07] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL2_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL2_MASK_SHIFT 7 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL1_MASK [06:06] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL1_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL1_MASK_SHIFT 6 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL0_MASK [05:05] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL0_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL0_MASK_SHIFT 5 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_ERR_MASK [04:04] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_ERR_MASK_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_ERR_MASK_SHIFT 4 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_MASK [02:02] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_MASK_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_MASK_SHIFT 2 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_RCV_MASK [01:01] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_RCV_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_RCV_MASK_SHIFT 1 - -/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_XMIT_MASK [00:00] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_XMIT_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_XMIT_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:24] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xff000000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 24 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BOOT_VER_FAIL_MASK [23:23] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_FAIL_MASK_MASK 0x00800000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_FAIL_MASK_SHIFT 23 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BOOT_VER_DONE_MASK [22:22] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_DONE_MASK_MASK 0x00400000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_DONE_MASK_SHIFT 22 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PREMATURE_ARM_REQ_MASK [21:21] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_SHIFT 21 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BAD_STARCH_CFG_MASK [20:20] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BAD_STARCH_CFG_MASK_MASK 0x00100000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BAD_STARCH_CFG_MASK_SHIFT 20 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SCRM_KEY_DONE_MASK [19:19] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SCRM_KEY_DONE_MASK_MASK 0x00080000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SCRM_KEY_DONE_MASK_SHIFT 19 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BORCH_ERROR_MASK [18:18] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BORCH_ERROR_MASK_MASK 0x00040000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BORCH_ERROR_MASK_SHIFT 18 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: GR_BRIDGE_ERROR_MASK [17:17] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_SHIFT 17 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: MEM_DMA_MASK [16:16] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_MEM_DMA_MASK_MASK 0x00010000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_MEM_DMA_MASK_SHIFT 16 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX4_MASK [15:15] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX4_MASK_MASK 0x00008000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX4_MASK_SHIFT 15 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX3_MASK [14:14] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX3_MASK_MASK 0x00004000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX3_MASK_SHIFT 14 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX2_MASK [13:13] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX2_MASK_MASK 0x00002000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX2_MASK_SHIFT 13 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX1_MASK [12:12] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX1_MASK_MASK 0x00001000 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX1_MASK_SHIFT 12 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX4_MASK [11:11] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX4_MASK_MASK 0x00000800 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX4_MASK_SHIFT 11 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX3_MASK [10:10] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX3_MASK_MASK 0x00000400 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX3_MASK_SHIFT 10 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX2_MASK [09:09] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX2_MASK_MASK 0x00000200 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX2_MASK_SHIFT 9 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX1_MASK [08:08] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX1_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX1_MASK_SHIFT 8 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL2_MASK [07:07] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL2_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL2_MASK_SHIFT 7 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL1_MASK [06:06] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL1_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL1_MASK_SHIFT 6 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL0_MASK [05:05] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL0_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL0_MASK_SHIFT 5 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_ERR_MASK [04:04] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_ERR_MASK_MASK 0x00000010 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_ERR_MASK_SHIFT 4 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_MASK [02:02] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_MASK_MASK 0x00000004 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_MASK_SHIFT 2 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_RCV_MASK [01:01] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_RCV_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_RCV_MASK_SHIFT 1 - -/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_XMIT_MASK [00:00] */ -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_XMIT_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_XMIT_MASK_SHIFT 0 - -#endif /* #ifndef BCHP_WRAP_MISC_INTR2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_secure_intr2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_secure_intr2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_secure_intr2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_secure_intr2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,490 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_wrap_misc_secure_intr2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:23p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:01 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_secure_intr2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:23p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_WRAP_MISC_SECURE_INTR2_H__ -#define BCHP_WRAP_MISC_SECURE_INTR2_H__ - -/*************************************************************************** - *WRAP_MISC_SECURE_INTR2 - MISC block secure Level 2 Interrupt Controller - ***************************************************************************/ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS 0x000ff500 /* CPU interrupt Status Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET 0x000ff504 /* CPU interrupt Set Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR 0x000ff508 /* CPU interrupt Clear Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS 0x000ff50c /* CPU interrupt Mask Status Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET 0x000ff510 /* CPU interrupt Mask Set Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR 0x000ff514 /* CPU interrupt Mask Clear Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS 0x000ff518 /* PCI interrupt Status Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET 0x000ff51c /* PCI interrupt Set Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR 0x000ff520 /* PCI interrupt Clear Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS 0x000ff524 /* PCI interrupt Mask Status Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET 0x000ff528 /* PCI interrupt Mask Set Register */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR 0x000ff52c /* PCI interrupt Mask Clear Register */ - -/*************************************************************************** - *CPU_STATUS - CPU interrupt Status Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: STARCH_SECURE_INTR [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_STARCH_SECURE_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_STARCH_SECURE_INTR_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: SHARF_SECURE_INTR [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_SHARF_SECURE_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_SHARF_SECURE_INTR_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: XPT_WR_CHECKER_INTR [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_XPT_WR_CHECKER_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_XPT_WR_CHECKER_INTR_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: AVD_VICH_INTR [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_AVD_VICH_INTR_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_AVD_VICH_INTR_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: ARB_WRITE_CHECKER_INTR [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_WRITE_CHECKER_INTR_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: ARB_SARCH_INTR [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_SARCH_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_SARCH_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_SET - CPU interrupt Set Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: STARCH_SECURE_INTR [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_STARCH_SECURE_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_STARCH_SECURE_INTR_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: SHARF_SECURE_INTR [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_SHARF_SECURE_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_SHARF_SECURE_INTR_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: XPT_WR_CHECKER_INTR [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_XPT_WR_CHECKER_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_XPT_WR_CHECKER_INTR_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: AVD_VICH_INTR [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_AVD_VICH_INTR_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_AVD_VICH_INTR_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: ARB_WRITE_CHECKER_INTR [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_WRITE_CHECKER_INTR_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: ARB_SARCH_INTR [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_SARCH_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_SARCH_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_CLEAR - CPU interrupt Clear Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: STARCH_SECURE_INTR [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_STARCH_SECURE_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_STARCH_SECURE_INTR_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: SHARF_SECURE_INTR [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_SHARF_SECURE_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_SHARF_SECURE_INTR_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: XPT_WR_CHECKER_INTR [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_XPT_WR_CHECKER_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_XPT_WR_CHECKER_INTR_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: AVD_VICH_INTR [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_AVD_VICH_INTR_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_AVD_VICH_INTR_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: ARB_WRITE_CHECKER_INTR [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_WRITE_CHECKER_INTR_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: ARB_SARCH_INTR [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_SARCH_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_SARCH_INTR_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_STATUS - CPU interrupt Mask Status Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: STARCH_SECURE_MASK [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_STARCH_SECURE_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_STARCH_SECURE_MASK_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: SHARF_SECURE_MASK [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_SHARF_SECURE_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_SHARF_SECURE_MASK_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: XPT_WR_CHECKER_MASK [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_XPT_WR_CHECKER_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_XPT_WR_CHECKER_MASK_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: AVD_VICH_MASK [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_AVD_VICH_MASK_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_AVD_VICH_MASK_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: ARB_WRITE_CHECKER_MASK [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_WRITE_CHECKER_MASK_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: ARB_SARCH_MASK [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_SARCH_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_SARCH_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_SET - CPU interrupt Mask Set Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: STARCH_SECURE_MASK [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_STARCH_SECURE_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_STARCH_SECURE_MASK_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: SHARF_SECURE_MASK [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_SHARF_SECURE_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_SHARF_SECURE_MASK_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: XPT_WR_CHECKER_MASK [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_XPT_WR_CHECKER_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_XPT_WR_CHECKER_MASK_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: AVD_VICH_MASK [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_AVD_VICH_MASK_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_AVD_VICH_MASK_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: ARB_WRITE_CHECKER_MASK [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_WRITE_CHECKER_MASK_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: ARB_SARCH_MASK [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_SARCH_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_SARCH_MASK_SHIFT 0 - -/*************************************************************************** - *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: STARCH_SECURE_MASK [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_STARCH_SECURE_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_STARCH_SECURE_MASK_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: SHARF_SECURE_MASK [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_SHARF_SECURE_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_SHARF_SECURE_MASK_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: XPT_WR_CHECKER_MASK [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_XPT_WR_CHECKER_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_XPT_WR_CHECKER_MASK_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: AVD_VICH_MASK [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_AVD_VICH_MASK_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_AVD_VICH_MASK_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: ARB_WRITE_CHECKER_MASK [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: ARB_SARCH_MASK [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_SARCH_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_SARCH_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_STATUS - PCI interrupt Status Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: STARCH_SECURE_INTR [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_STARCH_SECURE_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_STARCH_SECURE_INTR_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: SHARF_SECURE_INTR [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_SHARF_SECURE_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_SHARF_SECURE_INTR_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: XPT_WR_CHECKER_INTR [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_XPT_WR_CHECKER_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_XPT_WR_CHECKER_INTR_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: AVD_VICH_INTR [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_AVD_VICH_INTR_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_AVD_VICH_INTR_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: ARB_WRITE_CHECKER_INTR [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_WRITE_CHECKER_INTR_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: ARB_SARCH_INTR [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_SARCH_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_SARCH_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_SET - PCI interrupt Set Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: STARCH_SECURE_INTR [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_STARCH_SECURE_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_STARCH_SECURE_INTR_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: SHARF_SECURE_INTR [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_SHARF_SECURE_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_SHARF_SECURE_INTR_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: XPT_WR_CHECKER_INTR [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_XPT_WR_CHECKER_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_XPT_WR_CHECKER_INTR_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: AVD_VICH_INTR [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_AVD_VICH_INTR_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_AVD_VICH_INTR_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: ARB_WRITE_CHECKER_INTR [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_WRITE_CHECKER_INTR_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: ARB_SARCH_INTR [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_SARCH_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_SARCH_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_CLEAR - PCI interrupt Clear Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: STARCH_SECURE_INTR [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_STARCH_SECURE_INTR_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_STARCH_SECURE_INTR_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: SHARF_SECURE_INTR [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_SHARF_SECURE_INTR_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_SHARF_SECURE_INTR_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: XPT_WR_CHECKER_INTR [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_XPT_WR_CHECKER_INTR_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_XPT_WR_CHECKER_INTR_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: AVD_VICH_INTR [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_AVD_VICH_INTR_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_AVD_VICH_INTR_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: ARB_WRITE_CHECKER_INTR [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_WRITE_CHECKER_INTR_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: ARB_SARCH_INTR [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_SARCH_INTR_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_SARCH_INTR_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_STATUS - PCI interrupt Mask Status Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: STARCH_SECURE_MASK [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_STARCH_SECURE_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_STARCH_SECURE_MASK_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: SHARF_SECURE_MASK [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_SHARF_SECURE_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_SHARF_SECURE_MASK_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: XPT_WR_CHECKER_MASK [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_XPT_WR_CHECKER_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_XPT_WR_CHECKER_MASK_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: AVD_VICH_MASK [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_AVD_VICH_MASK_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_AVD_VICH_MASK_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: ARB_WRITE_CHECKER_MASK [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_WRITE_CHECKER_MASK_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: ARB_SARCH_MASK [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_SARCH_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_SARCH_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_SET - PCI interrupt Mask Set Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: STARCH_SECURE_MASK [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_STARCH_SECURE_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_STARCH_SECURE_MASK_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: SHARF_SECURE_MASK [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_SHARF_SECURE_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_SHARF_SECURE_MASK_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: XPT_WR_CHECKER_MASK [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_XPT_WR_CHECKER_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_XPT_WR_CHECKER_MASK_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: AVD_VICH_MASK [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_AVD_VICH_MASK_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_AVD_VICH_MASK_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: ARB_WRITE_CHECKER_MASK [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_WRITE_CHECKER_MASK_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: ARB_SARCH_MASK [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_SARCH_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_SARCH_MASK_SHIFT 0 - -/*************************************************************************** - *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register - ***************************************************************************/ -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:09] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xfffffe00 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 9 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: STARCH_SECURE_MASK [08:08] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_STARCH_SECURE_MASK_MASK 0x00000100 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_STARCH_SECURE_MASK_SHIFT 8 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: SHARF_SECURE_MASK [06:06] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_SHARF_SECURE_MASK_MASK 0x00000040 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_SHARF_SECURE_MASK_SHIFT 6 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: XPT_WR_CHECKER_MASK [05:05] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_XPT_WR_CHECKER_MASK_MASK 0x00000020 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_XPT_WR_CHECKER_MASK_SHIFT 5 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: AVD_VICH_MASK [04:02] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_AVD_VICH_MASK_MASK 0x0000001c -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_AVD_VICH_MASK_SHIFT 2 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: ARB_WRITE_CHECKER_MASK [01:01] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_SHIFT 1 - -/* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: ARB_SARCH_MASK [00:00] */ -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_SARCH_MASK_MASK 0x00000001 -#define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_SARCH_MASK_SHIFT 0 - -#endif /* #ifndef BCHP_WRAP_MISC_SECURE_INTR2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,250 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_bus_if.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:23p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:14 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:23p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_BUS_IF_H__ -#define BCHP_XPT_BUS_IF_H__ - -/*************************************************************************** - *XPT_BUS_IF - Data Transport Configuration Registers - ***************************************************************************/ -#define BCHP_XPT_BUS_IF_MISC_CTRL0 0x00200000 /* Data Transport Misc Control 0 Register */ -#define BCHP_XPT_BUS_IF_TEST_MODE 0x00200004 /* Data transport test register */ -#define BCHP_XPT_BUS_IF_REV_ID 0x00200008 /* Data Transport Revision Register */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG 0x00200038 /* Interrupt Status4 Register */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN 0x0020003c /* Interrupt Status4 Enable Register */ -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG 0x00200040 /* Interrupt Status5 Register */ -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN 0x00200044 /* Interrupt Status5 Enable Register */ -#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG 0x00200048 /* LCIF to XMEMIF Debug Registers */ -#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG 0x0020004c /* LCIF to XMEMIF Debug Registers */ -#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS 0x00200050 /* Data Transport max number of playbacks supported */ -#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS 0x00200058 /* Data Transport max number of PID channels supported */ -#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS 0x00200064 /* Data Transport max number of TPIT channels supported */ -#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS 0x00200068 /* Data Transport max number of RAVE contexts supported */ -#define BCHP_XPT_BUS_IF_MAX_SCDS 0x00200074 /* Data Transport max number of SCDs supported */ - -/*************************************************************************** - *MISC_CTRL0 - Data Transport Misc Control 0 Register - ***************************************************************************/ -/* XPT_BUS_IF :: MISC_CTRL0 :: reserved0 [31:03] */ -#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_SHIFT 3 - -/* XPT_BUS_IF :: MISC_CTRL0 :: ERROR_INT_TEST_MODE [02:02] */ -#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_MASK 0x00000004 -#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_SHIFT 2 - -/* XPT_BUS_IF :: MISC_CTRL0 :: reserved1 [01:01] */ -#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_MASK 0x00000002 -#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_SHIFT 1 - -/* XPT_BUS_IF :: MISC_CTRL0 :: LINK_LIST_DESC_ENDIAN_CTRL [00:00] */ -#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_MASK 0x00000001 -#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_SHIFT 0 - -/*************************************************************************** - *TEST_MODE - Data transport test register - ***************************************************************************/ -/* XPT_BUS_IF :: TEST_MODE :: reserved0 [31:01] */ -#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_MASK 0xfffffffe -#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_SHIFT 1 - -/* XPT_BUS_IF :: TEST_MODE :: PSG_SECRET_ENBLE [00:00] */ -#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_MASK 0x00000001 -#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_SHIFT 0 - -/*************************************************************************** - *REV_ID - Data Transport Revision Register - ***************************************************************************/ -/* XPT_BUS_IF :: REV_ID :: reserved0 [31:16] */ -#define BCHP_XPT_BUS_IF_REV_ID_reserved0_MASK 0xffff0000 -#define BCHP_XPT_BUS_IF_REV_ID_reserved0_SHIFT 16 - -/* XPT_BUS_IF :: REV_ID :: MAJOR_REV_NUMBER [15:08] */ -#define BCHP_XPT_BUS_IF_REV_ID_MAJOR_REV_NUMBER_MASK 0x0000ff00 -#define BCHP_XPT_BUS_IF_REV_ID_MAJOR_REV_NUMBER_SHIFT 8 - -/* XPT_BUS_IF :: REV_ID :: MINOR_REV_NUMBER [07:00] */ -#define BCHP_XPT_BUS_IF_REV_ID_MINOR_REV_NUMBER_MASK 0x000000ff -#define BCHP_XPT_BUS_IF_REV_ID_MINOR_REV_NUMBER_SHIFT 0 - -/*************************************************************************** - *INTR_STATUS4_REG - Interrupt Status4 Register - ***************************************************************************/ -/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved0 [31:15] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_MASK 0xffff8000 -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_SHIFT 15 - -/* XPT_BUS_IF :: INTR_STATUS4_REG :: GISB_BRIDGE [14:14] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_MASK 0x00004000 -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_SHIFT 14 - -/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved1 [13:00] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_MASK 0x00003fff -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_SHIFT 0 - -/*************************************************************************** - *INTR_STATUS4_REG_EN - Interrupt Status4 Enable Register - ***************************************************************************/ -/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved0 [31:15] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_MASK 0xffff8000 -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_SHIFT 15 - -/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: INTR_STATUS4_REG_EN [14:14] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_INTR_STATUS4_REG_EN_MASK 0x00004000 -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_INTR_STATUS4_REG_EN_SHIFT 14 - -/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved1 [13:00] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_MASK 0x00003fff -#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_SHIFT 0 - -/*************************************************************************** - *INTR_STATUS5_REG - Interrupt Status5 Register - ***************************************************************************/ -/* XPT_BUS_IF :: INTR_STATUS5_REG :: reserved0 [31:01] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_MASK 0xfffffffe -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_SHIFT 1 - -/* XPT_BUS_IF :: INTR_STATUS5_REG :: WRCHECKER_INT [00:00] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_MASK 0x00000001 -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_SHIFT 0 - -/*************************************************************************** - *INTR_STATUS5_REG_EN - Interrupt Status5 Enable Register - ***************************************************************************/ -/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: reserved0 [31:01] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_MASK 0xfffffffe -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_SHIFT 1 - -/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: INTR_STATUS5_REG_EN [00:00] */ -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_INTR_STATUS5_REG_EN_MASK 0x00000001 -#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_INTR_STATUS5_REG_EN_SHIFT 0 - -/*************************************************************************** - *XMEMIF_RD_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers - ***************************************************************************/ -/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: reserved0 [31:13] */ -#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved0_MASK 0xffffe000 -#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved0_SHIFT 13 - -/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: PB_DEBUG_REG [12:08] */ -#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_PB_DEBUG_REG_MASK 0x00001f00 -#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_PB_DEBUG_REG_SHIFT 8 - -/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: reserved1 [07:00] */ -#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved1_MASK 0x000000ff -#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved1_SHIFT 0 - -/*************************************************************************** - *XMEMIF_WR_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers - ***************************************************************************/ -/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: reserved0 [31:02] */ -#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_MASK 0xfffffffc -#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_SHIFT 2 - -/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RAVE_DEBUG_REG [01:00] */ -#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_MASK 0x00000003 -#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_SHIFT 0 - -/*************************************************************************** - *MAX_PLAYBACKS - Data Transport max number of playbacks supported - ***************************************************************************/ -/* XPT_BUS_IF :: MAX_PLAYBACKS :: reserved0 [31:04] */ -#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_SHIFT 4 - -/* XPT_BUS_IF :: MAX_PLAYBACKS :: MAX_PLAYBACKS [03:00] */ -#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_MASK 0x0000000f -#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_SHIFT 0 - -/*************************************************************************** - *MAX_PID_CHANNELS - Data Transport max number of PID channels supported - ***************************************************************************/ -/* XPT_BUS_IF :: MAX_PID_CHANNELS :: reserved0 [31:12] */ -#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_MASK 0xfffff000 -#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_SHIFT 12 - -/* XPT_BUS_IF :: MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */ -#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK 0x00000fff -#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT 0 - -/*************************************************************************** - *MAX_TPIT_CHANNELS - Data Transport max number of TPIT channels supported - ***************************************************************************/ -/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: reserved0 [31:04] */ -#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_SHIFT 4 - -/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: MAX_TPIT_CHANNELS [03:00] */ -#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_MASK 0x0000000f -#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_SHIFT 0 - -/*************************************************************************** - *MAX_RAVE_CONTEXTS - Data Transport max number of RAVE contexts supported - ***************************************************************************/ -/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: reserved0 [31:08] */ -#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_SHIFT 8 - -/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: MAX_RAVE_CONTEXTS [07:00] */ -#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_MASK 0x000000ff -#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_SHIFT 0 - -/*************************************************************************** - *MAX_SCDS - Data Transport max number of SCDs supported - ***************************************************************************/ -/* XPT_BUS_IF :: MAX_SCDS :: reserved0 [31:08] */ -#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_SHIFT 8 - -/* XPT_BUS_IF :: MAX_SCDS :: MAX_SCDS [07:00] */ -#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_MASK 0x000000ff -#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_SHIFT 0 - -#endif /* #ifndef BCHP_XPT_BUS_IF_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,449 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_fe.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:23p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:20 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:23p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_FE_H__ -#define BCHP_XPT_FE_H__ - -/*************************************************************************** - *XPT_FE - XPT FRONTEND Control Registers - ***************************************************************************/ -#define BCHP_XPT_FE_INTR_STATUS_REG 0x00208010 /* Interrupt Status Register */ -#define BCHP_XPT_FE_INTR_STATUS_REG_EN 0x00208014 /* Interrupt Status Enable Register */ -#define BCHP_XPT_FE_MAX_PID_CHANNEL 0x0020801c /* Maximum Pid Channel number register */ -#define BCHP_XPT_FE_PSG_CFG 0x00208300 /* Passage Config Register */ -#define BCHP_XPT_FE_PSG_RESET0 0x0020831c /* Passage Per PID Reset for Secondary PID Channels 0-31 Register */ -#define BCHP_XPT_FE_PSG_RESET1 0x00208320 /* Passage Per PID Reset for Secondary PID Channels 32-63 Register */ -#define BCHP_XPT_FE_PSG_RESET2 0x0020835c /* Passage Per PID Reset for Secondary PID Channels 64-95 Register */ -#define BCHP_XPT_FE_PSG_RESET3 0x00208360 /* Passage Per PID Reset for Secondary PID Channels 96-127 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR0 0x00208374 /* Passage Per PID Protocol Error for PID Channels 0-31 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR1 0x00208378 /* Passage Per PID Protocol Error for PID Channels 32-63 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR2 0x0020837c /* Passage Per PID Protocol Error for PID Channels 95-64 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR3 0x00208380 /* Passage Per PID Protocol Error for PID Channels 127-96 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN0 0x00208394 /* Passage Per PID Protocol Error Enable for PID Channels 0-31 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN1 0x00208398 /* Passage Per PID Protocol Error Enable for PID Channels 32-63 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN2 0x0020839c /* Passage Per PID Protocol Error Enable for PID Channels 64-95 Register */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN3 0x002083a0 /* Passage Per PID Protocol Error Enable for PID Channels 96-127 Register */ -#define BCHP_XPT_FE_SCC_ERROR0 0x002083b4 /* Per PID Secondary CC Error for PID Channels 0-31 Register */ -#define BCHP_XPT_FE_SCC_ERROR1 0x002083b8 /* Per PID Secondary CC Error for PID Channels 32-63 Register */ -#define BCHP_XPT_FE_SCC_ERROR2 0x002083bc /* Per PID Secondary CC Error for PID Channels 64-95 Register */ -#define BCHP_XPT_FE_SCC_ERROR3 0x002083c0 /* Per PID Secondary CC Error for PID Channels 96-127 Register */ -#define BCHP_XPT_FE_PCC_ERROR0 0x002083d4 /* Per PID Primary CC Error for PID Channels 0-31 Register */ -#define BCHP_XPT_FE_PCC_ERROR1 0x002083d8 /* Per PID Primary CC Error for PID Channels 32-63 Register */ -#define BCHP_XPT_FE_PCC_ERROR2 0x002083dc /* Per PID Primary CC Error for PID Channels 64-95 Register */ -#define BCHP_XPT_FE_PCC_ERROR3 0x002083e0 /* Per PID Primary CC Error for PID Channels 96-127 Register */ -#define BCHP_XPT_FE_PID_ERR_SNIFFER 0x002083f4 /* PID Error Sniffer Register */ - -/*************************************************************************** - *INTR_STATUS_REG - Interrupt Status Register - ***************************************************************************/ -/* XPT_FE :: INTR_STATUS_REG :: reserved0 [31:30] */ -#define BCHP_XPT_FE_INTR_STATUS_REG_reserved0_MASK 0xc0000000 -#define BCHP_XPT_FE_INTR_STATUS_REG_reserved0_SHIFT 30 - -/* XPT_FE :: INTR_STATUS_REG :: PSG_PROTOCOL_ERROR [29:29] */ -#define BCHP_XPT_FE_INTR_STATUS_REG_PSG_PROTOCOL_ERROR_MASK 0x20000000 -#define BCHP_XPT_FE_INTR_STATUS_REG_PSG_PROTOCOL_ERROR_SHIFT 29 - -/* XPT_FE :: INTR_STATUS_REG :: reserved1 [28:00] */ -#define BCHP_XPT_FE_INTR_STATUS_REG_reserved1_MASK 0x1fffffff -#define BCHP_XPT_FE_INTR_STATUS_REG_reserved1_SHIFT 0 - -/*************************************************************************** - *INTR_STATUS_REG_EN - Interrupt Status Enable Register - ***************************************************************************/ -/* XPT_FE :: INTR_STATUS_REG_EN :: reserved0 [31:30] */ -#define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved0_MASK 0xc0000000 -#define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved0_SHIFT 30 - -/* XPT_FE :: INTR_STATUS_REG_EN :: INTR_STATUS_REG_EN [29:29] */ -#define BCHP_XPT_FE_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_MASK 0x20000000 -#define BCHP_XPT_FE_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_SHIFT 29 - -/* XPT_FE :: INTR_STATUS_REG_EN :: reserved1 [28:00] */ -#define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved1_MASK 0x1fffffff -#define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved1_SHIFT 0 - -/*************************************************************************** - *MAX_PID_CHANNEL - Maximum Pid Channel number register - ***************************************************************************/ -/* XPT_FE :: MAX_PID_CHANNEL :: reserved0 [31:07] */ -#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_MASK 0xffffff80 -#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_SHIFT 7 - -/* XPT_FE :: MAX_PID_CHANNEL :: MAX_PID_CHANNEL [06:00] */ -#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_MASK 0x0000007f -#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_SHIFT 0 - -/*************************************************************************** - *PSG_CFG - Passage Config Register - ***************************************************************************/ -/* XPT_FE :: PSG_CFG :: reserved0 [31:12] */ -#define BCHP_XPT_FE_PSG_CFG_reserved0_MASK 0xfffff000 -#define BCHP_XPT_FE_PSG_CFG_reserved0_SHIFT 12 - -/* XPT_FE :: PSG_CFG :: PSG_PBP2_DROP_ON_SCC_ERR [11:11] */ -#define BCHP_XPT_FE_PSG_CFG_PSG_PBP2_DROP_ON_SCC_ERR_MASK 0x00000800 -#define BCHP_XPT_FE_PSG_CFG_PSG_PBP2_DROP_ON_SCC_ERR_SHIFT 11 - -/* XPT_FE :: PSG_CFG :: PSG_PBP1_DROP_ON_SCC_ERR [10:10] */ -#define BCHP_XPT_FE_PSG_CFG_PSG_PBP1_DROP_ON_SCC_ERR_MASK 0x00000400 -#define BCHP_XPT_FE_PSG_CFG_PSG_PBP1_DROP_ON_SCC_ERR_SHIFT 10 - -/* XPT_FE :: PSG_CFG :: PSG_PBP0_DROP_ON_SCC_ERR [09:09] */ -#define BCHP_XPT_FE_PSG_CFG_PSG_PBP0_DROP_ON_SCC_ERR_MASK 0x00000200 -#define BCHP_XPT_FE_PSG_CFG_PSG_PBP0_DROP_ON_SCC_ERR_SHIFT 9 - -/* XPT_FE :: PSG_CFG :: reserved1 [08:02] */ -#define BCHP_XPT_FE_PSG_CFG_reserved1_MASK 0x000001fc -#define BCHP_XPT_FE_PSG_CFG_reserved1_SHIFT 2 - -/* XPT_FE :: PSG_CFG :: PSG_START_IMMEDIATE [01:01] */ -#define BCHP_XPT_FE_PSG_CFG_PSG_START_IMMEDIATE_MASK 0x00000002 -#define BCHP_XPT_FE_PSG_CFG_PSG_START_IMMEDIATE_SHIFT 1 - -/* XPT_FE :: PSG_CFG :: PSG_MASTER_EN [00:00] */ -#define BCHP_XPT_FE_PSG_CFG_PSG_MASTER_EN_MASK 0x00000001 -#define BCHP_XPT_FE_PSG_CFG_PSG_MASTER_EN_SHIFT 0 - -/*************************************************************************** - *PSG_RESET0 - Passage Per PID Reset for Secondary PID Channels 0-31 Register - ***************************************************************************/ -/* XPT_FE :: PSG_RESET0 :: PSG_RST [31:00] */ -#define BCHP_XPT_FE_PSG_RESET0_PSG_RST_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_RESET0_PSG_RST_SHIFT 0 - -/*************************************************************************** - *PSG_RESET1 - Passage Per PID Reset for Secondary PID Channels 32-63 Register - ***************************************************************************/ -/* XPT_FE :: PSG_RESET1 :: PSG_RST [31:00] */ -#define BCHP_XPT_FE_PSG_RESET1_PSG_RST_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_RESET1_PSG_RST_SHIFT 0 - -/*************************************************************************** - *PSG_RESET2 - Passage Per PID Reset for Secondary PID Channels 64-95 Register - ***************************************************************************/ -/* XPT_FE :: PSG_RESET2 :: PSG_RST [31:00] */ -#define BCHP_XPT_FE_PSG_RESET2_PSG_RST_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_RESET2_PSG_RST_SHIFT 0 - -/*************************************************************************** - *PSG_RESET3 - Passage Per PID Reset for Secondary PID Channels 96-127 Register - ***************************************************************************/ -/* XPT_FE :: PSG_RESET3 :: PSG_RST [31:00] */ -#define BCHP_XPT_FE_PSG_RESET3_PSG_RST_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_RESET3_PSG_RST_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR0 - Passage Per PID Protocol Error for PID Channels 0-31 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR0 :: PSG_PR_ERROR [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR0_PSG_PR_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR0_PSG_PR_ERROR_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR1 - Passage Per PID Protocol Error for PID Channels 32-63 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR1 :: PSG_PR_ERROR [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR1_PSG_PR_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR1_PSG_PR_ERROR_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR2 - Passage Per PID Protocol Error for PID Channels 95-64 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR2 :: PSG_PR_ERROR [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR2_PSG_PR_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR2_PSG_PR_ERROR_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR3 - Passage Per PID Protocol Error for PID Channels 127-96 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR3 :: PSG_PR_ERROR [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR3_PSG_PR_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR3_PSG_PR_ERROR_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR_EN0 - Passage Per PID Protocol Error Enable for PID Channels 0-31 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR_EN0 :: PSG_PR_ERROR_EN [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN0_PSG_PR_ERROR_EN_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR_EN0_PSG_PR_ERROR_EN_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR_EN1 - Passage Per PID Protocol Error Enable for PID Channels 32-63 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR_EN1 :: PSG_PR_ERROR_EN [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN1_PSG_PR_ERROR_EN_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR_EN1_PSG_PR_ERROR_EN_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR_EN2 - Passage Per PID Protocol Error Enable for PID Channels 64-95 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR_EN2 :: PSG_PR_ERROR_EN [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN2_PSG_PR_ERROR_EN_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR_EN2_PSG_PR_ERROR_EN_SHIFT 0 - -/*************************************************************************** - *PSG_PR_ERR_EN3 - Passage Per PID Protocol Error Enable for PID Channels 96-127 Register - ***************************************************************************/ -/* XPT_FE :: PSG_PR_ERR_EN3 :: PSG_PR_ERROR_EN [31:00] */ -#define BCHP_XPT_FE_PSG_PR_ERR_EN3_PSG_PR_ERROR_EN_MASK 0xffffffff -#define BCHP_XPT_FE_PSG_PR_ERR_EN3_PSG_PR_ERROR_EN_SHIFT 0 - -/*************************************************************************** - *SCC_ERROR0 - Per PID Secondary CC Error for PID Channels 0-31 Register - ***************************************************************************/ -/* XPT_FE :: SCC_ERROR0 :: SCC_ERROR [31:00] */ -#define BCHP_XPT_FE_SCC_ERROR0_SCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_SCC_ERROR0_SCC_ERROR_SHIFT 0 - -/*************************************************************************** - *SCC_ERROR1 - Per PID Secondary CC Error for PID Channels 32-63 Register - ***************************************************************************/ -/* XPT_FE :: SCC_ERROR1 :: SCC_ERROR [31:00] */ -#define BCHP_XPT_FE_SCC_ERROR1_SCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_SCC_ERROR1_SCC_ERROR_SHIFT 0 - -/*************************************************************************** - *SCC_ERROR2 - Per PID Secondary CC Error for PID Channels 64-95 Register - ***************************************************************************/ -/* XPT_FE :: SCC_ERROR2 :: SCC_ERROR [31:00] */ -#define BCHP_XPT_FE_SCC_ERROR2_SCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_SCC_ERROR2_SCC_ERROR_SHIFT 0 - -/*************************************************************************** - *SCC_ERROR3 - Per PID Secondary CC Error for PID Channels 96-127 Register - ***************************************************************************/ -/* XPT_FE :: SCC_ERROR3 :: SCC_ERROR [31:00] */ -#define BCHP_XPT_FE_SCC_ERROR3_SCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_SCC_ERROR3_SCC_ERROR_SHIFT 0 - -/*************************************************************************** - *PCC_ERROR0 - Per PID Primary CC Error for PID Channels 0-31 Register - ***************************************************************************/ -/* XPT_FE :: PCC_ERROR0 :: PCC_ERROR [31:00] */ -#define BCHP_XPT_FE_PCC_ERROR0_PCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PCC_ERROR0_PCC_ERROR_SHIFT 0 - -/*************************************************************************** - *PCC_ERROR1 - Per PID Primary CC Error for PID Channels 32-63 Register - ***************************************************************************/ -/* XPT_FE :: PCC_ERROR1 :: PCC_ERROR [31:00] */ -#define BCHP_XPT_FE_PCC_ERROR1_PCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PCC_ERROR1_PCC_ERROR_SHIFT 0 - -/*************************************************************************** - *PCC_ERROR2 - Per PID Primary CC Error for PID Channels 64-95 Register - ***************************************************************************/ -/* XPT_FE :: PCC_ERROR2 :: PCC_ERROR [31:00] */ -#define BCHP_XPT_FE_PCC_ERROR2_PCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PCC_ERROR2_PCC_ERROR_SHIFT 0 - -/*************************************************************************** - *PCC_ERROR3 - Per PID Primary CC Error for PID Channels 96-127 Register - ***************************************************************************/ -/* XPT_FE :: PCC_ERROR3 :: PCC_ERROR [31:00] */ -#define BCHP_XPT_FE_PCC_ERROR3_PCC_ERROR_MASK 0xffffffff -#define BCHP_XPT_FE_PCC_ERROR3_PCC_ERROR_SHIFT 0 - -/*************************************************************************** - *PID_ERR_SNIFFER - PID Error Sniffer Register - ***************************************************************************/ -/* XPT_FE :: PID_ERR_SNIFFER :: SNIF_ERROR_COUNT [31:16] */ -#define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_ERROR_COUNT_MASK 0xffff0000 -#define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_ERROR_COUNT_SHIFT 16 - -/* XPT_FE :: PID_ERR_SNIFFER :: reserved0 [15:07] */ -#define BCHP_XPT_FE_PID_ERR_SNIFFER_reserved0_MASK 0x0000ff80 -#define BCHP_XPT_FE_PID_ERR_SNIFFER_reserved0_SHIFT 7 - -/* XPT_FE :: PID_ERR_SNIFFER :: SNIF_PID_CHANNEL_NUMBER [06:00] */ -#define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_PID_CHANNEL_NUMBER_MASK 0x0000007f -#define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_PID_CHANNEL_NUMBER_SHIFT 0 - -/*************************************************************************** - *PID_TABLE_%i - Data Transport Primary PID Table - ***************************************************************************/ -#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_BASE 0x00208800 -#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_START 0 -#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_END 127 -#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *PID_TABLE_%i - Data Transport Primary PID Table - ***************************************************************************/ -/* XPT_FE :: PID_TABLE_i :: reserved0 [31:29] */ -#define BCHP_XPT_FE_PID_TABLE_i_reserved0_MASK 0xe0000000 -#define BCHP_XPT_FE_PID_TABLE_i_reserved0_SHIFT 29 - -/* XPT_FE :: PID_TABLE_i :: IGNORE_PID_VERSION [28:28] */ -#define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_MASK 0x10000000 -#define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_SHIFT 28 - -/* XPT_FE :: PID_TABLE_i :: PLAYBACK_FE_SEL [27:27] */ -#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_MASK 0x08000000 -#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_SHIFT 27 - -/* XPT_FE :: PID_TABLE_i :: PID_VERSION [26:24] */ -#define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_MASK 0x07000000 -#define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_SHIFT 24 - -/* XPT_FE :: PID_TABLE_i :: reserved1 [23:21] */ -#define BCHP_XPT_FE_PID_TABLE_i_reserved1_MASK 0x00e00000 -#define BCHP_XPT_FE_PID_TABLE_i_reserved1_SHIFT 21 - -/* XPT_FE :: PID_TABLE_i :: PID_CHANNEL_ENABLE [20:20] */ -#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_MASK 0x00100000 -#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_SHIFT 20 - -/* XPT_FE :: PID_TABLE_i :: PID_CHANNEL_INPUT_SELECT [19:16] */ -#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_INPUT_SELECT_MASK 0x000f0000 -#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_INPUT_SELECT_SHIFT 16 - -/* XPT_FE :: PID_TABLE_i :: reserved2 [15:14] */ -#define BCHP_XPT_FE_PID_TABLE_i_reserved2_MASK 0x0000c000 -#define BCHP_XPT_FE_PID_TABLE_i_reserved2_SHIFT 14 - -/* XPT_FE :: PID_TABLE_i :: ENABLE_HD_FILTER [13:13] */ -#define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_MASK 0x00002000 -#define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_SHIFT 13 - -/* union - case HD_FILT_EN [12:00] */ -/* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: HD_FILTER_TYPE [12:12] */ -#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_MASK 0x00001000 -#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_SHIFT 12 - -/* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: PID_CHANNEL_SCID [11:00] */ -#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_MASK 0x00000fff -#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_SHIFT 0 - -/* union - case HD_FILT_DIS [12:00] */ -/* XPT_FE :: PID_TABLE_i :: HD_FILT_DIS :: PID_CHANNEL_PID [12:00] */ -#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_MASK 0x00001fff -#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_SHIFT 0 - - -/*************************************************************************** - *SPID_TABLE_%i - Data Transport Secondary PID Table - ***************************************************************************/ -#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_BASE 0x00208c00 -#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_START 0 -#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_END 127 -#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *SPID_TABLE_%i - Data Transport Secondary PID Table - ***************************************************************************/ -/* XPT_FE :: SPID_TABLE_i :: PID_DESTINATION [31:24] */ -#define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_MASK 0xff000000 -#define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_SHIFT 24 - -/* XPT_FE :: SPID_TABLE_i :: reserved0 [23:20] */ -#define BCHP_XPT_FE_SPID_TABLE_i_reserved0_MASK 0x00f00000 -#define BCHP_XPT_FE_SPID_TABLE_i_reserved0_SHIFT 20 - -/* XPT_FE :: SPID_TABLE_i :: SPID_MODE [19:16] */ -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_MASK 0x000f0000 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SHIFT 16 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_DISABLE_SPID 0 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_INSERTION 5 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE 6 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_REMAP 7 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_FILTER 8 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_RANGE 10 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_EXTENSION_FILTER 12 -#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SUBSTREAM_ID_FILTER 14 - -/* union - case STREAM_ID_FILTER [15:00] */ -/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: STREAM_ID [15:08] */ -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_MASK 0x0000ff00 -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_SHIFT 8 - -/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: reserved0 [07:00] */ -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_MASK 0x000000ff -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_SHIFT 0 - -/* union - case STREAM_ID_RANGE [15:00] */ -/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_SHIFT 8 - -/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_SHIFT 0 - -/* union - case STREAM_ID_EXTENSION_FILTER [15:00] */ -/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID [15:08] */ -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_MASK 0x0000ff00 -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_SHIFT 8 - -/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID_EXTENSION [07:00] */ -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_MASK 0x000000ff -#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_SHIFT 0 - -/* union - case SUBSTREAM_ID_FILTER [15:00] */ -/* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: STREAM_ID [15:08] */ -#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_MASK 0x0000ff00 -#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_SHIFT 8 - -/* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: SUBSTREAM_ID [07:00] */ -#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_MASK 0x000000ff -#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_SHIFT 0 - -/* union - case PID_FUNCTIONS [15:00] */ -/* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: reserved0 [15:13] */ -#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_MASK 0x0000e000 -#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_SHIFT 13 - -/* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: SPID_CHANNEL_PID [12:00] */ -#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_MASK 0x00001fff -#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_SHIFT 0 - - -#endif /* #ifndef BCHP_XPT_FE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,104 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_gr.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:23p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:11 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:23p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_GR_H__ -#define BCHP_XPT_GR_H__ - -/*************************************************************************** - *XPT_GR - XPT GR_BRIDGE Control Registers - ***************************************************************************/ -#define BCHP_XPT_GR_REVISION 0x00230000 /* GR Bridge Revision */ -#define BCHP_XPT_GR_CTRL 0x00230004 /* GR Bridge Control Register */ -#define BCHP_XPT_GR_SW_RESET_0 0x00230008 /* GR Bridge Software Reset 0 Register */ -#define BCHP_XPT_GR_SW_RESET_1 0x0023000c /* GR Bridge Software Reset 1 Register */ - -/*************************************************************************** - *REVISION - GR Bridge Revision - ***************************************************************************/ -/* XPT_GR :: REVISION :: reserved0 [31:16] */ -#define BCHP_XPT_GR_REVISION_reserved0_MASK 0xffff0000 -#define BCHP_XPT_GR_REVISION_reserved0_SHIFT 16 - -/* XPT_GR :: REVISION :: MAJOR [15:08] */ -#define BCHP_XPT_GR_REVISION_MAJOR_MASK 0x0000ff00 -#define BCHP_XPT_GR_REVISION_MAJOR_SHIFT 8 - -/* XPT_GR :: REVISION :: MINOR [07:00] */ -#define BCHP_XPT_GR_REVISION_MINOR_MASK 0x000000ff -#define BCHP_XPT_GR_REVISION_MINOR_SHIFT 0 - -/*************************************************************************** - *CTRL - GR Bridge Control Register - ***************************************************************************/ -/* XPT_GR :: CTRL :: reserved0 [31:01] */ -#define BCHP_XPT_GR_CTRL_reserved0_MASK 0xfffffffe -#define BCHP_XPT_GR_CTRL_reserved0_SHIFT 1 - -/* XPT_GR :: CTRL :: gisb_error_intr [00:00] */ -#define BCHP_XPT_GR_CTRL_gisb_error_intr_MASK 0x00000001 -#define BCHP_XPT_GR_CTRL_gisb_error_intr_SHIFT 0 -#define BCHP_XPT_GR_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define BCHP_XPT_GR_CTRL_gisb_error_intr_INTR_ENABLE 1 - -/*************************************************************************** - *SW_RESET_0 - GR Bridge Software Reset 0 Register - ***************************************************************************/ -/* XPT_GR :: SW_RESET_0 :: reserved0 [31:00] */ -#define BCHP_XPT_GR_SW_RESET_0_reserved0_MASK 0xffffffff -#define BCHP_XPT_GR_SW_RESET_0_reserved0_SHIFT 0 - -/*************************************************************************** - *SW_RESET_1 - GR Bridge Software Reset 1 Register - ***************************************************************************/ -/* XPT_GR :: SW_RESET_1 :: reserved0 [31:00] */ -#define BCHP_XPT_GR_SW_RESET_1_reserved0_MASK 0xffffffff -#define BCHP_XPT_GR_SW_RESET_1_reserved0_SHIFT 0 - -#endif /* #ifndef BCHP_XPT_GR_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,570 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_pb0.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:24p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:42 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:24p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_PB0_H__ -#define BCHP_XPT_PB0_H__ - -/*************************************************************************** - *XPT_PB0 - Playback 0 Control Registers - ***************************************************************************/ -#define BCHP_XPT_PB0_CTRL1 0x0020b000 /* Playback Control 1 Register */ -#define BCHP_XPT_PB0_CTRL2 0x0020b004 /* Playback Control 2 Register */ -#define BCHP_XPT_PB0_CTRL3 0x0020b008 /* Playback Control 3 Register */ -#define BCHP_XPT_PB0_CTRL4 0x0020b00c /* Playback Control 4 Register */ -#define BCHP_XPT_PB0_FIRST_DESC_ADDR 0x0020b010 /* Playback First Descriptor Address Register */ -#define BCHP_XPT_PB0_CURR_DESC_ADDR 0x0020b014 /* Playback Current Descriptor Address Register */ -#define BCHP_XPT_PB0_CURR_BUFF_ADDR 0x0020b018 /* Playback Current Buffer Address Register */ -#define BCHP_XPT_PB0_BLOCKOUT 0x0020b01c /* Data Transport Playback Block Out Control */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT0 0x0020b020 /* Data Transport Playback Packetize Mode Context 0 Control */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT1 0x0020b024 /* Data Transport Playback Packetize Mode Context 1 Control */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT2 0x0020b028 /* Data Transport Playback Packetize Mode Context 2 Control */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT3 0x0020b02c /* Data Transport Playback Packetize Mode Context 3 Control */ -#define BCHP_XPT_PB0_TS_ERR_BOUND 0x0020b030 /* Data Transport Playback Timestamp Error Bound Register */ -#define BCHP_XPT_PB0_PARSER_CTRL1 0x0020b034 /* Data Transport Playback Parser Control Register */ -#define BCHP_XPT_PB0_PARSER_CTRL2 0x0020b038 /* Data Transport Playback Parser Control Register 2 */ -#define BCHP_XPT_PB0_PARSER_TIMESTAMP 0x0020b03c /* Data Transport Playback Parser Local Timestamp */ -#define BCHP_XPT_PB0_INTR 0x0020b040 /* Playback Processing Error and Status Interrupt Register */ -#define BCHP_XPT_PB0_INTR_EN 0x0020b044 /* Playback Processing Error and Status Interrupt Enable Register */ -#define BCHP_XPT_PB0_INTR_TAGS 0x0020b048 /* Playback Interrupt Tag Register */ - -/*************************************************************************** - *CTRL1 - Playback Control 1 Register - ***************************************************************************/ -/* XPT_PB0 :: CTRL1 :: reserved0 [31:06] */ -#define BCHP_XPT_PB0_CTRL1_reserved0_MASK 0xffffffc0 -#define BCHP_XPT_PB0_CTRL1_reserved0_SHIFT 6 - -/* XPT_PB0 :: CTRL1 :: WAKE_MODE [05:05] */ -#define BCHP_XPT_PB0_CTRL1_WAKE_MODE_MASK 0x00000020 -#define BCHP_XPT_PB0_CTRL1_WAKE_MODE_SHIFT 5 - -/* XPT_PB0 :: CTRL1 :: OUT_OF_SYNC_STATUS [04:04] */ -#define BCHP_XPT_PB0_CTRL1_OUT_OF_SYNC_STATUS_MASK 0x00000010 -#define BCHP_XPT_PB0_CTRL1_OUT_OF_SYNC_STATUS_SHIFT 4 - -/* XPT_PB0 :: CTRL1 :: FINISHED [03:03] */ -#define BCHP_XPT_PB0_CTRL1_FINISHED_MASK 0x00000008 -#define BCHP_XPT_PB0_CTRL1_FINISHED_SHIFT 3 - -/* XPT_PB0 :: CTRL1 :: BUSY [02:02] */ -#define BCHP_XPT_PB0_CTRL1_BUSY_MASK 0x00000004 -#define BCHP_XPT_PB0_CTRL1_BUSY_SHIFT 2 - -/* XPT_PB0 :: CTRL1 :: RUN [01:01] */ -#define BCHP_XPT_PB0_CTRL1_RUN_MASK 0x00000002 -#define BCHP_XPT_PB0_CTRL1_RUN_SHIFT 1 - -/* XPT_PB0 :: CTRL1 :: WAKE [00:00] */ -#define BCHP_XPT_PB0_CTRL1_WAKE_MASK 0x00000001 -#define BCHP_XPT_PB0_CTRL1_WAKE_SHIFT 0 - -/*************************************************************************** - *CTRL2 - Playback Control 2 Register - ***************************************************************************/ -/* XPT_PB0 :: CTRL2 :: reserved0 [31:25] */ -#define BCHP_XPT_PB0_CTRL2_reserved0_MASK 0xfe000000 -#define BCHP_XPT_PB0_CTRL2_reserved0_SHIFT 25 - -/* XPT_PB0 :: CTRL2 :: REARM_TS_COUNTER [24:24] */ -#define BCHP_XPT_PB0_CTRL2_REARM_TS_COUNTER_MASK 0x01000000 -#define BCHP_XPT_PB0_CTRL2_REARM_TS_COUNTER_SHIFT 24 - -/* XPT_PB0 :: CTRL2 :: TIMESTAMP_MODE_32BIT [23:23] */ -#define BCHP_XPT_PB0_CTRL2_TIMESTAMP_MODE_32BIT_MASK 0x00800000 -#define BCHP_XPT_PB0_CTRL2_TIMESTAMP_MODE_32BIT_SHIFT 23 - -/* XPT_PB0 :: CTRL2 :: PROGRAM_STREAM_MODE [22:22] */ -#define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_MODE_MASK 0x00400000 -#define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_MODE_SHIFT 22 - -/* XPT_PB0 :: CTRL2 :: TS_PARITY_CHECK_DIS [21:21] */ -#define BCHP_XPT_PB0_CTRL2_TS_PARITY_CHECK_DIS_MASK 0x00200000 -#define BCHP_XPT_PB0_CTRL2_TS_PARITY_CHECK_DIS_SHIFT 21 - -/* XPT_PB0 :: CTRL2 :: TIMESTAMP_EN [20:20] */ -#define BCHP_XPT_PB0_CTRL2_TIMESTAMP_EN_MASK 0x00100000 -#define BCHP_XPT_PB0_CTRL2_TIMESTAMP_EN_SHIFT 20 - -/* XPT_PB0 :: CTRL2 :: SYNC_EXT_MODE [19:17] */ -#define BCHP_XPT_PB0_CTRL2_SYNC_EXT_MODE_MASK 0x000e0000 -#define BCHP_XPT_PB0_CTRL2_SYNC_EXT_MODE_SHIFT 17 - -/* XPT_PB0 :: CTRL2 :: reserved1 [16:09] */ -#define BCHP_XPT_PB0_CTRL2_reserved1_MASK 0x0001fe00 -#define BCHP_XPT_PB0_CTRL2_reserved1_SHIFT 9 - -/* XPT_PB0 :: CTRL2 :: MICRO_PAUSE [08:08] */ -#define BCHP_XPT_PB0_CTRL2_MICRO_PAUSE_MASK 0x00000100 -#define BCHP_XPT_PB0_CTRL2_MICRO_PAUSE_SHIFT 8 - -/* XPT_PB0 :: CTRL2 :: ENDIAN_CTRL [07:07] */ -#define BCHP_XPT_PB0_CTRL2_ENDIAN_CTRL_MASK 0x00000080 -#define BCHP_XPT_PB0_CTRL2_ENDIAN_CTRL_SHIFT 7 - -/* XPT_PB0 :: CTRL2 :: reserved2 [06:06] */ -#define BCHP_XPT_PB0_CTRL2_reserved2_MASK 0x00000040 -#define BCHP_XPT_PB0_CTRL2_reserved2_SHIFT 6 - -/* XPT_PB0 :: CTRL2 :: TS_RANGE_MODE [05:05] */ -#define BCHP_XPT_PB0_CTRL2_TS_RANGE_MODE_MASK 0x00000020 -#define BCHP_XPT_PB0_CTRL2_TS_RANGE_MODE_SHIFT 5 - -/* XPT_PB0 :: CTRL2 :: PACING_START [04:04] */ -#define BCHP_XPT_PB0_CTRL2_PACING_START_MASK 0x00000010 -#define BCHP_XPT_PB0_CTRL2_PACING_START_SHIFT 4 - -/* XPT_PB0 :: CTRL2 :: PACING_EN [03:03] */ -#define BCHP_XPT_PB0_CTRL2_PACING_EN_MASK 0x00000008 -#define BCHP_XPT_PB0_CTRL2_PACING_EN_SHIFT 3 - -/* XPT_PB0 :: CTRL2 :: PACING_OFFSET_ADJ_DIS [02:02] */ -#define BCHP_XPT_PB0_CTRL2_PACING_OFFSET_ADJ_DIS_MASK 0x00000004 -#define BCHP_XPT_PB0_CTRL2_PACING_OFFSET_ADJ_DIS_SHIFT 2 - -/* XPT_PB0 :: CTRL2 :: PACING_AUTOSTART_EN [01:01] */ -#define BCHP_XPT_PB0_CTRL2_PACING_AUTOSTART_EN_MASK 0x00000002 -#define BCHP_XPT_PB0_CTRL2_PACING_AUTOSTART_EN_SHIFT 1 - -/* XPT_PB0 :: CTRL2 :: PROGRAM_STREAM_EN [00:00] */ -#define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_EN_MASK 0x00000001 -#define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_EN_SHIFT 0 - -/*************************************************************************** - *CTRL3 - Playback Control 3 Register - ***************************************************************************/ -/* XPT_PB0 :: CTRL3 :: DIRECTV_SYNC_OUT_CNT [31:28] */ -#define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_OUT_CNT_MASK 0xf0000000 -#define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_OUT_CNT_SHIFT 28 - -/* XPT_PB0 :: CTRL3 :: DIRECTV_SYNC_IN_CNT [27:24] */ -#define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_IN_CNT_MASK 0x0f000000 -#define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_IN_CNT_SHIFT 24 - -/* XPT_PB0 :: CTRL3 :: SYNC_ID_HI [23:16] */ -#define BCHP_XPT_PB0_CTRL3_SYNC_ID_HI_MASK 0x00ff0000 -#define BCHP_XPT_PB0_CTRL3_SYNC_ID_HI_SHIFT 16 - -/* XPT_PB0 :: CTRL3 :: SYNC_ID_LO [15:08] */ -#define BCHP_XPT_PB0_CTRL3_SYNC_ID_LO_MASK 0x0000ff00 -#define BCHP_XPT_PB0_CTRL3_SYNC_ID_LO_SHIFT 8 - -/* XPT_PB0 :: CTRL3 :: SYNC_LENGTH [07:00] */ -#define BCHP_XPT_PB0_CTRL3_SYNC_LENGTH_MASK 0x000000ff -#define BCHP_XPT_PB0_CTRL3_SYNC_LENGTH_SHIFT 0 - -/*************************************************************************** - *CTRL4 - Playback Control 4 Register - ***************************************************************************/ -/* XPT_PB0 :: CTRL4 :: reserved0 [31:31] */ -#define BCHP_XPT_PB0_CTRL4_reserved0_MASK 0x80000000 -#define BCHP_XPT_PB0_CTRL4_reserved0_SHIFT 31 - -/* XPT_PB0 :: CTRL4 :: TS_USER_BITS_VALID [30:30] */ -#define BCHP_XPT_PB0_CTRL4_TS_USER_BITS_VALID_MASK 0x40000000 -#define BCHP_XPT_PB0_CTRL4_TS_USER_BITS_VALID_SHIFT 30 - -/* XPT_PB0 :: CTRL4 :: PKTZ_PACK_HDR_DROP_MODE [29:29] */ -#define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_DROP_MODE_MASK 0x20000000 -#define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_DROP_MODE_SHIFT 29 - -/* XPT_PB0 :: CTRL4 :: PKTZ_PACK_HDR_INSERT_EN [28:28] */ -#define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_INSERT_EN_MASK 0x10000000 -#define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_INSERT_EN_SHIFT 28 - -/* XPT_PB0 :: CTRL4 :: PKTZ_SUB_ID_EN [27:27] */ -#define BCHP_XPT_PB0_CTRL4_PKTZ_SUB_ID_EN_MASK 0x08000000 -#define BCHP_XPT_PB0_CTRL4_PKTZ_SUB_ID_EN_SHIFT 27 - -/* XPT_PB0 :: CTRL4 :: PKTZ_STREAM_ID_EXT_EN [26:26] */ -#define BCHP_XPT_PB0_CTRL4_PKTZ_STREAM_ID_EXT_EN_MASK 0x04000000 -#define BCHP_XPT_PB0_CTRL4_PKTZ_STREAM_ID_EXT_EN_SHIFT 26 - -/* XPT_PB0 :: CTRL4 :: PKTZ_PT_EN [25:25] */ -#define BCHP_XPT_PB0_CTRL4_PKTZ_PT_EN_MASK 0x02000000 -#define BCHP_XPT_PB0_CTRL4_PKTZ_PT_EN_SHIFT 25 - -/* XPT_PB0 :: CTRL4 :: PKTZ_PUSI_SET_DIS [24:24] */ -#define BCHP_XPT_PB0_CTRL4_PKTZ_PUSI_SET_DIS_MASK 0x01000000 -#define BCHP_XPT_PB0_CTRL4_PKTZ_PUSI_SET_DIS_SHIFT 24 - -/* XPT_PB0 :: CTRL4 :: PKTZ_CONTEXT_EN [23:23] */ -#define BCHP_XPT_PB0_CTRL4_PKTZ_CONTEXT_EN_MASK 0x00800000 -#define BCHP_XPT_PB0_CTRL4_PKTZ_CONTEXT_EN_SHIFT 23 - -/* XPT_PB0 :: CTRL4 :: PACKETIZE_EN [22:22] */ -#define BCHP_XPT_PB0_CTRL4_PACKETIZE_EN_MASK 0x00400000 -#define BCHP_XPT_PB0_CTRL4_PACKETIZE_EN_SHIFT 22 - -/* XPT_PB0 :: CTRL4 :: HW_PAUSE [21:21] */ -#define BCHP_XPT_PB0_CTRL4_HW_PAUSE_MASK 0x00200000 -#define BCHP_XPT_PB0_CTRL4_HW_PAUSE_SHIFT 21 - -/* XPT_PB0 :: CTRL4 :: MEM_ARB_MODE [20:20] */ -#define BCHP_XPT_PB0_CTRL4_MEM_ARB_MODE_MASK 0x00100000 -#define BCHP_XPT_PB0_CTRL4_MEM_ARB_MODE_SHIFT 20 - -/* XPT_PB0 :: CTRL4 :: OUTPUT_PIPE_SEL [19:19] */ -#define BCHP_XPT_PB0_CTRL4_OUTPUT_PIPE_SEL_MASK 0x00080000 -#define BCHP_XPT_PB0_CTRL4_OUTPUT_PIPE_SEL_SHIFT 19 - -/* XPT_PB0 :: CTRL4 :: TIMEBASE_SEL_MSB [18:18] */ -#define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_MSB_MASK 0x00040000 -#define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_MSB_SHIFT 18 - -/* XPT_PB0 :: CTRL4 :: TIMESTAMP_USER_BITS [17:16] */ -#define BCHP_XPT_PB0_CTRL4_TIMESTAMP_USER_BITS_MASK 0x00030000 -#define BCHP_XPT_PB0_CTRL4_TIMESTAMP_USER_BITS_SHIFT 16 - -/* XPT_PB0 :: CTRL4 :: TIMEBASE_SEL [15:14] */ -#define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_MASK 0x0000c000 -#define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_SHIFT 14 - -/* XPT_PB0 :: CTRL4 :: TIMESTAMP_MODE [13:12] */ -#define BCHP_XPT_PB0_CTRL4_TIMESTAMP_MODE_MASK 0x00003000 -#define BCHP_XPT_PB0_CTRL4_TIMESTAMP_MODE_SHIFT 12 - -/* XPT_PB0 :: CTRL4 :: PARSER_FORCE_RESTAMP [11:11] */ -#define BCHP_XPT_PB0_CTRL4_PARSER_FORCE_RESTAMP_MASK 0x00000800 -#define BCHP_XPT_PB0_CTRL4_PARSER_FORCE_RESTAMP_SHIFT 11 - -/* XPT_PB0 :: CTRL4 :: reserved_for_eco1 [10:10] */ -#define BCHP_XPT_PB0_CTRL4_reserved_for_eco1_MASK 0x00000400 -#define BCHP_XPT_PB0_CTRL4_reserved_for_eco1_SHIFT 10 - -/* XPT_PB0 :: CTRL4 :: reserved2 [09:00] */ -#define BCHP_XPT_PB0_CTRL4_reserved2_MASK 0x000003ff -#define BCHP_XPT_PB0_CTRL4_reserved2_SHIFT 0 - -/*************************************************************************** - *FIRST_DESC_ADDR - Playback First Descriptor Address Register - ***************************************************************************/ -/* XPT_PB0 :: FIRST_DESC_ADDR :: FIRST_DESC_ADDR [31:04] */ -#define BCHP_XPT_PB0_FIRST_DESC_ADDR_FIRST_DESC_ADDR_MASK 0xfffffff0 -#define BCHP_XPT_PB0_FIRST_DESC_ADDR_FIRST_DESC_ADDR_SHIFT 4 - -/* XPT_PB0 :: FIRST_DESC_ADDR :: reserved0 [03:00] */ -#define BCHP_XPT_PB0_FIRST_DESC_ADDR_reserved0_MASK 0x0000000f -#define BCHP_XPT_PB0_FIRST_DESC_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *CURR_DESC_ADDR - Playback Current Descriptor Address Register - ***************************************************************************/ -/* XPT_PB0 :: CURR_DESC_ADDR :: CURR_DESC_ADDR [31:04] */ -#define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_ADDR_MASK 0xfffffff0 -#define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_ADDR_SHIFT 4 - -/* XPT_PB0 :: CURR_DESC_ADDR :: FINISHED_SHADOW [03:03] */ -#define BCHP_XPT_PB0_CURR_DESC_ADDR_FINISHED_SHADOW_MASK 0x00000008 -#define BCHP_XPT_PB0_CURR_DESC_ADDR_FINISHED_SHADOW_SHIFT 3 - -/* XPT_PB0 :: CURR_DESC_ADDR :: BUSY_SHADOW [02:02] */ -#define BCHP_XPT_PB0_CURR_DESC_ADDR_BUSY_SHADOW_MASK 0x00000004 -#define BCHP_XPT_PB0_CURR_DESC_ADDR_BUSY_SHADOW_SHIFT 2 - -/* XPT_PB0 :: CURR_DESC_ADDR :: CURR_DESC_NOT_DONE [01:01] */ -#define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_NOT_DONE_MASK 0x00000002 -#define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_NOT_DONE_SHIFT 1 - -/* XPT_PB0 :: CURR_DESC_ADDR :: reserved0 [00:00] */ -#define BCHP_XPT_PB0_CURR_DESC_ADDR_reserved0_MASK 0x00000001 -#define BCHP_XPT_PB0_CURR_DESC_ADDR_reserved0_SHIFT 0 - -/*************************************************************************** - *CURR_BUFF_ADDR - Playback Current Buffer Address Register - ***************************************************************************/ -/* XPT_PB0 :: CURR_BUFF_ADDR :: CURR_BUFF_ADDR [31:00] */ -#define BCHP_XPT_PB0_CURR_BUFF_ADDR_CURR_BUFF_ADDR_MASK 0xffffffff -#define BCHP_XPT_PB0_CURR_BUFF_ADDR_CURR_BUFF_ADDR_SHIFT 0 - -/*************************************************************************** - *BLOCKOUT - Data Transport Playback Block Out Control - ***************************************************************************/ -/* XPT_PB0 :: BLOCKOUT :: reserved0 [31:25] */ -#define BCHP_XPT_PB0_BLOCKOUT_reserved0_MASK 0xfe000000 -#define BCHP_XPT_PB0_BLOCKOUT_reserved0_SHIFT 25 - -/* XPT_PB0 :: BLOCKOUT :: BO_SPARE_BW_EN [24:24] */ -#define BCHP_XPT_PB0_BLOCKOUT_BO_SPARE_BW_EN_MASK 0x01000000 -#define BCHP_XPT_PB0_BLOCKOUT_BO_SPARE_BW_EN_SHIFT 24 - -/* XPT_PB0 :: BLOCKOUT :: BO_COUNT [23:00] */ -#define BCHP_XPT_PB0_BLOCKOUT_BO_COUNT_MASK 0x00ffffff -#define BCHP_XPT_PB0_BLOCKOUT_BO_COUNT_SHIFT 0 - -/*************************************************************************** - *PKTZ_CONTEXT0 - Data Transport Playback Packetize Mode Context 0 Control - ***************************************************************************/ -/* XPT_PB0 :: PKTZ_CONTEXT0 :: reserved0 [31:29] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_reserved0_MASK 0xe0000000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_reserved0_SHIFT 29 - -/* XPT_PB0 :: PKTZ_CONTEXT0 :: PID [28:16] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_PID_MASK 0x1fff0000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_PID_SHIFT 16 - -/* XPT_PB0 :: PKTZ_CONTEXT0 :: CH_NUM [15:08] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_CH_NUM_MASK 0x0000ff00 -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_CH_NUM_SHIFT 8 - -/* XPT_PB0 :: PKTZ_CONTEXT0 :: PES_STREAM_ID [07:00] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_PES_STREAM_ID_MASK 0x000000ff -#define BCHP_XPT_PB0_PKTZ_CONTEXT0_PES_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *PKTZ_CONTEXT1 - Data Transport Playback Packetize Mode Context 1 Control - ***************************************************************************/ -/* XPT_PB0 :: PKTZ_CONTEXT1 :: reserved0 [31:29] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_reserved0_MASK 0xe0000000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_reserved0_SHIFT 29 - -/* XPT_PB0 :: PKTZ_CONTEXT1 :: PID [28:16] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_PID_MASK 0x1fff0000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_PID_SHIFT 16 - -/* XPT_PB0 :: PKTZ_CONTEXT1 :: CH_NUM [15:08] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_CH_NUM_MASK 0x0000ff00 -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_CH_NUM_SHIFT 8 - -/* XPT_PB0 :: PKTZ_CONTEXT1 :: PES_STREAM_ID [07:00] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_PES_STREAM_ID_MASK 0x000000ff -#define BCHP_XPT_PB0_PKTZ_CONTEXT1_PES_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *PKTZ_CONTEXT2 - Data Transport Playback Packetize Mode Context 2 Control - ***************************************************************************/ -/* XPT_PB0 :: PKTZ_CONTEXT2 :: reserved0 [31:29] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_reserved0_MASK 0xe0000000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_reserved0_SHIFT 29 - -/* XPT_PB0 :: PKTZ_CONTEXT2 :: PID [28:16] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_PID_MASK 0x1fff0000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_PID_SHIFT 16 - -/* XPT_PB0 :: PKTZ_CONTEXT2 :: CH_NUM [15:08] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_CH_NUM_MASK 0x0000ff00 -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_CH_NUM_SHIFT 8 - -/* XPT_PB0 :: PKTZ_CONTEXT2 :: PES_STREAM_ID [07:00] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_PES_STREAM_ID_MASK 0x000000ff -#define BCHP_XPT_PB0_PKTZ_CONTEXT2_PES_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *PKTZ_CONTEXT3 - Data Transport Playback Packetize Mode Context 3 Control - ***************************************************************************/ -/* XPT_PB0 :: PKTZ_CONTEXT3 :: reserved0 [31:29] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_reserved0_MASK 0xe0000000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_reserved0_SHIFT 29 - -/* XPT_PB0 :: PKTZ_CONTEXT3 :: PID [28:16] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_PID_MASK 0x1fff0000 -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_PID_SHIFT 16 - -/* XPT_PB0 :: PKTZ_CONTEXT3 :: CH_NUM [15:08] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_CH_NUM_MASK 0x0000ff00 -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_CH_NUM_SHIFT 8 - -/* XPT_PB0 :: PKTZ_CONTEXT3 :: PES_STREAM_ID [07:00] */ -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_PES_STREAM_ID_MASK 0x000000ff -#define BCHP_XPT_PB0_PKTZ_CONTEXT3_PES_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *TS_ERR_BOUND - Data Transport Playback Timestamp Error Bound Register - ***************************************************************************/ -/* XPT_PB0 :: TS_ERR_BOUND :: reserved0 [31:19] */ -#define BCHP_XPT_PB0_TS_ERR_BOUND_reserved0_MASK 0xfff80000 -#define BCHP_XPT_PB0_TS_ERR_BOUND_reserved0_SHIFT 19 - -/* XPT_PB0 :: TS_ERR_BOUND :: TS_ERR_BOUND [18:00] */ -#define BCHP_XPT_PB0_TS_ERR_BOUND_TS_ERR_BOUND_MASK 0x0007ffff -#define BCHP_XPT_PB0_TS_ERR_BOUND_TS_ERR_BOUND_SHIFT 0 - -/*************************************************************************** - *PARSER_CTRL1 - Data Transport Playback Parser Control Register - ***************************************************************************/ -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_TIMEBASE_SEL [31:29] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMEBASE_SEL_MASK 0xe0000000 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMEBASE_SEL_SHIFT 29 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27 - -/* XPT_PB0 :: PARSER_CTRL1 :: reserved0 [26:21] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_reserved0_MASK 0x07e00000 -#define BCHP_XPT_PB0_PARSER_CTRL1_reserved0_SHIFT 21 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ACCEPT_ADAPT_00 [20:20] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_ADAPT_00_MASK 0x00100000 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_ADAPT_00_SHIFT 20 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_PKT_LENGTH [19:12] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PKT_LENGTH_SHIFT 12 - -/* XPT_PB0 :: PARSER_CTRL1 :: reserved1 [11:08] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_reserved1_MASK 0x00000f00 -#define BCHP_XPT_PB0_PARSER_CTRL1_reserved1_SHIFT 8 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_PACKET_TYPE [07:05] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PACKET_TYPE_MASK 0x000000e0 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PACKET_TYPE_SHIFT 5 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ACCEPT_NULL_PKT [04:04] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_NULL_PKT_MASK 0x00000010 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_NULL_PKT_SHIFT 4 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_CONT_COUNT_IGNORE [03:03] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_CONT_COUNT_IGNORE_MASK 0x00000008 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_CONT_COUNT_IGNORE_SHIFT 3 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [02:02] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00000004 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 2 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ALL_PASS_CTRL [01:01] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ALL_PASS_CTRL_MASK 0x00000002 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ALL_PASS_CTRL_SHIFT 1 - -/* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ENABLE [00:00] */ -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ENABLE_SHIFT 0 - -/*************************************************************************** - *PARSER_CTRL2 - Data Transport Playback Parser Control Register 2 - ***************************************************************************/ -/* XPT_PB0 :: PARSER_CTRL2 :: reserved0 [31:08] */ -#define BCHP_XPT_PB0_PARSER_CTRL2_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PB0_PARSER_CTRL2_reserved0_SHIFT 8 - -/* XPT_PB0 :: PARSER_CTRL2 :: RAVE_CX_MODE [07:06] */ -#define BCHP_XPT_PB0_PARSER_CTRL2_RAVE_CX_MODE_MASK 0x000000c0 -#define BCHP_XPT_PB0_PARSER_CTRL2_RAVE_CX_MODE_SHIFT 6 - -/* XPT_PB0 :: PARSER_CTRL2 :: PARSER_SEC_CC_IGNORE [05:05] */ -#define BCHP_XPT_PB0_PARSER_CTRL2_PARSER_SEC_CC_IGNORE_MASK 0x00000020 -#define BCHP_XPT_PB0_PARSER_CTRL2_PARSER_SEC_CC_IGNORE_SHIFT 5 - -/* XPT_PB0 :: PARSER_CTRL2 :: reserved1 [04:00] */ -#define BCHP_XPT_PB0_PARSER_CTRL2_reserved1_MASK 0x0000001f -#define BCHP_XPT_PB0_PARSER_CTRL2_reserved1_SHIFT 0 - -/*************************************************************************** - *PARSER_TIMESTAMP - Data Transport Playback Parser Local Timestamp - ***************************************************************************/ -/* XPT_PB0 :: PARSER_TIMESTAMP :: TIMESTAMP [31:00] */ -#define BCHP_XPT_PB0_PARSER_TIMESTAMP_TIMESTAMP_MASK 0xffffffff -#define BCHP_XPT_PB0_PARSER_TIMESTAMP_TIMESTAMP_SHIFT 0 - -/*************************************************************************** - *INTR - Playback Processing Error and Status Interrupt Register - ***************************************************************************/ -/* XPT_PB0 :: INTR :: reserved0 [31:09] */ -#define BCHP_XPT_PB0_INTR_reserved0_MASK 0xfffffe00 -#define BCHP_XPT_PB0_INTR_reserved0_SHIFT 9 - -/* XPT_PB0 :: INTR :: PB_COPYRIGHT_CHANGE [08:08] */ -#define BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_MASK 0x00000100 -#define BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT 8 - -/* XPT_PB0 :: INTR :: PARSER_TRANSPORT_ERROR [07:07] */ -#define BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_MASK 0x00000080 -#define BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT 7 - -/* XPT_PB0 :: INTR :: PARSER_LENGTH_ERROR [06:06] */ -#define BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_MASK 0x00000040 -#define BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT 6 - -/* XPT_PB0 :: INTR :: PARSER_SEC_CC_ERROR [05:05] */ -#define BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_MASK 0x00000020 -#define BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT 5 - -/* XPT_PB0 :: INTR :: PARSER_CONTINUITY_ERROR [04:04] */ -#define BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_MASK 0x00000010 -#define BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT 4 - -/* XPT_PB0 :: INTR :: TS_RANGE_ERROR [03:03] */ -#define BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_MASK 0x00000008 -#define BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT 3 - -/* XPT_PB0 :: INTR :: TS_PARITY_ERROR [02:02] */ -#define BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_MASK 0x00000004 -#define BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT 2 - -/* XPT_PB0 :: INTR :: SE_OUT_OF_SYNC_INT [01:01] */ -#define BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_MASK 0x00000002 -#define BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT 1 - -/* XPT_PB0 :: INTR :: DONE_INT [00:00] */ -#define BCHP_XPT_PB0_INTR_DONE_INT_MASK 0x00000001 -#define BCHP_XPT_PB0_INTR_DONE_INT_SHIFT 0 - -/*************************************************************************** - *INTR_EN - Playback Processing Error and Status Interrupt Enable Register - ***************************************************************************/ -/* XPT_PB0 :: INTR_EN :: reserved0 [31:09] */ -#define BCHP_XPT_PB0_INTR_EN_reserved0_MASK 0xfffffe00 -#define BCHP_XPT_PB0_INTR_EN_reserved0_SHIFT 9 - -/* XPT_PB0 :: INTR_EN :: INTR_EN [08:00] */ -#define BCHP_XPT_PB0_INTR_EN_INTR_EN_MASK 0x000001ff -#define BCHP_XPT_PB0_INTR_EN_INTR_EN_SHIFT 0 - -/*************************************************************************** - *INTR_TAGS - Playback Interrupt Tag Register - ***************************************************************************/ -/* XPT_PB0 :: INTR_TAGS :: reserved0 [31:04] */ -#define BCHP_XPT_PB0_INTR_TAGS_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PB0_INTR_TAGS_reserved0_SHIFT 4 - -/* XPT_PB0 :: INTR_TAGS :: PB_DESC_TAG_ID [03:00] */ -#define BCHP_XPT_PB0_INTR_TAGS_PB_DESC_TAG_ID_MASK 0x0000000f -#define BCHP_XPT_PB0_INTR_TAGS_PB_DESC_TAG_ID_SHIFT 0 - -#endif /* #ifndef BCHP_XPT_PB0_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb1.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb1.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb1.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb1.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,77 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_pb1.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:24p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:51 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb1.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:24p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_PB1_H__ -#define BCHP_XPT_PB1_H__ - -/*************************************************************************** - *XPT_PB1 - Playback 1 Control Registers - ***************************************************************************/ -#define BCHP_XPT_PB1_CTRL1 0x0020b080 /* Playback Control 1 Register */ -#define BCHP_XPT_PB1_CTRL2 0x0020b084 /* Playback Control 2 Register */ -#define BCHP_XPT_PB1_CTRL3 0x0020b088 /* Playback Control 3 Register */ -#define BCHP_XPT_PB1_CTRL4 0x0020b08c /* Playback Control 4 Register */ -#define BCHP_XPT_PB1_FIRST_DESC_ADDR 0x0020b090 /* Playback First Descriptor Address Register */ -#define BCHP_XPT_PB1_CURR_DESC_ADDR 0x0020b094 /* Playback Current Descriptor Address Register */ -#define BCHP_XPT_PB1_CURR_BUFF_ADDR 0x0020b098 /* Playback Current Buffer Address Register */ -#define BCHP_XPT_PB1_BLOCKOUT 0x0020b09c /* Data Transport Playback Block Out Control */ -#define BCHP_XPT_PB1_PKTZ_CONTEXT0 0x0020b0a0 /* Data Transport Playback Packetize Mode Context 0 Control */ -#define BCHP_XPT_PB1_PKTZ_CONTEXT1 0x0020b0a4 /* Data Transport Playback Packetize Mode Context 1 Control */ -#define BCHP_XPT_PB1_PKTZ_CONTEXT2 0x0020b0a8 /* Data Transport Playback Packetize Mode Context 2 Control */ -#define BCHP_XPT_PB1_PKTZ_CONTEXT3 0x0020b0ac /* Data Transport Playback Packetize Mode Context 3 Control */ -#define BCHP_XPT_PB1_TS_ERR_BOUND 0x0020b0b0 /* Data Transport Playback Timestamp Error Bound Register */ -#define BCHP_XPT_PB1_PARSER_CTRL1 0x0020b0b4 /* Data Transport Playback Parser Control Register */ -#define BCHP_XPT_PB1_PARSER_CTRL2 0x0020b0b8 /* Data Transport Playback Parser Control Register 2 */ -#define BCHP_XPT_PB1_PARSER_TIMESTAMP 0x0020b0bc /* Data Transport Playback Parser Local Timestamp */ -#define BCHP_XPT_PB1_INTR 0x0020b0c0 /* Playback Processing Error and Status Interrupt Register */ -#define BCHP_XPT_PB1_INTR_EN 0x0020b0c4 /* Playback Processing Error and Status Interrupt Enable Register */ -#define BCHP_XPT_PB1_INTR_TAGS 0x0020b0c8 /* Playback Interrupt Tag Register */ - -#endif /* #ifndef BCHP_XPT_PB1_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb2.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb2.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb2.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb2.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,77 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_pb2.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:24p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:32 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb2.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:24p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_PB2_H__ -#define BCHP_XPT_PB2_H__ - -/*************************************************************************** - *XPT_PB2 - Playback 2 Control Registers - ***************************************************************************/ -#define BCHP_XPT_PB2_CTRL1 0x0020b100 /* Playback Control 1 Register */ -#define BCHP_XPT_PB2_CTRL2 0x0020b104 /* Playback Control 2 Register */ -#define BCHP_XPT_PB2_CTRL3 0x0020b108 /* Playback Control 3 Register */ -#define BCHP_XPT_PB2_CTRL4 0x0020b10c /* Playback Control 4 Register */ -#define BCHP_XPT_PB2_FIRST_DESC_ADDR 0x0020b110 /* Playback First Descriptor Address Register */ -#define BCHP_XPT_PB2_CURR_DESC_ADDR 0x0020b114 /* Playback Current Descriptor Address Register */ -#define BCHP_XPT_PB2_CURR_BUFF_ADDR 0x0020b118 /* Playback Current Buffer Address Register */ -#define BCHP_XPT_PB2_BLOCKOUT 0x0020b11c /* Data Transport Playback Block Out Control */ -#define BCHP_XPT_PB2_PKTZ_CONTEXT0 0x0020b120 /* Data Transport Playback Packetize Mode Context 0 Control */ -#define BCHP_XPT_PB2_PKTZ_CONTEXT1 0x0020b124 /* Data Transport Playback Packetize Mode Context 1 Control */ -#define BCHP_XPT_PB2_PKTZ_CONTEXT2 0x0020b128 /* Data Transport Playback Packetize Mode Context 2 Control */ -#define BCHP_XPT_PB2_PKTZ_CONTEXT3 0x0020b12c /* Data Transport Playback Packetize Mode Context 3 Control */ -#define BCHP_XPT_PB2_TS_ERR_BOUND 0x0020b130 /* Data Transport Playback Timestamp Error Bound Register */ -#define BCHP_XPT_PB2_PARSER_CTRL1 0x0020b134 /* Data Transport Playback Parser Control Register */ -#define BCHP_XPT_PB2_PARSER_CTRL2 0x0020b138 /* Data Transport Playback Parser Control Register 2 */ -#define BCHP_XPT_PB2_PARSER_TIMESTAMP 0x0020b13c /* Data Transport Playback Parser Local Timestamp */ -#define BCHP_XPT_PB2_INTR 0x0020b140 /* Playback Processing Error and Status Interrupt Register */ -#define BCHP_XPT_PB2_INTR_EN 0x0020b144 /* Playback Processing Error and Status Interrupt Enable Register */ -#define BCHP_XPT_PB2_INTR_TAGS 0x0020b148 /* Playback Interrupt Tag Register */ - -#endif /* #ifndef BCHP_XPT_PB2_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pcroffset.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pcroffset.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pcroffset.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pcroffset.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,7324 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_pcroffset.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:25p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:05 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pcroffset.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:25p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_PCROFFSET_H__ -#define BCHP_XPT_PCROFFSET_H__ - -/*************************************************************************** - *XPT_PCROFFSET - XPT PCROFFSET Control Registers - ***************************************************************************/ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS 0x00227000 /* PCR INTERRUPT STATUS register for Contexts 3 to 0 */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_ENABLE 0x00227004 /* PCR INTERRUPT ENABLE register for Contexts 3 to 0 */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS 0x00227008 /* PCR INTERRUPT STATUS register for Contexts 7 to 4 */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_ENABLE 0x0022700c /* PCR INTERRUPT ENABLE register for Contexts 7 to 4 */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS 0x00227010 /* PCR INTERRUPT STATUS register for Contexts 11 to 8 */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_ENABLE 0x00227014 /* PCR INTERRUPT ENABLE register for Contexts 11 to 8 */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS 0x00227018 /* PCR INTERRUPT STATUS register for Contexts 15 to 12 */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_ENABLE 0x0022701c /* PCR INTERRUPT ENABLE register for Contexts 15 to 12 */ -#define BCHP_XPT_PCROFFSET_STC0_CTRL 0x00227020 /* STC0 Counter Control */ -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL 0x00227024 /* STC0 Timebase Select */ -#define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL 0x00227028 /* STC0 Counter Increment and Prescale */ -#define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE 0x0022702c /* STC0 Capture PCR once */ -#define BCHP_XPT_PCROFFSET_STC0 0x00227030 /* STC0 Counter */ -#define BCHP_XPT_PCROFFSET_STC1_CTRL 0x00227034 /* STC1 Counter Control */ -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL 0x00227038 /* STC1 Timebase Select */ -#define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL 0x0022703c /* STC1 Counter Increment and Prescale */ -#define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE 0x00227040 /* STC1 Capture PCR once */ -#define BCHP_XPT_PCROFFSET_STC1 0x00227044 /* STC1 Counter */ -#define BCHP_XPT_PCROFFSET_STC2_CTRL 0x00227048 /* STC2 Counter Control */ -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL 0x0022704c /* STC2 Timebase Select */ -#define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL 0x00227050 /* STC2 Counter Increment and Prescale */ -#define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE 0x00227054 /* STC2 Capture PCR once */ -#define BCHP_XPT_PCROFFSET_STC2 0x00227058 /* STC2 Counter */ -#define BCHP_XPT_PCROFFSET_STC3_CTRL 0x0022705c /* STC3 Counter Control */ -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL 0x00227060 /* STC3 Timebase Select */ -#define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL 0x00227064 /* STC3 Counter Increment and Prescale */ -#define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE 0x00227068 /* STC3 Capture PCR once */ -#define BCHP_XPT_PCROFFSET_STC3 0x0022706c /* STC3 Counter */ -#define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE 0x00227070 /* TM Control */ -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL 0x00227074 /* STC Broadcast bus select */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL 0x00227800 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM 0x00227804 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE 0x00227808 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS 0x0022780c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR 0x00227810 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR 0x00227814 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1 0x00227818 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3 0x0022781c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5 0x00227820 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7 0x00227824 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE 0x00227828 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET 0x0022782c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID 0x00227830 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_MAX_ERROR 0x00227834 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_THRESHOLD 0x00227838 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_FIXED_OFFSET 0x0022783c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT 0x00227840 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_SEND_PCR_BASE 0x00227844 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_LAST_PCR_BASE 0x00227848 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_0 0x0022784c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_1 0x00227850 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_2 0x00227854 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_3 0x00227858 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_0 0x0022786c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_1 0x00227870 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_2 0x00227874 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_3 0x00227878 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_4 0x0022787c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL 0x00227880 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM 0x00227884 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE 0x00227888 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS 0x0022788c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR 0x00227890 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR 0x00227894 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1 0x00227898 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3 0x0022789c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5 0x002278a0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7 0x002278a4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE 0x002278a8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET 0x002278ac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID 0x002278b0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_MAX_ERROR 0x002278b4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_THRESHOLD 0x002278b8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_FIXED_OFFSET 0x002278bc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT 0x002278c0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_SEND_PCR_BASE 0x002278c4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_LAST_PCR_BASE 0x002278c8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_0 0x002278cc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_1 0x002278d0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_2 0x002278d4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_3 0x002278d8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_0 0x002278ec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_1 0x002278f0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_2 0x002278f4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_3 0x002278f8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_4 0x002278fc /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL 0x00227900 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM 0x00227904 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE 0x00227908 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS 0x0022790c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR 0x00227910 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR 0x00227914 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1 0x00227918 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3 0x0022791c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5 0x00227920 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7 0x00227924 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE 0x00227928 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET 0x0022792c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID 0x00227930 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_MAX_ERROR 0x00227934 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_THRESHOLD 0x00227938 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_FIXED_OFFSET 0x0022793c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT 0x00227940 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_SEND_PCR_BASE 0x00227944 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_LAST_PCR_BASE 0x00227948 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_0 0x0022794c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_1 0x00227950 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_2 0x00227954 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_3 0x00227958 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_0 0x0022796c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_1 0x00227970 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_2 0x00227974 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_3 0x00227978 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_4 0x0022797c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL 0x00227980 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM 0x00227984 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE 0x00227988 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS 0x0022798c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR 0x00227990 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR 0x00227994 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1 0x00227998 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3 0x0022799c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5 0x002279a0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7 0x002279a4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE 0x002279a8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET 0x002279ac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID 0x002279b0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_MAX_ERROR 0x002279b4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_THRESHOLD 0x002279b8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_FIXED_OFFSET 0x002279bc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT 0x002279c0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_SEND_PCR_BASE 0x002279c4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_LAST_PCR_BASE 0x002279c8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_0 0x002279cc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_1 0x002279d0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_2 0x002279d4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_3 0x002279d8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_0 0x002279ec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_1 0x002279f0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_2 0x002279f4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_3 0x002279f8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_4 0x002279fc /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL 0x00227a00 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM 0x00227a04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE 0x00227a08 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS 0x00227a0c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR 0x00227a10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR 0x00227a14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1 0x00227a18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3 0x00227a1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5 0x00227a20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7 0x00227a24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE 0x00227a28 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET 0x00227a2c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID 0x00227a30 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_MAX_ERROR 0x00227a34 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_THRESHOLD 0x00227a38 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_FIXED_OFFSET 0x00227a3c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT 0x00227a40 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_SEND_PCR_BASE 0x00227a44 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_LAST_PCR_BASE 0x00227a48 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_0 0x00227a4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_1 0x00227a50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_2 0x00227a54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_3 0x00227a58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_0 0x00227a6c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_1 0x00227a70 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_2 0x00227a74 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_3 0x00227a78 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_4 0x00227a7c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL 0x00227a80 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM 0x00227a84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE 0x00227a88 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS 0x00227a8c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR 0x00227a90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR 0x00227a94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1 0x00227a98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3 0x00227a9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5 0x00227aa0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7 0x00227aa4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE 0x00227aa8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET 0x00227aac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID 0x00227ab0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_MAX_ERROR 0x00227ab4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_THRESHOLD 0x00227ab8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_FIXED_OFFSET 0x00227abc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT 0x00227ac0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_SEND_PCR_BASE 0x00227ac4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_LAST_PCR_BASE 0x00227ac8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_0 0x00227acc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_1 0x00227ad0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_2 0x00227ad4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_3 0x00227ad8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_0 0x00227aec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_1 0x00227af0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_2 0x00227af4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_3 0x00227af8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_4 0x00227afc /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL 0x00227b00 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM 0x00227b04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE 0x00227b08 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS 0x00227b0c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR 0x00227b10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR 0x00227b14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1 0x00227b18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3 0x00227b1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5 0x00227b20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7 0x00227b24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE 0x00227b28 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET 0x00227b2c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID 0x00227b30 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_MAX_ERROR 0x00227b34 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_THRESHOLD 0x00227b38 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_FIXED_OFFSET 0x00227b3c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT 0x00227b40 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_SEND_PCR_BASE 0x00227b44 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_LAST_PCR_BASE 0x00227b48 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_0 0x00227b4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_1 0x00227b50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_2 0x00227b54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_3 0x00227b58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_0 0x00227b6c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_1 0x00227b70 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_2 0x00227b74 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_3 0x00227b78 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_4 0x00227b7c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL 0x00227b80 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM 0x00227b84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE 0x00227b88 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS 0x00227b8c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR 0x00227b90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR 0x00227b94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1 0x00227b98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3 0x00227b9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5 0x00227ba0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7 0x00227ba4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE 0x00227ba8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET 0x00227bac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID 0x00227bb0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_MAX_ERROR 0x00227bb4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_THRESHOLD 0x00227bb8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_FIXED_OFFSET 0x00227bbc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT 0x00227bc0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_SEND_PCR_BASE 0x00227bc4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_LAST_PCR_BASE 0x00227bc8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_0 0x00227bcc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_1 0x00227bd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_2 0x00227bd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_3 0x00227bd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_0 0x00227bec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_1 0x00227bf0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_2 0x00227bf4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_3 0x00227bf8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_4 0x00227bfc /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL 0x00227c00 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM 0x00227c04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE 0x00227c08 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS 0x00227c0c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR 0x00227c10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR 0x00227c14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1 0x00227c18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3 0x00227c1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5 0x00227c20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7 0x00227c24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE 0x00227c28 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET 0x00227c2c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID 0x00227c30 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_MAX_ERROR 0x00227c34 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_THRESHOLD 0x00227c38 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_FIXED_OFFSET 0x00227c3c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT 0x00227c40 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_SEND_PCR_BASE 0x00227c44 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_LAST_PCR_BASE 0x00227c48 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_0 0x00227c4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_1 0x00227c50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_2 0x00227c54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_3 0x00227c58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_0 0x00227c6c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_1 0x00227c70 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_2 0x00227c74 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_3 0x00227c78 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_4 0x00227c7c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL 0x00227c80 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM 0x00227c84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE 0x00227c88 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS 0x00227c8c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR 0x00227c90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR 0x00227c94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1 0x00227c98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3 0x00227c9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5 0x00227ca0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7 0x00227ca4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE 0x00227ca8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET 0x00227cac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID 0x00227cb0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_MAX_ERROR 0x00227cb4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_THRESHOLD 0x00227cb8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_FIXED_OFFSET 0x00227cbc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT 0x00227cc0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_SEND_PCR_BASE 0x00227cc4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_LAST_PCR_BASE 0x00227cc8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_0 0x00227ccc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_1 0x00227cd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_2 0x00227cd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_3 0x00227cd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_0 0x00227cec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_1 0x00227cf0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_2 0x00227cf4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_3 0x00227cf8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_4 0x00227cfc /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL 0x00227d00 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM 0x00227d04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE 0x00227d08 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS 0x00227d0c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR 0x00227d10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR 0x00227d14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1 0x00227d18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3 0x00227d1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5 0x00227d20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7 0x00227d24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE 0x00227d28 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET 0x00227d2c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID 0x00227d30 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_MAX_ERROR 0x00227d34 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_THRESHOLD 0x00227d38 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_FIXED_OFFSET 0x00227d3c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT 0x00227d40 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_SEND_PCR_BASE 0x00227d44 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_LAST_PCR_BASE 0x00227d48 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_0 0x00227d4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_1 0x00227d50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_2 0x00227d54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_3 0x00227d58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_0 0x00227d6c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_1 0x00227d70 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_2 0x00227d74 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_3 0x00227d78 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_4 0x00227d7c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL 0x00227d80 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM 0x00227d84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE 0x00227d88 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS 0x00227d8c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR 0x00227d90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR 0x00227d94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1 0x00227d98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3 0x00227d9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5 0x00227da0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7 0x00227da4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE 0x00227da8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET 0x00227dac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID 0x00227db0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_MAX_ERROR 0x00227db4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_THRESHOLD 0x00227db8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_FIXED_OFFSET 0x00227dbc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT 0x00227dc0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_SEND_PCR_BASE 0x00227dc4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_LAST_PCR_BASE 0x00227dc8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_0 0x00227dcc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_1 0x00227dd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_2 0x00227dd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_3 0x00227dd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_0 0x00227dec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_1 0x00227df0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_2 0x00227df4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_3 0x00227df8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_4 0x00227dfc /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL 0x00227e00 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM 0x00227e04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE 0x00227e08 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS 0x00227e0c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR 0x00227e10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR 0x00227e14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1 0x00227e18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3 0x00227e1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5 0x00227e20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7 0x00227e24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE 0x00227e28 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET 0x00227e2c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID 0x00227e30 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_MAX_ERROR 0x00227e34 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_THRESHOLD 0x00227e38 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_FIXED_OFFSET 0x00227e3c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT 0x00227e40 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_SEND_PCR_BASE 0x00227e44 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_LAST_PCR_BASE 0x00227e48 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_0 0x00227e4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_1 0x00227e50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_2 0x00227e54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_3 0x00227e58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_0 0x00227e6c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_1 0x00227e70 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_2 0x00227e74 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_3 0x00227e78 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_4 0x00227e7c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL 0x00227e80 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM 0x00227e84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE 0x00227e88 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS 0x00227e8c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR 0x00227e90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR 0x00227e94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1 0x00227e98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3 0x00227e9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5 0x00227ea0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7 0x00227ea4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE 0x00227ea8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET 0x00227eac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID 0x00227eb0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_MAX_ERROR 0x00227eb4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_THRESHOLD 0x00227eb8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_FIXED_OFFSET 0x00227ebc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT 0x00227ec0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_SEND_PCR_BASE 0x00227ec4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_LAST_PCR_BASE 0x00227ec8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_0 0x00227ecc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_1 0x00227ed0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_2 0x00227ed4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_3 0x00227ed8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_0 0x00227eec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_1 0x00227ef0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_2 0x00227ef4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_3 0x00227ef8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_4 0x00227efc /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL 0x00227f00 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM 0x00227f04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE 0x00227f08 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS 0x00227f0c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR 0x00227f10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR 0x00227f14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1 0x00227f18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3 0x00227f1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5 0x00227f20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7 0x00227f24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE 0x00227f28 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET 0x00227f2c /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID 0x00227f30 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_MAX_ERROR 0x00227f34 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_THRESHOLD 0x00227f38 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_FIXED_OFFSET 0x00227f3c /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT 0x00227f40 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_SEND_PCR_BASE 0x00227f44 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_LAST_PCR_BASE 0x00227f48 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_0 0x00227f4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_1 0x00227f50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_2 0x00227f54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_3 0x00227f58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_0 0x00227f6c /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_1 0x00227f70 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_2 0x00227f74 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_3 0x00227f78 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_4 0x00227f7c /* Config Word 31 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL 0x00227f80 /* Config word 0 - PCROFFSET Main Control */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM 0x00227f84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE 0x00227f88 /* Config Word 2 - SPLICE STATE Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS 0x00227f8c /* Config Word 3 - SPLICE STATUS Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR 0x00227f90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR 0x00227f94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1 0x00227f98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3 0x00227f9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5 0x00227fa0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7 0x00227fa4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE 0x00227fa8 /* Config Word 10 - OFFSET STATE register */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET 0x00227fac /* Config Word 11 - OFFSET read/write */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID 0x00227fb0 /* Config Word 12 - OFFSET Valid */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_MAX_ERROR 0x00227fb4 /* Config Word 13 - OFFSET MAX Error */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_THRESHOLD 0x00227fb8 /* Config Word 14 - OFFSET Threshold */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_FIXED_OFFSET 0x00227fbc /* Config Word 15 - Fixed OFFSET */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT 0x00227fc0 /* Config Word 16 - PCR COUNT register */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_SEND_PCR_BASE 0x00227fc4 /* Config Word 17 - Send PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_LAST_PCR_BASE 0x00227fc8 /* Config Word 18 - Last PCR Base Register */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_0 0x00227fcc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_1 0x00227fd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_2 0x00227fd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_3 0x00227fd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_0 0x00227fec /* Config Word 27 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_1 0x00227ff0 /* Config Word 28 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_2 0x00227ff4 /* Config Word 29 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_3 0x00227ff8 /* Config Word 30 - RESERVED */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_4 0x00227ffc /* Config Word 31 - RESERVED */ - -/*************************************************************************** - *INTERRUPT0_STATUS - PCR INTERRUPT STATUS register for Contexts 3 to 0 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco0_SHIFT 31 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_STC_CAPTURED [30:30] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_STC_CAPTURED_MASK 0x40000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_STC_CAPTURED_SHIFT 30 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_SPLICE_ERROR [29:29] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_ERROR_MASK 0x20000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_ERROR_SHIFT 29 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_SPLICE_DONE [28:28] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_DONE_MASK 0x10000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_DONE_SHIFT 28 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_TWO_ERROR [27:27] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_TWO_ERROR_MASK 0x08000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_TWO_ERROR_SHIFT 27 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_ONE_ERROR [26:26] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_ONE_ERROR_MASK 0x04000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_ONE_ERROR_SHIFT 26 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_DISCONT [25:25] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_DISCONT_MASK 0x02000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_DISCONT_SHIFT 25 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_NEW [24:24] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_NEW_MASK 0x01000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_NEW_SHIFT 24 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco1 [23:23] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco1_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco1_SHIFT 23 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_STC_CAPTURED [22:22] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_STC_CAPTURED_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_STC_CAPTURED_SHIFT 22 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_SPLICE_ERROR [21:21] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_ERROR_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_ERROR_SHIFT 21 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_SPLICE_DONE [20:20] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_DONE_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_DONE_SHIFT 20 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_TWO_ERROR [19:19] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_TWO_ERROR_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_TWO_ERROR_SHIFT 19 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_ONE_ERROR [18:18] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_ONE_ERROR_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_ONE_ERROR_SHIFT 18 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_DISCONT [17:17] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_DISCONT_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_DISCONT_SHIFT 17 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_NEW [16:16] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_NEW_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_NEW_SHIFT 16 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco2 [15:15] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco2_MASK 0x00008000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco2_SHIFT 15 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_STC_CAPTURED [14:14] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_STC_CAPTURED_MASK 0x00004000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_STC_CAPTURED_SHIFT 14 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_SPLICE_ERROR [13:13] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_ERROR_MASK 0x00002000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_ERROR_SHIFT 13 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_SPLICE_DONE [12:12] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_DONE_MASK 0x00001000 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_DONE_SHIFT 12 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_TWO_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_TWO_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_TWO_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_ONE_ERROR [10:10] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_ONE_ERROR_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_ONE_ERROR_SHIFT 10 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_DISCONT [09:09] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_DISCONT_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_DISCONT_SHIFT 9 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_NEW [08:08] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_NEW_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_NEW_SHIFT 8 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco3 [07:07] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco3_MASK 0x00000080 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco3_SHIFT 7 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_STC_CAPTURED [06:06] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_STC_CAPTURED_MASK 0x00000040 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_STC_CAPTURED_SHIFT 6 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_SPLICE_ERROR [05:05] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_ERROR_MASK 0x00000020 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_ERROR_SHIFT 5 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_SPLICE_DONE [04:04] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_DONE_MASK 0x00000010 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_DONE_SHIFT 4 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_TWO_ERROR [03:03] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_TWO_ERROR_MASK 0x00000008 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_TWO_ERROR_SHIFT 3 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_ONE_ERROR [02:02] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_ONE_ERROR_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_ONE_ERROR_SHIFT 2 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_DISCONT [01:01] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_DISCONT_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_DISCONT_SHIFT 1 - -/* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_NEW [00:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_NEW_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_NEW_SHIFT 0 - -/*************************************************************************** - *INTERRUPT0_ENABLE - PCR INTERRUPT ENABLE register for Contexts 3 to 0 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT0_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT0_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_INTERRUPT0_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 - -/*************************************************************************** - *INTERRUPT1_STATUS - PCR INTERRUPT STATUS register for Contexts 7 to 4 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco0_SHIFT 31 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_STC_CAPTURED [30:30] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_STC_CAPTURED_MASK 0x40000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_STC_CAPTURED_SHIFT 30 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_SPLICE_ERROR [29:29] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_ERROR_MASK 0x20000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_ERROR_SHIFT 29 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_SPLICE_DONE [28:28] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_DONE_MASK 0x10000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_DONE_SHIFT 28 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_TWO_ERROR [27:27] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_TWO_ERROR_MASK 0x08000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_TWO_ERROR_SHIFT 27 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_ONE_ERROR [26:26] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_ONE_ERROR_MASK 0x04000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_ONE_ERROR_SHIFT 26 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_DISCONT [25:25] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_DISCONT_MASK 0x02000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_DISCONT_SHIFT 25 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_NEW [24:24] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_NEW_MASK 0x01000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_NEW_SHIFT 24 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco1 [23:23] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco1_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco1_SHIFT 23 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_STC_CAPTURED [22:22] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_STC_CAPTURED_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_STC_CAPTURED_SHIFT 22 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_SPLICE_ERROR [21:21] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_ERROR_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_ERROR_SHIFT 21 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_SPLICE_DONE [20:20] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_DONE_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_DONE_SHIFT 20 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_TWO_ERROR [19:19] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_TWO_ERROR_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_TWO_ERROR_SHIFT 19 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_ONE_ERROR [18:18] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_ONE_ERROR_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_ONE_ERROR_SHIFT 18 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_DISCONT [17:17] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_DISCONT_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_DISCONT_SHIFT 17 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_NEW [16:16] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_NEW_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_NEW_SHIFT 16 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco2 [15:15] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco2_MASK 0x00008000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco2_SHIFT 15 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_STC_CAPTURED [14:14] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_STC_CAPTURED_MASK 0x00004000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_STC_CAPTURED_SHIFT 14 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_SPLICE_ERROR [13:13] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_ERROR_MASK 0x00002000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_ERROR_SHIFT 13 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_SPLICE_DONE [12:12] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_DONE_MASK 0x00001000 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_DONE_SHIFT 12 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_TWO_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_TWO_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_TWO_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_ONE_ERROR [10:10] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_ONE_ERROR_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_ONE_ERROR_SHIFT 10 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_DISCONT [09:09] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_DISCONT_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_DISCONT_SHIFT 9 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_NEW [08:08] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_NEW_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_NEW_SHIFT 8 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco3 [07:07] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco3_MASK 0x00000080 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco3_SHIFT 7 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_STC_CAPTURED [06:06] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_STC_CAPTURED_MASK 0x00000040 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_STC_CAPTURED_SHIFT 6 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_SPLICE_ERROR [05:05] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_ERROR_MASK 0x00000020 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_ERROR_SHIFT 5 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_SPLICE_DONE [04:04] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_DONE_MASK 0x00000010 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_DONE_SHIFT 4 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_TWO_ERROR [03:03] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_TWO_ERROR_MASK 0x00000008 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_TWO_ERROR_SHIFT 3 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_ONE_ERROR [02:02] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_ONE_ERROR_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_ONE_ERROR_SHIFT 2 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_DISCONT [01:01] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_DISCONT_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_DISCONT_SHIFT 1 - -/* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_NEW [00:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_NEW_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_NEW_SHIFT 0 - -/*************************************************************************** - *INTERRUPT1_ENABLE - PCR INTERRUPT ENABLE register for Contexts 7 to 4 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT1_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT1_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_INTERRUPT1_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 - -/*************************************************************************** - *INTERRUPT2_STATUS - PCR INTERRUPT STATUS register for Contexts 11 to 8 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco0_SHIFT 31 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_STC_CAPTURED [30:30] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_STC_CAPTURED_MASK 0x40000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_STC_CAPTURED_SHIFT 30 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_SPLICE_ERROR [29:29] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_ERROR_MASK 0x20000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_ERROR_SHIFT 29 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_SPLICE_DONE [28:28] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_DONE_MASK 0x10000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_DONE_SHIFT 28 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_TWO_ERROR [27:27] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_TWO_ERROR_MASK 0x08000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_TWO_ERROR_SHIFT 27 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_ONE_ERROR [26:26] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_ONE_ERROR_MASK 0x04000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_ONE_ERROR_SHIFT 26 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_DISCONT [25:25] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_DISCONT_MASK 0x02000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_DISCONT_SHIFT 25 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_NEW [24:24] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_NEW_MASK 0x01000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_NEW_SHIFT 24 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco1 [23:23] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco1_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco1_SHIFT 23 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_STC_CAPTURED [22:22] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_STC_CAPTURED_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_STC_CAPTURED_SHIFT 22 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_SPLICE_ERROR [21:21] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_ERROR_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_ERROR_SHIFT 21 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_SPLICE_DONE [20:20] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_DONE_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_DONE_SHIFT 20 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_TWO_ERROR [19:19] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_TWO_ERROR_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_TWO_ERROR_SHIFT 19 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_ONE_ERROR [18:18] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_ONE_ERROR_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_ONE_ERROR_SHIFT 18 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_DISCONT [17:17] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_DISCONT_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_DISCONT_SHIFT 17 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_NEW [16:16] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_NEW_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_NEW_SHIFT 16 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco2 [15:15] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco2_MASK 0x00008000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco2_SHIFT 15 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_STC_CAPTURED [14:14] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_STC_CAPTURED_MASK 0x00004000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_STC_CAPTURED_SHIFT 14 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_SPLICE_ERROR [13:13] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_ERROR_MASK 0x00002000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_ERROR_SHIFT 13 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_SPLICE_DONE [12:12] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_DONE_MASK 0x00001000 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_DONE_SHIFT 12 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_TWO_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_TWO_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_TWO_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_ONE_ERROR [10:10] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_ONE_ERROR_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_ONE_ERROR_SHIFT 10 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_DISCONT [09:09] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_DISCONT_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_DISCONT_SHIFT 9 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_NEW [08:08] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_NEW_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_NEW_SHIFT 8 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco3 [07:07] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco3_MASK 0x00000080 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco3_SHIFT 7 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_STC_CAPTURED [06:06] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_STC_CAPTURED_MASK 0x00000040 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_STC_CAPTURED_SHIFT 6 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_SPLICE_ERROR [05:05] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_ERROR_MASK 0x00000020 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_ERROR_SHIFT 5 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_SPLICE_DONE [04:04] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_DONE_MASK 0x00000010 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_DONE_SHIFT 4 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_TWO_ERROR [03:03] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_TWO_ERROR_MASK 0x00000008 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_TWO_ERROR_SHIFT 3 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_ONE_ERROR [02:02] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_ONE_ERROR_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_ONE_ERROR_SHIFT 2 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_DISCONT [01:01] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_DISCONT_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_DISCONT_SHIFT 1 - -/* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_NEW [00:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_NEW_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_NEW_SHIFT 0 - -/*************************************************************************** - *INTERRUPT2_ENABLE - PCR INTERRUPT ENABLE register for Contexts 11 to 8 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT2_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT2_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_INTERRUPT2_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 - -/*************************************************************************** - *INTERRUPT3_STATUS - PCR INTERRUPT STATUS register for Contexts 15 to 12 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco0_SHIFT 31 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_STC_CAPTURED [30:30] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_STC_CAPTURED_MASK 0x40000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_STC_CAPTURED_SHIFT 30 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_SPLICE_ERROR [29:29] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_ERROR_MASK 0x20000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_ERROR_SHIFT 29 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_SPLICE_DONE [28:28] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_DONE_MASK 0x10000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_DONE_SHIFT 28 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_TWO_ERROR [27:27] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_TWO_ERROR_MASK 0x08000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_TWO_ERROR_SHIFT 27 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_ONE_ERROR [26:26] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_ONE_ERROR_MASK 0x04000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_ONE_ERROR_SHIFT 26 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_DISCONT [25:25] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_DISCONT_MASK 0x02000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_DISCONT_SHIFT 25 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_NEW [24:24] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_NEW_MASK 0x01000000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_NEW_SHIFT 24 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco1 [23:23] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco1_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco1_SHIFT 23 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_STC_CAPTURED [22:22] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_STC_CAPTURED_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_STC_CAPTURED_SHIFT 22 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_SPLICE_ERROR [21:21] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_ERROR_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_ERROR_SHIFT 21 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_SPLICE_DONE [20:20] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_DONE_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_DONE_SHIFT 20 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_TWO_ERROR [19:19] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_TWO_ERROR_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_TWO_ERROR_SHIFT 19 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_ONE_ERROR [18:18] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_ONE_ERROR_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_ONE_ERROR_SHIFT 18 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_DISCONT [17:17] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_DISCONT_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_DISCONT_SHIFT 17 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_NEW [16:16] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_NEW_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_NEW_SHIFT 16 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco2 [15:15] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco2_MASK 0x00008000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco2_SHIFT 15 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_STC_CAPTURED [14:14] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_STC_CAPTURED_MASK 0x00004000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_STC_CAPTURED_SHIFT 14 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_SPLICE_ERROR [13:13] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_ERROR_MASK 0x00002000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_ERROR_SHIFT 13 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_SPLICE_DONE [12:12] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_DONE_MASK 0x00001000 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_DONE_SHIFT 12 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_TWO_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_TWO_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_TWO_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_ONE_ERROR [10:10] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_ONE_ERROR_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_ONE_ERROR_SHIFT 10 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_DISCONT [09:09] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_DISCONT_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_DISCONT_SHIFT 9 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_NEW [08:08] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_NEW_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_NEW_SHIFT 8 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco3 [07:07] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco3_MASK 0x00000080 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco3_SHIFT 7 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_STC_CAPTURED [06:06] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_STC_CAPTURED_MASK 0x00000040 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_STC_CAPTURED_SHIFT 6 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_SPLICE_ERROR [05:05] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_ERROR_MASK 0x00000020 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_ERROR_SHIFT 5 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_SPLICE_DONE [04:04] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_DONE_MASK 0x00000010 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_DONE_SHIFT 4 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_TWO_ERROR [03:03] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_TWO_ERROR_MASK 0x00000008 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_TWO_ERROR_SHIFT 3 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_ONE_ERROR [02:02] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_ONE_ERROR_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_ONE_ERROR_SHIFT 2 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_DISCONT [01:01] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_DISCONT_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_DISCONT_SHIFT 1 - -/* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_NEW [00:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_NEW_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_NEW_SHIFT 0 - -/*************************************************************************** - *INTERRUPT3_ENABLE - PCR INTERRUPT ENABLE register for Contexts 15 to 12 - ***************************************************************************/ -/* XPT_PCROFFSET :: INTERRUPT3_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ -#define BCHP_XPT_PCROFFSET_INTERRUPT3_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_INTERRUPT3_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 - -/*************************************************************************** - *STC0_CTRL - STC0 Counter Control - ***************************************************************************/ -/* XPT_PCROFFSET :: STC0_CTRL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC0_CTRL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC0_CTRL :: MODE [02:02] */ -#define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_SHIFT 2 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_BINARY 1 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_MOD_300 0 - -/* XPT_PCROFFSET :: STC0_CTRL :: FREEZE [01:01] */ -#define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_SHIFT 1 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_STC_FREEZE 1 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_STC_NORMAL 0 - -/* XPT_PCROFFSET :: STC0_CTRL :: RESET [00:00] */ -#define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_STC_RESET 1 -#define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_STC_NORMAL 0 - -/*************************************************************************** - *STC0_TIMEBASE_SEL - STC0 Timebase Select - ***************************************************************************/ -/* XPT_PCROFFSET :: STC0_TIMEBASE_SEL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC0_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 -#define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 - -/*************************************************************************** - *STC0_RATE_CTRL - STC0 Counter Increment and Prescale - ***************************************************************************/ -/* XPT_PCROFFSET :: STC0_RATE_CTRL :: reserved0 [31:16] */ -#define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_reserved0_MASK 0xffff0000 -#define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_reserved0_SHIFT 16 - -/* XPT_PCROFFSET :: STC0_RATE_CTRL :: PRESCALE [15:08] */ -#define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_PRESCALE_MASK 0x0000ff00 -#define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_PRESCALE_SHIFT 8 - -/* XPT_PCROFFSET :: STC0_RATE_CTRL :: INCREMENT [07:00] */ -#define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_INCREMENT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_INCREMENT_SHIFT 0 - -/*************************************************************************** - *STC0_CAPTURE_PCR_ONCE - STC0 Capture PCR once - ***************************************************************************/ -/* XPT_PCROFFSET :: STC0_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: STC0_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 -#define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 - -/*************************************************************************** - *STC0 - STC0 Counter - ***************************************************************************/ -/* XPT_PCROFFSET :: STC0 :: COUNT [31:00] */ -#define BCHP_XPT_PCROFFSET_STC0_COUNT_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_STC0_COUNT_SHIFT 0 - -/*************************************************************************** - *STC1_CTRL - STC1 Counter Control - ***************************************************************************/ -/* XPT_PCROFFSET :: STC1_CTRL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC1_CTRL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC1_CTRL :: MODE [02:02] */ -#define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_SHIFT 2 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_BINARY 1 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_MOD_300 0 - -/* XPT_PCROFFSET :: STC1_CTRL :: FREEZE [01:01] */ -#define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_SHIFT 1 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_STC_FREEZE 1 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_STC_NORMAL 0 - -/* XPT_PCROFFSET :: STC1_CTRL :: RESET [00:00] */ -#define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_STC_RESET 1 -#define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_STC_NORMAL 0 - -/*************************************************************************** - *STC1_TIMEBASE_SEL - STC1 Timebase Select - ***************************************************************************/ -/* XPT_PCROFFSET :: STC1_TIMEBASE_SEL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC1_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 -#define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 - -/*************************************************************************** - *STC1_RATE_CTRL - STC1 Counter Increment and Prescale - ***************************************************************************/ -/* XPT_PCROFFSET :: STC1_RATE_CTRL :: reserved0 [31:16] */ -#define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_reserved0_MASK 0xffff0000 -#define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_reserved0_SHIFT 16 - -/* XPT_PCROFFSET :: STC1_RATE_CTRL :: PRESCALE [15:08] */ -#define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_PRESCALE_MASK 0x0000ff00 -#define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_PRESCALE_SHIFT 8 - -/* XPT_PCROFFSET :: STC1_RATE_CTRL :: INCREMENT [07:00] */ -#define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_INCREMENT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_INCREMENT_SHIFT 0 - -/*************************************************************************** - *STC1_CAPTURE_PCR_ONCE - STC1 Capture PCR once - ***************************************************************************/ -/* XPT_PCROFFSET :: STC1_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: STC1_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 -#define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 - -/*************************************************************************** - *STC1 - STC1 Counter - ***************************************************************************/ -/* XPT_PCROFFSET :: STC1 :: COUNT [31:00] */ -#define BCHP_XPT_PCROFFSET_STC1_COUNT_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_STC1_COUNT_SHIFT 0 - -/*************************************************************************** - *STC2_CTRL - STC2 Counter Control - ***************************************************************************/ -/* XPT_PCROFFSET :: STC2_CTRL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC2_CTRL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC2_CTRL :: MODE [02:02] */ -#define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_SHIFT 2 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_BINARY 1 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_MOD_300 0 - -/* XPT_PCROFFSET :: STC2_CTRL :: FREEZE [01:01] */ -#define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_SHIFT 1 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_STC_FREEZE 1 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_STC_NORMAL 0 - -/* XPT_PCROFFSET :: STC2_CTRL :: RESET [00:00] */ -#define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_STC_RESET 1 -#define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_STC_NORMAL 0 - -/*************************************************************************** - *STC2_TIMEBASE_SEL - STC2 Timebase Select - ***************************************************************************/ -/* XPT_PCROFFSET :: STC2_TIMEBASE_SEL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC2_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 -#define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 - -/*************************************************************************** - *STC2_RATE_CTRL - STC2 Counter Increment and Prescale - ***************************************************************************/ -/* XPT_PCROFFSET :: STC2_RATE_CTRL :: reserved0 [31:16] */ -#define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_reserved0_MASK 0xffff0000 -#define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_reserved0_SHIFT 16 - -/* XPT_PCROFFSET :: STC2_RATE_CTRL :: PRESCALE [15:08] */ -#define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_PRESCALE_MASK 0x0000ff00 -#define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_PRESCALE_SHIFT 8 - -/* XPT_PCROFFSET :: STC2_RATE_CTRL :: INCREMENT [07:00] */ -#define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_INCREMENT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_INCREMENT_SHIFT 0 - -/*************************************************************************** - *STC2_CAPTURE_PCR_ONCE - STC2 Capture PCR once - ***************************************************************************/ -/* XPT_PCROFFSET :: STC2_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: STC2_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 -#define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 - -/*************************************************************************** - *STC2 - STC2 Counter - ***************************************************************************/ -/* XPT_PCROFFSET :: STC2 :: COUNT [31:00] */ -#define BCHP_XPT_PCROFFSET_STC2_COUNT_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_STC2_COUNT_SHIFT 0 - -/*************************************************************************** - *STC3_CTRL - STC3 Counter Control - ***************************************************************************/ -/* XPT_PCROFFSET :: STC3_CTRL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC3_CTRL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC3_CTRL :: MODE [02:02] */ -#define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_MASK 0x00000004 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_SHIFT 2 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_BINARY 1 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_MOD_300 0 - -/* XPT_PCROFFSET :: STC3_CTRL :: FREEZE [01:01] */ -#define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_SHIFT 1 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_STC_FREEZE 1 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_STC_NORMAL 0 - -/* XPT_PCROFFSET :: STC3_CTRL :: RESET [00:00] */ -#define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_STC_RESET 1 -#define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_STC_NORMAL 0 - -/*************************************************************************** - *STC3_TIMEBASE_SEL - STC3 Timebase Select - ***************************************************************************/ -/* XPT_PCROFFSET :: STC3_TIMEBASE_SEL :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: STC3_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 -#define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 - -/*************************************************************************** - *STC3_RATE_CTRL - STC3 Counter Increment and Prescale - ***************************************************************************/ -/* XPT_PCROFFSET :: STC3_RATE_CTRL :: reserved0 [31:16] */ -#define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_reserved0_MASK 0xffff0000 -#define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_reserved0_SHIFT 16 - -/* XPT_PCROFFSET :: STC3_RATE_CTRL :: PRESCALE [15:08] */ -#define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_PRESCALE_MASK 0x0000ff00 -#define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_PRESCALE_SHIFT 8 - -/* XPT_PCROFFSET :: STC3_RATE_CTRL :: INCREMENT [07:00] */ -#define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_INCREMENT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_INCREMENT_SHIFT 0 - -/*************************************************************************** - *STC3_CAPTURE_PCR_ONCE - STC3 Capture PCR once - ***************************************************************************/ -/* XPT_PCROFFSET :: STC3_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: STC3_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 -#define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 -#define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 - -/*************************************************************************** - *STC3 - STC3 Counter - ***************************************************************************/ -/* XPT_PCROFFSET :: STC3 :: COUNT [31:00] */ -#define BCHP_XPT_PCROFFSET_STC3_COUNT_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_STC3_COUNT_SHIFT 0 - -/*************************************************************************** - *TM_PCROFFSET_CONFIG_TABLE - TM Control - ***************************************************************************/ -/* XPT_PCROFFSET :: TM_PCROFFSET_CONFIG_TABLE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: TM_PCROFFSET_CONFIG_TABLE :: TM [03:00] */ -#define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_TM_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_TM_SHIFT 0 - -/*************************************************************************** - *STC_BROADCAST_SEL - STC Broadcast bus select - ***************************************************************************/ -/* XPT_PCROFFSET :: STC_BROADCAST_SEL :: reserved0 [31:16] */ -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_reserved0_MASK 0xffff0000 -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_reserved0_SHIFT 16 - -/* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST3_SEL [15:12] */ -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST3_SEL_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST3_SEL_SHIFT 12 - -/* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST2_SEL [11:08] */ -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST2_SEL_MASK 0x00000f00 -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST2_SEL_SHIFT 8 - -/* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST1_SEL [07:04] */ -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST1_SEL_MASK 0x000000f0 -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST1_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST0_SEL [03:00] */ -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST0_SEL_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST0_SEL_SHIFT 0 - -/*************************************************************************** - *PID_CONFIG_TABLE_%i - PID Configuration Table - ***************************************************************************/ -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_BASE 0x00227400 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_START 0 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_END 127 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *PID_CONFIG_TABLE_%i - PID Configuration Table - ***************************************************************************/ -/* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: reserved_for_eco1 [07:07] */ -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved_for_eco1_MASK 0x00000080 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: JITTER_DIS [06:06] */ -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_MASK 0x00000040 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_SHIFT 6 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_ENABLE 0 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_DISABLE 1 - -/* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: FIXED_OFFSET_EN [05:05] */ -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_MASK 0x00000020 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_SHIFT 5 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_ENABLE 1 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_DISABLE 0 - -/* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: PCROFFSET_EN [04:04] */ -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_MASK 0x00000010 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_SHIFT 4 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_ENABLE 1 -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_DISABLE 0 - -/* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: OFFSET_INDEX [03:00] */ -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_OFFSET_INDEX_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_OFFSET_INDEX_SHIFT 0 - - -/*************************************************************************** - *CONTEXT0_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT0_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT0_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT0_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT0_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT1_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT1_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT1_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT1_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT2_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT2_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT2_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT2_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT3_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT3_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT3_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT3_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT4_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT4_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT4_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT4_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT5_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT5_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT5_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT5_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT6_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT6_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT6_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT6_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT7_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT7_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT7_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT7_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT8_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT8_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT8_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT8_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT9_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT9_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT9_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT9_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT10_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT10_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT10_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT10_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT11_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT11_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT11_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT11_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT12_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT12_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT12_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT12_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT13_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT13_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT13_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT13_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT14_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT14_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT14_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT14_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_4_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved0 [31:24] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved0_MASK 0xff000000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved0_SHIFT 24 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: STC_SEL [05:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_STC_SEL_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT15_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_STATE - Config Word 2 - SPLICE STATE Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATE :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATE :: SPLICE_STATE [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_SPLICE_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATUS :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATUS :: COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_RD_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_WR_PTR :: reserved0 [31:03] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_reserved0_SHIFT 3 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 - -/* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f -#define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET_STATE - Config Word 10 - OFFSET STATE register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATE :: reserved0 [31:04] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_reserved0_SHIFT 4 - -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATE :: OFFSET_STATE [03:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_OFFSET_STATE_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET - Config Word 11 - OFFSET read/write - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET :: PCR_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_PCR_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_PCR_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET_VALID - Config Word 12 - OFFSET Valid - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_VALID :: reserved0 [31:01] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_reserved0_MASK 0xfffffffe -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_reserved0_SHIFT 1 - -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 - -/*************************************************************************** - *CONTEXT15_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_FIXED_OFFSET - Config Word 15 - Fixed OFFSET - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_PP_PCR_COUNT - Config Word 16 - PCR COUNT register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_PP_PCR_COUNT :: reserved0 [31:08] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_reserved0_MASK 0xffffff00 -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_reserved0_SHIFT 8 - -/* XPT_PCROFFSET :: CONTEXT15_PP_PCR_COUNT :: PCR_COUNT [07:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_RESERVED_CFG_0 - Config Word 27 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_0 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_0_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_0_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_RESERVED_CFG_1 - Config Word 28 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_1 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_1_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_1_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_RESERVED_CFG_2 - Config Word 29 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_2 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_2_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_2_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_RESERVED_CFG_3 - Config Word 30 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_3 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_3_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_3_RESERVED_SHIFT 0 - -/*************************************************************************** - *CONTEXT15_RESERVED_CFG_4 - Config Word 31 - RESERVED - ***************************************************************************/ -/* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_4 :: RESERVED [31:00] */ -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_4_RESERVED_MASK 0xffffffff -#define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_4_RESERVED_SHIFT 0 - -#endif /* #ifndef BCHP_XPT_PCROFFSET_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,49378 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_rave.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:26p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:27 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:26p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_RAVE_H__ -#define BCHP_XPT_RAVE_H__ - -/*************************************************************************** - *XPT_RAVE - XPT RAV Control Registers - ***************************************************************************/ -#define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR 0x00210000 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR 0x00210004 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR 0x00210008 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR 0x0021000c /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR 0x00210010 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR 0x00210014 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL 0x00210018 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH 0x0021001c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS 0x00210020 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR 0x00210024 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR 0x00210028 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR 0x0021002c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR 0x00210030 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR 0x00210034 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR 0x00210038 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL 0x0021003c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH 0x00210040 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG 0x00210044 /* Context 0 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB 0x00210048 /* Context 0 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD 0x0021004c /* Context 0 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF 0x00210050 /* Context 0 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH 0x00210054 /* Context 0 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1 0x00210058 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2 0x0021005c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3 0x00210060 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES 0x00210064 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL 0x00210068 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL 0x0021006c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL 0x00210070 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL 0x00210074 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL 0x00210078 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL 0x0021007c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL 0x00210080 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL 0x00210084 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL 0x00210088 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL 0x0021008c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode 0x00210090 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID 0x00210094 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1 0x00210098 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX0_REC_INIT_TS 0x0021009c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL 0x002100a0 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG 0x002100a4 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4 0x002100a8 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR 0x002100ac /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE 0x002100b0 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX0_REC_TIMER 0x002100b4 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX0_REC_STATE0 0x002100b8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX0_REC_STATE1 0x002100bc /* Record State Register */ -#define BCHP_XPT_RAVE_CX0_REC_STATE2 0x002100c0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX0_REC_STATE2b 0x002100c4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX0_REC_STATE3 0x002100c8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX0_REC_COUNT 0x002100cc /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL 0x002100d0 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1 0x002100d4 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_0 0x002100d8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_1 0x002100dc /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_2 0x002100e0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_3 0x002100e4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR 0x002100e8 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR 0x002100ec /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR 0x002100f0 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR 0x002100f4 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR 0x002100f8 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR 0x002100fc /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL 0x00210100 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH 0x00210104 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS 0x00210108 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR 0x0021010c /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR 0x00210110 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR 0x00210114 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR 0x00210118 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR 0x0021011c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR 0x00210120 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL 0x00210124 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH 0x00210128 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG 0x0021012c /* Context 1 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB 0x00210130 /* Context 1 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD 0x00210134 /* Context 1 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF 0x00210138 /* Context 1 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH 0x0021013c /* Context 1 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1 0x00210140 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2 0x00210144 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3 0x00210148 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES 0x0021014c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL 0x00210150 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL 0x00210154 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL 0x00210158 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL 0x0021015c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL 0x00210160 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL 0x00210164 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL 0x00210168 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL 0x0021016c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL 0x00210170 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL 0x00210174 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE 0x00210178 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID 0x0021017c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1 0x00210180 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX1_REC_INIT_TS 0x00210184 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL 0x00210188 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG 0x0021018c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4 0x00210190 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR 0x00210194 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE 0x00210198 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX1_REC_TIMER 0x0021019c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX1_REC_STATE0 0x002101a0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX1_REC_STATE1 0x002101a4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX1_REC_STATE2 0x002101a8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX1_REC_STATE2b 0x002101ac /* Record State Register */ -#define BCHP_XPT_RAVE_CX1_REC_STATE3 0x002101b0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX1_REC_COUNT 0x002101b4 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL 0x002101b8 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1 0x002101bc /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_0 0x002101c0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_1 0x002101c4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_2 0x002101c8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_3 0x002101cc /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR 0x002101d0 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR 0x002101d4 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR 0x002101d8 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR 0x002101dc /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR 0x002101e0 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR 0x002101e4 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL 0x002101e8 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH 0x002101ec /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS 0x002101f0 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR 0x002101f4 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR 0x002101f8 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR 0x002101fc /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR 0x00210200 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR 0x00210204 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR 0x00210208 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL 0x0021020c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH 0x00210210 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG 0x00210214 /* Context 2 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB 0x00210218 /* Context 2 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD 0x0021021c /* Context 2 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF 0x00210220 /* Context 2 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH 0x00210224 /* Context 2 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1 0x00210228 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2 0x0021022c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3 0x00210230 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES 0x00210234 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL 0x00210238 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL 0x0021023c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL 0x00210240 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL 0x00210244 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL 0x00210248 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL 0x0021024c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL 0x00210250 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL 0x00210254 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL 0x00210258 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL 0x0021025c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode 0x00210260 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID 0x00210264 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1 0x00210268 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX2_REC_INIT_TS 0x0021026c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL 0x00210270 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG 0x00210274 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4 0x00210278 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR 0x0021027c /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE 0x00210280 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX2_REC_TIMER 0x00210284 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX2_REC_STATE0 0x00210288 /* Record State Register */ -#define BCHP_XPT_RAVE_CX2_REC_STATE1 0x0021028c /* Record State Register */ -#define BCHP_XPT_RAVE_CX2_REC_STATE2 0x00210290 /* Record State Register */ -#define BCHP_XPT_RAVE_CX2_REC_STATE2b 0x00210294 /* Record State Register */ -#define BCHP_XPT_RAVE_CX2_REC_STATE3 0x00210298 /* Record State Register */ -#define BCHP_XPT_RAVE_CX2_REC_COUNT 0x0021029c /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL 0x002102a0 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1 0x002102a4 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_0 0x002102a8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_1 0x002102ac /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_2 0x002102b0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_3 0x002102b4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR 0x002102b8 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR 0x002102bc /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR 0x002102c0 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR 0x002102c4 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR 0x002102c8 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR 0x002102cc /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL 0x002102d0 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH 0x002102d4 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS 0x002102d8 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR 0x002102dc /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR 0x002102e0 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR 0x002102e4 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR 0x002102e8 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR 0x002102ec /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR 0x002102f0 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL 0x002102f4 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH 0x002102f8 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG 0x002102fc /* Context 3 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB 0x00210300 /* Context 3 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD 0x00210304 /* Context 3 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF 0x00210308 /* Context 3 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH 0x0021030c /* Context 3 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1 0x00210310 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2 0x00210314 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3 0x00210318 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES 0x0021031c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL 0x00210320 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL 0x00210324 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL 0x00210328 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL 0x0021032c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL 0x00210330 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL 0x00210334 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL 0x00210338 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL 0x0021033c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL 0x00210340 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL 0x00210344 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode 0x00210348 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID 0x0021034c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1 0x00210350 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX3_REC_INIT_TS 0x00210354 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL 0x00210358 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG 0x0021035c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4 0x00210360 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR 0x00210364 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE 0x00210368 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX3_REC_TIMER 0x0021036c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX3_REC_STATE0 0x00210370 /* Record State Register */ -#define BCHP_XPT_RAVE_CX3_REC_STATE1 0x00210374 /* Record State Register */ -#define BCHP_XPT_RAVE_CX3_REC_STATE2 0x00210378 /* Record State Register */ -#define BCHP_XPT_RAVE_CX3_REC_STATE2b 0x0021037c /* Record State Register */ -#define BCHP_XPT_RAVE_CX3_REC_STATE3 0x00210380 /* Record State Register */ -#define BCHP_XPT_RAVE_CX3_REC_COUNT 0x00210384 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL 0x00210388 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1 0x0021038c /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_0 0x00210390 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_1 0x00210394 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_2 0x00210398 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_3 0x0021039c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR 0x002103a0 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR 0x002103a4 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR 0x002103a8 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR 0x002103ac /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR 0x002103b0 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR 0x002103b4 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL 0x002103b8 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH 0x002103bc /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS 0x002103c0 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR 0x002103c4 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR 0x002103c8 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR 0x002103cc /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR 0x002103d0 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR 0x002103d4 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR 0x002103d8 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL 0x002103dc /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH 0x002103e0 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG 0x002103e4 /* Context 4 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB 0x002103e8 /* Context 4 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD 0x002103ec /* Context 4 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF 0x002103f0 /* Context 4 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH 0x002103f4 /* Context 4 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1 0x002103f8 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2 0x002103fc /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3 0x00210400 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES 0x00210404 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL 0x00210408 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL 0x0021040c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL 0x00210410 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL 0x00210414 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL 0x00210418 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL 0x0021041c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL 0x00210420 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL 0x00210424 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL 0x00210428 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL 0x0021042c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode 0x00210430 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID 0x00210434 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1 0x00210438 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX4_REC_INIT_TS 0x0021043c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL 0x00210440 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG 0x00210444 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4 0x00210448 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR 0x0021044c /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE 0x00210450 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX4_REC_TIMER 0x00210454 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX4_REC_STATE0 0x00210458 /* Record State Register */ -#define BCHP_XPT_RAVE_CX4_REC_STATE1 0x0021045c /* Record State Register */ -#define BCHP_XPT_RAVE_CX4_REC_STATE2 0x00210460 /* Record State Register */ -#define BCHP_XPT_RAVE_CX4_REC_STATE2b 0x00210464 /* Record State Register */ -#define BCHP_XPT_RAVE_CX4_REC_STATE3 0x00210468 /* Record State Register */ -#define BCHP_XPT_RAVE_CX4_REC_COUNT 0x0021046c /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL 0x00210470 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1 0x00210474 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_0 0x00210478 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_1 0x0021047c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_2 0x00210480 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_3 0x00210484 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR 0x00210488 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR 0x0021048c /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR 0x00210490 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR 0x00210494 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR 0x00210498 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR 0x0021049c /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL 0x002104a0 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH 0x002104a4 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS 0x002104a8 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR 0x002104ac /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR 0x002104b0 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR 0x002104b4 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR 0x002104b8 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR 0x002104bc /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR 0x002104c0 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL 0x002104c4 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH 0x002104c8 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG 0x002104cc /* Context 5 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB 0x002104d0 /* Context 5 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD 0x002104d4 /* Context 5 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF 0x002104d8 /* Context 5 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH 0x002104dc /* Context 5 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1 0x002104e0 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2 0x002104e4 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3 0x002104e8 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES 0x002104ec /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL 0x002104f0 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL 0x002104f4 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL 0x002104f8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL 0x002104fc /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL 0x00210500 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL 0x00210504 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL 0x00210508 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL 0x0021050c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL 0x00210510 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL 0x00210514 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE 0x00210518 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID 0x0021051c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1 0x00210520 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX5_REC_INIT_TS 0x00210524 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL 0x00210528 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG 0x0021052c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4 0x00210530 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR 0x00210534 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE 0x00210538 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX5_REC_TIMER 0x0021053c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX5_REC_STATE0 0x00210540 /* Record State Register */ -#define BCHP_XPT_RAVE_CX5_REC_STATE1 0x00210544 /* Record State Register */ -#define BCHP_XPT_RAVE_CX5_REC_STATE2 0x00210548 /* Record State Register */ -#define BCHP_XPT_RAVE_CX5_REC_STATE2b 0x0021054c /* Record State Register */ -#define BCHP_XPT_RAVE_CX5_REC_STATE3 0x00210550 /* Record State Register */ -#define BCHP_XPT_RAVE_CX5_REC_COUNT 0x00210554 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL 0x00210558 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1 0x0021055c /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_0 0x00210560 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_1 0x00210564 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_2 0x00210568 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_3 0x0021056c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR 0x00210570 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR 0x00210574 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR 0x00210578 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR 0x0021057c /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR 0x00210580 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR 0x00210584 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL 0x00210588 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH 0x0021058c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS 0x00210590 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR 0x00210594 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR 0x00210598 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR 0x0021059c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR 0x002105a0 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR 0x002105a4 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR 0x002105a8 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL 0x002105ac /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH 0x002105b0 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG 0x002105b4 /* Context 6 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB 0x002105b8 /* Context 6 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD 0x002105bc /* Context 6 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF 0x002105c0 /* Context 6 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH 0x002105c4 /* Context 6 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1 0x002105c8 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2 0x002105cc /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3 0x002105d0 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES 0x002105d4 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL 0x002105d8 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL 0x002105dc /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL 0x002105e0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL 0x002105e4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL 0x002105e8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL 0x002105ec /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL 0x002105f0 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL 0x002105f4 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL 0x002105f8 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL 0x002105fc /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode 0x00210600 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID 0x00210604 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1 0x00210608 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX6_REC_INIT_TS 0x0021060c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL 0x00210610 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG 0x00210614 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4 0x00210618 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR 0x0021061c /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE 0x00210620 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX6_REC_TIMER 0x00210624 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX6_REC_STATE0 0x00210628 /* Record State Register */ -#define BCHP_XPT_RAVE_CX6_REC_STATE1 0x0021062c /* Record State Register */ -#define BCHP_XPT_RAVE_CX6_REC_STATE2 0x00210630 /* Record State Register */ -#define BCHP_XPT_RAVE_CX6_REC_STATE2b 0x00210634 /* Record State Register */ -#define BCHP_XPT_RAVE_CX6_REC_STATE3 0x00210638 /* Record State Register */ -#define BCHP_XPT_RAVE_CX6_REC_COUNT 0x0021063c /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL 0x00210640 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1 0x00210644 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_0 0x00210648 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_1 0x0021064c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_2 0x00210650 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_3 0x00210654 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR 0x00210658 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR 0x0021065c /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR 0x00210660 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR 0x00210664 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR 0x00210668 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR 0x0021066c /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL 0x00210670 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH 0x00210674 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS 0x00210678 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR 0x0021067c /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR 0x00210680 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR 0x00210684 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR 0x00210688 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR 0x0021068c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR 0x00210690 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL 0x00210694 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH 0x00210698 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG 0x0021069c /* Context 7 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB 0x002106a0 /* Context 7 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD 0x002106a4 /* Context 7 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF 0x002106a8 /* Context 7 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH 0x002106ac /* Context 7 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1 0x002106b0 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2 0x002106b4 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3 0x002106b8 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES 0x002106bc /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL 0x002106c0 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL 0x002106c4 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL 0x002106c8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL 0x002106cc /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL 0x002106d0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL 0x002106d4 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL 0x002106d8 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL 0x002106dc /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL 0x002106e0 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL 0x002106e4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE 0x002106e8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID 0x002106ec /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1 0x002106f0 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX7_REC_INIT_TS 0x002106f4 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL 0x002106f8 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG 0x002106fc /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4 0x00210700 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR 0x00210704 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE 0x00210708 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX7_REC_TIMER 0x0021070c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX7_REC_STATE0 0x00210710 /* Record State Register */ -#define BCHP_XPT_RAVE_CX7_REC_STATE1 0x00210714 /* Record State Register */ -#define BCHP_XPT_RAVE_CX7_REC_STATE2 0x00210718 /* Record State Register */ -#define BCHP_XPT_RAVE_CX7_REC_STATE2b 0x0021071c /* Record State Register */ -#define BCHP_XPT_RAVE_CX7_REC_STATE3 0x00210720 /* Record State Register */ -#define BCHP_XPT_RAVE_CX7_REC_COUNT 0x00210724 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL 0x00210728 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1 0x0021072c /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_0 0x00210730 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_1 0x00210734 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_2 0x00210738 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_3 0x0021073c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR 0x00210740 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR 0x00210744 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR 0x00210748 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR 0x0021074c /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR 0x00210750 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR 0x00210754 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL 0x00210758 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH 0x0021075c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS 0x00210760 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR 0x00210764 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR 0x00210768 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR 0x0021076c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR 0x00210770 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR 0x00210774 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR 0x00210778 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL 0x0021077c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH 0x00210780 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG 0x00210784 /* Context 8 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB 0x00210788 /* Context 8 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD 0x0021078c /* Context 8 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF 0x00210790 /* Context 8 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH 0x00210794 /* Context 8 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1 0x00210798 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2 0x0021079c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3 0x002107a0 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES 0x002107a4 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL 0x002107a8 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL 0x002107ac /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL 0x002107b0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL 0x002107b4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL 0x002107b8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL 0x002107bc /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL 0x002107c0 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL 0x002107c4 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL 0x002107c8 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL 0x002107cc /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode 0x002107d0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID 0x002107d4 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1 0x002107d8 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX8_REC_INIT_TS 0x002107dc /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL 0x002107e0 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG 0x002107e4 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4 0x002107e8 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR 0x002107ec /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE 0x002107f0 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX8_REC_TIMER 0x002107f4 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX8_REC_STATE0 0x002107f8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX8_REC_STATE1 0x002107fc /* Record State Register */ -#define BCHP_XPT_RAVE_CX8_REC_STATE2 0x00210800 /* Record State Register */ -#define BCHP_XPT_RAVE_CX8_REC_STATE2b 0x00210804 /* Record State Register */ -#define BCHP_XPT_RAVE_CX8_REC_STATE3 0x00210808 /* Record State Register */ -#define BCHP_XPT_RAVE_CX8_REC_COUNT 0x0021080c /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL 0x00210810 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1 0x00210814 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_0 0x00210818 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_1 0x0021081c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_2 0x00210820 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_3 0x00210824 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR 0x00210828 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR 0x0021082c /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR 0x00210830 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR 0x00210834 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR 0x00210838 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR 0x0021083c /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL 0x00210840 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH 0x00210844 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS 0x00210848 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR 0x0021084c /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR 0x00210850 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR 0x00210854 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR 0x00210858 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR 0x0021085c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR 0x00210860 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL 0x00210864 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH 0x00210868 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG 0x0021086c /* Context 9 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB 0x00210870 /* Context 9 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD 0x00210874 /* Context 9 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF 0x00210878 /* Context 9 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH 0x0021087c /* Context 9 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1 0x00210880 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2 0x00210884 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3 0x00210888 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES 0x0021088c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL 0x00210890 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL 0x00210894 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL 0x00210898 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL 0x0021089c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL 0x002108a0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL 0x002108a4 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL 0x002108a8 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL 0x002108ac /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL 0x002108b0 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL 0x002108b4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode 0x002108b8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID 0x002108bc /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1 0x002108c0 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX9_REC_INIT_TS 0x002108c4 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL 0x002108c8 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG 0x002108cc /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4 0x002108d0 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR 0x002108d4 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE 0x002108d8 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX9_REC_TIMER 0x002108dc /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX9_REC_STATE0 0x002108e0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX9_REC_STATE1 0x002108e4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX9_REC_STATE2 0x002108e8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX9_REC_STATE2b 0x002108ec /* Record State Register */ -#define BCHP_XPT_RAVE_CX9_REC_STATE3 0x002108f0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX9_REC_COUNT 0x002108f4 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL 0x002108f8 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1 0x002108fc /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_0 0x00210900 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_1 0x00210904 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_2 0x00210908 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_3 0x0021090c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR 0x00210910 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR 0x00210914 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR 0x00210918 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR 0x0021091c /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR 0x00210920 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR 0x00210924 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL 0x00210928 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH 0x0021092c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS 0x00210930 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR 0x00210934 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR 0x00210938 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR 0x0021093c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR 0x00210940 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR 0x00210944 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR 0x00210948 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL 0x0021094c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH 0x00210950 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG 0x00210954 /* Context 10 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB 0x00210958 /* Context 10 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD 0x0021095c /* Context 10 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF 0x00210960 /* Context 10 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH 0x00210964 /* Context 10 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1 0x00210968 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2 0x0021096c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3 0x00210970 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES 0x00210974 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL 0x00210978 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL 0x0021097c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL 0x00210980 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL 0x00210984 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL 0x00210988 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL 0x0021098c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL 0x00210990 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL 0x00210994 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL 0x00210998 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL 0x0021099c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE 0x002109a0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID 0x002109a4 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1 0x002109a8 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX10_REC_INIT_TS 0x002109ac /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL 0x002109b0 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG 0x002109b4 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4 0x002109b8 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR 0x002109bc /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE 0x002109c0 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX10_REC_TIMER 0x002109c4 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX10_REC_STATE0 0x002109c8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX10_REC_STATE1 0x002109cc /* Record State Register */ -#define BCHP_XPT_RAVE_CX10_REC_STATE2 0x002109d0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX10_REC_STATE2b 0x002109d4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX10_REC_STATE3 0x002109d8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX10_REC_COUNT 0x002109dc /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL 0x002109e0 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1 0x002109e4 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_0 0x002109e8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_1 0x002109ec /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_2 0x002109f0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_3 0x002109f4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR 0x002109f8 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR 0x002109fc /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR 0x00210a00 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR 0x00210a04 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR 0x00210a08 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR 0x00210a0c /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL 0x00210a10 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH 0x00210a14 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS 0x00210a18 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR 0x00210a1c /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR 0x00210a20 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR 0x00210a24 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR 0x00210a28 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR 0x00210a2c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR 0x00210a30 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL 0x00210a34 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH 0x00210a38 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG 0x00210a3c /* Context 11 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB 0x00210a40 /* Context 11 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD 0x00210a44 /* Context 11 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF 0x00210a48 /* Context 11 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH 0x00210a4c /* Context 11 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1 0x00210a50 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2 0x00210a54 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3 0x00210a58 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES 0x00210a5c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL 0x00210a60 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL 0x00210a64 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL 0x00210a68 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL 0x00210a6c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL 0x00210a70 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL 0x00210a74 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL 0x00210a78 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL 0x00210a7c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL 0x00210a80 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL 0x00210a84 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE 0x00210a88 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID 0x00210a8c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1 0x00210a90 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX11_REC_INIT_TS 0x00210a94 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL 0x00210a98 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG 0x00210a9c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4 0x00210aa0 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR 0x00210aa4 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE 0x00210aa8 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX11_REC_TIMER 0x00210aac /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX11_REC_STATE0 0x00210ab0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX11_REC_STATE1 0x00210ab4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX11_REC_STATE2 0x00210ab8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX11_REC_STATE2b 0x00210abc /* Record State Register */ -#define BCHP_XPT_RAVE_CX11_REC_STATE3 0x00210ac0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX11_REC_COUNT 0x00210ac4 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL 0x00210ac8 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1 0x00210acc /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_0 0x00210ad0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_1 0x00210ad4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_2 0x00210ad8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_3 0x00210adc /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR 0x00210ae0 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR 0x00210ae4 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR 0x00210ae8 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR 0x00210aec /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR 0x00210af0 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR 0x00210af4 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL 0x00210af8 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH 0x00210afc /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS 0x00210b00 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR 0x00210b04 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR 0x00210b08 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR 0x00210b0c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR 0x00210b10 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR 0x00210b14 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR 0x00210b18 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL 0x00210b1c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH 0x00210b20 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG 0x00210b24 /* Context 12 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB 0x00210b28 /* Context 12 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD 0x00210b2c /* Context 12 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF 0x00210b30 /* Context 12 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH 0x00210b34 /* Context 12 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1 0x00210b38 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2 0x00210b3c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3 0x00210b40 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES 0x00210b44 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL 0x00210b48 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL 0x00210b4c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL 0x00210b50 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL 0x00210b54 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL 0x00210b58 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL 0x00210b5c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL 0x00210b60 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL 0x00210b64 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL 0x00210b68 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL 0x00210b6c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode 0x00210b70 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID 0x00210b74 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1 0x00210b78 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX12_REC_INIT_TS 0x00210b7c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL 0x00210b80 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG 0x00210b84 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4 0x00210b88 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR 0x00210b8c /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE 0x00210b90 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX12_REC_TIMER 0x00210b94 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX12_REC_STATE0 0x00210b98 /* Record State Register */ -#define BCHP_XPT_RAVE_CX12_REC_STATE1 0x00210b9c /* Record State Register */ -#define BCHP_XPT_RAVE_CX12_REC_STATE2 0x00210ba0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX12_REC_STATE2b 0x00210ba4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX12_REC_STATE3 0x00210ba8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX12_REC_COUNT 0x00210bac /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL 0x00210bb0 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1 0x00210bb4 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_0 0x00210bb8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_1 0x00210bbc /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_2 0x00210bc0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_3 0x00210bc4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR 0x00210bc8 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR 0x00210bcc /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR 0x00210bd0 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR 0x00210bd4 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR 0x00210bd8 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR 0x00210bdc /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL 0x00210be0 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH 0x00210be4 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS 0x00210be8 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR 0x00210bec /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR 0x00210bf0 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR 0x00210bf4 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR 0x00210bf8 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR 0x00210bfc /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR 0x00210c00 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL 0x00210c04 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH 0x00210c08 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG 0x00210c0c /* Context 13 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB 0x00210c10 /* Context 13 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD 0x00210c14 /* Context 13 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF 0x00210c18 /* Context 13 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH 0x00210c1c /* Context 13 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1 0x00210c20 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2 0x00210c24 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3 0x00210c28 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES 0x00210c2c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL 0x00210c30 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL 0x00210c34 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL 0x00210c38 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL 0x00210c3c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL 0x00210c40 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL 0x00210c44 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL 0x00210c48 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL 0x00210c4c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL 0x00210c50 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL 0x00210c54 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE 0x00210c58 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID 0x00210c5c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1 0x00210c60 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX13_REC_INIT_TS 0x00210c64 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL 0x00210c68 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG 0x00210c6c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4 0x00210c70 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR 0x00210c74 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE 0x00210c78 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX13_REC_TIMER 0x00210c7c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX13_REC_STATE0 0x00210c80 /* Record State Register */ -#define BCHP_XPT_RAVE_CX13_REC_STATE1 0x00210c84 /* Record State Register */ -#define BCHP_XPT_RAVE_CX13_REC_STATE2 0x00210c88 /* Record State Register */ -#define BCHP_XPT_RAVE_CX13_REC_STATE2b 0x00210c8c /* Record State Register */ -#define BCHP_XPT_RAVE_CX13_REC_STATE3 0x00210c90 /* Record State Register */ -#define BCHP_XPT_RAVE_CX13_REC_COUNT 0x00210c94 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL 0x00210c98 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1 0x00210c9c /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_0 0x00210ca0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_1 0x00210ca4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_2 0x00210ca8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_3 0x00210cac /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR 0x00210cb0 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR 0x00210cb4 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR 0x00210cb8 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR 0x00210cbc /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR 0x00210cc0 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR 0x00210cc4 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL 0x00210cc8 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH 0x00210ccc /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS 0x00210cd0 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR 0x00210cd4 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR 0x00210cd8 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR 0x00210cdc /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR 0x00210ce0 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR 0x00210ce4 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR 0x00210ce8 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL 0x00210cec /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH 0x00210cf0 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG 0x00210cf4 /* Context 14 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB 0x00210cf8 /* Context 14 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD 0x00210cfc /* Context 14 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF 0x00210d00 /* Context 14 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH 0x00210d04 /* Context 14 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1 0x00210d08 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2 0x00210d0c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3 0x00210d10 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES 0x00210d14 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL 0x00210d18 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL 0x00210d1c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL 0x00210d20 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL 0x00210d24 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL 0x00210d28 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL 0x00210d2c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL 0x00210d30 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL 0x00210d34 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL 0x00210d38 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL 0x00210d3c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode 0x00210d40 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID 0x00210d44 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1 0x00210d48 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX14_REC_INIT_TS 0x00210d4c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL 0x00210d50 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG 0x00210d54 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4 0x00210d58 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR 0x00210d5c /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE 0x00210d60 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX14_REC_TIMER 0x00210d64 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX14_REC_STATE0 0x00210d68 /* Record State Register */ -#define BCHP_XPT_RAVE_CX14_REC_STATE1 0x00210d6c /* Record State Register */ -#define BCHP_XPT_RAVE_CX14_REC_STATE2 0x00210d70 /* Record State Register */ -#define BCHP_XPT_RAVE_CX14_REC_STATE2b 0x00210d74 /* Record State Register */ -#define BCHP_XPT_RAVE_CX14_REC_STATE3 0x00210d78 /* Record State Register */ -#define BCHP_XPT_RAVE_CX14_REC_COUNT 0x00210d7c /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL 0x00210d80 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1 0x00210d84 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_0 0x00210d88 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_1 0x00210d8c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_2 0x00210d90 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_3 0x00210d94 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR 0x00210d98 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR 0x00210d9c /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR 0x00210da0 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR 0x00210da4 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR 0x00210da8 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR 0x00210dac /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL 0x00210db0 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH 0x00210db4 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS 0x00210db8 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR 0x00210dbc /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR 0x00210dc0 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR 0x00210dc4 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR 0x00210dc8 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR 0x00210dcc /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR 0x00210dd0 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL 0x00210dd4 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH 0x00210dd8 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG 0x00210ddc /* Context 15 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB 0x00210de0 /* Context 15 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD 0x00210de4 /* Context 15 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF 0x00210de8 /* Context 15 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH 0x00210dec /* Context 15 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1 0x00210df0 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2 0x00210df4 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3 0x00210df8 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES 0x00210dfc /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL 0x00210e00 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL 0x00210e04 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL 0x00210e08 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL 0x00210e0c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL 0x00210e10 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL 0x00210e14 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL 0x00210e18 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL 0x00210e1c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL 0x00210e20 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL 0x00210e24 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE 0x00210e28 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID 0x00210e2c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1 0x00210e30 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX15_REC_INIT_TS 0x00210e34 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL 0x00210e38 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG 0x00210e3c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4 0x00210e40 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR 0x00210e44 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE 0x00210e48 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX15_REC_TIMER 0x00210e4c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX15_REC_STATE0 0x00210e50 /* Record State Register */ -#define BCHP_XPT_RAVE_CX15_REC_STATE1 0x00210e54 /* Record State Register */ -#define BCHP_XPT_RAVE_CX15_REC_STATE2 0x00210e58 /* Record State Register */ -#define BCHP_XPT_RAVE_CX15_REC_STATE2b 0x00210e5c /* Record State Register */ -#define BCHP_XPT_RAVE_CX15_REC_STATE3 0x00210e60 /* Record State Register */ -#define BCHP_XPT_RAVE_CX15_REC_COUNT 0x00210e64 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL 0x00210e68 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1 0x00210e6c /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_0 0x00210e70 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_1 0x00210e74 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_2 0x00210e78 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_3 0x00210e7c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR 0x00210e80 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR 0x00210e84 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR 0x00210e88 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR 0x00210e8c /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR 0x00210e90 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR 0x00210e94 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL 0x00210e98 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH 0x00210e9c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS 0x00210ea0 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR 0x00210ea4 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR 0x00210ea8 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR 0x00210eac /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR 0x00210eb0 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR 0x00210eb4 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR 0x00210eb8 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL 0x00210ebc /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH 0x00210ec0 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG 0x00210ec4 /* Context 16 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB 0x00210ec8 /* Context 16 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD 0x00210ecc /* Context 16 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF 0x00210ed0 /* Context 16 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH 0x00210ed4 /* Context 16 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1 0x00210ed8 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2 0x00210edc /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3 0x00210ee0 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES 0x00210ee4 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL 0x00210ee8 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL 0x00210eec /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL 0x00210ef0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL 0x00210ef4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL 0x00210ef8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL 0x00210efc /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL 0x00210f00 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL 0x00210f04 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL 0x00210f08 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL 0x00210f0c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE 0x00210f10 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID 0x00210f14 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1 0x00210f18 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX16_REC_INIT_TS 0x00210f1c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL 0x00210f20 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG 0x00210f24 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4 0x00210f28 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR 0x00210f2c /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE 0x00210f30 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX16_REC_TIMER 0x00210f34 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX16_REC_STATE0 0x00210f38 /* Record State Register */ -#define BCHP_XPT_RAVE_CX16_REC_STATE1 0x00210f3c /* Record State Register */ -#define BCHP_XPT_RAVE_CX16_REC_STATE2 0x00210f40 /* Record State Register */ -#define BCHP_XPT_RAVE_CX16_REC_STATE2b 0x00210f44 /* Record State Register */ -#define BCHP_XPT_RAVE_CX16_REC_STATE3 0x00210f48 /* Record State Register */ -#define BCHP_XPT_RAVE_CX16_REC_COUNT 0x00210f4c /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL 0x00210f50 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1 0x00210f54 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_0 0x00210f58 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_1 0x00210f5c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_2 0x00210f60 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_3 0x00210f64 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR 0x00210f68 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR 0x00210f6c /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR 0x00210f70 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR 0x00210f74 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR 0x00210f78 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR 0x00210f7c /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL 0x00210f80 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH 0x00210f84 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS 0x00210f88 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR 0x00210f8c /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR 0x00210f90 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR 0x00210f94 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR 0x00210f98 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR 0x00210f9c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR 0x00210fa0 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL 0x00210fa4 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH 0x00210fa8 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG 0x00210fac /* Context 17 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB 0x00210fb0 /* Context 17 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD 0x00210fb4 /* Context 17 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF 0x00210fb8 /* Context 17 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH 0x00210fbc /* Context 17 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1 0x00210fc0 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2 0x00210fc4 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3 0x00210fc8 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES 0x00210fcc /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL 0x00210fd0 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL 0x00210fd4 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL 0x00210fd8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL 0x00210fdc /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL 0x00210fe0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL 0x00210fe4 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL 0x00210fe8 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL 0x00210fec /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL 0x00210ff0 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL 0x00210ff4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE 0x00210ff8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID 0x00210ffc /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1 0x00211000 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX17_REC_INIT_TS 0x00211004 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL 0x00211008 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG 0x0021100c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4 0x00211010 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR 0x00211014 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE 0x00211018 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX17_REC_TIMER 0x0021101c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX17_REC_STATE0 0x00211020 /* Record State Register */ -#define BCHP_XPT_RAVE_CX17_REC_STATE1 0x00211024 /* Record State Register */ -#define BCHP_XPT_RAVE_CX17_REC_STATE2 0x00211028 /* Record State Register */ -#define BCHP_XPT_RAVE_CX17_REC_STATE2b 0x0021102c /* Record State Register */ -#define BCHP_XPT_RAVE_CX17_REC_STATE3 0x00211030 /* Record State Register */ -#define BCHP_XPT_RAVE_CX17_REC_COUNT 0x00211034 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL 0x00211038 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1 0x0021103c /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_0 0x00211040 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_1 0x00211044 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_2 0x00211048 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_3 0x0021104c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR 0x00211050 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR 0x00211054 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR 0x00211058 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR 0x0021105c /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR 0x00211060 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR 0x00211064 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL 0x00211068 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH 0x0021106c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS 0x00211070 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR 0x00211074 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR 0x00211078 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR 0x0021107c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR 0x00211080 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR 0x00211084 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR 0x00211088 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL 0x0021108c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH 0x00211090 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG 0x00211094 /* Context 18 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB 0x00211098 /* Context 18 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD 0x0021109c /* Context 18 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF 0x002110a0 /* Context 18 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH 0x002110a4 /* Context 18 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1 0x002110a8 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2 0x002110ac /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3 0x002110b0 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES 0x002110b4 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL 0x002110b8 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL 0x002110bc /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL 0x002110c0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL 0x002110c4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL 0x002110c8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL 0x002110cc /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL 0x002110d0 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL 0x002110d4 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL 0x002110d8 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL 0x002110dc /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE 0x002110e0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID 0x002110e4 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1 0x002110e8 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX18_REC_INIT_TS 0x002110ec /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL 0x002110f0 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG 0x002110f4 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4 0x002110f8 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR 0x002110fc /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE 0x00211100 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX18_REC_TIMER 0x00211104 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX18_REC_STATE0 0x00211108 /* Record State Register */ -#define BCHP_XPT_RAVE_CX18_REC_STATE1 0x0021110c /* Record State Register */ -#define BCHP_XPT_RAVE_CX18_REC_STATE2 0x00211110 /* Record State Register */ -#define BCHP_XPT_RAVE_CX18_REC_STATE2b 0x00211114 /* Record State Register */ -#define BCHP_XPT_RAVE_CX18_REC_STATE3 0x00211118 /* Record State Register */ -#define BCHP_XPT_RAVE_CX18_REC_COUNT 0x0021111c /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL 0x00211120 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1 0x00211124 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_0 0x00211128 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_1 0x0021112c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_2 0x00211130 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_3 0x00211134 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR 0x00211138 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR 0x0021113c /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR 0x00211140 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR 0x00211144 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR 0x00211148 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR 0x0021114c /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL 0x00211150 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH 0x00211154 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS 0x00211158 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR 0x0021115c /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR 0x00211160 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR 0x00211164 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR 0x00211168 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR 0x0021116c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR 0x00211170 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL 0x00211174 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH 0x00211178 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG 0x0021117c /* Context 19 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB 0x00211180 /* Context 19 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD 0x00211184 /* Context 19 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF 0x00211188 /* Context 19 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH 0x0021118c /* Context 19 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1 0x00211190 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2 0x00211194 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3 0x00211198 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES 0x0021119c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL 0x002111a0 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL 0x002111a4 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL 0x002111a8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL 0x002111ac /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL 0x002111b0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL 0x002111b4 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL 0x002111b8 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL 0x002111bc /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL 0x002111c0 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL 0x002111c4 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE 0x002111c8 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID 0x002111cc /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1 0x002111d0 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX19_REC_INIT_TS 0x002111d4 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL 0x002111d8 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG 0x002111dc /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4 0x002111e0 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR 0x002111e4 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE 0x002111e8 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX19_REC_TIMER 0x002111ec /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX19_REC_STATE0 0x002111f0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX19_REC_STATE1 0x002111f4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX19_REC_STATE2 0x002111f8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX19_REC_STATE2b 0x002111fc /* Record State Register */ -#define BCHP_XPT_RAVE_CX19_REC_STATE3 0x00211200 /* Record State Register */ -#define BCHP_XPT_RAVE_CX19_REC_COUNT 0x00211204 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL 0x00211208 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1 0x0021120c /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_0 0x00211210 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_1 0x00211214 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_2 0x00211218 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_3 0x0021121c /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR 0x00211220 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR 0x00211224 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR 0x00211228 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR 0x0021122c /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR 0x00211230 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR 0x00211234 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL 0x00211238 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH 0x0021123c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS 0x00211240 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR 0x00211244 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR 0x00211248 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR 0x0021124c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR 0x00211250 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR 0x00211254 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR 0x00211258 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL 0x0021125c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH 0x00211260 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG 0x00211264 /* Context 20 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB 0x00211268 /* Context 20 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD 0x0021126c /* Context 20 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF 0x00211270 /* Context 20 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH 0x00211274 /* Context 20 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1 0x00211278 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2 0x0021127c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3 0x00211280 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES 0x00211284 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL 0x00211288 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL 0x0021128c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL 0x00211290 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL 0x00211294 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL 0x00211298 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL 0x0021129c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL 0x002112a0 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL 0x002112a4 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL 0x002112a8 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL 0x002112ac /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode 0x002112b0 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID 0x002112b4 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1 0x002112b8 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX20_REC_INIT_TS 0x002112bc /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL 0x002112c0 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG 0x002112c4 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4 0x002112c8 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR 0x002112cc /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE 0x002112d0 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX20_REC_TIMER 0x002112d4 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX20_REC_STATE0 0x002112d8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX20_REC_STATE1 0x002112dc /* Record State Register */ -#define BCHP_XPT_RAVE_CX20_REC_STATE2 0x002112e0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX20_REC_STATE2b 0x002112e4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX20_REC_STATE3 0x002112e8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX20_REC_COUNT 0x002112ec /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL 0x002112f0 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1 0x002112f4 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_0 0x002112f8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_1 0x002112fc /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_2 0x00211300 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_3 0x00211304 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR 0x00211308 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR 0x0021130c /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR 0x00211310 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR 0x00211314 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR 0x00211318 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR 0x0021131c /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL 0x00211320 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH 0x00211324 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS 0x00211328 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR 0x0021132c /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR 0x00211330 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR 0x00211334 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR 0x00211338 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR 0x0021133c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR 0x00211340 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL 0x00211344 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH 0x00211348 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG 0x0021134c /* Context 21 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB 0x00211350 /* Context 21 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD 0x00211354 /* Context 21 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF 0x00211358 /* Context 21 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH 0x0021135c /* Context 21 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1 0x00211360 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2 0x00211364 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3 0x00211368 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES 0x0021136c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL 0x00211370 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL 0x00211374 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL 0x00211378 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL 0x0021137c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL 0x00211380 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL 0x00211384 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL 0x00211388 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL 0x0021138c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL 0x00211390 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL 0x00211394 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE 0x00211398 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID 0x0021139c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1 0x002113a0 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX21_REC_INIT_TS 0x002113a4 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL 0x002113a8 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG 0x002113ac /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4 0x002113b0 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR 0x002113b4 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE 0x002113b8 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX21_REC_TIMER 0x002113bc /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX21_REC_STATE0 0x002113c0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX21_REC_STATE1 0x002113c4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX21_REC_STATE2 0x002113c8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX21_REC_STATE2b 0x002113cc /* Record State Register */ -#define BCHP_XPT_RAVE_CX21_REC_STATE3 0x002113d0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX21_REC_COUNT 0x002113d4 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL 0x002113d8 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1 0x002113dc /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_0 0x002113e0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_1 0x002113e4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_2 0x002113e8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_3 0x002113ec /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR 0x002113f0 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR 0x002113f4 /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR 0x002113f8 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR 0x002113fc /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR 0x00211400 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR 0x00211404 /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL 0x00211408 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH 0x0021140c /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS 0x00211410 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR 0x00211414 /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR 0x00211418 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR 0x0021141c /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR 0x00211420 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR 0x00211424 /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR 0x00211428 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL 0x0021142c /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH 0x00211430 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG 0x00211434 /* Context 22 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB 0x00211438 /* Context 22 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD 0x0021143c /* Context 22 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF 0x00211440 /* Context 22 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH 0x00211444 /* Context 22 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1 0x00211448 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2 0x0021144c /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3 0x00211450 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES 0x00211454 /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL 0x00211458 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL 0x0021145c /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL 0x00211460 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL 0x00211464 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL 0x00211468 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL 0x0021146c /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL 0x00211470 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL 0x00211474 /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL 0x00211478 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL 0x0021147c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode 0x00211480 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID 0x00211484 /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1 0x00211488 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX22_REC_INIT_TS 0x0021148c /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL 0x00211490 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG 0x00211494 /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4 0x00211498 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR 0x0021149c /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE 0x002114a0 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX22_REC_TIMER 0x002114a4 /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX22_REC_STATE0 0x002114a8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX22_REC_STATE1 0x002114ac /* Record State Register */ -#define BCHP_XPT_RAVE_CX22_REC_STATE2 0x002114b0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX22_REC_STATE2b 0x002114b4 /* Record State Register */ -#define BCHP_XPT_RAVE_CX22_REC_STATE3 0x002114b8 /* Record State Register */ -#define BCHP_XPT_RAVE_CX22_REC_COUNT 0x002114bc /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL 0x002114c0 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1 0x002114c4 /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_0 0x002114c8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_1 0x002114cc /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_2 0x002114d0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_3 0x002114d4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR 0x002114d8 /* Context CDB Write Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR 0x002114dc /* Context CDB Read Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR 0x002114e0 /* Context CDB Base Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR 0x002114e4 /* Context CDB End Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR 0x002114e8 /* Context CDB Valid Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR 0x002114ec /* Context CDB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL 0x002114f0 /* Context CDB Watermark Level */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH 0x002114f4 /* Context CDB Depth */ -#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS 0x002114f8 /* Context Thresholds */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR 0x002114fc /* Context ITB Write Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR 0x00211500 /* Context ITB Read Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR 0x00211504 /* Context ITB Base Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR 0x00211508 /* Context ITB End Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR 0x0021150c /* Context ITB Valid Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR 0x00211510 /* Context ITB Wraparound Pointer */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL 0x00211514 /* Context ITB Watermark Level */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH 0x00211518 /* Context ITB Depth */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG 0x0021151c /* Context 23 Miscellaneous Config */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB 0x00211520 /* Context 23 SCD map PIDS A and B */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD 0x00211524 /* Context 23 SCD map PIDS C and D */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF 0x00211528 /* Context 23 SCD map PIDS E and F */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH 0x0021152c /* Context 23 SCD map PIDS G and H */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1 0x00211530 /* Context Miscellaneous Config 1 Register */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2 0x00211534 /* Context Miscellaneous Config 2 Register */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3 0x00211538 /* Context Miscellaneous Config 3 Register */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES 0x0021153c /* Context Interrupt Enables */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL 0x00211540 /* Context Comparator 1 Control Register */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL 0x00211544 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL 0x00211548 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL 0x0021154c /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL 0x00211550 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL 0x00211554 /* Context Comparator 2 Control Register */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL 0x00211558 /* Context Comparator 2 32-bit compare value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL 0x0021155c /* Context Comparator 2 32-bit mask value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL 0x00211560 /* Context Comparator 1 32-bit compare value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL 0x00211564 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE 0x00211568 /* Context Comparator 1 32-bit mask value */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID 0x0021156c /* Context PID and Stream ID Filter Value */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1 0x00211570 /* Record Control Register 1 */ -#define BCHP_XPT_RAVE_CX23_REC_INIT_TS 0x00211574 /* Record Initial Timestamp Value Register */ -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL 0x00211578 /* Record Timestamp Control Register */ -#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG 0x0021157c /* Record Time Configuration Register */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4 0x00211580 /* Context Miscellaneous Config 4 Register */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR 0x00211584 /* Picture Counter register */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE 0x00211588 /* Picture Counter Mode Register */ -#define BCHP_XPT_RAVE_CX23_REC_TIMER 0x0021158c /* Record Timer Register */ -#define BCHP_XPT_RAVE_CX23_REC_STATE0 0x00211590 /* Record State Register */ -#define BCHP_XPT_RAVE_CX23_REC_STATE1 0x00211594 /* Record State Register */ -#define BCHP_XPT_RAVE_CX23_REC_STATE2 0x00211598 /* Record State Register */ -#define BCHP_XPT_RAVE_CX23_REC_STATE2b 0x0021159c /* Record State Register */ -#define BCHP_XPT_RAVE_CX23_REC_STATE3 0x002115a0 /* Record State Register */ -#define BCHP_XPT_RAVE_CX23_REC_COUNT 0x002115a4 /* Record Packet Count Register */ -#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL 0x002115a8 /* Picture Counter Increment/Decrement/Reset Control Register */ -#define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1 0x002115ac /* Reserved Record State Register */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_0 0x002115b0 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_1 0x002115b4 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_2 0x002115b8 /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_3 0x002115bc /* Reserved Rave Register for future use */ -#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG 0x002115c0 /* SCD 0 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0 0x002115c4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1 0x002115c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2 0x002115cc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3 0x002115d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4 0x002115d4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5 0x002115d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6 0x002115dc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7 0x002115e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8 0x002115e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9 0x002115e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10 0x002115ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11 0x002115f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0 0x002115f4 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0 0x002115f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1 0x002115fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2 0x00211600 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3 0x00211604 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT 0x00211608 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0 0x0021160c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1 0x00211610 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE0 0x00211614 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE1 0x00211618 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE2 0x0021161c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE3 0x00211620 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE4 0x00211624 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE5 0x00211628 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0 0x0021162c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1 0x00211630 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2 0x00211634 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3 0x00211638 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG 0x0021163c /* SCD 1 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0 0x00211640 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1 0x00211644 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2 0x00211648 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3 0x0021164c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4 0x00211650 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5 0x00211654 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6 0x00211658 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7 0x0021165c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8 0x00211660 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9 0x00211664 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10 0x00211668 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11 0x0021166c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0 0x00211670 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0 0x00211674 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1 0x00211678 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2 0x0021167c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3 0x00211680 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT 0x00211684 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0 0x00211688 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1 0x0021168c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE0 0x00211690 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE1 0x00211694 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE2 0x00211698 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE3 0x0021169c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE4 0x002116a0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE5 0x002116a4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0 0x002116a8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1 0x002116ac /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2 0x002116b0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3 0x002116b4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG 0x002116b8 /* SCD 2 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0 0x002116bc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1 0x002116c0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2 0x002116c4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3 0x002116c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4 0x002116cc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5 0x002116d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6 0x002116d4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7 0x002116d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8 0x002116dc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9 0x002116e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10 0x002116e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11 0x002116e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0 0x002116ec /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0 0x002116f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1 0x002116f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2 0x002116f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3 0x002116fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT 0x00211700 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0 0x00211704 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1 0x00211708 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE0 0x0021170c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE1 0x00211710 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE2 0x00211714 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE3 0x00211718 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE4 0x0021171c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE5 0x00211720 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0 0x00211724 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1 0x00211728 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2 0x0021172c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3 0x00211730 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG 0x00211734 /* SCD 3 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0 0x00211738 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1 0x0021173c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2 0x00211740 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3 0x00211744 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4 0x00211748 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5 0x0021174c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6 0x00211750 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7 0x00211754 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8 0x00211758 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9 0x0021175c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10 0x00211760 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11 0x00211764 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0 0x00211768 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0 0x0021176c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1 0x00211770 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2 0x00211774 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3 0x00211778 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT 0x0021177c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0 0x00211780 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1 0x00211784 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE0 0x00211788 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE1 0x0021178c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE2 0x00211790 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE3 0x00211794 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE4 0x00211798 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE5 0x0021179c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0 0x002117a0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1 0x002117a4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2 0x002117a8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3 0x002117ac /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG 0x002117b0 /* SCD 4 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0 0x002117b4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1 0x002117b8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2 0x002117bc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3 0x002117c0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4 0x002117c4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5 0x002117c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6 0x002117cc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7 0x002117d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8 0x002117d4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9 0x002117d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10 0x002117dc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11 0x002117e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0 0x002117e4 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0 0x002117e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1 0x002117ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2 0x002117f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3 0x002117f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT 0x002117f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0 0x002117fc /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1 0x00211800 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE0 0x00211804 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE1 0x00211808 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE2 0x0021180c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE3 0x00211810 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE4 0x00211814 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE5 0x00211818 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0 0x0021181c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1 0x00211820 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2 0x00211824 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3 0x00211828 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG 0x0021182c /* SCD 5 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0 0x00211830 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1 0x00211834 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2 0x00211838 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3 0x0021183c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4 0x00211840 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5 0x00211844 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6 0x00211848 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7 0x0021184c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8 0x00211850 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9 0x00211854 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10 0x00211858 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11 0x0021185c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0 0x00211860 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0 0x00211864 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1 0x00211868 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2 0x0021186c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3 0x00211870 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT 0x00211874 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0 0x00211878 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1 0x0021187c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE0 0x00211880 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE1 0x00211884 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE2 0x00211888 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE3 0x0021188c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE4 0x00211890 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE5 0x00211894 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0 0x00211898 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1 0x0021189c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2 0x002118a0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3 0x002118a4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG 0x002118a8 /* SCD 6 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0 0x002118ac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1 0x002118b0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2 0x002118b4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3 0x002118b8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4 0x002118bc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5 0x002118c0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6 0x002118c4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7 0x002118c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8 0x002118cc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9 0x002118d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10 0x002118d4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11 0x002118d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0 0x002118dc /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0 0x002118e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1 0x002118e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2 0x002118e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3 0x002118ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT 0x002118f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0 0x002118f4 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1 0x002118f8 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE0 0x002118fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE1 0x00211900 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE2 0x00211904 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE3 0x00211908 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE4 0x0021190c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE5 0x00211910 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0 0x00211914 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1 0x00211918 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2 0x0021191c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3 0x00211920 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG 0x00211924 /* SCD 7 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0 0x00211928 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1 0x0021192c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2 0x00211930 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3 0x00211934 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4 0x00211938 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5 0x0021193c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6 0x00211940 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7 0x00211944 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8 0x00211948 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9 0x0021194c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10 0x00211950 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11 0x00211954 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0 0x00211958 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0 0x0021195c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1 0x00211960 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2 0x00211964 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3 0x00211968 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT 0x0021196c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0 0x00211970 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1 0x00211974 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE0 0x00211978 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE1 0x0021197c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE2 0x00211980 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE3 0x00211984 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE4 0x00211988 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE5 0x0021198c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0 0x00211990 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1 0x00211994 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2 0x00211998 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3 0x0021199c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG 0x002119a0 /* SCD 8 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0 0x002119a4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1 0x002119a8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2 0x002119ac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3 0x002119b0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4 0x002119b4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5 0x002119b8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6 0x002119bc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7 0x002119c0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8 0x002119c4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9 0x002119c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10 0x002119cc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11 0x002119d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0 0x002119d4 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0 0x002119d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1 0x002119dc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2 0x002119e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3 0x002119e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT 0x002119e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0 0x002119ec /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1 0x002119f0 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE0 0x002119f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE1 0x002119f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE2 0x002119fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE3 0x00211a00 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE4 0x00211a04 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE5 0x00211a08 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0 0x00211a0c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1 0x00211a10 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2 0x00211a14 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3 0x00211a18 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG 0x00211a1c /* SCD 9 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0 0x00211a20 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1 0x00211a24 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2 0x00211a28 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3 0x00211a2c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4 0x00211a30 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5 0x00211a34 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6 0x00211a38 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7 0x00211a3c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8 0x00211a40 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9 0x00211a44 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10 0x00211a48 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11 0x00211a4c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0 0x00211a50 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0 0x00211a54 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1 0x00211a58 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2 0x00211a5c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3 0x00211a60 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT 0x00211a64 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0 0x00211a68 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1 0x00211a6c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE0 0x00211a70 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE1 0x00211a74 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE2 0x00211a78 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE3 0x00211a7c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE4 0x00211a80 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE5 0x00211a84 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0 0x00211a88 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1 0x00211a8c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2 0x00211a90 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3 0x00211a94 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG 0x00211a98 /* SCD 10 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0 0x00211a9c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1 0x00211aa0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2 0x00211aa4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3 0x00211aa8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4 0x00211aac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5 0x00211ab0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6 0x00211ab4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7 0x00211ab8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8 0x00211abc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9 0x00211ac0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10 0x00211ac4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11 0x00211ac8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0 0x00211acc /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0 0x00211ad0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1 0x00211ad4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2 0x00211ad8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3 0x00211adc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT 0x00211ae0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0 0x00211ae4 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1 0x00211ae8 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE0 0x00211aec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE1 0x00211af0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE2 0x00211af4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE3 0x00211af8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE4 0x00211afc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE5 0x00211b00 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0 0x00211b04 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1 0x00211b08 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2 0x00211b0c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3 0x00211b10 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG 0x00211b14 /* SCD 11 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0 0x00211b18 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1 0x00211b1c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2 0x00211b20 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3 0x00211b24 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4 0x00211b28 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5 0x00211b2c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6 0x00211b30 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7 0x00211b34 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8 0x00211b38 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9 0x00211b3c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10 0x00211b40 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11 0x00211b44 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0 0x00211b48 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0 0x00211b4c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1 0x00211b50 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2 0x00211b54 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3 0x00211b58 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT 0x00211b5c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0 0x00211b60 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1 0x00211b64 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE0 0x00211b68 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE1 0x00211b6c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE2 0x00211b70 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE3 0x00211b74 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE4 0x00211b78 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE5 0x00211b7c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0 0x00211b80 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1 0x00211b84 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2 0x00211b88 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3 0x00211b8c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG 0x00211b90 /* SCD 12 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0 0x00211b94 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1 0x00211b98 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2 0x00211b9c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3 0x00211ba0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4 0x00211ba4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5 0x00211ba8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6 0x00211bac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7 0x00211bb0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8 0x00211bb4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9 0x00211bb8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10 0x00211bbc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11 0x00211bc0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0 0x00211bc4 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0 0x00211bc8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1 0x00211bcc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2 0x00211bd0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3 0x00211bd4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT 0x00211bd8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0 0x00211bdc /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1 0x00211be0 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE0 0x00211be4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE1 0x00211be8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE2 0x00211bec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE3 0x00211bf0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE4 0x00211bf4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE5 0x00211bf8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0 0x00211bfc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1 0x00211c00 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2 0x00211c04 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3 0x00211c08 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG 0x00211c0c /* SCD 13 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0 0x00211c10 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1 0x00211c14 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2 0x00211c18 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3 0x00211c1c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4 0x00211c20 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5 0x00211c24 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6 0x00211c28 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7 0x00211c2c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8 0x00211c30 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9 0x00211c34 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10 0x00211c38 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11 0x00211c3c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0 0x00211c40 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0 0x00211c44 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1 0x00211c48 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2 0x00211c4c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3 0x00211c50 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT 0x00211c54 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0 0x00211c58 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1 0x00211c5c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE0 0x00211c60 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE1 0x00211c64 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE2 0x00211c68 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE3 0x00211c6c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE4 0x00211c70 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE5 0x00211c74 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0 0x00211c78 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1 0x00211c7c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2 0x00211c80 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3 0x00211c84 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG 0x00211c88 /* SCD 14 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0 0x00211c8c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1 0x00211c90 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2 0x00211c94 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3 0x00211c98 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4 0x00211c9c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5 0x00211ca0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6 0x00211ca4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7 0x00211ca8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8 0x00211cac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9 0x00211cb0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10 0x00211cb4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11 0x00211cb8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0 0x00211cbc /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0 0x00211cc0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1 0x00211cc4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2 0x00211cc8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3 0x00211ccc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT 0x00211cd0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0 0x00211cd4 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1 0x00211cd8 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE0 0x00211cdc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE1 0x00211ce0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE2 0x00211ce4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE3 0x00211ce8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE4 0x00211cec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE5 0x00211cf0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0 0x00211cf4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1 0x00211cf8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2 0x00211cfc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3 0x00211d00 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG 0x00211d04 /* SCD 15 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0 0x00211d08 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1 0x00211d0c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2 0x00211d10 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3 0x00211d14 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4 0x00211d18 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5 0x00211d1c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6 0x00211d20 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7 0x00211d24 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8 0x00211d28 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9 0x00211d2c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10 0x00211d30 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11 0x00211d34 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0 0x00211d38 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0 0x00211d3c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1 0x00211d40 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2 0x00211d44 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3 0x00211d48 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT 0x00211d4c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0 0x00211d50 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1 0x00211d54 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE0 0x00211d58 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE1 0x00211d5c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE2 0x00211d60 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE3 0x00211d64 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE4 0x00211d68 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE5 0x00211d6c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0 0x00211d70 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1 0x00211d74 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2 0x00211d78 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3 0x00211d7c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG 0x00211d80 /* SCD 16 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0 0x00211d84 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1 0x00211d88 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2 0x00211d8c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3 0x00211d90 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4 0x00211d94 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5 0x00211d98 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6 0x00211d9c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7 0x00211da0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8 0x00211da4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9 0x00211da8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10 0x00211dac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11 0x00211db0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0 0x00211db4 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0 0x00211db8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1 0x00211dbc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2 0x00211dc0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3 0x00211dc4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT 0x00211dc8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0 0x00211dcc /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1 0x00211dd0 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE0 0x00211dd4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE1 0x00211dd8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE2 0x00211ddc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE3 0x00211de0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE4 0x00211de4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE5 0x00211de8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0 0x00211dec /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1 0x00211df0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2 0x00211df4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3 0x00211df8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG 0x00211dfc /* SCD 17 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0 0x00211e00 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1 0x00211e04 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2 0x00211e08 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3 0x00211e0c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4 0x00211e10 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5 0x00211e14 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6 0x00211e18 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7 0x00211e1c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8 0x00211e20 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9 0x00211e24 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10 0x00211e28 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11 0x00211e2c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0 0x00211e30 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0 0x00211e34 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1 0x00211e38 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2 0x00211e3c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3 0x00211e40 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT 0x00211e44 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0 0x00211e48 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1 0x00211e4c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE0 0x00211e50 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE1 0x00211e54 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE2 0x00211e58 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE3 0x00211e5c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE4 0x00211e60 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE5 0x00211e64 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0 0x00211e68 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1 0x00211e6c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2 0x00211e70 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3 0x00211e74 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG 0x00211e78 /* SCD 18 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0 0x00211e7c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1 0x00211e80 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2 0x00211e84 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3 0x00211e88 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4 0x00211e8c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5 0x00211e90 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6 0x00211e94 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7 0x00211e98 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8 0x00211e9c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9 0x00211ea0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10 0x00211ea4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11 0x00211ea8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0 0x00211eac /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0 0x00211eb0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1 0x00211eb4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2 0x00211eb8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3 0x00211ebc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT 0x00211ec0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0 0x00211ec4 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1 0x00211ec8 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE0 0x00211ecc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE1 0x00211ed0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE2 0x00211ed4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE3 0x00211ed8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE4 0x00211edc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE5 0x00211ee0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0 0x00211ee4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1 0x00211ee8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2 0x00211eec /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3 0x00211ef0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG 0x00211ef4 /* SCD 19 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0 0x00211ef8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1 0x00211efc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2 0x00211f00 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3 0x00211f04 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4 0x00211f08 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5 0x00211f0c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6 0x00211f10 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7 0x00211f14 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8 0x00211f18 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9 0x00211f1c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10 0x00211f20 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11 0x00211f24 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0 0x00211f28 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0 0x00211f2c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1 0x00211f30 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2 0x00211f34 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3 0x00211f38 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT 0x00211f3c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0 0x00211f40 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1 0x00211f44 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE0 0x00211f48 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE1 0x00211f4c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE2 0x00211f50 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE3 0x00211f54 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE4 0x00211f58 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE5 0x00211f5c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0 0x00211f60 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1 0x00211f64 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2 0x00211f68 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3 0x00211f6c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG 0x00211f70 /* SCD 20 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0 0x00211f74 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1 0x00211f78 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2 0x00211f7c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3 0x00211f80 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4 0x00211f84 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5 0x00211f88 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6 0x00211f8c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7 0x00211f90 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8 0x00211f94 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9 0x00211f98 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10 0x00211f9c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11 0x00211fa0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0 0x00211fa4 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0 0x00211fa8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1 0x00211fac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2 0x00211fb0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3 0x00211fb4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT 0x00211fb8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0 0x00211fbc /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1 0x00211fc0 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE0 0x00211fc4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE1 0x00211fc8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE2 0x00211fcc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE3 0x00211fd0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE4 0x00211fd4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE5 0x00211fd8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0 0x00211fdc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1 0x00211fe0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2 0x00211fe4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3 0x00211fe8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG 0x00211fec /* SCD 21 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0 0x00211ff0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1 0x00211ff4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2 0x00211ff8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3 0x00211ffc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4 0x00212000 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5 0x00212004 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6 0x00212008 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7 0x0021200c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8 0x00212010 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9 0x00212014 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10 0x00212018 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11 0x0021201c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0 0x00212020 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0 0x00212024 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1 0x00212028 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2 0x0021202c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3 0x00212030 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT 0x00212034 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0 0x00212038 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1 0x0021203c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE0 0x00212040 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE1 0x00212044 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE2 0x00212048 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE3 0x0021204c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE4 0x00212050 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE5 0x00212054 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0 0x00212058 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1 0x0021205c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2 0x00212060 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3 0x00212064 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG 0x00212068 /* SCD 22 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0 0x0021206c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1 0x00212070 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2 0x00212074 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3 0x00212078 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4 0x0021207c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5 0x00212080 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6 0x00212084 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7 0x00212088 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8 0x0021208c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9 0x00212090 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10 0x00212094 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11 0x00212098 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0 0x0021209c /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0 0x002120a0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1 0x002120a4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2 0x002120a8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3 0x002120ac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT 0x002120b0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0 0x002120b4 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1 0x002120b8 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE0 0x002120bc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE1 0x002120c0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE2 0x002120c4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE3 0x002120c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE4 0x002120cc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE5 0x002120d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0 0x002120d4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1 0x002120d8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2 0x002120dc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3 0x002120e0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG 0x002120e4 /* SCD 23 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0 0x002120e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1 0x002120ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2 0x002120f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3 0x002120f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4 0x002120f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5 0x002120fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6 0x00212100 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7 0x00212104 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8 0x00212108 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9 0x0021210c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10 0x00212110 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11 0x00212114 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0 0x00212118 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0 0x0021211c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1 0x00212120 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2 0x00212124 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3 0x00212128 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT 0x0021212c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0 0x00212130 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1 0x00212134 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE0 0x00212138 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE1 0x0021213c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE2 0x00212140 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE3 0x00212144 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE4 0x00212148 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE5 0x0021214c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0 0x00212150 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1 0x00212154 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2 0x00212158 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3 0x0021215c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG 0x00212160 /* SCD 24 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0 0x00212164 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1 0x00212168 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2 0x0021216c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3 0x00212170 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4 0x00212174 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5 0x00212178 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6 0x0021217c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7 0x00212180 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8 0x00212184 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9 0x00212188 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10 0x0021218c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11 0x00212190 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0 0x00212194 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0 0x00212198 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1 0x0021219c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2 0x002121a0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3 0x002121a4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT 0x002121a8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0 0x002121ac /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1 0x002121b0 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE0 0x002121b4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE1 0x002121b8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE2 0x002121bc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE3 0x002121c0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE4 0x002121c4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE5 0x002121c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0 0x002121cc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1 0x002121d0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2 0x002121d4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3 0x002121d8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG 0x002121dc /* SCD 25 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0 0x002121e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1 0x002121e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2 0x002121e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3 0x002121ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4 0x002121f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5 0x002121f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6 0x002121f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7 0x002121fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8 0x00212200 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9 0x00212204 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10 0x00212208 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11 0x0021220c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0 0x00212210 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0 0x00212214 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1 0x00212218 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2 0x0021221c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3 0x00212220 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT 0x00212224 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0 0x00212228 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1 0x0021222c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE0 0x00212230 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE1 0x00212234 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE2 0x00212238 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE3 0x0021223c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE4 0x00212240 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE5 0x00212244 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0 0x00212248 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1 0x0021224c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2 0x00212250 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3 0x00212254 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG 0x00212258 /* SCD 26 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0 0x0021225c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1 0x00212260 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2 0x00212264 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3 0x00212268 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4 0x0021226c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5 0x00212270 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6 0x00212274 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7 0x00212278 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8 0x0021227c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9 0x00212280 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10 0x00212284 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11 0x00212288 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0 0x0021228c /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0 0x00212290 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1 0x00212294 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2 0x00212298 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3 0x0021229c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT 0x002122a0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0 0x002122a4 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1 0x002122a8 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE0 0x002122ac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE1 0x002122b0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE2 0x002122b4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE3 0x002122b8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE4 0x002122bc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE5 0x002122c0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0 0x002122c4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1 0x002122c8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2 0x002122cc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3 0x002122d0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG 0x002122d4 /* SCD 27 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0 0x002122d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1 0x002122dc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2 0x002122e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3 0x002122e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4 0x002122e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5 0x002122ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6 0x002122f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7 0x002122f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8 0x002122f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9 0x002122fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10 0x00212300 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11 0x00212304 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0 0x00212308 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0 0x0021230c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1 0x00212310 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2 0x00212314 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3 0x00212318 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT 0x0021231c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0 0x00212320 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1 0x00212324 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE0 0x00212328 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE1 0x0021232c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE2 0x00212330 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE3 0x00212334 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE4 0x00212338 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE5 0x0021233c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0 0x00212340 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1 0x00212344 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2 0x00212348 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3 0x0021234c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG 0x00212350 /* SCD 28 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0 0x00212354 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1 0x00212358 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2 0x0021235c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3 0x00212360 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4 0x00212364 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5 0x00212368 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6 0x0021236c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7 0x00212370 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8 0x00212374 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9 0x00212378 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10 0x0021237c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11 0x00212380 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0 0x00212384 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0 0x00212388 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1 0x0021238c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2 0x00212390 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3 0x00212394 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT 0x00212398 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0 0x0021239c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1 0x002123a0 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE0 0x002123a4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE1 0x002123a8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE2 0x002123ac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE3 0x002123b0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE4 0x002123b4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE5 0x002123b8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0 0x002123bc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1 0x002123c0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2 0x002123c4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3 0x002123c8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG 0x002123cc /* SCD 29 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0 0x002123d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1 0x002123d4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2 0x002123d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3 0x002123dc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4 0x002123e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5 0x002123e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6 0x002123e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7 0x002123ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8 0x002123f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9 0x002123f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10 0x002123f8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11 0x002123fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0 0x00212400 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0 0x00212404 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1 0x00212408 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2 0x0021240c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3 0x00212410 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT 0x00212414 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0 0x00212418 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1 0x0021241c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE0 0x00212420 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE1 0x00212424 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE2 0x00212428 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE3 0x0021242c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE4 0x00212430 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE5 0x00212434 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0 0x00212438 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1 0x0021243c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2 0x00212440 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3 0x00212444 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG 0x00212448 /* SCD 30 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0 0x0021244c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1 0x00212450 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2 0x00212454 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3 0x00212458 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4 0x0021245c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5 0x00212460 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6 0x00212464 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7 0x00212468 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8 0x0021246c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9 0x00212470 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10 0x00212474 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11 0x00212478 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0 0x0021247c /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0 0x00212480 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1 0x00212484 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2 0x00212488 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3 0x0021248c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT 0x00212490 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0 0x00212494 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1 0x00212498 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE0 0x0021249c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE1 0x002124a0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE2 0x002124a4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE3 0x002124a8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE4 0x002124ac /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE5 0x002124b0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0 0x002124b4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1 0x002124b8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2 0x002124bc /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3 0x002124c0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG 0x002124c4 /* SCD 31 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0 0x002124c8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1 0x002124cc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2 0x002124d0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3 0x002124d4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4 0x002124d8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5 0x002124dc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6 0x002124e0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7 0x002124e4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8 0x002124e8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9 0x002124ec /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10 0x002124f0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11 0x002124f4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0 0x002124f8 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0 0x002124fc /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1 0x00212500 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2 0x00212504 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3 0x00212508 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT 0x0021250c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0 0x00212510 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1 0x00212514 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE0 0x00212518 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE1 0x0021251c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE2 0x00212520 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE3 0x00212524 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE4 0x00212528 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE5 0x0021252c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0 0x00212530 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1 0x00212534 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2 0x00212538 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3 0x0021253c /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG 0x00212540 /* SCD 32 Misc Config Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0 0x00212544 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1 0x00212548 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2 0x0021254c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3 0x00212550 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4 0x00212554 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5 0x00212558 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6 0x0021255c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7 0x00212560 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8 0x00212564 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9 0x00212568 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10 0x0021256c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11 0x00212570 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0 0x00212574 /* Reserved Comparator State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0 0x00212578 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1 0x0021257c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2 0x00212580 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3 0x00212584 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT 0x00212588 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0 0x0021258c /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1 0x00212590 /* Reserved PES State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE0 0x00212594 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE1 0x00212598 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE2 0x0021259c /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE3 0x002125a0 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE4 0x002125a4 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE5 0x002125a8 /* SCD State Register */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0 0x002125ac /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1 0x002125b0 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2 0x002125b4 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3 0x002125b8 /* SCD Reserved State Register */ -#define BCHP_XPT_RAVE_XPU_CONFIG 0x00213000 /* XPU TEST ENABLE REGISTER */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL 0x00213004 /* XPU TEST CONTROL REGISTER */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO 0x00213008 /* XPU TEST CONTROL EXT IO */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0 0x0021300c /* XPU TEST OBSERVE REGISTER */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1 0x00213010 /* XPU TEST OBSERVE REGISTER */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO 0x00213014 /* XPU TEST OBSERVE EXT IO REGISTER */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL 0x00213018 /* RAVE Diagnostics Control Register */ -#define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE 0x0021301c /* Stop Packet Count Value */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL 0x00213020 /* AVS SCV Filter mode */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3 0x00213024 /* AVS SCV Filter value 0 to 3 */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7 0x00213028 /* AVS SCV Filter value 4 to 7 */ -#define BCHP_XPT_RAVE_AV_STATUS 0x00213040 /* RAVE Status */ -#define BCHP_XPT_RAVE_PACKET_COUNT 0x00213044 /* RAVE input packet counter */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_A 0x00213048 /* Pkt and HWA data buffer A base addresses */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_B 0x0021304c /* Pkt and HWA data buffer B base addresses */ -#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE 0x00213050 /* Watchdog Timer Timeout Value */ -#define BCHP_XPT_RAVE_MISC_CONTROL 0x00213058 /* Miscellaneous Control */ -#define BCHP_XPT_RAVE_BASE_ADDRESSES 0x0021305c /* Record and SCD Base Addresses */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS 0x00213064 /* Context Hold Status and Clear */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS 0x00213060 /* Band Hold Status and Clear */ -#define BCHP_XPT_RAVE_FW_WATERMARK 0x00213068 /* Firmware throughput watermark */ -#define BCHP_XPT_RAVE_HW_WATCHDOG 0x0021306c /* Hardware Watchdog Counter */ -#define BCHP_XPT_RAVE_MISC_CONTROL2 0x00213070 /* Miscellaneous Control 2 */ -#define BCHP_XPT_RAVE_RC0_SP_CONTROL 0x00213080 /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC1_SP_CONTROL 0x00213084 /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC2_SP_CONTROL 0x00213088 /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC3_SP_CONTROL 0x0021308c /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC4_SP_CONTROL 0x00213090 /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC5_SP_CONTROL 0x00213094 /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC6_SP_CONTROL 0x00213098 /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC7_SP_CONTROL 0x0021309c /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_RC8_SP_CONTROL 0x002130a0 /* Seamless Pause Control */ -#define BCHP_XPT_RAVE_AV_STATUS2 0x002130a4 /* RAVE Status */ -#define BCHP_XPT_RAVE_TM_DMEM 0x002130b0 /* TM Control */ -#define BCHP_XPT_RAVE_TM_IMEM 0x002130b4 /* TM Control */ -#define BCHP_XPT_RAVE_TM_POINTER_RAM 0x002130b8 /* TM Control */ -#define BCHP_XPT_RAVE_TM_MUX_BUFFER 0x002130bc /* TM Control */ -#define BCHP_XPT_RAVE_TM_CX_TABLE 0x002130c0 /* TM Control */ -#define BCHP_XPT_RAVE_TM_CX_TABLE_HI 0x002130c4 /* TM Control */ -#define BCHP_XPT_RAVE_TM_SMEM 0x002130c8 /* TM Control */ -#define BCHP_XPT_RAVE_INT_CX0 0x00213100 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX1 0x00213104 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX2 0x00213108 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX3 0x0021310c /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX4 0x00213110 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX5 0x00213114 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX6 0x00213118 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX7 0x0021311c /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX8 0x00213120 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX9 0x00213124 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX10 0x00213128 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX11 0x0021312c /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX12 0x00213130 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX13 0x00213134 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX14 0x00213138 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX15 0x0021313c /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX16 0x00213140 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX17 0x00213144 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX18 0x00213148 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX19 0x0021314c /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX20 0x00213150 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX21 0x00213154 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX22 0x00213158 /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_CX23 0x0021315c /* Context Interrupts */ -#define BCHP_XPT_RAVE_INT_MISC 0x00213160 /* Miscellaneous Interrupts */ -#define BCHP_XPT_RAVE_EMM_TID_MODE 0x00216000 /* TPIT EMM_TID_MODE Register (NDS only) */ -#define BCHP_XPT_RAVE_EMM_DATA_ID_1 0x00216004 /* TPIT EMM_DATA_ID_1 Register (NDS only) */ -#define BCHP_XPT_RAVE_EMM_DATA_ID_2 0x00216008 /* TPIT EMM_DATA_ID_2 Register (NDS only) */ -#define BCHP_XPT_RAVE_EMM_DATA_ID_3 0x0021600c /* TPIT EMM_DATA_ID_3 Register (NDS only) */ -#define BCHP_XPT_RAVE_EMM_MASK_ID_1 0x00216010 /* TPIT EMM_MASK_ID_1 Register (NDS only) */ -#define BCHP_XPT_RAVE_EMM_MASK_ID_2 0x00216014 /* TPIT EMM_MASK_ID_2 Register (NDS only) */ -#define BCHP_XPT_RAVE_EMM_MASK_ID_3 0x00216018 /* TPIT EMM_MASK_ID_3 Register (NDS only) */ -#define BCHP_XPT_RAVE_TPIT_TIME_TICK 0x00216020 /* TPIT Time Tick Register */ -#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT 0x00216024 /* TPIT Time Packet Timeout Register */ -#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT 0x00216028 /* TPIT Time Event Timeout Register */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1 0x0021a300 /* TPIT 0 Control Register 1 */ -#define BCHP_XPT_RAVE_TPIT0_COR1 0x0021a304 /* TPIT 0 Corrupt Register */ -#define BCHP_XPT_RAVE_TPIT0_TID 0x0021a308 /* TPIT TID Register */ -#define BCHP_XPT_RAVE_TPIT0_TID2 0x0021a30c /* TPIT TID Register 2 */ -#define BCHP_XPT_RAVE_TPIT0_STATE0 0x0021a310 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE1 0x0021a314 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE2 0x0021a318 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE2a 0x0021a31c /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE2b 0x0021a320 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE2c 0x0021a324 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE2d 0x0021a328 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE3 0x0021a32c /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE4 0x0021a330 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE5 0x0021a334 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE6 0x0021a338 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE7 0x0021a33c /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE8 0x0021a340 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT0_STATE9 0x0021a344 /* TPIT 0 State Register */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1 0x0021a348 /* TPIT 1 Control Register 1 */ -#define BCHP_XPT_RAVE_TPIT1_COR1 0x0021a34c /* TPIT 1 Corrupt Register */ -#define BCHP_XPT_RAVE_TPIT1_TID 0x0021a350 /* TPIT TID Register */ -#define BCHP_XPT_RAVE_TPIT1_TID2 0x0021a354 /* TPIT TID Register 2 */ -#define BCHP_XPT_RAVE_TPIT1_STATE0 0x0021a358 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE1 0x0021a35c /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE2 0x0021a360 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE2a 0x0021a364 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE2b 0x0021a368 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE2c 0x0021a36c /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE2d 0x0021a370 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE3 0x0021a374 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE4 0x0021a378 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE5 0x0021a37c /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE6 0x0021a380 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE7 0x0021a384 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE8 0x0021a388 /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT1_STATE9 0x0021a38c /* TPIT 1 State Register */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1 0x0021a390 /* TPIT 2 Control Register 1 */ -#define BCHP_XPT_RAVE_TPIT2_COR1 0x0021a394 /* TPIT 2 Corrupt Register */ -#define BCHP_XPT_RAVE_TPIT2_TID 0x0021a398 /* TPIT TID Register */ -#define BCHP_XPT_RAVE_TPIT2_TID2 0x0021a39c /* TPIT TID Register 2 */ -#define BCHP_XPT_RAVE_TPIT2_STATE0 0x0021a3a0 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE1 0x0021a3a4 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE2 0x0021a3a8 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE2a 0x0021a3ac /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE2b 0x0021a3b0 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE2c 0x0021a3b4 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE2d 0x0021a3b8 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE3 0x0021a3bc /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE4 0x0021a3c0 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE5 0x0021a3c4 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE6 0x0021a3c8 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE7 0x0021a3cc /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE8 0x0021a3d0 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT2_STATE9 0x0021a3d4 /* TPIT 2 State Register */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1 0x0021a3d8 /* TPIT 3 Control Register 1 */ -#define BCHP_XPT_RAVE_TPIT3_COR1 0x0021a3dc /* TPIT 3 Corrupt Register */ -#define BCHP_XPT_RAVE_TPIT3_TID 0x0021a3e0 /* TPIT TID Register */ -#define BCHP_XPT_RAVE_TPIT3_TID2 0x0021a3e4 /* TPIT TID Register 2 */ -#define BCHP_XPT_RAVE_TPIT3_STATE0 0x0021a3e8 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE1 0x0021a3ec /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE2 0x0021a3f0 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE2a 0x0021a3f4 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE2b 0x0021a3f8 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE2c 0x0021a3fc /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE2d 0x0021a400 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE3 0x0021a404 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE4 0x0021a408 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE5 0x0021a40c /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE6 0x0021a410 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE7 0x0021a414 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE8 0x0021a418 /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT3_STATE9 0x0021a41c /* TPIT 3 State Register */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1 0x0021a420 /* TPIT 4 Control Register 1 */ -#define BCHP_XPT_RAVE_TPIT4_COR1 0x0021a424 /* TPIT 4 Corrupt Register */ -#define BCHP_XPT_RAVE_TPIT4_TID 0x0021a428 /* TPIT TID Register */ -#define BCHP_XPT_RAVE_TPIT4_TID2 0x0021a42c /* TPIT TID Register 2 */ -#define BCHP_XPT_RAVE_TPIT4_STATE0 0x0021a430 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE1 0x0021a434 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE2 0x0021a438 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE2a 0x0021a43c /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE2b 0x0021a440 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE2c 0x0021a444 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE2d 0x0021a448 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE3 0x0021a44c /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE4 0x0021a450 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE5 0x0021a454 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE6 0x0021a458 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE7 0x0021a45c /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE8 0x0021a460 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT4_STATE9 0x0021a464 /* TPIT 4 State Register */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1 0x0021a468 /* TPIT 5 Control Register 1 */ -#define BCHP_XPT_RAVE_TPIT5_COR1 0x0021a46c /* TPIT 5 Corrupt Register */ -#define BCHP_XPT_RAVE_TPIT5_TID 0x0021a470 /* TPIT TID Register */ -#define BCHP_XPT_RAVE_TPIT5_TID2 0x0021a474 /* TPIT TID Register 2 */ -#define BCHP_XPT_RAVE_TPIT5_STATE0 0x0021a478 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE1 0x0021a47c /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE2 0x0021a480 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE2a 0x0021a484 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE2b 0x0021a488 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE2c 0x0021a48c /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE2d 0x0021a490 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE3 0x0021a494 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE4 0x0021a498 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE5 0x0021a49c /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE6 0x0021a4a0 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE7 0x0021a4a4 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE8 0x0021a4a8 /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT5_STATE9 0x0021a4ac /* TPIT 5 State Register */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0 0x0021a4b0 /* TPIT State Register for Context 0 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1 0x0021a4b4 /* TPIT State Register for Context 1 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2 0x0021a4b8 /* TPIT State Register for Context 2 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3 0x0021a4bc /* TPIT State Register for Context 3 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4 0x0021a4c0 /* TPIT State Register for Context 4 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5 0x0021a4c4 /* TPIT State Register for Context 5 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6 0x0021a4c8 /* TPIT State Register for Context 6 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7 0x0021a4cc /* TPIT State Register for Context 7 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8 0x0021a4d0 /* TPIT State Register for Context 8 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9 0x0021a4d4 /* TPIT State Register for Context 9 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10 0x0021a4d8 /* TPIT State Register for Context 10 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11 0x0021a4dc /* TPIT State Register for Context 11 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12 0x0021a4e0 /* TPIT State Register for Context 12 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13 0x0021a4e4 /* TPIT State Register for Context 13 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14 0x0021a4e8 /* TPIT State Register for Context 14 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15 0x0021a4ec /* TPIT State Register for Context 15 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16 0x0021a4f0 /* TPIT State Register for Context 16 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17 0x0021a4f4 /* TPIT State Register for Context 17 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18 0x0021a4f8 /* TPIT State Register for Context 18 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19 0x0021a4fc /* TPIT State Register for Context 19 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20 0x0021a500 /* TPIT State Register for Context 20 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21 0x0021a504 /* TPIT State Register for Context 21 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22 0x0021a508 /* TPIT State Register for Context 22 */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23 0x0021a50c /* TPIT State Register for Context 23 */ - -/*************************************************************************** - *CX0_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX0_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX0_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX0_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX0_REC_MISC_CONFIG - Context 0 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX0_REC_SCD_PIDS_AB - Context 0 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX0_REC_SCD_PIDS_CD - Context 0 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX0_REC_SCD_PIDS_EF - Context 0 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX0_REC_SCD_PIDS_GH - Context 0 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX0_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX0_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX0_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX0_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX0_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX0_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX0_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX0_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX0_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX0_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX0_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX0_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX0_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX0_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX0_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX0_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX0_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX0_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX0_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX0_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX0_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX0_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX0_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX0_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX0_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX0_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX0_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX0_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX0_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX0_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX0_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX0_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX0_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX0_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX0_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX0_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX0_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX0_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX0_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX0_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX0_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX0_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX0_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX0_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX0_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX0_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX0_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX0_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX0_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX0_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX0_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX1_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX1_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX1_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX1_REC_MISC_CONFIG - Context 1 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX1_REC_SCD_PIDS_AB - Context 1 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX1_REC_SCD_PIDS_CD - Context 1 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX1_REC_SCD_PIDS_EF - Context 1 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX1_REC_SCD_PIDS_GH - Context 1 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX1_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX1_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX1_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX1_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX1_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX1_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX1_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX1_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX1_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX1_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX1_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX1_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX1_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX1_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX1_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX1_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX1_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX1_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX1_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX1_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX1_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX1_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX1_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX1_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX1_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX1_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX1_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX1_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX1_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX1_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX1_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX1_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX1_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX1_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX1_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX1_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX1_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX1_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX1_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX1_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX1_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX1_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX1_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX1_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX1_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX1_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX1_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX1_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX1_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX1_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX1_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX2_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX2_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX2_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX2_REC_MISC_CONFIG - Context 2 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX2_REC_SCD_PIDS_AB - Context 2 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX2_REC_SCD_PIDS_CD - Context 2 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX2_REC_SCD_PIDS_EF - Context 2 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX2_REC_SCD_PIDS_GH - Context 2 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX2_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX2_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX2_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX2_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX2_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX2_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX2_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX2_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX2_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX2_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX2_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX2_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX2_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX2_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX2_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX2_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX2_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX2_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX2_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX2_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX2_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX2_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX2_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX2_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX2_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX2_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX2_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX2_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX2_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX2_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX2_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX2_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX2_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX2_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX2_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX2_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX2_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX2_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX2_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX2_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX2_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX2_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX2_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX2_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX2_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX2_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX2_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX2_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX2_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX2_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX2_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX3_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX3_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX3_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX3_REC_MISC_CONFIG - Context 3 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX3_REC_SCD_PIDS_AB - Context 3 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX3_REC_SCD_PIDS_CD - Context 3 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX3_REC_SCD_PIDS_EF - Context 3 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX3_REC_SCD_PIDS_GH - Context 3 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX3_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX3_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX3_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX3_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX3_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX3_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX3_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX3_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX3_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX3_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX3_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX3_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX3_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX3_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX3_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX3_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX3_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX3_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX3_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX3_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX3_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX3_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX3_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX3_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX3_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX3_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX3_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX3_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX3_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX3_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX3_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX3_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX3_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX3_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX3_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX3_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX3_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX3_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX3_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX3_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX3_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX3_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX3_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX3_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX3_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX3_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX3_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX3_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX3_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX3_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX3_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX4_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX4_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX4_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX4_REC_MISC_CONFIG - Context 4 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX4_REC_SCD_PIDS_AB - Context 4 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX4_REC_SCD_PIDS_CD - Context 4 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX4_REC_SCD_PIDS_EF - Context 4 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX4_REC_SCD_PIDS_GH - Context 4 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX4_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX4_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX4_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX4_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX4_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX4_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX4_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX4_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX4_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX4_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX4_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX4_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX4_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX4_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX4_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX4_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX4_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX4_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX4_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX4_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX4_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX4_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX4_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX4_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX4_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX4_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX4_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX4_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX4_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX4_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX4_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX4_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX4_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX4_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX4_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX4_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX4_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX4_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX4_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX4_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX4_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX4_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX4_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX4_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX4_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX4_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX4_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX4_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX4_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX4_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX4_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX5_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX5_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX5_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX5_REC_MISC_CONFIG - Context 5 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX5_REC_SCD_PIDS_AB - Context 5 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX5_REC_SCD_PIDS_CD - Context 5 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX5_REC_SCD_PIDS_EF - Context 5 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX5_REC_SCD_PIDS_GH - Context 5 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX5_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX5_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX5_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX5_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX5_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX5_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX5_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX5_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX5_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX5_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX5_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX5_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX5_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX5_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX5_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX5_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX5_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX5_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX5_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX5_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX5_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX5_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX5_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX5_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX5_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX5_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX5_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX5_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX5_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX5_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX5_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX5_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX5_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX5_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX5_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX5_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX5_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX5_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX5_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX5_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX5_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX5_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX5_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX5_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX5_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX5_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX5_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX5_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX5_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX5_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX5_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX6_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX6_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX6_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX6_REC_MISC_CONFIG - Context 6 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX6_REC_SCD_PIDS_AB - Context 6 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX6_REC_SCD_PIDS_CD - Context 6 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX6_REC_SCD_PIDS_EF - Context 6 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX6_REC_SCD_PIDS_GH - Context 6 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX6_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX6_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX6_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX6_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX6_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX6_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX6_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX6_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX6_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX6_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX6_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX6_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX6_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX6_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX6_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX6_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX6_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX6_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX6_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX6_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX6_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX6_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX6_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX6_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX6_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX6_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX6_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX6_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX6_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX6_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX6_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX6_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX6_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX6_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX6_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX6_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX6_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX6_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX6_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX6_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX6_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX6_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX6_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX6_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX6_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX6_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX6_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX6_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX6_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX6_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX6_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX7_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX7_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX7_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX7_REC_MISC_CONFIG - Context 7 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX7_REC_SCD_PIDS_AB - Context 7 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX7_REC_SCD_PIDS_CD - Context 7 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX7_REC_SCD_PIDS_EF - Context 7 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX7_REC_SCD_PIDS_GH - Context 7 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX7_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX7_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX7_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX7_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX7_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX7_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX7_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX7_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX7_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX7_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX7_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX7_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX7_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX7_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX7_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX7_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX7_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX7_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX7_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX7_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX7_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX7_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX7_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX7_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX7_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX7_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX7_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX7_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX7_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX7_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX7_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX7_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX7_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX7_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX7_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX7_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX7_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX7_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX7_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX7_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX7_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX7_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX7_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX7_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX7_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX7_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX7_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX7_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX7_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX7_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX7_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX8_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX8_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX8_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX8_REC_MISC_CONFIG - Context 8 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX8_REC_SCD_PIDS_AB - Context 8 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX8_REC_SCD_PIDS_CD - Context 8 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX8_REC_SCD_PIDS_EF - Context 8 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX8_REC_SCD_PIDS_GH - Context 8 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX8_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX8_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX8_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX8_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX8_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX8_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX8_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX8_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX8_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX8_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX8_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX8_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX8_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX8_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX8_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX8_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX8_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX8_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX8_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX8_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX8_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX8_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX8_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX8_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX8_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX8_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX8_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX8_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX8_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX8_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX8_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX8_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX8_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX8_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX8_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX8_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX8_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX8_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX8_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX8_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX8_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX8_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX8_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX8_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX8_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX8_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX8_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX8_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX8_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX8_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX8_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX9_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX9_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX9_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX9_REC_MISC_CONFIG - Context 9 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX9_REC_SCD_PIDS_AB - Context 9 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX9_REC_SCD_PIDS_CD - Context 9 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX9_REC_SCD_PIDS_EF - Context 9 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX9_REC_SCD_PIDS_GH - Context 9 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX9_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX9_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX9_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX9_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX9_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX9_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX9_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX9_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX9_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX9_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX9_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX9_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX9_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX9_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX9_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX9_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX9_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX9_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX9_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX9_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX9_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX9_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX9_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX9_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX9_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX9_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX9_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX9_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX9_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX9_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX9_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX9_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX9_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX9_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX9_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX9_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX9_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX9_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX9_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX9_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX9_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX9_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX9_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX9_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX9_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX9_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX9_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX9_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX9_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX9_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX9_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX10_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX10_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX10_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX10_REC_MISC_CONFIG - Context 10 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX10_REC_SCD_PIDS_AB - Context 10 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX10_REC_SCD_PIDS_CD - Context 10 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX10_REC_SCD_PIDS_EF - Context 10 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX10_REC_SCD_PIDS_GH - Context 10 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX10_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX10_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX10_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX10_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX10_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX10_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX10_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX10_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX10_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX10_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX10_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX10_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX10_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX10_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX10_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX10_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX10_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX10_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX10_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX10_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX10_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX10_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX10_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX10_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX10_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX10_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX10_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX10_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX10_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX10_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX10_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX10_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX10_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX10_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX10_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX10_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX10_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX10_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX10_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX10_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX10_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX10_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX10_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX10_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX10_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX10_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX10_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX10_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX10_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX10_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX10_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX11_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX11_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX11_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX11_REC_MISC_CONFIG - Context 11 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX11_REC_SCD_PIDS_AB - Context 11 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX11_REC_SCD_PIDS_CD - Context 11 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX11_REC_SCD_PIDS_EF - Context 11 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX11_REC_SCD_PIDS_GH - Context 11 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX11_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX11_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX11_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX11_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX11_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX11_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX11_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX11_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX11_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX11_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX11_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX11_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX11_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX11_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX11_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX11_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX11_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX11_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX11_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX11_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX11_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX11_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX11_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX11_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX11_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX11_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX11_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX11_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX11_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX11_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX11_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX11_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX11_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX11_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX11_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX11_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX11_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX11_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX11_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX11_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX11_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX11_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX11_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX11_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX11_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX11_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX11_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX11_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX11_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX11_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX11_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX12_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX12_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX12_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX12_REC_MISC_CONFIG - Context 12 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX12_REC_SCD_PIDS_AB - Context 12 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX12_REC_SCD_PIDS_CD - Context 12 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX12_REC_SCD_PIDS_EF - Context 12 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX12_REC_SCD_PIDS_GH - Context 12 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX12_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX12_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX12_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX12_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX12_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX12_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX12_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX12_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX12_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX12_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX12_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX12_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX12_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX12_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX12_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX12_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX12_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX12_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX12_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX12_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX12_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX12_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX12_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX12_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX12_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX12_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX12_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX12_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX12_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX12_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX12_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX12_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX12_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX12_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX12_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX12_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX12_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX12_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX12_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX12_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX12_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX12_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX12_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX12_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX12_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX12_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX12_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX12_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX12_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX12_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX12_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX13_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX13_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX13_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX13_REC_MISC_CONFIG - Context 13 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX13_REC_SCD_PIDS_AB - Context 13 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX13_REC_SCD_PIDS_CD - Context 13 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX13_REC_SCD_PIDS_EF - Context 13 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX13_REC_SCD_PIDS_GH - Context 13 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX13_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX13_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX13_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX13_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX13_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX13_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX13_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX13_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX13_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX13_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX13_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX13_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX13_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX13_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX13_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX13_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX13_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX13_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX13_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX13_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX13_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX13_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX13_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX13_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX13_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX13_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX13_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX13_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX13_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX13_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX13_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX13_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX13_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX13_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX13_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX13_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX13_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX13_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX13_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX13_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX13_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX13_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX13_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX13_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX13_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX13_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX13_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX13_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX13_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX13_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX13_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX14_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX14_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX14_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX14_REC_MISC_CONFIG - Context 14 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX14_REC_SCD_PIDS_AB - Context 14 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX14_REC_SCD_PIDS_CD - Context 14 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX14_REC_SCD_PIDS_EF - Context 14 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX14_REC_SCD_PIDS_GH - Context 14 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX14_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX14_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX14_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX14_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX14_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX14_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX14_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX14_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX14_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX14_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX14_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX14_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX14_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX14_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX14_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX14_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX14_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX14_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX14_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX14_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX14_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX14_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX14_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX14_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX14_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX14_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX14_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX14_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX14_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX14_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX14_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX14_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX14_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX14_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX14_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX14_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX14_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX14_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX14_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX14_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX14_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX14_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX14_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX14_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX14_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX14_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX14_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX14_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX14_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX14_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX14_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX15_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX15_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX15_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX15_REC_MISC_CONFIG - Context 15 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX15_REC_SCD_PIDS_AB - Context 15 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX15_REC_SCD_PIDS_CD - Context 15 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX15_REC_SCD_PIDS_EF - Context 15 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX15_REC_SCD_PIDS_GH - Context 15 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX15_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX15_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX15_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX15_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX15_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX15_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX15_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX15_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX15_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX15_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX15_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX15_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX15_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX15_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX15_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX15_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX15_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX15_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX15_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX15_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX15_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX15_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX15_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX15_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX15_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX15_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX15_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX15_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX15_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX15_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX15_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX15_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX15_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX15_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX15_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX15_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX15_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX15_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX15_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX15_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX15_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX15_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX15_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX15_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX15_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX15_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX15_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX15_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX15_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX15_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX15_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX16_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX16_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX16_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX16_REC_MISC_CONFIG - Context 16 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX16_REC_SCD_PIDS_AB - Context 16 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX16_REC_SCD_PIDS_CD - Context 16 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX16_REC_SCD_PIDS_EF - Context 16 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX16_REC_SCD_PIDS_GH - Context 16 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX16_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX16_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX16_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX16_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX16_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX16_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX16_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX16_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX16_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX16_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX16_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX16_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX16_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX16_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX16_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX16_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX16_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX16_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX16_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX16_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX16_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX16_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX16_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX16_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX16_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX16_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX16_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX16_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX16_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX16_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX16_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX16_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX16_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX16_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX16_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX16_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX16_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX16_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX16_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX16_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX16_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX16_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX16_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX16_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX16_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX16_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX16_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX16_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX16_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX16_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX16_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX17_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX17_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX17_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX17_REC_MISC_CONFIG - Context 17 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX17_REC_SCD_PIDS_AB - Context 17 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX17_REC_SCD_PIDS_CD - Context 17 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX17_REC_SCD_PIDS_EF - Context 17 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX17_REC_SCD_PIDS_GH - Context 17 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX17_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX17_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX17_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX17_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX17_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX17_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX17_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX17_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX17_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX17_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX17_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX17_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX17_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX17_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX17_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX17_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX17_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX17_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX17_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX17_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX17_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX17_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX17_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX17_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX17_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX17_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX17_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX17_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX17_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX17_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX17_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX17_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX17_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX17_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX17_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX17_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX17_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX17_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX17_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX17_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX17_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX17_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX17_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX17_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX17_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX17_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX17_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX17_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX17_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX17_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX17_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX18_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX18_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX18_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX18_REC_MISC_CONFIG - Context 18 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX18_REC_SCD_PIDS_AB - Context 18 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX18_REC_SCD_PIDS_CD - Context 18 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX18_REC_SCD_PIDS_EF - Context 18 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX18_REC_SCD_PIDS_GH - Context 18 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX18_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX18_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX18_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX18_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX18_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX18_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX18_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX18_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX18_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX18_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX18_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX18_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX18_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX18_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX18_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX18_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX18_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX18_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX18_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX18_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX18_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX18_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX18_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX18_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX18_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX18_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX18_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX18_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX18_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX18_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX18_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX18_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX18_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX18_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX18_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX18_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX18_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX18_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX18_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX18_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX18_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX18_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX18_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX18_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX18_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX18_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX18_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX18_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX18_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX18_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX18_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX19_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX19_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX19_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX19_REC_MISC_CONFIG - Context 19 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX19_REC_SCD_PIDS_AB - Context 19 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX19_REC_SCD_PIDS_CD - Context 19 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX19_REC_SCD_PIDS_EF - Context 19 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX19_REC_SCD_PIDS_GH - Context 19 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX19_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX19_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX19_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX19_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX19_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX19_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX19_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX19_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX19_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX19_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX19_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX19_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX19_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX19_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX19_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX19_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX19_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX19_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX19_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX19_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX19_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX19_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX19_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX19_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX19_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX19_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX19_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX19_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX19_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX19_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX19_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX19_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX19_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX19_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX19_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX19_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX19_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX19_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX19_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX19_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX19_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX19_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX19_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX19_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX19_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX19_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX19_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX19_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX19_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX19_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX19_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX20_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX20_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX20_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX20_REC_MISC_CONFIG - Context 20 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX20_REC_SCD_PIDS_AB - Context 20 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX20_REC_SCD_PIDS_CD - Context 20 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX20_REC_SCD_PIDS_EF - Context 20 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX20_REC_SCD_PIDS_GH - Context 20 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX20_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX20_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX20_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX20_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX20_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX20_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX20_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX20_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX20_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX20_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX20_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX20_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX20_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX20_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX20_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX20_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX20_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX20_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX20_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX20_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX20_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX20_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX20_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX20_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX20_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX20_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX20_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX20_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX20_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX20_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX20_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX20_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX20_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX20_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX20_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX20_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX20_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX20_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX20_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX20_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX20_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX20_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX20_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX20_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX20_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX20_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX20_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX20_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX20_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX20_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX20_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX21_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX21_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX21_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX21_REC_MISC_CONFIG - Context 21 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX21_REC_SCD_PIDS_AB - Context 21 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX21_REC_SCD_PIDS_CD - Context 21 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX21_REC_SCD_PIDS_EF - Context 21 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX21_REC_SCD_PIDS_GH - Context 21 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX21_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX21_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX21_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX21_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX21_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX21_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX21_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX21_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX21_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX21_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX21_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX21_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX21_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX21_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX21_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX21_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX21_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX21_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX21_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX21_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX21_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX21_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX21_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX21_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX21_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX21_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX21_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX21_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX21_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX21_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX21_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX21_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX21_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX21_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX21_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX21_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX21_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX21_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX21_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX21_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX21_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX21_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX21_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX21_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX21_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX21_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX21_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX21_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX21_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX21_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX21_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX22_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX22_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX22_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX22_REC_MISC_CONFIG - Context 22 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX22_REC_SCD_PIDS_AB - Context 22 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX22_REC_SCD_PIDS_CD - Context 22 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX22_REC_SCD_PIDS_EF - Context 22 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX22_REC_SCD_PIDS_GH - Context 22 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX22_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX22_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX22_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX22_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX22_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX22_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX22_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX22_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX22_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX22_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX22_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX22_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX22_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX22_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX22_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX22_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX22_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX22_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX22_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX22_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX22_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX22_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX22_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX22_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX22_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX22_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX22_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX22_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX22_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX22_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX22_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX22_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX22_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX22_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX22_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX22_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX22_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX22_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX22_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX22_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX22_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX22_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX22_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX22_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX22_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX22_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX22_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX22_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX22_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX22_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX22_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_WRITE_PTR - Context CDB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_READ_PTR - Context CDB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_BASE_PTR - Context CDB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_END_PTR - Context CDB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_VALID_PTR - Context CDB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX23_AV_CDB_DEPTH - Context CDB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX23_AV_THRESHOLDS - Context Thresholds - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_WRITE_PTR - Context ITB Write Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_READ_PTR - Context ITB Read Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_BASE_PTR - Context ITB Base Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_END_PTR - Context ITB End Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_VALID_PTR - Context ITB Valid Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 - -/*************************************************************************** - *CX23_AV_ITB_DEPTH - Context ITB Depth - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 - -/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 - -/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 - -/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff -#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *CX23_REC_MISC_CONFIG - Context 23 Miscellaneous Config - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 - -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: REC_AVN [14:14] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_REC_AVN_SHIFT 14 - -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 - -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 - -/*************************************************************************** - *CX23_REC_SCD_PIDS_AB - Context 23 SCD map PIDS A and B - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 - -/*************************************************************************** - *CX23_REC_SCD_PIDS_CD - Context 23 SCD map PIDS C and D - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 - -/*************************************************************************** - *CX23_REC_SCD_PIDS_EF - Context 23 SCD map PIDS E and F - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 - -/*************************************************************************** - *CX23_REC_SCD_PIDS_GH - Context 23 SCD map PIDS G and H - ***************************************************************************/ -/* union - case Mapped_SCD_via_PID_channels [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 - -/* union - case Mapped_SCD_via_stream_PID_values [31:00] */ -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 - -/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff -#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 - -/*************************************************************************** - *CX23_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 - -/*************************************************************************** - *CX23_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *CX23_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 - -/*************************************************************************** - *CX23_AV_INTERRUPT_ENABLES - Context Interrupt Enables - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 - -/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP1_CONTROL - Context Comparator 1 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP2_CONTROL - Context Comparator 2 Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 - -/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f -#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value - ***************************************************************************/ -/* union - case Exclusion_Value_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 - -/* union - case Exclusion_Value_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 - -/* union - case Exclusion_Value_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 - -/* union - case Exclusion_Value_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* union - case Exclusion_Mask_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 - -/* union - case Inclusion_Range_D [31:24] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 - -/* union - case Exclusion_Mask_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 - -/* union - case Inclusion_Range_C [23:16] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 - -/* union - case Exclusion_Mask_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 - -/* union - case Inclusion_Range_B [15:08] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 - -/* union - case Exclusion_Mask_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 - -/* union - case Inclusion_Range_A [07:00] */ -/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 - -/*************************************************************************** - *CX23_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 - -/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 - -/*************************************************************************** - *CX23_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 - -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: PID_VALID [30:30] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 - -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 - -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 - -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 - -/*************************************************************************** - *CX23_REC_CTRL1 - Record Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_CTRL1 :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: reserved_for_eco1 [07:06] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco1_SHIFT 6 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: PARSE_SC [04:04] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_PARSE_SC_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_PARSE_SC_SHIFT 4 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 - -/* XPT_RAVE :: CX23_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 - -/*************************************************************************** - *CX23_REC_INIT_TS - Record Initial Timestamp Value Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_INIT_TS :: INIT_TS [31:00] */ -#define BCHP_XPT_RAVE_CX23_REC_INIT_TS_INIT_TS_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_REC_INIT_TS_INIT_TS_SHIFT 0 - -/*************************************************************************** - *CX23_REC_TS_CTRL - Record Timestamp Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 - -/* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 - -/* XPT_RAVE :: CX23_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 - -/* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_INIT_EN [02:02] */ -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 - -/* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_USER_BITS [01:00] */ -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 - -/*************************************************************************** - *CX23_REC_TIME_CONFIG - Record Time Configuration Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ -#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 -#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 - -/* XPT_RAVE :: CX23_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ -#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 -#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 - -/* XPT_RAVE :: CX23_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ -#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff -#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 - -/*************************************************************************** - *CX23_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 - -/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 - -/*************************************************************************** - *CX23_PIC_CTR - Picture Counter register - ***************************************************************************/ -/* XPT_RAVE :: CX23_PIC_CTR :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_reserved0_SHIFT 16 - -/* XPT_RAVE :: CX23_PIC_CTR :: VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX23_PIC_CTR_VALUE_SHIFT 0 - -/*************************************************************************** - *CX23_PIC_CTR_MODE - Picture Counter Mode Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved0_SHIFT 31 - -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 - -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 - -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: reserved1 [26:26] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved1_MASK 0x04000000 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved1_SHIFT 26 - -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 - -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV0 [23:16] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV0_SHIFT 16 - -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV1 [15:08] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV1_SHIFT 8 - -/* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV2 [07:00] */ -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV2_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV2_SHIFT 0 - -/*************************************************************************** - *CX23_REC_TIMER - Record Timer Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_TIMER :: REC_TIMER [31:00] */ -#define BCHP_XPT_RAVE_CX23_REC_TIMER_REC_TIMER_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_REC_TIMER_REC_TIMER_SHIFT 0 - -/*************************************************************************** - *CX23_REC_STATE0 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_STATE0 :: reserved_for_eco0 [31:18] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco0_SHIFT 18 - -/* XPT_RAVE :: CX23_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 -#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_STATE0 :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: CX23_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c -#define BCHP_XPT_RAVE_CX23_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 - -/* XPT_RAVE :: CX23_REC_STATE0 :: TS_INITIALIZED [01:01] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX23_REC_STATE0_TS_INITIALIZED_SHIFT 1 - -/* XPT_RAVE :: CX23_REC_STATE0 :: REC_INITIALIZED [00:00] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INITIALIZED_SHIFT 0 - -/*************************************************************************** - *CX23_REC_STATE1 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 - -/*************************************************************************** - *CX23_REC_STATE2 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_STATE2 :: INT_TIME_STAMP [31:00] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_REC_STATE2_INT_TIME_STAMP_SHIFT 0 - -/*************************************************************************** - *CX23_REC_STATE2b - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 - -/*************************************************************************** - *CX23_REC_STATE3 - Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_STATE3 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_CX23_REC_STATE3_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: CX23_REC_STATE3 :: REC_DSS_PARITY [08:08] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_DSS_PARITY_SHIFT 8 - -/* XPT_RAVE :: CX23_REC_STATE3 :: REC_COUNT_HI [07:00] */ -#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff -#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_COUNT_HI_SHIFT 0 - -/*************************************************************************** - *CX23_REC_COUNT - Record Packet Count Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_COUNT :: REC_COUNT [31:00] */ -#define BCHP_XPT_RAVE_CX23_REC_COUNT_REC_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_REC_COUNT_REC_COUNT_SHIFT 0 - -/*************************************************************************** - *CX23_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ -#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 -#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 - -/* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ -#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 -#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 - -/* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ -#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 - -/*************************************************************************** - *CX23_REC_RESERVE_STATE1 - Reserved Record State Register - ***************************************************************************/ -/* XPT_RAVE :: CX23_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX23_RAVE_Reg_0 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX23_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX23_RAVE_Reg_1 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX23_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX23_RAVE_Reg_2 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX23_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *CX23_RAVE_Reg_3 - Reserved Rave Register for future use - ***************************************************************************/ -/* XPT_RAVE :: CX23_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_CX23_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_MISC_CONFIG - SCD 0 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD0_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD0_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD0_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD0_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD0_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD0_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD0_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD0_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_MISC_CONFIG - SCD 1 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD1_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD1_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD1_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD1_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD1_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD1_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD1_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD1_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_MISC_CONFIG - SCD 2 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD2_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD2_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD2_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD2_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD2_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD2_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD2_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD2_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_MISC_CONFIG - SCD 3 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD3_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD3_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD3_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD3_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD3_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD3_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD3_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD3_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_MISC_CONFIG - SCD 4 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD4_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD4_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD4_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD4_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD4_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD4_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD4_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD4_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_MISC_CONFIG - SCD 5 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD5_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD5_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD5_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD5_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD5_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD5_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD5_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD5_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_MISC_CONFIG - SCD 6 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD6_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD6_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD6_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD6_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD6_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD6_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD6_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD6_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_MISC_CONFIG - SCD 7 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD7_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD7_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD7_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD7_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD7_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD7_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD7_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD7_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_MISC_CONFIG - SCD 8 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD8_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD8_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD8_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD8_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD8_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD8_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD8_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD8_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_MISC_CONFIG - SCD 9 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD9_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD9_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD9_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD9_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD9_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD9_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD9_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD9_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_MISC_CONFIG - SCD 10 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD10_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD10_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD10_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD10_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD10_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD10_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD10_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD10_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_MISC_CONFIG - SCD 11 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD11_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD11_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD11_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD11_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD11_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD11_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD11_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD11_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_MISC_CONFIG - SCD 12 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD12_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD12_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD12_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD12_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD12_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD12_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD12_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD12_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_MISC_CONFIG - SCD 13 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD13_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD13_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD13_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD13_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD13_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD13_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD13_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD13_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_MISC_CONFIG - SCD 14 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD14_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD14_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD14_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD14_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD14_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD14_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD14_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD14_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_MISC_CONFIG - SCD 15 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD15_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD15_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD15_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD15_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD15_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD15_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD15_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD15_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_MISC_CONFIG - SCD 16 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD16_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD16_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD16_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD16_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD16_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD16_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD16_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD16_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_MISC_CONFIG - SCD 17 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD17_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD17_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD17_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD17_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD17_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD17_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD17_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD17_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_MISC_CONFIG - SCD 18 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD18_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD18_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD18_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD18_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD18_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD18_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD18_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD18_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_MISC_CONFIG - SCD 19 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD19_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD19_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD19_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD19_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD19_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD19_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD19_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD19_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_MISC_CONFIG - SCD 20 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD20_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD20_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD20_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD20_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD20_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD20_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD20_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD20_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_MISC_CONFIG - SCD 21 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD21_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD21_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD21_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD21_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD21_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD21_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD21_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD21_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_MISC_CONFIG - SCD 22 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD22_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD22_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD22_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD22_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD22_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD22_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD22_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD22_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_MISC_CONFIG - SCD 23 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD23_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD23_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD23_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD23_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD23_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD23_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD23_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD23_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_MISC_CONFIG - SCD 24 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD24_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD24_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD24_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD24_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD24_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD24_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD24_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD24_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_MISC_CONFIG - SCD 25 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD25_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD25_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD25_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD25_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD25_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD25_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD25_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD25_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_MISC_CONFIG - SCD 26 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD26_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD26_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD26_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD26_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD26_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD26_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD26_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD26_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_MISC_CONFIG - SCD 27 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD27_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD27_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD27_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD27_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD27_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD27_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD27_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD27_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_MISC_CONFIG - SCD 28 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD28_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD28_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD28_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD28_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD28_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD28_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD28_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD28_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_MISC_CONFIG - SCD 29 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD29_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD29_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD29_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD29_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD29_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD29_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD29_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD29_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_MISC_CONFIG - SCD 30 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD30_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD30_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD30_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD30_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD30_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD30_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD30_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD30_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_MISC_CONFIG - SCD 31 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD31_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD31_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD31_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD31_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD31_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD31_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD31_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD31_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_MISC_CONFIG - SCD 32 Misc Config Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ -#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 -#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 - -/* XPT_RAVE :: SCD32_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff -#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE6 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE7 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE8 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE9 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE10 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_COMP_STATE11 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_RESERVE_COMP_STATE0 - Reserved Comparator State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_PES_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_PES_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_PES_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_PES_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_PACKET_COUNT - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *SCD32_RESERVE_PES_STATE0 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_RESERVE_PES_STATE1 - Reserved PES State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_STATE0 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_STATE1 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_STATE2 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD32_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_STATE3 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_STATE4 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 - -/*************************************************************************** - *SCD32_SCD_STATE5 - SCD State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 -#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 - -/* XPT_RAVE :: SCD32_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ -#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff -#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 - -/*************************************************************************** - *SCD32_RESERVED_STATE0 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_RESERVED_STATE1 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_RESERVED_STATE2 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *SCD32_RESERVED_STATE3 - SCD Reserved State Register - ***************************************************************************/ -/* XPT_RAVE :: SCD32_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff -#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 - -/*************************************************************************** - *XPU_CONFIG - XPU TEST ENABLE REGISTER - ***************************************************************************/ -/* XPT_RAVE :: XPU_CONFIG :: reserved0 [31:01] */ -#define BCHP_XPT_RAVE_XPU_CONFIG_reserved0_MASK 0xfffffffe -#define BCHP_XPT_RAVE_XPU_CONFIG_reserved0_SHIFT 1 - -/* XPT_RAVE :: XPU_CONFIG :: TEST_ENABLE [00:00] */ -#define BCHP_XPT_RAVE_XPU_CONFIG_TEST_ENABLE_MASK 0x00000001 -#define BCHP_XPT_RAVE_XPU_CONFIG_TEST_ENABLE_SHIFT 0 - -/*************************************************************************** - *XPU_TEST_CONTROL - XPU TEST CONTROL REGISTER - ***************************************************************************/ -/* XPT_RAVE :: XPU_TEST_CONTROL :: reserved0 [31:04] */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_reserved0_SHIFT 4 - -/* XPT_RAVE :: XPU_TEST_CONTROL :: EXT_IN [03:02] */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IN_MASK 0x0000000c -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IN_SHIFT 2 - -/* XPT_RAVE :: XPU_TEST_CONTROL :: WAKE [01:01] */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_WAKE_MASK 0x00000002 -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_WAKE_SHIFT 1 - -/* XPT_RAVE :: XPU_TEST_CONTROL :: INTR [00:00] */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_INTR_MASK 0x00000001 -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_INTR_SHIFT 0 - -/*************************************************************************** - *XPU_TEST_CONTROL_EXT_IO - XPU TEST CONTROL EXT IO - ***************************************************************************/ -/* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: reserved0 [31:09] */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_reserved0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_reserved0_SHIFT 9 - -/* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: WAIT [08:08] */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_WAIT_MASK 0x00000100 -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_WAIT_SHIFT 8 - -/* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: RD_DATA [07:00] */ -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_RD_DATA_MASK 0x000000ff -#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_RD_DATA_SHIFT 0 - -/*************************************************************************** - *XPU_TEST_OBSERVE_0 - XPU TEST OBSERVE REGISTER - ***************************************************************************/ -/* XPT_RAVE :: XPU_TEST_OBSERVE_0 :: reserved0 [31:02] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_reserved0_MASK 0xfffffffc -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_reserved0_SHIFT 2 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_0 :: P_BITS [01:00] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_P_BITS_MASK 0x00000003 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_P_BITS_SHIFT 0 - -/*************************************************************************** - *XPU_TEST_OBSERVE_1 - XPU TEST OBSERVE REGISTER - ***************************************************************************/ -/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: reserved0 [31:31] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_reserved0_MASK 0x80000000 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_reserved0_SHIFT 31 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_PSW [30:20] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PSW_MASK 0x7ff00000 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PSW_SHIFT 20 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_PC [19:08] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PC_MASK 0x000fff00 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PC_SHIFT 8 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_DATA [07:00] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_DATA_MASK 0x000000ff -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_DATA_SHIFT 0 - -/*************************************************************************** - *XPU_TEST_OBSERVE_EXT_IO - XPU TEST OBSERVE EXT IO REGISTER - ***************************************************************************/ -/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: reserved0 [31:22] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_reserved0_MASK 0xffc00000 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_reserved0_SHIFT 22 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: ADDR [21:10] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_ADDR_MASK 0x003ffc00 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_ADDR_SHIFT 10 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: WR_DATA [09:02] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_DATA_MASK 0x000003fc -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_DATA_SHIFT 2 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: RD_STROBE [01:01] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_RD_STROBE_MASK 0x00000002 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_RD_STROBE_SHIFT 1 - -/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: WR_STROBE [00:00] */ -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_STROBE_MASK 0x00000001 -#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_STROBE_SHIFT 0 - -/*************************************************************************** - *RAVE_DIAGNOSTICS_CONTROL - RAVE Diagnostics Control Register - ***************************************************************************/ -/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: reserved0 [31:14] */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved0_MASK 0xffffc000 -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved0_SHIFT 14 - -/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: UPPER_TESTBUS_SEL [13:09] */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_UPPER_TESTBUS_SEL_MASK 0x00003e00 -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_UPPER_TESTBUS_SEL_SHIFT 9 - -/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: LOWER_TESTBUS_SEL [08:04] */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_LOWER_TESTBUS_SEL_MASK 0x000001f0 -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_LOWER_TESTBUS_SEL_SHIFT 4 - -/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: reserved_for_eco1 [03:03] */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved_for_eco1_MASK 0x00000008 -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved_for_eco1_SHIFT 3 - -/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: NEXT_BREAKPOINT [02:02] */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_NEXT_BREAKPOINT_MASK 0x00000004 -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_NEXT_BREAKPOINT_SHIFT 2 - -/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: BREAKPOINT_EN [01:01] */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_BREAKPOINT_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_BREAKPOINT_EN_SHIFT 1 - -/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: DIAG_EN [00:00] */ -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_DIAG_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_DIAG_EN_SHIFT 0 - -/*************************************************************************** - *STOP_PACKET_COUNT_VALUE - Stop Packet Count Value - ***************************************************************************/ -/* XPT_RAVE :: STOP_PACKET_COUNT_VALUE :: STOP_PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE_STOP_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE_STOP_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *AVS_SCV_FILTER_MODE_CONTROL - AVS SCV Filter mode - ***************************************************************************/ -/* XPT_RAVE :: AVS_SCV_FILTER_MODE_CONTROL :: reserved0 [31:02] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_reserved0_MASK 0xfffffffc -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_reserved0_SHIFT 2 - -/* XPT_RAVE :: AVS_SCV_FILTER_MODE_CONTROL :: AVS_SCV_FILTER_MODE [01:00] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_AVS_SCV_FILTER_MODE_MASK 0x00000003 -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_AVS_SCV_FILTER_MODE_SHIFT 0 - -/*************************************************************************** - *AVS_SCV_FILTER_VALUE_0_TO_3 - AVS SCV Filter value 0 to 3 - ***************************************************************************/ -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_3 [31:24] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_3_MASK 0xff000000 -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_3_SHIFT 24 - -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_2 [23:16] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_2_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_2_SHIFT 16 - -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_1 [15:08] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_1_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_1_SHIFT 8 - -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_0 [07:00] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_0_MASK 0x000000ff -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_0_SHIFT 0 - -/*************************************************************************** - *AVS_SCV_FILTER_VALUE_4_TO_7 - AVS SCV Filter value 4 to 7 - ***************************************************************************/ -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_7 [31:24] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_7_MASK 0xff000000 -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_7_SHIFT 24 - -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_6 [23:16] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_6_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_6_SHIFT 16 - -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_5 [15:08] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_5_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_5_SHIFT 8 - -/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_4 [07:00] */ -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_4_MASK 0x000000ff -#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_4_SHIFT 0 - -/*************************************************************************** - *AV_STATUS - RAVE Status - ***************************************************************************/ -/* XPT_RAVE :: AV_STATUS :: reserved0 [31:26] */ -#define BCHP_XPT_RAVE_AV_STATUS_reserved0_MASK 0xfc000000 -#define BCHP_XPT_RAVE_AV_STATUS_reserved0_SHIFT 26 - -/* XPT_RAVE :: AV_STATUS :: XPU_RDY [25:25] */ -#define BCHP_XPT_RAVE_AV_STATUS_XPU_RDY_MASK 0x02000000 -#define BCHP_XPT_RAVE_AV_STATUS_XPU_RDY_SHIFT 25 - -/* XPT_RAVE :: AV_STATUS :: ITB_MEM_STATE_IDLE [24:24] */ -#define BCHP_XPT_RAVE_AV_STATUS_ITB_MEM_STATE_IDLE_MASK 0x01000000 -#define BCHP_XPT_RAVE_AV_STATUS_ITB_MEM_STATE_IDLE_SHIFT 24 - -/* XPT_RAVE :: AV_STATUS :: CDB_MEM_STATE_IDLE [23:23] */ -#define BCHP_XPT_RAVE_AV_STATUS_CDB_MEM_STATE_IDLE_MASK 0x00800000 -#define BCHP_XPT_RAVE_AV_STATUS_CDB_MEM_STATE_IDLE_SHIFT 23 - -/* XPT_RAVE :: AV_STATUS :: HWA_PKT_ACTIVE [22:22] */ -#define BCHP_XPT_RAVE_AV_STATUS_HWA_PKT_ACTIVE_MASK 0x00400000 -#define BCHP_XPT_RAVE_AV_STATUS_HWA_PKT_ACTIVE_SHIFT 22 - -/* XPT_RAVE :: AV_STATUS :: DMA_BUSY [21:21] */ -#define BCHP_XPT_RAVE_AV_STATUS_DMA_BUSY_MASK 0x00200000 -#define BCHP_XPT_RAVE_AV_STATUS_DMA_BUSY_SHIFT 21 - -/* XPT_RAVE :: AV_STATUS :: AV_MUX_BUF_OVERFLOW [20:20] */ -#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUF_OVERFLOW_MASK 0x00100000 -#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUF_OVERFLOW_SHIFT 20 - -/* XPT_RAVE :: AV_STATUS :: AV_MUX_BUFFER_WATERMARK [19:10] */ -#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_WATERMARK_MASK 0x000ffc00 -#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_WATERMARK_SHIFT 10 - -/* XPT_RAVE :: AV_STATUS :: AV_MUX_BUFFER_DEPTH [09:00] */ -#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_DEPTH_MASK 0x000003ff -#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_DEPTH_SHIFT 0 - -/*************************************************************************** - *PACKET_COUNT - RAVE input packet counter - ***************************************************************************/ -/* XPT_RAVE :: PACKET_COUNT :: PACKET_COUNT [31:00] */ -#define BCHP_XPT_RAVE_PACKET_COUNT_PACKET_COUNT_MASK 0xffffffff -#define BCHP_XPT_RAVE_PACKET_COUNT_PACKET_COUNT_SHIFT 0 - -/*************************************************************************** - *DATA_START_ADDR_A - Pkt and HWA data buffer A base addresses - ***************************************************************************/ -/* XPT_RAVE :: DATA_START_ADDR_A :: reserved0 [31:27] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved0_SHIFT 27 - -/* XPT_RAVE :: DATA_START_ADDR_A :: HWA_START [26:16] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_HWA_START_MASK 0x07ff0000 -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_HWA_START_SHIFT 16 - -/* XPT_RAVE :: DATA_START_ADDR_A :: reserved1 [15:11] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved1_MASK 0x0000f800 -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved1_SHIFT 11 - -/* XPT_RAVE :: DATA_START_ADDR_A :: PKT_START [10:00] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_PKT_START_MASK 0x000007ff -#define BCHP_XPT_RAVE_DATA_START_ADDR_A_PKT_START_SHIFT 0 - -/*************************************************************************** - *DATA_START_ADDR_B - Pkt and HWA data buffer B base addresses - ***************************************************************************/ -/* XPT_RAVE :: DATA_START_ADDR_B :: reserved0 [31:27] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved0_MASK 0xf8000000 -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved0_SHIFT 27 - -/* XPT_RAVE :: DATA_START_ADDR_B :: HWA_START [26:16] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_HWA_START_MASK 0x07ff0000 -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_HWA_START_SHIFT 16 - -/* XPT_RAVE :: DATA_START_ADDR_B :: reserved1 [15:11] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved1_MASK 0x0000f800 -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved1_SHIFT 11 - -/* XPT_RAVE :: DATA_START_ADDR_B :: PKT_START [10:00] */ -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_PKT_START_MASK 0x000007ff -#define BCHP_XPT_RAVE_DATA_START_ADDR_B_PKT_START_SHIFT 0 - -/*************************************************************************** - *WATCHDOG_TIMER_VALUE - Watchdog Timer Timeout Value - ***************************************************************************/ -/* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: reserved0 [31:17] */ -#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_reserved0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_reserved0_SHIFT 17 - -/* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: WATCHDOG_TIMER_ENABLE [16:16] */ -#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_ENABLE_MASK 0x00010000 -#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_ENABLE_SHIFT 16 - -/* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: WATCHDOG_TIMER_LOAD_VALUE [15:00] */ -#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_LOAD_VALUE_MASK 0x0000ffff -#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_LOAD_VALUE_SHIFT 0 - -/*************************************************************************** - *MISC_CONTROL - Miscellaneous Control - ***************************************************************************/ -/* XPT_RAVE :: MISC_CONTROL :: PACKET_CNT_CLR [31:31] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_PACKET_CNT_CLR_MASK 0x80000000 -#define BCHP_XPT_RAVE_MISC_CONTROL_PACKET_CNT_CLR_SHIFT 31 - -/* XPT_RAVE :: MISC_CONTROL :: WMARK_GRANULARITY [30:28] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_WMARK_GRANULARITY_MASK 0x70000000 -#define BCHP_XPT_RAVE_MISC_CONTROL_WMARK_GRANULARITY_SHIFT 28 - -/* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco0 [27:26] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco0_MASK 0x0c000000 -#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco0_SHIFT 26 - -/* XPT_RAVE :: MISC_CONTROL :: NUM_CONTEXTS [25:20] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_CONTEXTS_MASK 0x03f00000 -#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_CONTEXTS_SHIFT 20 - -/* XPT_RAVE :: MISC_CONTROL :: EMU_STATE_CLEAR [19:19] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_EMU_STATE_CLEAR_MASK 0x00080000 -#define BCHP_XPT_RAVE_MISC_CONTROL_EMU_STATE_CLEAR_SHIFT 19 - -/* XPT_RAVE :: MISC_CONTROL :: AV_WMARK_CLEAR [18:18] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_AV_WMARK_CLEAR_MASK 0x00040000 -#define BCHP_XPT_RAVE_MISC_CONTROL_AV_WMARK_CLEAR_SHIFT 18 - -/* XPT_RAVE :: MISC_CONTROL :: DMA_SPEEDUP_EN [17:17] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_DMA_SPEEDUP_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_MISC_CONTROL_DMA_SPEEDUP_EN_SHIFT 17 - -/* XPT_RAVE :: MISC_CONTROL :: MUX_BUFFER_SLOT_SIZE [16:16] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_MUX_BUFFER_SLOT_SIZE_MASK 0x00010000 -#define BCHP_XPT_RAVE_MISC_CONTROL_MUX_BUFFER_SLOT_SIZE_SHIFT 16 - -/* XPT_RAVE :: MISC_CONTROL :: INPUT_READ_RATE [15:12] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_INPUT_READ_RATE_MASK 0x0000f000 -#define BCHP_XPT_RAVE_MISC_CONTROL_INPUT_READ_RATE_SHIFT 12 - -/* XPT_RAVE :: MISC_CONTROL :: PES_COMPARATOR_RESET [11:11] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_PES_COMPARATOR_RESET_MASK 0x00000800 -#define BCHP_XPT_RAVE_MISC_CONTROL_PES_COMPARATOR_RESET_SHIFT 11 - -/* XPT_RAVE :: MISC_CONTROL :: FORCE_SWITCH [10:10] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_FORCE_SWITCH_MASK 0x00000400 -#define BCHP_XPT_RAVE_MISC_CONTROL_FORCE_SWITCH_SHIFT 10 - -/* XPT_RAVE :: MISC_CONTROL :: HW_FORCE_SWITCH_EN [09:09] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_HW_FORCE_SWITCH_EN_MASK 0x00000200 -#define BCHP_XPT_RAVE_MISC_CONTROL_HW_FORCE_SWITCH_EN_SHIFT 9 - -/* XPT_RAVE :: MISC_CONTROL :: COUNTER_MODE [08:08] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_COUNTER_MODE_MASK 0x00000100 -#define BCHP_XPT_RAVE_MISC_CONTROL_COUNTER_MODE_SHIFT 8 - -/* XPT_RAVE :: MISC_CONTROL :: NUM_DMA_CYCLES [07:04] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_DMA_CYCLES_MASK 0x000000f0 -#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_DMA_CYCLES_SHIFT 4 - -/* XPT_RAVE :: MISC_CONTROL :: AV_ENABLE [03:03] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_AV_ENABLE_MASK 0x00000008 -#define BCHP_XPT_RAVE_MISC_CONTROL_AV_ENABLE_SHIFT 3 - -/* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco1 [02:02] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco1_MASK 0x00000004 -#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco1_SHIFT 2 - -/* XPT_RAVE :: MISC_CONTROL :: PS_WAKE [01:01] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_PS_WAKE_MASK 0x00000002 -#define BCHP_XPT_RAVE_MISC_CONTROL_PS_WAKE_SHIFT 1 - -/* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco2 [00:00] */ -#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco2_MASK 0x00000001 -#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco2_SHIFT 0 - -/*************************************************************************** - *BASE_ADDRESSES - Record and SCD Base Addresses - ***************************************************************************/ -/* XPT_RAVE :: BASE_ADDRESSES :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_BASE_ADDRESSES_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_BASE_ADDRESSES_reserved0_SHIFT 12 - -/* XPT_RAVE :: BASE_ADDRESSES :: SCD_BASE_ADDR [11:00] */ -#define BCHP_XPT_RAVE_BASE_ADDRESSES_SCD_BASE_ADDR_MASK 0x00000fff -#define BCHP_XPT_RAVE_BASE_ADDRESSES_SCD_BASE_ADDR_SHIFT 0 - -/*************************************************************************** - *CX_HOLD_CLR_STATUS - Context Hold Status and Clear - ***************************************************************************/ -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: reserved0 [31:24] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_reserved0_MASK 0xff000000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_reserved0_SHIFT 24 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX23_HOLD [23:23] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX23_HOLD_MASK 0x00800000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX23_HOLD_SHIFT 23 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX22_HOLD [22:22] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX22_HOLD_MASK 0x00400000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX22_HOLD_SHIFT 22 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX21_HOLD [21:21] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX21_HOLD_MASK 0x00200000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX21_HOLD_SHIFT 21 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX20_HOLD [20:20] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX20_HOLD_MASK 0x00100000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX20_HOLD_SHIFT 20 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX19_HOLD [19:19] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX19_HOLD_MASK 0x00080000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX19_HOLD_SHIFT 19 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX18_HOLD [18:18] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX18_HOLD_MASK 0x00040000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX18_HOLD_SHIFT 18 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX17_HOLD [17:17] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX17_HOLD_MASK 0x00020000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX17_HOLD_SHIFT 17 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX16_HOLD [16:16] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX16_HOLD_MASK 0x00010000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX16_HOLD_SHIFT 16 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX15_HOLD [15:15] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX15_HOLD_MASK 0x00008000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX15_HOLD_SHIFT 15 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX14_HOLD [14:14] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX14_HOLD_MASK 0x00004000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX14_HOLD_SHIFT 14 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX13_HOLD [13:13] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX13_HOLD_MASK 0x00002000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX13_HOLD_SHIFT 13 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX12_HOLD [12:12] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX12_HOLD_MASK 0x00001000 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX12_HOLD_SHIFT 12 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX11_HOLD [11:11] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX11_HOLD_MASK 0x00000800 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX11_HOLD_SHIFT 11 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX10_HOLD [10:10] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX10_HOLD_MASK 0x00000400 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX10_HOLD_SHIFT 10 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX9_HOLD [09:09] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX9_HOLD_MASK 0x00000200 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX9_HOLD_SHIFT 9 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX8_HOLD [08:08] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX8_HOLD_MASK 0x00000100 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX8_HOLD_SHIFT 8 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX7_HOLD [07:07] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX7_HOLD_MASK 0x00000080 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX7_HOLD_SHIFT 7 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX6_HOLD [06:06] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX6_HOLD_MASK 0x00000040 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX6_HOLD_SHIFT 6 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX5_HOLD [05:05] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX5_HOLD_MASK 0x00000020 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX5_HOLD_SHIFT 5 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX4_HOLD [04:04] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX4_HOLD_MASK 0x00000010 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX4_HOLD_SHIFT 4 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX3_HOLD [03:03] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX3_HOLD_MASK 0x00000008 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX3_HOLD_SHIFT 3 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX2_HOLD [02:02] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX2_HOLD_MASK 0x00000004 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX2_HOLD_SHIFT 2 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX1_HOLD [01:01] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX1_HOLD_MASK 0x00000002 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX1_HOLD_SHIFT 1 - -/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX0_HOLD [00:00] */ -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX0_HOLD_MASK 0x00000001 -#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX0_HOLD_SHIFT 0 - -/*************************************************************************** - *BAND_HOLD_CLR_STATUS - Band Hold Status and Clear - ***************************************************************************/ -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: reserved0 [31:17] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved0_MASK 0xfffe0000 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved0_SHIFT 17 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK4_HOLD [16:16] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK4_HOLD_MASK 0x00010000 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK4_HOLD_SHIFT 16 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK3_HOLD [15:15] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK3_HOLD_MASK 0x00008000 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK3_HOLD_SHIFT 15 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK2_HOLD [14:14] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK2_HOLD_MASK 0x00004000 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK2_HOLD_SHIFT 14 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK1_HOLD [13:13] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK1_HOLD_MASK 0x00002000 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK1_HOLD_SHIFT 13 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK0_HOLD [12:12] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK0_HOLD_MASK 0x00001000 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK0_HOLD_SHIFT 12 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: reserved1 [11:07] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved1_MASK 0x00000f80 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved1_SHIFT 7 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND6_HOLD [06:06] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND6_HOLD_MASK 0x00000040 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND6_HOLD_SHIFT 6 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND5_HOLD [05:05] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND5_HOLD_MASK 0x00000020 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND5_HOLD_SHIFT 5 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND4_HOLD [04:04] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND4_HOLD_MASK 0x00000010 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND4_HOLD_SHIFT 4 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND3_HOLD [03:03] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND3_HOLD_MASK 0x00000008 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND3_HOLD_SHIFT 3 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND2_HOLD [02:02] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND2_HOLD_MASK 0x00000004 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND2_HOLD_SHIFT 2 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND1_HOLD [01:01] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND1_HOLD_MASK 0x00000002 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND1_HOLD_SHIFT 1 - -/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND0_HOLD [00:00] */ -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND0_HOLD_MASK 0x00000001 -#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND0_HOLD_SHIFT 0 - -/*************************************************************************** - *FW_WATERMARK - Firmware throughput watermark - ***************************************************************************/ -/* XPT_RAVE :: FW_WATERMARK :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_FW_WATERMARK_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_FW_WATERMARK_reserved0_SHIFT 16 - -/* XPT_RAVE :: FW_WATERMARK :: FIRMWARE_WMARK [15:00] */ -#define BCHP_XPT_RAVE_FW_WATERMARK_FIRMWARE_WMARK_MASK 0x0000ffff -#define BCHP_XPT_RAVE_FW_WATERMARK_FIRMWARE_WMARK_SHIFT 0 - -/*************************************************************************** - *HW_WATCHDOG - Hardware Watchdog Counter - ***************************************************************************/ -/* XPT_RAVE :: HW_WATCHDOG :: reserved0 [31:16] */ -#define BCHP_XPT_RAVE_HW_WATCHDOG_reserved0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_HW_WATCHDOG_reserved0_SHIFT 16 - -/* XPT_RAVE :: HW_WATCHDOG :: HW_WATCHDOG_COUNT [15:00] */ -#define BCHP_XPT_RAVE_HW_WATCHDOG_HW_WATCHDOG_COUNT_MASK 0x0000ffff -#define BCHP_XPT_RAVE_HW_WATCHDOG_HW_WATCHDOG_COUNT_SHIFT 0 - -/*************************************************************************** - *MISC_CONTROL2 - Miscellaneous Control 2 - ***************************************************************************/ -/* XPT_RAVE :: MISC_CONTROL2 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_MISC_CONTROL2_reserved0_SHIFT 8 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN7 [07:07] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN7_MASK 0x00000080 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN7_SHIFT 7 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN6 [06:06] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN6_MASK 0x00000040 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN6_SHIFT 6 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN5 [05:05] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN5_MASK 0x00000020 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN5_SHIFT 5 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN4 [04:04] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN4_MASK 0x00000010 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN4_SHIFT 4 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN3 [03:03] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN3_MASK 0x00000008 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN3_SHIFT 3 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN2 [02:02] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN2_MASK 0x00000004 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN2_SHIFT 2 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN1 [01:01] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN1_MASK 0x00000002 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN1_SHIFT 1 - -/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN0 [00:00] */ -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN0_MASK 0x00000001 -#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN0_SHIFT 0 - -/*************************************************************************** - *RC0_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC0_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC0_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC0_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC0_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC0_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC1_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC1_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC1_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC1_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC1_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC1_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC2_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC2_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC2_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC2_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC2_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC2_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC3_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC3_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC3_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC3_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC3_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC3_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC4_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC4_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC4_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC4_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC4_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC4_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC5_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC5_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC5_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC5_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC5_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC5_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC6_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC6_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC6_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC6_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC6_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC6_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC7_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC7_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC7_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC7_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC7_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC7_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *RC8_SP_CONTROL - Seamless Pause Control - ***************************************************************************/ -/* XPT_RAVE :: RC8_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 - -/* XPT_RAVE :: RC8_SP_CONTROL :: reserved0 [30:30] */ -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_reserved0_MASK 0x40000000 -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_reserved0_SHIFT 30 - -/* XPT_RAVE :: RC8_SP_CONTROL :: REC_CX_NUM [29:24] */ -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_REC_CX_NUM_SHIFT 24 - -/* XPT_RAVE :: RC8_SP_CONTROL :: CXX_MASK [23:00] */ -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_CXX_MASK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_RC8_SP_CONTROL_CXX_MASK_SHIFT 0 - -/*************************************************************************** - *AV_STATUS2 - RAVE Status - ***************************************************************************/ -/* XPT_RAVE :: AV_STATUS2 :: reserved0 [31:20] */ -#define BCHP_XPT_RAVE_AV_STATUS2_reserved0_MASK 0xfff00000 -#define BCHP_XPT_RAVE_AV_STATUS2_reserved0_SHIFT 20 - -/* XPT_RAVE :: AV_STATUS2 :: PONG_SCD_NUM [19:14] */ -#define BCHP_XPT_RAVE_AV_STATUS2_PONG_SCD_NUM_MASK 0x000fc000 -#define BCHP_XPT_RAVE_AV_STATUS2_PONG_SCD_NUM_SHIFT 14 - -/* XPT_RAVE :: AV_STATUS2 :: PING_SCD_NUM [13:08] */ -#define BCHP_XPT_RAVE_AV_STATUS2_PING_SCD_NUM_MASK 0x00003f00 -#define BCHP_XPT_RAVE_AV_STATUS2_PING_SCD_NUM_SHIFT 8 - -/* XPT_RAVE :: AV_STATUS2 :: PONG_CONTEXT_NUM [07:04] */ -#define BCHP_XPT_RAVE_AV_STATUS2_PONG_CONTEXT_NUM_MASK 0x000000f0 -#define BCHP_XPT_RAVE_AV_STATUS2_PONG_CONTEXT_NUM_SHIFT 4 - -/* XPT_RAVE :: AV_STATUS2 :: PING_CONTEXT_NUM [03:00] */ -#define BCHP_XPT_RAVE_AV_STATUS2_PING_CONTEXT_NUM_MASK 0x0000000f -#define BCHP_XPT_RAVE_AV_STATUS2_PING_CONTEXT_NUM_SHIFT 0 - -/*************************************************************************** - *TM_DMEM - TM Control - ***************************************************************************/ -/* XPT_RAVE :: TM_DMEM :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TM_DMEM_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TM_DMEM_reserved0_SHIFT 8 - -/* XPT_RAVE :: TM_DMEM :: TMB [07:04] */ -#define BCHP_XPT_RAVE_TM_DMEM_TMB_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TM_DMEM_TMB_SHIFT 4 - -/* XPT_RAVE :: TM_DMEM :: TMA [03:00] */ -#define BCHP_XPT_RAVE_TM_DMEM_TMA_MASK 0x0000000f -#define BCHP_XPT_RAVE_TM_DMEM_TMA_SHIFT 0 - -/*************************************************************************** - *TM_IMEM - TM Control - ***************************************************************************/ -/* XPT_RAVE :: TM_IMEM :: reserved0 [31:04] */ -#define BCHP_XPT_RAVE_TM_IMEM_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_RAVE_TM_IMEM_reserved0_SHIFT 4 - -/* XPT_RAVE :: TM_IMEM :: TM [03:00] */ -#define BCHP_XPT_RAVE_TM_IMEM_TM_MASK 0x0000000f -#define BCHP_XPT_RAVE_TM_IMEM_TM_SHIFT 0 - -/*************************************************************************** - *TM_POINTER_RAM - TM Control - ***************************************************************************/ -/* XPT_RAVE :: TM_POINTER_RAM :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TM_POINTER_RAM_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TM_POINTER_RAM_reserved0_SHIFT 8 - -/* XPT_RAVE :: TM_POINTER_RAM :: TM [07:00] */ -#define BCHP_XPT_RAVE_TM_POINTER_RAM_TM_MASK 0x000000ff -#define BCHP_XPT_RAVE_TM_POINTER_RAM_TM_SHIFT 0 - -/*************************************************************************** - *TM_MUX_BUFFER - TM Control - ***************************************************************************/ -/* XPT_RAVE :: TM_MUX_BUFFER :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TM_MUX_BUFFER_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TM_MUX_BUFFER_reserved0_SHIFT 8 - -/* XPT_RAVE :: TM_MUX_BUFFER :: TM [07:00] */ -#define BCHP_XPT_RAVE_TM_MUX_BUFFER_TM_MASK 0x000000ff -#define BCHP_XPT_RAVE_TM_MUX_BUFFER_TM_SHIFT 0 - -/*************************************************************************** - *TM_CX_TABLE - TM Control - ***************************************************************************/ -/* XPT_RAVE :: TM_CX_TABLE :: reserved0 [31:04] */ -#define BCHP_XPT_RAVE_TM_CX_TABLE_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_RAVE_TM_CX_TABLE_reserved0_SHIFT 4 - -/* XPT_RAVE :: TM_CX_TABLE :: TM [03:00] */ -#define BCHP_XPT_RAVE_TM_CX_TABLE_TM_MASK 0x0000000f -#define BCHP_XPT_RAVE_TM_CX_TABLE_TM_SHIFT 0 - -/*************************************************************************** - *TM_CX_TABLE_HI - TM Control - ***************************************************************************/ -/* XPT_RAVE :: TM_CX_TABLE_HI :: reserved0 [31:04] */ -#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_reserved0_SHIFT 4 - -/* XPT_RAVE :: TM_CX_TABLE_HI :: TM [03:00] */ -#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_TM_MASK 0x0000000f -#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_TM_SHIFT 0 - -/*************************************************************************** - *TM_SMEM - TM Control - ***************************************************************************/ -/* XPT_RAVE :: TM_SMEM :: reserved0 [31:04] */ -#define BCHP_XPT_RAVE_TM_SMEM_reserved0_MASK 0xfffffff0 -#define BCHP_XPT_RAVE_TM_SMEM_reserved0_SHIFT 4 - -/* XPT_RAVE :: TM_SMEM :: TM [03:00] */ -#define BCHP_XPT_RAVE_TM_SMEM_TM_MASK 0x0000000f -#define BCHP_XPT_RAVE_TM_SMEM_TM_SHIFT 0 - -/*************************************************************************** - *INT_CX0 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX0 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX0_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX0_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX0 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX0_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX0_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX0 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX0_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX0_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX0 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX0_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX0_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX0 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX0_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX0_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX0 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX0_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX0_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX0 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX0_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX0_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX0 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX0_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX0_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX0 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX0_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX0_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX0 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX0_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX0_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX0 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX0_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX0_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX0 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX0_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX0_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX0 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX0_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX0_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX0 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX0_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX0_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX1 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX1 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX1_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX1_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX1 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX1_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX1_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX1 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX1_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX1_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX1 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX1_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX1_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX1 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX1_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX1_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX1 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX1_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX1_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX1 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX1_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX1_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX1 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX1_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX1_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX1 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX1_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX1_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX1 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX1_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX1_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX1 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX1_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX1_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX1 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX1_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX1_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX1 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX1_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX1_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX1 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX1_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX1_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX2 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX2 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX2_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX2_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX2 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX2_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX2_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX2 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX2_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX2_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX2 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX2_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX2_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX2 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX2_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX2_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX2 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX2_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX2_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX2 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX2_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX2_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX2 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX2_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX2_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX2 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX2_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX2_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX2 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX2_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX2_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX2 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX2_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX2_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX2 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX2_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX2_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX2 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX2_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX2_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX2 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX2_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX2_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX3 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX3 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX3_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX3_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX3 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX3_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX3_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX3 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX3_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX3_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX3 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX3_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX3_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX3 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX3_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX3_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX3 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX3_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX3_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX3 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX3_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX3_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX3 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX3_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX3_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX3 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX3_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX3_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX3 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX3_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX3_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX3 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX3_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX3_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX3 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX3_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX3_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX3 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX3_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX3_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX3 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX3_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX3_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX4 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX4 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX4_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX4_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX4 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX4_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX4_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX4 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX4_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX4_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX4 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX4_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX4_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX4 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX4_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX4_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX4 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX4_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX4_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX4 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX4_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX4_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX4 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX4_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX4_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX4 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX4_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX4_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX4 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX4_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX4_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX4 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX4_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX4_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX4 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX4_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX4_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX4 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX4_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX4_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX4 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX4_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX4_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX5 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX5 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX5_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX5_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX5 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX5 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX5 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX5 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX5 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX5 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX5 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX5 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX5 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX5 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX5 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX5 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX5 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX6 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX6 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX6_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX6_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX6 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX6_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX6_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX6 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX6_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX6_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX6 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX6_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX6_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX6 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX6_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX6_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX6 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX6_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX6_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX6 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX6_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX6_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX6 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX6_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX6_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX6 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX6_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX6_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX6 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX6_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX6_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX6 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX6_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX6_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX6 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX6_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX6_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX6 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX6_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX6_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX6 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX6_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX6_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX7 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX7 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX7_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX7_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX7 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX7_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX7_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX7 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX7_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX7_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX7 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX7_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX7_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX7 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX7_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX7_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX7 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX7_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX7_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX7 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX7_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX7_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX7 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX7_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX7_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX7 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX7_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX7_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX7 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX7_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX7_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX7 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX7_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX7_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX7 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX7_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX7_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX7 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX7_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX7_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX7 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX7_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX7_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX8 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX8 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX8_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX8_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX8 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX8_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX8_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX8 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX8_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX8_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX8 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX8_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX8_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX8 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX8_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX8_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX8 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX8_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX8_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX8 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX8_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX8_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX8 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX8_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX8_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX8 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX8_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX8_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX8 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX8_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX8_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX8 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX8_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX8_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX8 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX8_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX8_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX8 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX8_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX8_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX8 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX8_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX8_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX9 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX9 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX9_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX9_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX9 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX9_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX9_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX9 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX9_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX9_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX9 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX9_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX9_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX9 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX9_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX9_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX9 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX9_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX9_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX9 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX9_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX9_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX9 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX9_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX9_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX9 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX9_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX9_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX9 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX9_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX9_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX9 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX9_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX9_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX9 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX9_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX9_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX9 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX9_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX9_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX9 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX9_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX9_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX10 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX10 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX10_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX10_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX10 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX10_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX10_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX10 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX10_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX10_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX10 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX10_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX10_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX10 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX10_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX10_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX10 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX10_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX10_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX10 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX10_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX10_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX10 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX10_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX10_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX10 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX10_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX10_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX10 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX10_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX10_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX10 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX10_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX10_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX10 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX10_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX10_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX10 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX10_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX10_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX10 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX10_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX10_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX11 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX11 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX11_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX11_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX11 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX11_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX11_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX11 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX11_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX11_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX11 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX11_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX11_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX11 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX11_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX11_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX11 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX11_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX11_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX11 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX11_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX11_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX11 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX11_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX11_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX11 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX11_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX11_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX11 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX11_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX11_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX11 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX11_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX11_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX11 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX11_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX11_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX11 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX11_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX11_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX11 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX11_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX11_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX12 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX12 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX12_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX12_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX12 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX12_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX12_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX12 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX12_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX12_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX12 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX12_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX12_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX12 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX12_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX12_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX12 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX12_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX12_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX12 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX12_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX12_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX12 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX12_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX12_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX12 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX12_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX12_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX12 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX12_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX12_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX12 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX12_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX12_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX12 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX12_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX12_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX12 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX12_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX12_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX12 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX12_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX12_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX13 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX13 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX13_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX13_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX13 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX13_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX13_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX13 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX13_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX13_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX13 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX13_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX13_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX13 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX13_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX13_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX13 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX13_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX13_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX13 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX13_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX13_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX13 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX13_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX13_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX13 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX13_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX13_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX13 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX13_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX13_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX13 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX13_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX13_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX13 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX13_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX13_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX13 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX13_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX13_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX13 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX13_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX13_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX14 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX14 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX14_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX14_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX14 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX14_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX14_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX14 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX14_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX14_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX14 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX14_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX14_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX14 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX14_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX14_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX14 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX14_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX14_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX14 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX14_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX14_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX14 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX14_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX14_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX14 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX14_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX14_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX14 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX14_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX14_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX14 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX14_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX14_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX14 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX14_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX14_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX14 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX14_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX14_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX14 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX14_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX14_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX15 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX15 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX15_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX15_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX15 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX15_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX15_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX15 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX15_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX15_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX15 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX15_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX15_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX15 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX15_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX15_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX15 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX15_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX15_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX15 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX15_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX15_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX15 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX15_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX15_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX15 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX15_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX15_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX15 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX15_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX15_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX15 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX15_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX15_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX15 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX15_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX15_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX15 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX15_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX15_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX15 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX15_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX15_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX16 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX16 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX16_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX16_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX16 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX16_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX16_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX16 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX16_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX16_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX16 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX16_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX16_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX16 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX16_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX16_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX16 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX16_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX16_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX16 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX16_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX16_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX16 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX16_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX16_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX16 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX16_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX16_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX16 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX16_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX16_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX16 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX16_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX16_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX16 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX16_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX16_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX16 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX16_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX16_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX16 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX16_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX16_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX17 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX17 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX17_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX17_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX17 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX17_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX17_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX17 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX17_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX17_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX17 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX17_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX17_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX17 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX17_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX17_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX17 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX17_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX17_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX17 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX17_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX17_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX17 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX17_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX17_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX17 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX17_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX17_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX17 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX17_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX17_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX17 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX17_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX17_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX17 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX17_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX17_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX17 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX17_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX17_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX17 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX17_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX17_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX18 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX18 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX18_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX18_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX18 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX18_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX18_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX18 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX18_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX18_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX18 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX18_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX18_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX18 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX18_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX18_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX18 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX18_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX18_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX18 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX18_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX18_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX18 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX18_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX18_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX18 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX18_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX18_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX18 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX18_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX18_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX18 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX18_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX18_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX18 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX18_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX18_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX18 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX18_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX18_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX18 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX18_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX18_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX19 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX19 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX19_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX19_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX19 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX19_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX19_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX19 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX19_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX19_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX19 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX19_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX19_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX19 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX19_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX19_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX19 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX19_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX19_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX19 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX19_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX19_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX19 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX19_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX19_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX19 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX19_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX19_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX19 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX19_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX19_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX19 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX19_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX19_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX19 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX19_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX19_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX19 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX19_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX19_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX19 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX19_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX19_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX20 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX20 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX20_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX20_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX20 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX20_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX20_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX20 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX20_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX20_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX20 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX20_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX20_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX20 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX20_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX20_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX20 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX20_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX20_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX20 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX20_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX20_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX20 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX20_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX20_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX20 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX20_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX20_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX20 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX20_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX20_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX20 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX20_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX20_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX20 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX20_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX20_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX20 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX20_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX20_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX20 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX20_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX20_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX21 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX21 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX21_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX21_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX21 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX21_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX21_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX21 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX21_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX21_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX21 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX21_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX21_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX21 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX21_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX21_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX21 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX21_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX21_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX21 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX21_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX21_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX21 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX21_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX21_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX21 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX21_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX21_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX21 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX21_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX21_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX21 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX21_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX21_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX21 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX21_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX21_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX21 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX21_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX21_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX21 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX21_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX21_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX22 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX22 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX22_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX22_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX22 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX22_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX22_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX22 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX22_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX22_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX22 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX22_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX22_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX22 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX22_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX22_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX22 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX22_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX22_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX22 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX22_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX22_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX22 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX22_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX22_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX22 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX22_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX22_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX22 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX22_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX22_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX22 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX22_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX22_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX22 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX22_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX22_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX22 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX22_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX22_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX22 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX22_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX22_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_CX23 - Context Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_CX23 :: reserved0 [31:15] */ -#define BCHP_XPT_RAVE_INT_CX23_reserved0_MASK 0xffff8000 -#define BCHP_XPT_RAVE_INT_CX23_reserved0_SHIFT 15 - -/* XPT_RAVE :: INT_CX23 :: SCD_INDEX [14:12] */ -#define BCHP_XPT_RAVE_INT_CX23_SCD_INDEX_MASK 0x00007000 -#define BCHP_XPT_RAVE_INT_CX23_SCD_INDEX_SHIFT 12 - -/* XPT_RAVE :: INT_CX23 :: ITB_UPPER_THRESH_INT [11:11] */ -#define BCHP_XPT_RAVE_INT_CX23_ITB_UPPER_THRESH_INT_MASK 0x00000800 -#define BCHP_XPT_RAVE_INT_CX23_ITB_UPPER_THRESH_INT_SHIFT 11 - -/* XPT_RAVE :: INT_CX23 :: ITB_LOWER_THRESH_INT [10:10] */ -#define BCHP_XPT_RAVE_INT_CX23_ITB_LOWER_THRESH_INT_MASK 0x00000400 -#define BCHP_XPT_RAVE_INT_CX23_ITB_LOWER_THRESH_INT_SHIFT 10 - -/* XPT_RAVE :: INT_CX23 :: CDB_UPPER_THRESH_INT [09:09] */ -#define BCHP_XPT_RAVE_INT_CX23_CDB_UPPER_THRESH_INT_MASK 0x00000200 -#define BCHP_XPT_RAVE_INT_CX23_CDB_UPPER_THRESH_INT_SHIFT 9 - -/* XPT_RAVE :: INT_CX23 :: CDB_LOWER_THRESH_INT [08:08] */ -#define BCHP_XPT_RAVE_INT_CX23_CDB_LOWER_THRESH_INT_MASK 0x00000100 -#define BCHP_XPT_RAVE_INT_CX23_CDB_LOWER_THRESH_INT_SHIFT 8 - -/* XPT_RAVE :: INT_CX23 :: LAST_CMD_INT [07:07] */ -#define BCHP_XPT_RAVE_INT_CX23_LAST_CMD_INT_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_CX23_LAST_CMD_INT_SHIFT 7 - -/* XPT_RAVE :: INT_CX23 :: SPLICE_INT [06:06] */ -#define BCHP_XPT_RAVE_INT_CX23_SPLICE_INT_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_CX23_SPLICE_INT_SHIFT 6 - -/* XPT_RAVE :: INT_CX23 :: ITB_OVERFLOW_INT [05:05] */ -#define BCHP_XPT_RAVE_INT_CX23_ITB_OVERFLOW_INT_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_CX23_ITB_OVERFLOW_INT_SHIFT 5 - -/* XPT_RAVE :: INT_CX23 :: CDB_OVERFLOW_INT [04:04] */ -#define BCHP_XPT_RAVE_INT_CX23_CDB_OVERFLOW_INT_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_CX23_CDB_OVERFLOW_INT_SHIFT 4 - -/* XPT_RAVE :: INT_CX23 :: CC_ERROR_INT [03:03] */ -#define BCHP_XPT_RAVE_INT_CX23_CC_ERROR_INT_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_CX23_CC_ERROR_INT_SHIFT 3 - -/* XPT_RAVE :: INT_CX23 :: TEI_ERROR_INT [02:02] */ -#define BCHP_XPT_RAVE_INT_CX23_TEI_ERROR_INT_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_CX23_TEI_ERROR_INT_SHIFT 2 - -/* XPT_RAVE :: INT_CX23 :: PUSI_ERROR_INT [01:01] */ -#define BCHP_XPT_RAVE_INT_CX23_PUSI_ERROR_INT_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_CX23_PUSI_ERROR_INT_SHIFT 1 - -/* XPT_RAVE :: INT_CX23 :: EMU_ERROR_INT [00:00] */ -#define BCHP_XPT_RAVE_INT_CX23_EMU_ERROR_INT_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_CX23_EMU_ERROR_INT_SHIFT 0 - -/*************************************************************************** - *INT_MISC - Miscellaneous Interrupts - ***************************************************************************/ -/* XPT_RAVE :: INT_MISC :: reserved0 [31:12] */ -#define BCHP_XPT_RAVE_INT_MISC_reserved0_MASK 0xfffff000 -#define BCHP_XPT_RAVE_INT_MISC_reserved0_SHIFT 12 - -/* XPT_RAVE :: INT_MISC :: reserved_for_eco1 [11:08] */ -#define BCHP_XPT_RAVE_INT_MISC_reserved_for_eco1_MASK 0x00000f00 -#define BCHP_XPT_RAVE_INT_MISC_reserved_for_eco1_SHIFT 8 - -/* XPT_RAVE :: INT_MISC :: MISC_INT7 [07:07] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT7_MASK 0x00000080 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT7_SHIFT 7 - -/* XPT_RAVE :: INT_MISC :: MISC_INT6 [06:06] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT6_MASK 0x00000040 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT6_SHIFT 6 - -/* XPT_RAVE :: INT_MISC :: MISC_INT5 [05:05] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT5_MASK 0x00000020 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT5_SHIFT 5 - -/* XPT_RAVE :: INT_MISC :: MISC_INT4 [04:04] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT4_MASK 0x00000010 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT4_SHIFT 4 - -/* XPT_RAVE :: INT_MISC :: MISC_INT3 [03:03] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT3_MASK 0x00000008 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT3_SHIFT 3 - -/* XPT_RAVE :: INT_MISC :: MISC_INT2 [02:02] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT2_MASK 0x00000004 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT2_SHIFT 2 - -/* XPT_RAVE :: INT_MISC :: MISC_INT1 [01:01] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT1_MASK 0x00000002 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT1_SHIFT 1 - -/* XPT_RAVE :: INT_MISC :: MISC_INT0 [00:00] */ -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT0_MASK 0x00000001 -#define BCHP_XPT_RAVE_INT_MISC_MISC_INT0_SHIFT 0 - -/*************************************************************************** - *CXMEM_LO%i - Context Table 0 (for contexts 0 - 15) 0..287 - ***************************************************************************/ -#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_BASE 0x00213200 -#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_START 0 -#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_END 287 -#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *CXMEM_LO%i - Context Table 0 (for contexts 0 - 15) 0..287 - ***************************************************************************/ -/* XPT_RAVE :: CXMEM_LOi :: CX15_MAP_G [31:31] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_G_MASK 0x80000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_G_SHIFT 31 - -/* XPT_RAVE :: CXMEM_LOi :: CX15_MAP_R [30:30] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_R_MASK 0x40000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_R_SHIFT 30 - -/* XPT_RAVE :: CXMEM_LOi :: CX14_MAP_G [29:29] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_G_MASK 0x20000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_G_SHIFT 29 - -/* XPT_RAVE :: CXMEM_LOi :: CX14_MAP_R [28:28] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_R_MASK 0x10000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_R_SHIFT 28 - -/* XPT_RAVE :: CXMEM_LOi :: CX13_MAP_G [27:27] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_G_MASK 0x08000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_G_SHIFT 27 - -/* XPT_RAVE :: CXMEM_LOi :: CX13_MAP_R [26:26] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_R_MASK 0x04000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_R_SHIFT 26 - -/* XPT_RAVE :: CXMEM_LOi :: CX12_MAP_G [25:25] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_G_MASK 0x02000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_G_SHIFT 25 - -/* XPT_RAVE :: CXMEM_LOi :: CX12_MAP_R [24:24] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_R_MASK 0x01000000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_R_SHIFT 24 - -/* XPT_RAVE :: CXMEM_LOi :: CX11_MAP_G [23:23] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_G_MASK 0x00800000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_G_SHIFT 23 - -/* XPT_RAVE :: CXMEM_LOi :: CX11_MAP_R [22:22] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_R_MASK 0x00400000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_R_SHIFT 22 - -/* XPT_RAVE :: CXMEM_LOi :: CX10_MAP_G [21:21] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_G_MASK 0x00200000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_G_SHIFT 21 - -/* XPT_RAVE :: CXMEM_LOi :: CX10_MAP_R [20:20] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_R_MASK 0x00100000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_R_SHIFT 20 - -/* XPT_RAVE :: CXMEM_LOi :: CX9_MAP_G [19:19] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_G_MASK 0x00080000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_G_SHIFT 19 - -/* XPT_RAVE :: CXMEM_LOi :: CX9_MAP_R [18:18] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_R_MASK 0x00040000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_R_SHIFT 18 - -/* XPT_RAVE :: CXMEM_LOi :: CX8_MAP_G [17:17] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_G_MASK 0x00020000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_G_SHIFT 17 - -/* XPT_RAVE :: CXMEM_LOi :: CX8_MAP_R [16:16] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_R_MASK 0x00010000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_R_SHIFT 16 - -/* XPT_RAVE :: CXMEM_LOi :: CX7_MAP_G [15:15] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_G_MASK 0x00008000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_G_SHIFT 15 - -/* XPT_RAVE :: CXMEM_LOi :: CX7_MAP_R [14:14] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_R_MASK 0x00004000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_R_SHIFT 14 - -/* XPT_RAVE :: CXMEM_LOi :: CX6_MAP_G [13:13] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_G_MASK 0x00002000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_G_SHIFT 13 - -/* XPT_RAVE :: CXMEM_LOi :: CX6_MAP_R [12:12] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_R_MASK 0x00001000 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_R_SHIFT 12 - -/* XPT_RAVE :: CXMEM_LOi :: CX5_MAP_G [11:11] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_G_MASK 0x00000800 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_G_SHIFT 11 - -/* XPT_RAVE :: CXMEM_LOi :: CX5_MAP_R [10:10] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_R_MASK 0x00000400 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_R_SHIFT 10 - -/* XPT_RAVE :: CXMEM_LOi :: CX4_MAP_G [09:09] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_G_MASK 0x00000200 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_G_SHIFT 9 - -/* XPT_RAVE :: CXMEM_LOi :: CX4_MAP_R [08:08] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_R_MASK 0x00000100 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_R_SHIFT 8 - -/* XPT_RAVE :: CXMEM_LOi :: CX3_MAP_G [07:07] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_G_MASK 0x00000080 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_G_SHIFT 7 - -/* XPT_RAVE :: CXMEM_LOi :: CX3_MAP_R [06:06] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_R_MASK 0x00000040 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_R_SHIFT 6 - -/* XPT_RAVE :: CXMEM_LOi :: CX2_MAP_G [05:05] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_G_MASK 0x00000020 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_G_SHIFT 5 - -/* XPT_RAVE :: CXMEM_LOi :: CX2_MAP_R [04:04] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_R_MASK 0x00000010 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_R_SHIFT 4 - -/* XPT_RAVE :: CXMEM_LOi :: CX1_MAP_G [03:03] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_G_MASK 0x00000008 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_G_SHIFT 3 - -/* XPT_RAVE :: CXMEM_LOi :: CX1_MAP_R [02:02] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_R_MASK 0x00000004 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_R_SHIFT 2 - -/* XPT_RAVE :: CXMEM_LOi :: CX0_MAP_G [01:01] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_G_MASK 0x00000002 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_G_SHIFT 1 - -/* XPT_RAVE :: CXMEM_LOi :: CX0_MAP_R [00:00] */ -#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_R_MASK 0x00000001 -#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_R_SHIFT 0 - - -/*************************************************************************** - *CXMEM_HI%i - Context Table 1 (for contexts 16 - 23) 0..287 - ***************************************************************************/ -#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_BASE 0x00213800 -#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_START 0 -#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_END 287 -#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *CXMEM_HI%i - Context Table 1 (for contexts 16 - 23) 0..287 - ***************************************************************************/ -/* XPT_RAVE :: CXMEM_HIi :: reserved_for_eco0 [31:16] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_reserved_for_eco0_MASK 0xffff0000 -#define BCHP_XPT_RAVE_CXMEM_HIi_reserved_for_eco0_SHIFT 16 - -/* XPT_RAVE :: CXMEM_HIi :: CX23_MAP_G [15:15] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_G_MASK 0x00008000 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_G_SHIFT 15 - -/* XPT_RAVE :: CXMEM_HIi :: CX23_MAP_R [14:14] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_R_MASK 0x00004000 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_R_SHIFT 14 - -/* XPT_RAVE :: CXMEM_HIi :: CX22_MAP_G [13:13] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_G_MASK 0x00002000 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_G_SHIFT 13 - -/* XPT_RAVE :: CXMEM_HIi :: CX22_MAP_R [12:12] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_R_MASK 0x00001000 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_R_SHIFT 12 - -/* XPT_RAVE :: CXMEM_HIi :: CX21_MAP_G [11:11] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_G_MASK 0x00000800 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_G_SHIFT 11 - -/* XPT_RAVE :: CXMEM_HIi :: CX21_MAP_R [10:10] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_R_MASK 0x00000400 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_R_SHIFT 10 - -/* XPT_RAVE :: CXMEM_HIi :: CX20_MAP_G [09:09] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_G_MASK 0x00000200 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_G_SHIFT 9 - -/* XPT_RAVE :: CXMEM_HIi :: CX20_MAP_R [08:08] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_R_MASK 0x00000100 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_R_SHIFT 8 - -/* XPT_RAVE :: CXMEM_HIi :: CX19_MAP_G [07:07] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_G_MASK 0x00000080 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_G_SHIFT 7 - -/* XPT_RAVE :: CXMEM_HIi :: CX19_MAP_R [06:06] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_R_MASK 0x00000040 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_R_SHIFT 6 - -/* XPT_RAVE :: CXMEM_HIi :: CX18_MAP_G [05:05] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_G_MASK 0x00000020 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_G_SHIFT 5 - -/* XPT_RAVE :: CXMEM_HIi :: CX18_MAP_R [04:04] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_R_MASK 0x00000010 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_R_SHIFT 4 - -/* XPT_RAVE :: CXMEM_HIi :: CX17_MAP_G [03:03] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_G_MASK 0x00000008 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_G_SHIFT 3 - -/* XPT_RAVE :: CXMEM_HIi :: CX17_MAP_R [02:02] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_R_MASK 0x00000004 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_R_SHIFT 2 - -/* XPT_RAVE :: CXMEM_HIi :: CX16_MAP_G [01:01] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_G_MASK 0x00000002 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_G_SHIFT 1 - -/* XPT_RAVE :: CXMEM_HIi :: CX16_MAP_R [00:00] */ -#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_R_MASK 0x00000001 -#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_R_SHIFT 0 - - -/*************************************************************************** - *DMEM%i - Data Memory Address 0..2047 - ***************************************************************************/ -#define BCHP_XPT_RAVE_DMEMi_ARRAY_BASE 0x00214000 -#define BCHP_XPT_RAVE_DMEMi_ARRAY_START 0 -#define BCHP_XPT_RAVE_DMEMi_ARRAY_END 2047 -#define BCHP_XPT_RAVE_DMEMi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *DMEM%i - Data Memory Address 0..2047 - ***************************************************************************/ -/* XPT_RAVE :: DMEMi :: reserved_for_eco0 [31:08] */ -#define BCHP_XPT_RAVE_DMEMi_reserved_for_eco0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_DMEMi_reserved_for_eco0_SHIFT 8 - -/* XPT_RAVE :: DMEMi :: DATA [07:00] */ -#define BCHP_XPT_RAVE_DMEMi_DATA_MASK 0x000000ff -#define BCHP_XPT_RAVE_DMEMi_DATA_SHIFT 0 - - -/*************************************************************************** - *EMM_TID_MODE - TPIT EMM_TID_MODE Register (NDS only) - ***************************************************************************/ -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_F [31:30] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_F_MASK 0xc0000000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_F_SHIFT 30 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_E [29:28] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_E_MASK 0x30000000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_E_SHIFT 28 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_D [27:26] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_D_MASK 0x0c000000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_D_SHIFT 26 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_C [25:24] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_C_MASK 0x03000000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_C_SHIFT 24 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_B [23:22] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_B_MASK 0x00c00000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_B_SHIFT 22 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_A [21:20] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_A_MASK 0x00300000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_A_SHIFT 20 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_9 [19:18] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_9_MASK 0x000c0000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_9_SHIFT 18 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_8 [17:16] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_8_MASK 0x00030000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_8_SHIFT 16 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_7 [15:14] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_7_MASK 0x0000c000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_7_SHIFT 14 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_6 [13:12] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_6_MASK 0x00003000 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_6_SHIFT 12 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_5 [11:10] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_5_MASK 0x00000c00 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_5_SHIFT 10 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_4 [09:08] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_4_MASK 0x00000300 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_4_SHIFT 8 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_3 [07:06] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_3_MASK 0x000000c0 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_3_SHIFT 6 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_2 [05:04] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_2_MASK 0x00000030 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_2_SHIFT 4 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_1 [03:02] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_1_MASK 0x0000000c -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_1_SHIFT 2 - -/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_0 [01:00] */ -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_0_MASK 0x00000003 -#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_0_SHIFT 0 - -/*************************************************************************** - *EMM_DATA_ID_1 - TPIT EMM_DATA_ID_1 Register (NDS only) - ***************************************************************************/ -/* XPT_RAVE :: EMM_DATA_ID_1 :: EMM_DATA_ID_1 [31:00] */ -#define BCHP_XPT_RAVE_EMM_DATA_ID_1_EMM_DATA_ID_1_MASK 0xffffffff -#define BCHP_XPT_RAVE_EMM_DATA_ID_1_EMM_DATA_ID_1_SHIFT 0 - -/*************************************************************************** - *EMM_DATA_ID_2 - TPIT EMM_DATA_ID_2 Register (NDS only) - ***************************************************************************/ -/* XPT_RAVE :: EMM_DATA_ID_2 :: EMM_DATA_ID_2 [31:00] */ -#define BCHP_XPT_RAVE_EMM_DATA_ID_2_EMM_DATA_ID_2_MASK 0xffffffff -#define BCHP_XPT_RAVE_EMM_DATA_ID_2_EMM_DATA_ID_2_SHIFT 0 - -/*************************************************************************** - *EMM_DATA_ID_3 - TPIT EMM_DATA_ID_3 Register (NDS only) - ***************************************************************************/ -/* XPT_RAVE :: EMM_DATA_ID_3 :: EMM_DATA_ID_3 [31:00] */ -#define BCHP_XPT_RAVE_EMM_DATA_ID_3_EMM_DATA_ID_3_MASK 0xffffffff -#define BCHP_XPT_RAVE_EMM_DATA_ID_3_EMM_DATA_ID_3_SHIFT 0 - -/*************************************************************************** - *EMM_MASK_ID_1 - TPIT EMM_MASK_ID_1 Register (NDS only) - ***************************************************************************/ -/* XPT_RAVE :: EMM_MASK_ID_1 :: EMM_DATA_MASK_ID_1 [31:00] */ -#define BCHP_XPT_RAVE_EMM_MASK_ID_1_EMM_DATA_MASK_ID_1_MASK 0xffffffff -#define BCHP_XPT_RAVE_EMM_MASK_ID_1_EMM_DATA_MASK_ID_1_SHIFT 0 - -/*************************************************************************** - *EMM_MASK_ID_2 - TPIT EMM_MASK_ID_2 Register (NDS only) - ***************************************************************************/ -/* XPT_RAVE :: EMM_MASK_ID_2 :: EMM_DATA_MASK_ID_2 [31:00] */ -#define BCHP_XPT_RAVE_EMM_MASK_ID_2_EMM_DATA_MASK_ID_2_MASK 0xffffffff -#define BCHP_XPT_RAVE_EMM_MASK_ID_2_EMM_DATA_MASK_ID_2_SHIFT 0 - -/*************************************************************************** - *EMM_MASK_ID_3 - TPIT EMM_MASK_ID_3 Register (NDS only) - ***************************************************************************/ -/* XPT_RAVE :: EMM_MASK_ID_3 :: EMM_DATA_MASK_ID_3 [31:00] */ -#define BCHP_XPT_RAVE_EMM_MASK_ID_3_EMM_DATA_MASK_ID_3_MASK 0xffffffff -#define BCHP_XPT_RAVE_EMM_MASK_ID_3_EMM_DATA_MASK_ID_3_SHIFT 0 - -/*************************************************************************** - *TPIT_TIME_TICK - TPIT Time Tick Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT_TIME_TICK :: reserved0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT_TIME_TICK_reserved0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT_TIME_TICK_reserved0_SHIFT 24 - -/* XPT_RAVE :: TPIT_TIME_TICK :: TPIT_TIME_TICK [23:00] */ -#define BCHP_XPT_RAVE_TPIT_TIME_TICK_TPIT_TIME_TICK_MASK 0x00ffffff -#define BCHP_XPT_RAVE_TPIT_TIME_TICK_TPIT_TIME_TICK_SHIFT 0 - -/*************************************************************************** - *TPIT_PKT_TIMEOUT - TPIT Time Packet Timeout Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT_PKT_TIMEOUT :: reserved0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_reserved0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_reserved0_SHIFT 24 - -/* XPT_RAVE :: TPIT_PKT_TIMEOUT :: TPIT_PKT_TIMEOUT [23:00] */ -#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_TPIT_PKT_TIMEOUT_MASK 0x00ffffff -#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_TPIT_PKT_TIMEOUT_SHIFT 0 - -/*************************************************************************** - *TPIT_EVE_TIMEOUT - TPIT Time Event Timeout Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT_EVE_TIMEOUT :: reserved0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_reserved0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_reserved0_SHIFT 24 - -/* XPT_RAVE :: TPIT_EVE_TIMEOUT :: TPIT_EVE_TIMEOUT [23:00] */ -#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_TPIT_EVE_TIMEOUT_MASK 0x00ffffff -#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_TPIT_EVE_TIMEOUT_SHIFT 0 - -/*************************************************************************** - *TPIT0_PID_TABLE%i - TPIT0 PID Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_BASE 0x0021a000 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT0_PID_TABLE%i - TPIT0 PID Table 0..15 - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_PID_TABLEi :: reserved_for_eco0 [31:21] */ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_HD [20:17] */ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_MASK 0x001e0000 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_SHIFT 17 - -/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT0_PID_TABLEi :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 - -/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 - -/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_PID [12:00] */ -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PID_MASK 0x00001fff -#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PID_SHIFT 0 - - -/*************************************************************************** - *TPIT0_PAR_TABLE%i - TPIT0 Parse Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_BASE 0x0021a040 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT0_PAR_TABLE%i - TPIT0 Parse Table 0..15 - ***************************************************************************/ -/* union - case MPEG [31:00] */ -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved1_SHIFT 13 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved0_SHIFT 2 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 - -/* union - case DIRECTV [31:00] */ -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 - -/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 - - -/*************************************************************************** - *TPIT1_PID_TABLE%i - TPIT1 PID Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_BASE 0x0021a080 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT1_PID_TABLE%i - TPIT1 PID Table 0..15 - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_PID_TABLEi :: reserved_for_eco0 [31:21] */ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_HD [20:17] */ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_MASK 0x001e0000 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_SHIFT 17 - -/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT1_PID_TABLEi :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 - -/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 - -/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_PID [12:00] */ -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PID_MASK 0x00001fff -#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PID_SHIFT 0 - - -/*************************************************************************** - *TPIT1_PAR_TABLE%i - TPIT1 Parse Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_BASE 0x0021a0c0 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT1_PAR_TABLE%i - TPIT1 Parse Table 0..15 - ***************************************************************************/ -/* union - case MPEG [31:00] */ -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved1_SHIFT 13 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved0_SHIFT 2 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 - -/* union - case DIRECTV [31:00] */ -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 - -/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 - - -/*************************************************************************** - *TPIT2_PID_TABLE%i - TPIT2 PID Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_BASE 0x0021a100 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT2_PID_TABLE%i - TPIT2 PID Table 0..15 - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_PID_TABLEi :: reserved_for_eco0 [31:21] */ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_HD [20:17] */ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_MASK 0x001e0000 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_SHIFT 17 - -/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT2_PID_TABLEi :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 - -/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 - -/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_PID [12:00] */ -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PID_MASK 0x00001fff -#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PID_SHIFT 0 - - -/*************************************************************************** - *TPIT2_PAR_TABLE%i - TPIT2 Parse Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_BASE 0x0021a140 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT2_PAR_TABLE%i - TPIT2 Parse Table 0..15 - ***************************************************************************/ -/* union - case MPEG [31:00] */ -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved1_SHIFT 13 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved0_SHIFT 2 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 - -/* union - case DIRECTV [31:00] */ -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 - -/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 - - -/*************************************************************************** - *TPIT3_PID_TABLE%i - TPIT3 PID Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_BASE 0x0021a180 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT3_PID_TABLE%i - TPIT3 PID Table 0..15 - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_PID_TABLEi :: reserved_for_eco0 [31:21] */ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_HD [20:17] */ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_MASK 0x001e0000 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_SHIFT 17 - -/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT3_PID_TABLEi :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 - -/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 - -/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_PID [12:00] */ -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PID_MASK 0x00001fff -#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PID_SHIFT 0 - - -/*************************************************************************** - *TPIT3_PAR_TABLE%i - TPIT3 Parse Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_BASE 0x0021a1c0 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT3_PAR_TABLE%i - TPIT3 Parse Table 0..15 - ***************************************************************************/ -/* union - case MPEG [31:00] */ -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved1_SHIFT 13 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved0_SHIFT 2 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 - -/* union - case DIRECTV [31:00] */ -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 - -/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 - - -/*************************************************************************** - *TPIT4_PID_TABLE%i - TPIT4 PID Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_BASE 0x0021a200 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT4_PID_TABLE%i - TPIT4 PID Table 0..15 - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_PID_TABLEi :: reserved_for_eco0 [31:21] */ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_HD [20:17] */ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_MASK 0x001e0000 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_SHIFT 17 - -/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT4_PID_TABLEi :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 - -/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 - -/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_PID [12:00] */ -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PID_MASK 0x00001fff -#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PID_SHIFT 0 - - -/*************************************************************************** - *TPIT4_PAR_TABLE%i - TPIT4 Parse Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_BASE 0x0021a240 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT4_PAR_TABLE%i - TPIT4 Parse Table 0..15 - ***************************************************************************/ -/* union - case MPEG [31:00] */ -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved1_SHIFT 13 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved0_SHIFT 2 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 - -/* union - case DIRECTV [31:00] */ -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 - -/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 - - -/*************************************************************************** - *TPIT5_PID_TABLE%i - TPIT5 PID Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_BASE 0x0021a280 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT5_PID_TABLE%i - TPIT5 PID Table 0..15 - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_PID_TABLEi :: reserved_for_eco0 [31:21] */ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco0_SHIFT 21 - -/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_HD [20:17] */ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_MASK 0x001e0000 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_SHIFT 17 - -/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT5_PID_TABLEi :: reserved_for_eco1 [15:15] */ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco1_SHIFT 15 - -/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 - -/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 - -/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_PID [12:00] */ -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PID_MASK 0x00001fff -#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PID_SHIFT 0 - - -/*************************************************************************** - *TPIT5_PAR_TABLE%i - TPIT5 Parse Table 0..15 - ***************************************************************************/ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_BASE 0x0021a2c0 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_START 0 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_END 15 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *TPIT5_PAR_TABLE%i - TPIT5 Parse Table 0..15 - ***************************************************************************/ -/* union - case MPEG [31:00] */ -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved1_SHIFT 13 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved0_SHIFT 2 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 - -/* union - case DIRECTV [31:00] */ -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 - -/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 - - -/*************************************************************************** - *TPIT0_CTRL1 - TPIT 0 Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_CTRL1 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: TPIT0_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 - -/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 - -/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 - -/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_PCR_MODE [04:04] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_PCR_MODE_SHIFT 4 - -/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 - -/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 - -/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 - -/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 - -/*************************************************************************** - *TPIT0_COR1 - TPIT 0 Corrupt Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_COR1 :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT0_COR1_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT0_COR1_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_BYTE [23:16] */ -#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_BYTE_SHIFT 16 - -/* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_START [15:08] */ -#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_START_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_START_SHIFT 8 - -/* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_END [07:00] */ -#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_END_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_END_SHIFT 0 - -/*************************************************************************** - *TPIT0_TID - TPIT TID Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_TID :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT0_TID :: ECM_TID_ODD [23:16] */ -#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_ODD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_ODD_SHIFT 16 - -/* XPT_RAVE :: TPIT0_TID :: ECM_TID_EVEN [15:08] */ -#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_EVEN_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_EVEN_SHIFT 8 - -/* XPT_RAVE :: TPIT0_TID :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: TPIT0_TID :: EMM_TID [03:00] */ -#define BCHP_XPT_RAVE_TPIT0_TID_EMM_TID_MASK 0x0000000f -#define BCHP_XPT_RAVE_TPIT0_TID_EMM_TID_SHIFT 0 - -/*************************************************************************** - *TPIT0_TID2 - TPIT TID Register 2 - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_ODD3 [31:24] */ -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD3_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD3_SHIFT 24 - -/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_EVEN3 [23:16] */ -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN3_SHIFT 16 - -/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_ODD2 [15:08] */ -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD2_SHIFT 8 - -/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_EVEN2 [07:00] */ -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN2_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN2_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE0 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE0_TPIT_TRACK_STATE0_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE1 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE1_TPIT_TRACK_STATE1_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE2 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE2_TPIT_TRACK_STATE2_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE2a - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE2b - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE2c - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE2d - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE3 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE3_TPIT_TRACK_STATE3_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE4 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE4 :: TPIT_CUR_PCR [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE4_TPIT_CUR_PCR_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE4_TPIT_CUR_PCR_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE5 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE6 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE7 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE7 :: reserved_for_eco0 [31:20] */ -#define BCHP_XPT_RAVE_TPIT0_STATE7_reserved_for_eco0_MASK 0xfff00000 -#define BCHP_XPT_RAVE_TPIT0_STATE7_reserved_for_eco0_SHIFT 20 - -/* XPT_RAVE :: TPIT0_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ -#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 -#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 - -/* XPT_RAVE :: TPIT0_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE8 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT0_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 - -/*************************************************************************** - *TPIT0_STATE9 - TPIT 0 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT0_STATE9 :: reserved_for_eco0 [31:10] */ -#define BCHP_XPT_RAVE_TPIT0_STATE9_reserved_for_eco0_MASK 0xfffffc00 -#define BCHP_XPT_RAVE_TPIT0_STATE9_reserved_for_eco0_SHIFT 10 - -/* XPT_RAVE :: TPIT0_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT0_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT0_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 - -/*************************************************************************** - *TPIT1_CTRL1 - TPIT 1 Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_CTRL1 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: TPIT1_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 - -/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 - -/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 - -/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_PCR_MODE [04:04] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_PCR_MODE_SHIFT 4 - -/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 - -/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 - -/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 - -/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 - -/*************************************************************************** - *TPIT1_COR1 - TPIT 1 Corrupt Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_COR1 :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT1_COR1_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT1_COR1_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_BYTE [23:16] */ -#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_BYTE_SHIFT 16 - -/* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_START [15:08] */ -#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_START_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_START_SHIFT 8 - -/* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_END [07:00] */ -#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_END_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_END_SHIFT 0 - -/*************************************************************************** - *TPIT1_TID - TPIT TID Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_TID :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT1_TID :: ECM_TID_ODD [23:16] */ -#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_ODD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_ODD_SHIFT 16 - -/* XPT_RAVE :: TPIT1_TID :: ECM_TID_EVEN [15:08] */ -#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_EVEN_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_EVEN_SHIFT 8 - -/* XPT_RAVE :: TPIT1_TID :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: TPIT1_TID :: EMM_TID [03:00] */ -#define BCHP_XPT_RAVE_TPIT1_TID_EMM_TID_MASK 0x0000000f -#define BCHP_XPT_RAVE_TPIT1_TID_EMM_TID_SHIFT 0 - -/*************************************************************************** - *TPIT1_TID2 - TPIT TID Register 2 - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_ODD3 [31:24] */ -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD3_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD3_SHIFT 24 - -/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_EVEN3 [23:16] */ -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN3_SHIFT 16 - -/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_ODD2 [15:08] */ -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD2_SHIFT 8 - -/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_EVEN2 [07:00] */ -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN2_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN2_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE0 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE0_TPIT_TRACK_STATE0_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE1 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE1_TPIT_TRACK_STATE1_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE2 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE2_TPIT_TRACK_STATE2_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE2a - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE2b - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE2c - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE2d - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE3 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE3_TPIT_TRACK_STATE3_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE4 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE4 :: TPIT_CUR_PCR [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE4_TPIT_CUR_PCR_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE4_TPIT_CUR_PCR_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE5 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE6 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE7 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE7 :: reserved_for_eco0 [31:20] */ -#define BCHP_XPT_RAVE_TPIT1_STATE7_reserved_for_eco0_MASK 0xfff00000 -#define BCHP_XPT_RAVE_TPIT1_STATE7_reserved_for_eco0_SHIFT 20 - -/* XPT_RAVE :: TPIT1_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ -#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 -#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 - -/* XPT_RAVE :: TPIT1_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE8 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT1_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 - -/*************************************************************************** - *TPIT1_STATE9 - TPIT 1 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT1_STATE9 :: reserved_for_eco0 [31:10] */ -#define BCHP_XPT_RAVE_TPIT1_STATE9_reserved_for_eco0_MASK 0xfffffc00 -#define BCHP_XPT_RAVE_TPIT1_STATE9_reserved_for_eco0_SHIFT 10 - -/* XPT_RAVE :: TPIT1_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT1_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT1_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 - -/*************************************************************************** - *TPIT2_CTRL1 - TPIT 2 Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_CTRL1 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: TPIT2_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 - -/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 - -/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 - -/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_PCR_MODE [04:04] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_PCR_MODE_SHIFT 4 - -/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 - -/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 - -/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 - -/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 - -/*************************************************************************** - *TPIT2_COR1 - TPIT 2 Corrupt Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_COR1 :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT2_COR1_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT2_COR1_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_BYTE [23:16] */ -#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_BYTE_SHIFT 16 - -/* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_START [15:08] */ -#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_START_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_START_SHIFT 8 - -/* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_END [07:00] */ -#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_END_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_END_SHIFT 0 - -/*************************************************************************** - *TPIT2_TID - TPIT TID Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_TID :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT2_TID :: ECM_TID_ODD [23:16] */ -#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_ODD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_ODD_SHIFT 16 - -/* XPT_RAVE :: TPIT2_TID :: ECM_TID_EVEN [15:08] */ -#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_EVEN_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_EVEN_SHIFT 8 - -/* XPT_RAVE :: TPIT2_TID :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: TPIT2_TID :: EMM_TID [03:00] */ -#define BCHP_XPT_RAVE_TPIT2_TID_EMM_TID_MASK 0x0000000f -#define BCHP_XPT_RAVE_TPIT2_TID_EMM_TID_SHIFT 0 - -/*************************************************************************** - *TPIT2_TID2 - TPIT TID Register 2 - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_ODD3 [31:24] */ -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD3_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD3_SHIFT 24 - -/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_EVEN3 [23:16] */ -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN3_SHIFT 16 - -/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_ODD2 [15:08] */ -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD2_SHIFT 8 - -/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_EVEN2 [07:00] */ -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN2_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN2_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE0 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE0_TPIT_TRACK_STATE0_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE1 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE1_TPIT_TRACK_STATE1_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE2 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE2_TPIT_TRACK_STATE2_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE2a - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE2b - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE2c - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE2d - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE3 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE3_TPIT_TRACK_STATE3_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE4 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE4 :: TPIT_CUR_PCR [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE4_TPIT_CUR_PCR_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE4_TPIT_CUR_PCR_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE5 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE6 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE7 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE7 :: reserved_for_eco0 [31:20] */ -#define BCHP_XPT_RAVE_TPIT2_STATE7_reserved_for_eco0_MASK 0xfff00000 -#define BCHP_XPT_RAVE_TPIT2_STATE7_reserved_for_eco0_SHIFT 20 - -/* XPT_RAVE :: TPIT2_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ -#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 -#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 - -/* XPT_RAVE :: TPIT2_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE8 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT2_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 - -/*************************************************************************** - *TPIT2_STATE9 - TPIT 2 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT2_STATE9 :: reserved_for_eco0 [31:10] */ -#define BCHP_XPT_RAVE_TPIT2_STATE9_reserved_for_eco0_MASK 0xfffffc00 -#define BCHP_XPT_RAVE_TPIT2_STATE9_reserved_for_eco0_SHIFT 10 - -/* XPT_RAVE :: TPIT2_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT2_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT2_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 - -/*************************************************************************** - *TPIT3_CTRL1 - TPIT 3 Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_CTRL1 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: TPIT3_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 - -/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 - -/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 - -/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_PCR_MODE [04:04] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_PCR_MODE_SHIFT 4 - -/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 - -/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 - -/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 - -/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 - -/*************************************************************************** - *TPIT3_COR1 - TPIT 3 Corrupt Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_COR1 :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT3_COR1_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT3_COR1_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_BYTE [23:16] */ -#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_BYTE_SHIFT 16 - -/* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_START [15:08] */ -#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_START_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_START_SHIFT 8 - -/* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_END [07:00] */ -#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_END_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_END_SHIFT 0 - -/*************************************************************************** - *TPIT3_TID - TPIT TID Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_TID :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT3_TID :: ECM_TID_ODD [23:16] */ -#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_ODD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_ODD_SHIFT 16 - -/* XPT_RAVE :: TPIT3_TID :: ECM_TID_EVEN [15:08] */ -#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_EVEN_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_EVEN_SHIFT 8 - -/* XPT_RAVE :: TPIT3_TID :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: TPIT3_TID :: EMM_TID [03:00] */ -#define BCHP_XPT_RAVE_TPIT3_TID_EMM_TID_MASK 0x0000000f -#define BCHP_XPT_RAVE_TPIT3_TID_EMM_TID_SHIFT 0 - -/*************************************************************************** - *TPIT3_TID2 - TPIT TID Register 2 - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_ODD3 [31:24] */ -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD3_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD3_SHIFT 24 - -/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_EVEN3 [23:16] */ -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN3_SHIFT 16 - -/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_ODD2 [15:08] */ -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD2_SHIFT 8 - -/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_EVEN2 [07:00] */ -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN2_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN2_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE0 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE0_TPIT_TRACK_STATE0_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE1 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE1_TPIT_TRACK_STATE1_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE2 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE2_TPIT_TRACK_STATE2_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE2a - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE2b - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE2c - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE2d - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE3 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE3_TPIT_TRACK_STATE3_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE4 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE4 :: TPIT_CUR_PCR [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE4_TPIT_CUR_PCR_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE4_TPIT_CUR_PCR_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE5 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE6 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE7 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE7 :: reserved_for_eco0 [31:20] */ -#define BCHP_XPT_RAVE_TPIT3_STATE7_reserved_for_eco0_MASK 0xfff00000 -#define BCHP_XPT_RAVE_TPIT3_STATE7_reserved_for_eco0_SHIFT 20 - -/* XPT_RAVE :: TPIT3_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ -#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 -#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 - -/* XPT_RAVE :: TPIT3_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE8 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT3_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 - -/*************************************************************************** - *TPIT3_STATE9 - TPIT 3 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT3_STATE9 :: reserved_for_eco0 [31:10] */ -#define BCHP_XPT_RAVE_TPIT3_STATE9_reserved_for_eco0_MASK 0xfffffc00 -#define BCHP_XPT_RAVE_TPIT3_STATE9_reserved_for_eco0_SHIFT 10 - -/* XPT_RAVE :: TPIT3_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT3_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT3_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 - -/*************************************************************************** - *TPIT4_CTRL1 - TPIT 4 Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_CTRL1 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: TPIT4_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 - -/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 - -/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 - -/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_PCR_MODE [04:04] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_PCR_MODE_SHIFT 4 - -/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 - -/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 - -/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 - -/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 - -/*************************************************************************** - *TPIT4_COR1 - TPIT 4 Corrupt Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_COR1 :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT4_COR1_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT4_COR1_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_BYTE [23:16] */ -#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_BYTE_SHIFT 16 - -/* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_START [15:08] */ -#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_START_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_START_SHIFT 8 - -/* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_END [07:00] */ -#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_END_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_END_SHIFT 0 - -/*************************************************************************** - *TPIT4_TID - TPIT TID Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_TID :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT4_TID :: ECM_TID_ODD [23:16] */ -#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_ODD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_ODD_SHIFT 16 - -/* XPT_RAVE :: TPIT4_TID :: ECM_TID_EVEN [15:08] */ -#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_EVEN_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_EVEN_SHIFT 8 - -/* XPT_RAVE :: TPIT4_TID :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: TPIT4_TID :: EMM_TID [03:00] */ -#define BCHP_XPT_RAVE_TPIT4_TID_EMM_TID_MASK 0x0000000f -#define BCHP_XPT_RAVE_TPIT4_TID_EMM_TID_SHIFT 0 - -/*************************************************************************** - *TPIT4_TID2 - TPIT TID Register 2 - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_ODD3 [31:24] */ -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD3_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD3_SHIFT 24 - -/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_EVEN3 [23:16] */ -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN3_SHIFT 16 - -/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_ODD2 [15:08] */ -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD2_SHIFT 8 - -/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_EVEN2 [07:00] */ -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN2_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN2_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE0 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE0_TPIT_TRACK_STATE0_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE1 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE1_TPIT_TRACK_STATE1_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE2 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE2_TPIT_TRACK_STATE2_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE2a - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE2b - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE2c - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE2d - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE3 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE3_TPIT_TRACK_STATE3_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE4 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE4 :: TPIT_CUR_PCR [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE4_TPIT_CUR_PCR_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE4_TPIT_CUR_PCR_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE5 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE6 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE7 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE7 :: reserved_for_eco0 [31:20] */ -#define BCHP_XPT_RAVE_TPIT4_STATE7_reserved_for_eco0_MASK 0xfff00000 -#define BCHP_XPT_RAVE_TPIT4_STATE7_reserved_for_eco0_SHIFT 20 - -/* XPT_RAVE :: TPIT4_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ -#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 -#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 - -/* XPT_RAVE :: TPIT4_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE8 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT4_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 - -/*************************************************************************** - *TPIT4_STATE9 - TPIT 4 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT4_STATE9 :: reserved_for_eco0 [31:10] */ -#define BCHP_XPT_RAVE_TPIT4_STATE9_reserved_for_eco0_MASK 0xfffffc00 -#define BCHP_XPT_RAVE_TPIT4_STATE9_reserved_for_eco0_SHIFT 10 - -/* XPT_RAVE :: TPIT4_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT4_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT4_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 - -/*************************************************************************** - *TPIT5_CTRL1 - TPIT 5 Control Register 1 - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_CTRL1 :: reserved_for_eco0 [31:09] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_reserved_for_eco0_MASK 0xfffffe00 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_reserved_for_eco0_SHIFT 9 - -/* XPT_RAVE :: TPIT5_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 - -/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 - -/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 - -/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_PCR_MODE [04:04] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_PCR_MODE_SHIFT 4 - -/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 - -/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 - -/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 - -/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 -#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 - -/*************************************************************************** - *TPIT5_COR1 - TPIT 5 Corrupt Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_COR1 :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT5_COR1_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT5_COR1_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_BYTE [23:16] */ -#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_BYTE_SHIFT 16 - -/* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_START [15:08] */ -#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_START_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_START_SHIFT 8 - -/* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_END [07:00] */ -#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_END_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_END_SHIFT 0 - -/*************************************************************************** - *TPIT5_TID - TPIT TID Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_TID :: reserved_for_eco0 [31:24] */ -#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco0_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco0_SHIFT 24 - -/* XPT_RAVE :: TPIT5_TID :: ECM_TID_ODD [23:16] */ -#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_ODD_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_ODD_SHIFT 16 - -/* XPT_RAVE :: TPIT5_TID :: ECM_TID_EVEN [15:08] */ -#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_EVEN_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_EVEN_SHIFT 8 - -/* XPT_RAVE :: TPIT5_TID :: reserved_for_eco1 [07:04] */ -#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco1_MASK 0x000000f0 -#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco1_SHIFT 4 - -/* XPT_RAVE :: TPIT5_TID :: EMM_TID [03:00] */ -#define BCHP_XPT_RAVE_TPIT5_TID_EMM_TID_MASK 0x0000000f -#define BCHP_XPT_RAVE_TPIT5_TID_EMM_TID_SHIFT 0 - -/*************************************************************************** - *TPIT5_TID2 - TPIT TID Register 2 - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_ODD3 [31:24] */ -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD3_MASK 0xff000000 -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD3_SHIFT 24 - -/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_EVEN3 [23:16] */ -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN3_SHIFT 16 - -/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_ODD2 [15:08] */ -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD2_MASK 0x0000ff00 -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD2_SHIFT 8 - -/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_EVEN2 [07:00] */ -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN2_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN2_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE0 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE0_TPIT_TRACK_STATE0_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE1 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE1_TPIT_TRACK_STATE1_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE2 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE2_TPIT_TRACK_STATE2_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE2a - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE2b - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE2c - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE2d - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE3 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE3_TPIT_TRACK_STATE3_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE4 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE4 :: TPIT_CUR_PCR [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE4_TPIT_CUR_PCR_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE4_TPIT_CUR_PCR_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE5 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE6 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE7 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE7 :: reserved_for_eco0 [31:20] */ -#define BCHP_XPT_RAVE_TPIT5_STATE7_reserved_for_eco0_MASK 0xfff00000 -#define BCHP_XPT_RAVE_TPIT5_STATE7_reserved_for_eco0_SHIFT 20 - -/* XPT_RAVE :: TPIT5_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ -#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 -#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 - -/* XPT_RAVE :: TPIT5_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE8 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff -#define BCHP_XPT_RAVE_TPIT5_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 - -/*************************************************************************** - *TPIT5_STATE9 - TPIT 5 State Register - ***************************************************************************/ -/* XPT_RAVE :: TPIT5_STATE9 :: reserved_for_eco0 [31:10] */ -#define BCHP_XPT_RAVE_TPIT5_STATE9_reserved_for_eco0_MASK 0xfffffc00 -#define BCHP_XPT_RAVE_TPIT5_STATE9_reserved_for_eco0_SHIFT 10 - -/* XPT_RAVE :: TPIT5_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ -#define BCHP_XPT_RAVE_TPIT5_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff -#define BCHP_XPT_RAVE_TPIT5_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT0 - TPIT State Register for Context 0 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT0 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT0 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT1 - TPIT State Register for Context 1 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT1 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT1 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT2 - TPIT State Register for Context 2 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT2 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT2 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT3 - TPIT State Register for Context 3 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT3 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT3 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT4 - TPIT State Register for Context 4 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT4 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT4 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT5 - TPIT State Register for Context 5 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT5 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT5 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT6 - TPIT State Register for Context 6 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT6 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT6 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT7 - TPIT State Register for Context 7 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT7 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT7 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT8 - TPIT State Register for Context 8 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT8 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT8 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT9 - TPIT State Register for Context 9 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT9 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT9 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT10 - TPIT State Register for Context 10 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT10 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT10 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT11 - TPIT State Register for Context 11 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT11 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT11 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT12 - TPIT State Register for Context 12 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT12 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT12 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT13 - TPIT State Register for Context 13 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT13 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT13 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT14 - TPIT State Register for Context 14 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT14 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT14 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT15 - TPIT State Register for Context 15 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT15 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT15 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT16 - TPIT State Register for Context 16 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT16 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT16 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT17 - TPIT State Register for Context 17 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT17 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT17 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT18 - TPIT State Register for Context 18 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT18 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT18 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT19 - TPIT State Register for Context 19 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT19 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT19 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT20 - TPIT State Register for Context 20 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT20 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT20 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT21 - TPIT State Register for Context 21 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT21 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT21 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT22 - TPIT State Register for Context 22 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT22 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT22 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -/*************************************************************************** - *TPIT_STATE_CONTEXT23 - TPIT State Register for Context 23 - ***************************************************************************/ -/* XPT_RAVE :: TPIT_STATE_CONTEXT23 :: reserved0 [31:08] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_reserved0_MASK 0xffffff00 -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_reserved0_SHIFT 8 - -/* XPT_RAVE :: TPIT_STATE_CONTEXT23 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff -#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 - -#endif /* #ifndef BCHP_XPT_RAVE_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xmemif.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xmemif.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xmemif.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xmemif.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,230 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_xmemif.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:27p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:43:10 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xmemif.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:27p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_XMEMIF_H__ -#define BCHP_XPT_XMEMIF_H__ - -/*************************************************************************** - *XPT_XMEMIF - XPT XMEMIF Control Registers - ***************************************************************************/ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB 0x00202008 /* SCB Write Client select register for RAVE CDB */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB 0x0020200c /* SCB Write Client select register for RAVE ITB */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE 0x00202040 /* SCB Write Client Arbiter Mode Control */ -#define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE 0x00202044 /* SCB Read Client Arbiter Mode Control */ -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0 0x00202048 /* TM Control */ -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1 0x0020204c /* TM Control */ -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0 0x00202050 /* TM Control */ -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1 0x00202054 /* TM Control */ -#define BCHP_XPT_XMEMIF_WR_DEBUG 0x00202058 /* Debug and Test register for XMEMIF write */ -#define BCHP_XPT_XMEMIF_RD_DEBUG 0x0020205c /* Debug and Test register for XMEMIF read */ -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG 0x00202060 /* Interrupt Status Register */ -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN 0x00202064 /* Interrupt Status Enable Register */ - -/*************************************************************************** - *SCB_WR_ARB_SEL_RAVE_CDB - SCB Write Client select register for RAVE CDB - ***************************************************************************/ -/* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_CDB :: reserved0 [31:02] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_reserved0_MASK 0xfffffffc -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_reserved0_SHIFT 2 - -/* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_CDB :: SCB_WR_CLIENT_SEL [01:00] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_SCB_WR_CLIENT_SEL_MASK 0x00000003 -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_SCB_WR_CLIENT_SEL_SHIFT 0 - -/*************************************************************************** - *SCB_WR_ARB_SEL_RAVE_ITB - SCB Write Client select register for RAVE ITB - ***************************************************************************/ -/* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_ITB :: reserved0 [31:02] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_reserved0_MASK 0xfffffffc -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_reserved0_SHIFT 2 - -/* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_ITB :: SCB_WR_CLIENT_SEL [01:00] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_SCB_WR_CLIENT_SEL_MASK 0x00000003 -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_SCB_WR_CLIENT_SEL_SHIFT 0 - -/*************************************************************************** - *SCB_WR_ARB_MODE - SCB Write Client Arbiter Mode Control - ***************************************************************************/ -/* XPT_XMEMIF :: SCB_WR_ARB_MODE :: reserved0 [31:10] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved0_MASK 0xfffffc00 -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved0_SHIFT 10 - -/* XPT_XMEMIF :: SCB_WR_ARB_MODE :: SCB_WR_1_ARB_MODE [09:08] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_1_ARB_MODE_MASK 0x00000300 -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_1_ARB_MODE_SHIFT 8 - -/* XPT_XMEMIF :: SCB_WR_ARB_MODE :: reserved1 [07:02] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved1_MASK 0x000000fc -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved1_SHIFT 2 - -/* XPT_XMEMIF :: SCB_WR_ARB_MODE :: SCB_WR_0_ARB_MODE [01:00] */ -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_0_ARB_MODE_MASK 0x00000003 -#define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_0_ARB_MODE_SHIFT 0 - -/*************************************************************************** - *SCB_RD_ARB_MODE - SCB Read Client Arbiter Mode Control - ***************************************************************************/ -/* XPT_XMEMIF :: SCB_RD_ARB_MODE :: reserved0 [31:02] */ -#define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_reserved0_MASK 0xfffffffc -#define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_reserved0_SHIFT 2 - -/* XPT_XMEMIF :: SCB_RD_ARB_MODE :: SCB_RD_0_ARB_MODE [01:00] */ -#define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_SCB_RD_0_ARB_MODE_MASK 0x00000003 -#define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_SCB_RD_0_ARB_MODE_SHIFT 0 - -/*************************************************************************** - *TM_SCB_WR_DBUF0 - TM Control - ***************************************************************************/ -/* XPT_XMEMIF :: TM_SCB_WR_DBUF0 :: reserved0 [31:08] */ -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_reserved0_MASK 0xffffff00 -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_reserved0_SHIFT 8 - -/* XPT_XMEMIF :: TM_SCB_WR_DBUF0 :: TM [07:00] */ -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_TM_MASK 0x000000ff -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_TM_SHIFT 0 - -/*************************************************************************** - *TM_SCB_WR_DBUF1 - TM Control - ***************************************************************************/ -/* XPT_XMEMIF :: TM_SCB_WR_DBUF1 :: reserved0 [31:08] */ -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_reserved0_MASK 0xffffff00 -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_reserved0_SHIFT 8 - -/* XPT_XMEMIF :: TM_SCB_WR_DBUF1 :: TM [07:00] */ -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_TM_MASK 0x000000ff -#define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_TM_SHIFT 0 - -/*************************************************************************** - *TM_SCB_RD_DBUF0 - TM Control - ***************************************************************************/ -/* XPT_XMEMIF :: TM_SCB_RD_DBUF0 :: reserved0 [31:08] */ -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_reserved0_MASK 0xffffff00 -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_reserved0_SHIFT 8 - -/* XPT_XMEMIF :: TM_SCB_RD_DBUF0 :: TM [07:00] */ -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_TM_MASK 0x000000ff -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_TM_SHIFT 0 - -/*************************************************************************** - *TM_SCB_RD_DBUF1 - TM Control - ***************************************************************************/ -/* XPT_XMEMIF :: TM_SCB_RD_DBUF1 :: reserved0 [31:08] */ -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_reserved0_MASK 0xffffff00 -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_reserved0_SHIFT 8 - -/* XPT_XMEMIF :: TM_SCB_RD_DBUF1 :: TM [07:00] */ -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_TM_MASK 0x000000ff -#define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_TM_SHIFT 0 - -/*************************************************************************** - *WR_DEBUG - Debug and Test register for XMEMIF write - ***************************************************************************/ -/* XPT_XMEMIF :: WR_DEBUG :: reserved0 [31:17] */ -#define BCHP_XPT_XMEMIF_WR_DEBUG_reserved0_MASK 0xfffe0000 -#define BCHP_XPT_XMEMIF_WR_DEBUG_reserved0_SHIFT 17 - -/* XPT_XMEMIF :: WR_DEBUG :: SOFT_RESET [16:16] */ -#define BCHP_XPT_XMEMIF_WR_DEBUG_SOFT_RESET_MASK 0x00010000 -#define BCHP_XPT_XMEMIF_WR_DEBUG_SOFT_RESET_SHIFT 16 - -/* XPT_XMEMIF :: WR_DEBUG :: reserved1 [15:02] */ -#define BCHP_XPT_XMEMIF_WR_DEBUG_reserved1_MASK 0x0000fffc -#define BCHP_XPT_XMEMIF_WR_DEBUG_reserved1_SHIFT 2 - -/* XPT_XMEMIF :: WR_DEBUG :: WR_LCIF_ERROR [01:00] */ -#define BCHP_XPT_XMEMIF_WR_DEBUG_WR_LCIF_ERROR_MASK 0x00000003 -#define BCHP_XPT_XMEMIF_WR_DEBUG_WR_LCIF_ERROR_SHIFT 0 - -/*************************************************************************** - *RD_DEBUG - Debug and Test register for XMEMIF read - ***************************************************************************/ -/* XPT_XMEMIF :: RD_DEBUG :: reserved0 [31:17] */ -#define BCHP_XPT_XMEMIF_RD_DEBUG_reserved0_MASK 0xfffe0000 -#define BCHP_XPT_XMEMIF_RD_DEBUG_reserved0_SHIFT 17 - -/* XPT_XMEMIF :: RD_DEBUG :: SOFT_RESET [16:16] */ -#define BCHP_XPT_XMEMIF_RD_DEBUG_SOFT_RESET_MASK 0x00010000 -#define BCHP_XPT_XMEMIF_RD_DEBUG_SOFT_RESET_SHIFT 16 - -/* XPT_XMEMIF :: RD_DEBUG :: reserved1 [15:03] */ -#define BCHP_XPT_XMEMIF_RD_DEBUG_reserved1_MASK 0x0000fff8 -#define BCHP_XPT_XMEMIF_RD_DEBUG_reserved1_SHIFT 3 - -/* XPT_XMEMIF :: RD_DEBUG :: RD_LCIF_ERROR [02:00] */ -#define BCHP_XPT_XMEMIF_RD_DEBUG_RD_LCIF_ERROR_MASK 0x00000007 -#define BCHP_XPT_XMEMIF_RD_DEBUG_RD_LCIF_ERROR_SHIFT 0 - -/*************************************************************************** - *INTR_STATUS_REG - Interrupt Status Register - ***************************************************************************/ -/* XPT_XMEMIF :: INTR_STATUS_REG :: reserved0 [31:02] */ -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_reserved0_MASK 0xfffffffc -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_reserved0_SHIFT 2 - -/* XPT_XMEMIF :: INTR_STATUS_REG :: XMEMIF_WRITE_ERROR [01:01] */ -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_WRITE_ERROR_MASK 0x00000002 -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_WRITE_ERROR_SHIFT 1 - -/* XPT_XMEMIF :: INTR_STATUS_REG :: XMEMIF_READ_ERROR [00:00] */ -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_READ_ERROR_MASK 0x00000001 -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_READ_ERROR_SHIFT 0 - -/*************************************************************************** - *INTR_STATUS_REG_EN - Interrupt Status Enable Register - ***************************************************************************/ -/* XPT_XMEMIF :: INTR_STATUS_REG_EN :: reserved0 [31:02] */ -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_reserved0_MASK 0xfffffffc -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_reserved0_SHIFT 2 - -/* XPT_XMEMIF :: INTR_STATUS_REG_EN :: INTR_STATUS_REG_EN [01:00] */ -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_MASK 0x00000003 -#define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_SHIFT 0 - -#endif /* #ifndef BCHP_XPT_XMEMIF_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.h crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,358 +0,0 @@ -/*************************************************************************** - * Copyright (c) 1999-2009, Broadcom Corporation - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - ********************************************************************** - * - * $brcm_Workfile: bchp_xpt_xpu.h $ - * $brcm_Revision: Hydra_Software_Devel/1 $ - * $brcm_Date: 7/17/09 8:28p $ - * - * Module Description: - * DO NOT EDIT THIS FILE DIRECTLY - * - * This module was generated magically with RDB from a source description - * file. You must edit the source file for changes to be made to this file. - * - * - * Date: Generated on Fri Jul 17 19:42:07 2009 - * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 - * - * Compiled with: RDB Utility combo_header.pl - * RDB Parser 3.0 - * unknown unknown - * Perl Interpreter 5.008008 - * Operating System linux - * - * Revision History: - * - * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.h $ - * - * Hydra_Software_Devel/1 7/17/09 8:28p albertl - * PR56880: Initial revision. - * - ***************************************************************************/ - -#ifndef BCHP_XPT_XPU_H__ -#define BCHP_XPT_XPU_H__ - -/*************************************************************************** - *XPT_XPU - XPT XPU Control Registers - ***************************************************************************/ -#define BCHP_XPT_XPU_TESTREG 0x00220000 /* Test register - reserved */ -#define BCHP_XPT_XPU_PSW 0x00220004 /* Processor status word */ -#define BCHP_XPT_XPU_PSWSH 0x00220008 /* Processor status word shadow */ -#define BCHP_XPT_XPU_SP 0x00220010 /* Stack pointer */ -#define BCHP_XPT_XPU_PC 0x00220018 /* Program counter */ -#define BCHP_XPT_XPU_STACK_0 0x00220020 /* Stack 0 */ -#define BCHP_XPT_XPU_STACK_1 0x00220024 /* Stack 1 */ -#define BCHP_XPT_XPU_STACK_2 0x00220028 /* Stack 2 */ -#define BCHP_XPT_XPU_STACK_3 0x0022002c /* Stack 3 */ -#define BCHP_XPT_XPU_REG_R0_R1 0x00220030 /* Register pair r0/r1 */ -#define BCHP_XPT_XPU_REG_R2_R3 0x00220034 /* Register pair r2/r3 */ -#define BCHP_XPT_XPU_REG_R4_R5 0x00220038 /* Register pair r4/r5 */ -#define BCHP_XPT_XPU_REG_R6_R7 0x0022003c /* Register pair r6/r7 */ -#define BCHP_XPT_XPU_REG_R8_R9 0x00220040 /* Register pair r8/r9 */ -#define BCHP_XPT_XPU_REG_R10_R11 0x00220044 /* Register pair r10/r11 */ -#define BCHP_XPT_XPU_REG_R12_R13 0x00220048 /* Register pair r12/r13 */ -#define BCHP_XPT_XPU_REG_R14_R15 0x0022004c /* Register pair r14/r15 */ - -/*************************************************************************** - *TESTREG - Test register - reserved - ***************************************************************************/ -/* XPT_XPU :: TESTREG :: reserved0 [31:01] */ -#define BCHP_XPT_XPU_TESTREG_reserved0_MASK 0xfffffffe -#define BCHP_XPT_XPU_TESTREG_reserved0_SHIFT 1 - -/* XPT_XPU :: TESTREG :: TESTBIT [00:00] */ -#define BCHP_XPT_XPU_TESTREG_TESTBIT_MASK 0x00000001 -#define BCHP_XPT_XPU_TESTREG_TESTBIT_SHIFT 0 - -/*************************************************************************** - *PSW - Processor status word - ***************************************************************************/ -/* XPT_XPU :: PSW :: reserved0 [31:11] */ -#define BCHP_XPT_XPU_PSW_reserved0_MASK 0xfffff800 -#define BCHP_XPT_XPU_PSW_reserved0_SHIFT 11 - -/* XPT_XPU :: PSW :: DFLAG [10:10] */ -#define BCHP_XPT_XPU_PSW_DFLAG_MASK 0x00000400 -#define BCHP_XPT_XPU_PSW_DFLAG_SHIFT 10 - -/* XPT_XPU :: PSW :: LFLAG [09:09] */ -#define BCHP_XPT_XPU_PSW_LFLAG_MASK 0x00000200 -#define BCHP_XPT_XPU_PSW_LFLAG_SHIFT 9 - -/* XPT_XPU :: PSW :: VFLAG [08:08] */ -#define BCHP_XPT_XPU_PSW_VFLAG_MASK 0x00000100 -#define BCHP_XPT_XPU_PSW_VFLAG_SHIFT 8 - -/* XPT_XPU :: PSW :: HFLAG [07:07] */ -#define BCHP_XPT_XPU_PSW_HFLAG_MASK 0x00000080 -#define BCHP_XPT_XPU_PSW_HFLAG_SHIFT 7 - -/* XPT_XPU :: PSW :: WFLAG [06:06] */ -#define BCHP_XPT_XPU_PSW_WFLAG_MASK 0x00000040 -#define BCHP_XPT_XPU_PSW_WFLAG_SHIFT 6 - -/* XPT_XPU :: PSW :: IFLAG [05:05] */ -#define BCHP_XPT_XPU_PSW_IFLAG_MASK 0x00000020 -#define BCHP_XPT_XPU_PSW_IFLAG_SHIFT 5 - -/* XPT_XPU :: PSW :: EFLAG [04:04] */ -#define BCHP_XPT_XPU_PSW_EFLAG_MASK 0x00000010 -#define BCHP_XPT_XPU_PSW_EFLAG_SHIFT 4 - -/* XPT_XPU :: PSW :: CFLAG [03:03] */ -#define BCHP_XPT_XPU_PSW_CFLAG_MASK 0x00000008 -#define BCHP_XPT_XPU_PSW_CFLAG_SHIFT 3 - -/* XPT_XPU :: PSW :: SFLAG [02:02] */ -#define BCHP_XPT_XPU_PSW_SFLAG_MASK 0x00000004 -#define BCHP_XPT_XPU_PSW_SFLAG_SHIFT 2 - -/* XPT_XPU :: PSW :: ZFLAG [01:01] */ -#define BCHP_XPT_XPU_PSW_ZFLAG_MASK 0x00000002 -#define BCHP_XPT_XPU_PSW_ZFLAG_SHIFT 1 - -/* XPT_XPU :: PSW :: OFLAG [00:00] */ -#define BCHP_XPT_XPU_PSW_OFLAG_MASK 0x00000001 -#define BCHP_XPT_XPU_PSW_OFLAG_SHIFT 0 - -/*************************************************************************** - *PSWSH - Processor status word shadow - ***************************************************************************/ -/* XPT_XPU :: PSWSH :: reserved0 [31:07] */ -#define BCHP_XPT_XPU_PSWSH_reserved0_MASK 0xffffff80 -#define BCHP_XPT_XPU_PSWSH_reserved0_SHIFT 7 - -/* XPT_XPU :: PSWSH :: WFLAG [06:06] */ -#define BCHP_XPT_XPU_PSWSH_WFLAG_MASK 0x00000040 -#define BCHP_XPT_XPU_PSWSH_WFLAG_SHIFT 6 - -/* XPT_XPU :: PSWSH :: reserved1 [05:04] */ -#define BCHP_XPT_XPU_PSWSH_reserved1_MASK 0x00000030 -#define BCHP_XPT_XPU_PSWSH_reserved1_SHIFT 4 - -/* XPT_XPU :: PSWSH :: CFLAG [03:03] */ -#define BCHP_XPT_XPU_PSWSH_CFLAG_MASK 0x00000008 -#define BCHP_XPT_XPU_PSWSH_CFLAG_SHIFT 3 - -/* XPT_XPU :: PSWSH :: SFLAG [02:02] */ -#define BCHP_XPT_XPU_PSWSH_SFLAG_MASK 0x00000004 -#define BCHP_XPT_XPU_PSWSH_SFLAG_SHIFT 2 - -/* XPT_XPU :: PSWSH :: ZFLAG [01:01] */ -#define BCHP_XPT_XPU_PSWSH_ZFLAG_MASK 0x00000002 -#define BCHP_XPT_XPU_PSWSH_ZFLAG_SHIFT 1 - -/* XPT_XPU :: PSWSH :: OFLAG [00:00] */ -#define BCHP_XPT_XPU_PSWSH_OFLAG_MASK 0x00000001 -#define BCHP_XPT_XPU_PSWSH_OFLAG_SHIFT 0 - -/*************************************************************************** - *SP - Stack pointer - ***************************************************************************/ -/* XPT_XPU :: SP :: reserved0 [31:02] */ -#define BCHP_XPT_XPU_SP_reserved0_MASK 0xfffffffc -#define BCHP_XPT_XPU_SP_reserved0_SHIFT 2 - -/* XPT_XPU :: SP :: SPTR [01:00] */ -#define BCHP_XPT_XPU_SP_SPTR_MASK 0x00000003 -#define BCHP_XPT_XPU_SP_SPTR_SHIFT 0 - -/*************************************************************************** - *PC - Program counter - ***************************************************************************/ -/* XPT_XPU :: PC :: reserved0 [31:12] */ -#define BCHP_XPT_XPU_PC_reserved0_MASK 0xfffff000 -#define BCHP_XPT_XPU_PC_reserved0_SHIFT 12 - -/* XPT_XPU :: PC :: PC [11:00] */ -#define BCHP_XPT_XPU_PC_PC_MASK 0x00000fff -#define BCHP_XPT_XPU_PC_PC_SHIFT 0 - -/*************************************************************************** - *STACK_0 - Stack 0 - ***************************************************************************/ -/* XPT_XPU :: STACK_0 :: reserved0 [31:13] */ -#define BCHP_XPT_XPU_STACK_0_reserved0_MASK 0xffffe000 -#define BCHP_XPT_XPU_STACK_0_reserved0_SHIFT 13 - -/* XPT_XPU :: STACK_0 :: VALID [12:12] */ -#define BCHP_XPT_XPU_STACK_0_VALID_MASK 0x00001000 -#define BCHP_XPT_XPU_STACK_0_VALID_SHIFT 12 - -/* XPT_XPU :: STACK_0 :: STACK_DATA [11:00] */ -#define BCHP_XPT_XPU_STACK_0_STACK_DATA_MASK 0x00000fff -#define BCHP_XPT_XPU_STACK_0_STACK_DATA_SHIFT 0 - -/*************************************************************************** - *STACK_1 - Stack 1 - ***************************************************************************/ -/* XPT_XPU :: STACK_1 :: reserved0 [31:13] */ -#define BCHP_XPT_XPU_STACK_1_reserved0_MASK 0xffffe000 -#define BCHP_XPT_XPU_STACK_1_reserved0_SHIFT 13 - -/* XPT_XPU :: STACK_1 :: VALID [12:12] */ -#define BCHP_XPT_XPU_STACK_1_VALID_MASK 0x00001000 -#define BCHP_XPT_XPU_STACK_1_VALID_SHIFT 12 - -/* XPT_XPU :: STACK_1 :: STACK_DATA [11:00] */ -#define BCHP_XPT_XPU_STACK_1_STACK_DATA_MASK 0x00000fff -#define BCHP_XPT_XPU_STACK_1_STACK_DATA_SHIFT 0 - -/*************************************************************************** - *STACK_2 - Stack 2 - ***************************************************************************/ -/* XPT_XPU :: STACK_2 :: reserved0 [31:13] */ -#define BCHP_XPT_XPU_STACK_2_reserved0_MASK 0xffffe000 -#define BCHP_XPT_XPU_STACK_2_reserved0_SHIFT 13 - -/* XPT_XPU :: STACK_2 :: VALID [12:12] */ -#define BCHP_XPT_XPU_STACK_2_VALID_MASK 0x00001000 -#define BCHP_XPT_XPU_STACK_2_VALID_SHIFT 12 - -/* XPT_XPU :: STACK_2 :: STACK_DATA [11:00] */ -#define BCHP_XPT_XPU_STACK_2_STACK_DATA_MASK 0x00000fff -#define BCHP_XPT_XPU_STACK_2_STACK_DATA_SHIFT 0 - -/*************************************************************************** - *STACK_3 - Stack 3 - ***************************************************************************/ -/* XPT_XPU :: STACK_3 :: reserved0 [31:13] */ -#define BCHP_XPT_XPU_STACK_3_reserved0_MASK 0xffffe000 -#define BCHP_XPT_XPU_STACK_3_reserved0_SHIFT 13 - -/* XPT_XPU :: STACK_3 :: VALID [12:12] */ -#define BCHP_XPT_XPU_STACK_3_VALID_MASK 0x00001000 -#define BCHP_XPT_XPU_STACK_3_VALID_SHIFT 12 - -/* XPT_XPU :: STACK_3 :: STACK_DATA [11:00] */ -#define BCHP_XPT_XPU_STACK_3_STACK_DATA_MASK 0x00000fff -#define BCHP_XPT_XPU_STACK_3_STACK_DATA_SHIFT 0 - -/*************************************************************************** - *REG_R0_R1 - Register pair r0/r1 - ***************************************************************************/ -/* XPT_XPU :: REG_R0_R1 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R0_R1_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R0_R1_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R0_R1 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R0_R1_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R0_R1_REGISTER_SHIFT 0 - -/*************************************************************************** - *REG_R2_R3 - Register pair r2/r3 - ***************************************************************************/ -/* XPT_XPU :: REG_R2_R3 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R2_R3_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R2_R3_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R2_R3 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R2_R3_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R2_R3_REGISTER_SHIFT 0 - -/*************************************************************************** - *REG_R4_R5 - Register pair r4/r5 - ***************************************************************************/ -/* XPT_XPU :: REG_R4_R5 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R4_R5_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R4_R5_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R4_R5 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R4_R5_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R4_R5_REGISTER_SHIFT 0 - -/*************************************************************************** - *REG_R6_R7 - Register pair r6/r7 - ***************************************************************************/ -/* XPT_XPU :: REG_R6_R7 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R6_R7_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R6_R7_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R6_R7 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R6_R7_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R6_R7_REGISTER_SHIFT 0 - -/*************************************************************************** - *REG_R8_R9 - Register pair r8/r9 - ***************************************************************************/ -/* XPT_XPU :: REG_R8_R9 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R8_R9_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R8_R9_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R8_R9 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R8_R9_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R8_R9_REGISTER_SHIFT 0 - -/*************************************************************************** - *REG_R10_R11 - Register pair r10/r11 - ***************************************************************************/ -/* XPT_XPU :: REG_R10_R11 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R10_R11_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R10_R11_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R10_R11 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R10_R11_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R10_R11_REGISTER_SHIFT 0 - -/*************************************************************************** - *REG_R12_R13 - Register pair r12/r13 - ***************************************************************************/ -/* XPT_XPU :: REG_R12_R13 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R12_R13_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R12_R13_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R12_R13 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R12_R13_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R12_R13_REGISTER_SHIFT 0 - -/*************************************************************************** - *REG_R14_R15 - Register pair r14/r15 - ***************************************************************************/ -/* XPT_XPU :: REG_R14_R15 :: reserved0 [31:16] */ -#define BCHP_XPT_XPU_REG_R14_R15_reserved0_MASK 0xffff0000 -#define BCHP_XPT_XPU_REG_R14_R15_reserved0_SHIFT 16 - -/* XPT_XPU :: REG_R14_R15 :: REGISTER [15:00] */ -#define BCHP_XPT_XPU_REG_R14_R15_REGISTER_MASK 0x0000ffff -#define BCHP_XPT_XPU_REG_R14_R15_REGISTER_SHIFT 0 - -/*************************************************************************** - *IMEM%i - Instruction memory address 0..2047 - ***************************************************************************/ -#define BCHP_XPT_XPU_IMEMi_ARRAY_BASE 0x00220800 -#define BCHP_XPT_XPU_IMEMi_ARRAY_START 0 -#define BCHP_XPT_XPU_IMEMi_ARRAY_END 2047 -#define BCHP_XPT_XPU_IMEMi_ARRAY_ELEMENT_SIZE 32 - -/*************************************************************************** - *IMEM%i - Instruction memory address 0..2047 - ***************************************************************************/ -/* XPT_XPU :: IMEMi :: reserved0 [31:22] */ -#define BCHP_XPT_XPU_IMEMi_reserved0_MASK 0xffc00000 -#define BCHP_XPT_XPU_IMEMi_reserved0_SHIFT 22 - -/* XPT_XPU :: IMEMi :: INSTRUCTION [21:00] */ -#define BCHP_XPT_XPU_IMEMi_INSTRUCTION_MASK 0x003fffff -#define BCHP_XPT_XPU_IMEMi_INSTRUCTION_SHIFT 0 - - -#endif /* #ifndef BCHP_XPT_XPU_H__ */ - -/* End of File */ diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/crystalhd_flea_rdb.h crystalhd-0.0~git20101029.6df10a0/include/flea/crystalhd_flea_rdb.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/crystalhd_flea_rdb.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/crystalhd_flea_rdb.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,158 +0,0 @@ -/******************************************************************** - * Copyright(c) 2006-2009 Broadcom Corporation. - * - * Name: crystalhd_flea_rdb.h - * - * Description: common include for flea register definition. - * - * AU - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ - -// 70015\magnum\basemodules\chp\70015\rdb\a0 - -#include "bchp_armcr4_bridge.h" -#include "bchp_armcr4_bridge_axi_slave.h" -#include "bchp_arm_uart.h" -#include "bchp_avd_block_avg_regs_0.h" -#include "bchp_avd_cache_0.h" -#include "bchp_avd_gr_0.h" -#include "bchp_avd_intr2_0.h" -#include "bchp_bop_aes.h" -#include "bchp_bop_gr_bridge.h" -#include "bchp_bvnt_gr_bridge.h" -#include "bchp_bvnt_intr2.h" -#include "bchp_cce_rgr_bridge.h" -#include "bchp_clk.h" -#include "bchp_clk_gr.h" -#include "bchp_common.h" -#include "bchp_csc.h" -#include "bchp_ddr23_ctl_regs_0.h" -#include "bchp_ddr23_phy_byte_lane_0.h" -#include "bchp_ddr23_phy_byte_lane_1.h" -#include "bchp_ddr23_phy_control_regs.h" -#include "bchp_decode_cpuaux2_0.h" -#include "bchp_decode_cpuaux_0.h" -#include "bchp_decode_cpucore2_0.h" -#include "bchp_decode_cpucore_0.h" -#include "bchp_decode_cpudma2_0.h" -#include "bchp_decode_cpudma_0.h" -#include "bchp_decode_cpudmem2_0.h" -#include "bchp_decode_cpudmem_0.h" -#include "bchp_decode_cpuimem2_0.h" -#include "bchp_decode_cpuimem_0.h" -#include "bchp_decode_cpuregs2_0.h" -#include "bchp_decode_cpuregs_0.h" -#include "bchp_decode_dblk_0.h" -#include "bchp_decode_dmamem2_0.h" -#include "bchp_decode_dmamem_0.h" -#include "bchp_decode_dqnt_0.h" -#include "bchp_decode_dqnt_8x8_0.h" -#include "bchp_decode_ind_sdram_regs2_0.h" -#include "bchp_decode_ind_sdram_regs_0.h" -#include "bchp_decode_ip_shim_0.h" -#include "bchp_decode_main_0.h" -#include "bchp_decode_mb_0.h" -#include "bchp_decode_mcom_0.h" -#include "bchp_decode_rvc_0.h" -#include "bchp_decode_sint_0.h" -#include "bchp_decode_sint_oloop_0.h" -#include "bchp_decode_spre_0.h" -#include "bchp_decode_wprd_0.h" -#include "bchp_decode_wptbl_0.h" -#include "bchp_decode_xfrm_0.h" -#include "bchp_dnr.h" -#include "bchp_gio.h" -#include "bchp_i2c.h" -#include "bchp_i2c_gr_bridge.h" -#include "bchp_intr.h" -#include "bchp_int_id_irq0.h" -#include "bchp_int_id_timer.h" -#include "bchp_int_id_xpt_pb0.h" -#include "bchp_int_id_xpt_pb1.h" -#include "bchp_int_id_xpt_pb2.h" -#include "bchp_int_id_xpt_rave.h" -#include "bchp_irq0.h" -#include "bchp_irq1.h" -#include "bchp_l1_intr.h" -#include "bchp_mdio.h" -#include "bchp_mem_dma.h" -#include "bchp_mem_dma_secure.h" -#include "bchp_mfd.h" -#include "bchp_misc1.h" -#include "bchp_misc2.h" -#include "bchp_misc3.h" -#include "bchp_misc_gr_bridge.h" -#include "bchp_misc_perst.h" -#include "bchp_mmscram.h" -#include "bchp_pcie_cfg.h" -#include "bchp_pcie_dll.h" -#include "bchp_pcie_phy.h" -#include "bchp_pcie_tl.h" -#include "bchp_pm_l2.h" -#include "bchp_pri_arb_arch_regs.h" -#include "bchp_pri_arb_arc_l1_regs.h" -#include "bchp_pri_arb_control_regs.h" -#include "bchp_pri_arb_mips_l2_regs.h" -#include "bchp_pri_arb_msa_regs.h" -#include "bchp_pri_arb_sarch_regs.h" -#include "bchp_pri_arb_starch_regs.h" -#include "bchp_pri_arb_trace_regs.h" -#include "bchp_pri_arb_wrch_regs.h" -#include "bchp_pri_client_regs.h" -#include "bchp_pri_crit_l2_regs_1.h" -#include "bchp_pri_crit_l2_regs_2.h" -#include "bchp_pri_crit_l2_regs_3.h" -#include "bchp_pri_rts_l2_regs_1.h" -#include "bchp_pri_rts_l2_regs_2.h" -#include "bchp_pri_rts_l2_regs_3.h" -#include "bchp_reg_cabac2bins2_0.h" -#include "bchp_reg_cabac2bins_0.h" -#include "bchp_scl_hd.h" -#include "bchp_scrub_ctrl.h" -#include "bchp_sentinel.h" -#include "bchp_sharf_mem_dma0.h" -#include "bchp_sharf_top.h" -#include "bchp_sun_gisb_arb.h" -#include "bchp_sun_gisb_arb_sec.h" -#include "bchp_sun_l2.h" -#include "bchp_sun_rg.h" -#include "bchp_sun_rgr.h" -#include "bchp_sun_top_ctrl.h" -#include "bchp_tgt_rgr_bridge.h" -#include "bchp_timer.h" -#include "bchp_tmisc.h" -#include "bchp_trb_top.h" -#include "bchp_triple_sec.h" -#include "bchp_vich_0.h" -#include "bchp_wakeup_ctrl2.h" -#include "bchp_wrap_misc_gr_bridge.h" -#include "bchp_wrap_misc_intr2.h" -#include "bchp_wrap_misc_secure_intr2.h" -#include "bchp_xpt_bus_if.h" -#include "bchp_xpt_fe.h" -#include "bchp_xpt_gr.h" -#include "bchp_xpt_pb0.h" -#include "bchp_xpt_pb1.h" -#include "bchp_xpt_pb2.h" -#include "bchp_xpt_pcroffset.h" -#include "bchp_xpt_rave.h" -#include "bchp_xpt_xmemif.h" -#include "bchp_xpt_xpu.h" - diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/flea/DriverFwShare.h crystalhd-0.0~git20101029.6df10a0/include/flea/DriverFwShare.h --- crystalhd-0.0~git20101012.a3a83b8/include/flea/DriverFwShare.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/flea/DriverFwShare.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,93 +0,0 @@ -#ifndef _DRIVER_FW_SHARE_ -#define _DRIVER_FW_SHARE_ - -#ifndef USE_MULTI_DECODE_DEFINES -#define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x400 /*Original single Decode Offset*/ -#else -//#define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x200 /*New offset that we plan to use eventually*/ -#define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x400 //This is just for testing..remove this once tested -#endif - - -/* - * The TX address does not change between the - * single decode and multiple decode. - */ -#define TX_BUFF_UPDATE_ADDR 0x300 //This is relative to BORCH - -typedef -struct -_PIC_DELIVERY_HOST_INFO_ -{ -/* --- The list ping-pong code is already there in the driver --- to save from re-inventing the code, the driver will indicate --- to firmware on which list the command should be posted. - */ - unsigned int ListIndex; - unsigned int HostDescMemLowAddr_Y; - unsigned int HostDescMemHighAddr_Y; - unsigned int HostDescMemLowAddr_UV; - unsigned int HostDescMemHighAddr_UV; - unsigned int RxSeqNumber; - unsigned int ChannelID; - unsigned int Reserved[1]; -}PIC_DELIVERY_HOST_INFO, -*PPIC_DELIVERY_HOST_INFO; - -/* --- We write the driver's FLL to this memory location. --- This is the array for FLL of all the channels. -*/ -#define HOST_TO_FW_FLL_ADDR (HOST_TO_FW_PIC_DEL_INFO_ADDR + sizeof(PIC_DELIVERY_HOST_INFO)) - - -typedef enum _DRIVER_FW_FLAGS_{ - DFW_FLAGS_CLEAR =0, - DFW_FLAGS_TX_ABORT =BC_BIT(0), //Firmware is stopped and will not give anymore buffers. - DFW_FLAGS_WRAP =BC_BIT(1) //Instruct the Firmware to WRAP the input buffer pointer -}DRIVER_FW_FLAGS; - -typedef struct -_TX_INPUT_BUFFER_INFO_ -{ - unsigned int DramBuffAdd; /* Address of the DRAM buffer where the data can be pushed*/ - unsigned int DramBuffSzInBytes; /* Size of the available DRAM buffer, in bytes*/ - unsigned int HostXferSzInBytes; /* Actual Transfer Done By Host, In Bytes*/ - unsigned int Flags; /* DRIVER_FW_FLAGS Written By Firmware to handle Stop of TX*/ - unsigned int SeqNum; /* Sequence number of the tranfer that is done. Read-Modify-Write*/ - unsigned int ChannelID; /* To which Channel this buffer belongs to*/ - unsigned int Reserved[2]; -}TX_INPUT_BUFFER_INFO, -*PTX_INPUT_BUFFER_INFO; - - -/* --- Out of band firmware handshake. -===================================== --- The driver writes the SCRATCH-8 register with a Error code. --- The driver then writes a mailbox register with 0x01. --- The driver then polls for the ACK. This ack is if the value of the SCRATCH-8 becomes zero. -*/ - -#define OOB_ERR_CODE_BASE 70015 -typedef enum _OUT_OF_BAND_ERR_CODE_ -{ - OOB_INVALID = 0, - OOB_CODE_ACK = OOB_ERR_CODE_BASE, - OOB_CODE_STOPRX = OOB_ERR_CODE_BASE + 1, -}OUT_OF_BAND_ERR_CODE; - - -#define OOB_CMD_RESPONSE_REGISTER BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8 -#define OOB_PCI_TO_ARM_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3 -#define TX_BUFFER_AVAILABLE_INTR BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3 -#define HEART_BEAT_REGISTER BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1 -#define HEART_BEAT_POLL_CNT 5 - - -#define FLEA_WORK_AROUND_SIG 0xF1EA -#define RX_PIC_Q_STS_WRKARND BC_BIT(0) -#define RX_DRAM_WRITE_WRKARND BC_BIT(1) -#define RX_MBOX_WRITE_WRKARND BC_BIT(2) -#endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/include/libcrystalhd_version.h crystalhd-0.0~git20101029.6df10a0/include/libcrystalhd_version.h --- crystalhd-0.0~git20101012.a3a83b8/include/libcrystalhd_version.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/include/libcrystalhd_version.h 2010-08-16 04:38:08.000000000 +0000 @@ -53,17 +53,15 @@ /*========================== Common For All Components =================================*/ #define BRCM_MAJOR_VERSION 3 -// Note: the driver doesn't currently use these defines, it has its own -// version information (which should match) stored in bc_dts_glob_lnx.h #define DRIVER_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DRIVER_MINOR_VERSION 8 +#define DRIVER_MINOR_VERSION 6 #define DRIVER_REVISION 0 #define RC_FILE_VERSION STRINGIFY_VERSION(DRIVER_MAJOR_VERSION,DRIVER_MINOR_VERSION,DRIVER_REVISION) ".0" /*======================= Device Interface Library ========================*/ #define DIL_MAJOR_VERSION BRCM_MAJOR_VERSION -#define DIL_MINOR_VERSION 20 +#define DIL_MINOR_VERSION 6 #define DIL_REVISION 0 #define DIL_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_if.cpp crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_if.cpp --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_if.cpp 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_if.cpp 2010-08-16 04:38:08.000000000 +0000 @@ -273,6 +273,37 @@ static __attribute__((aligned(4))) uint8_t ExtData[] = { 0x00, 0x00}; +pid_t g_nProcID = 0; +uint8_t g_bDecOpened = 0; + +uint8_t DtsIsDecOpened(pid_t nNewPID) +{ + if (nNewPID == 0) + return g_bDecOpened; + + if (nNewPID == g_nProcID) + return false; + + return g_bDecOpened; +} + +bool DtsChkPID(pid_t nCurPID) +{ + if (!g_nProcID) + return true; + + return (nCurPID == g_nProcID); +} + +void DtsSetDecStat(bool bDecOpen, pid_t PID) +{ + if (bDecOpen == true) + g_nProcID = PID; + else + g_nProcID = 0; + + g_bDecOpened = bDecOpen; +} static BC_STATUS DtsSetupHardware(HANDLE hDevice, BOOL IgnClkChk) { @@ -296,10 +327,6 @@ sts = DtsPushAuthFwToLink(hDevice,NULL); else if (Ctx->DevId == BC_PCI_DEVID_FLEA) sts = DtsPushFwToFlea(hDevice,NULL); - else { - DebugLog_Trace(LDIL_DBG,"HW Type not found\n"); - return BC_STS_ERROR; - } if(sts != BC_STS_SUCCESS){ return sts; @@ -391,7 +418,9 @@ } //===================================Externs ============================================ +#ifdef _USE_SHMEM_ extern BOOL glob_mode_valid; +#endif DRVIFLIB_API BC_STATUS DtsDeviceOpen( @@ -407,7 +436,9 @@ uint32_t drvVer, dilVer; uint32_t fwVer, decVer, hwVer; pid_t processID; +#ifdef _USE_SHMEM_ int shmid=0; +#endif DebugLog_Trace(LDIL_DBG,"Running DIL (%d.%d.%d) Version\n", DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION ); @@ -417,15 +448,10 @@ FixFlags = mode; mode &= 0xFF; - Sts = DtsCreateShMem(&shmid); - if(BC_STS_SUCCESS !=Sts) - return Sts; - if (mode != DTS_MONITOR_MODE && DtsIsDecOpened(processID)) { DebugLog_Trace(LDIL_DBG, "DtsDeviceOpen: Decoder is already opened\n"); - DtsDelDilShMem(); - return BC_STS_DEC_EXIST_OPEN; + return BC_STS_ERROR; } DebugLog_Trace(LDIL_DBG,"DtsDeviceOpen: Opening HW in mode %x\n", mode); @@ -433,20 +459,58 @@ /* For External API case, we support only Plyaback mode. */ if( !(BC_DTS_DEF_CFG & BC_EN_DIAG_MODE) && (mode != DTS_PLAYBACK_MODE) ){ DebugLog_Trace(LDIL_ERR,"DtsDeviceOpen: mode %d not supported\n",mode); - DtsDelDilShMem(); return BC_STS_INV_ARG; } +#ifdef _USE_SHMEM_ + Sts = DtsCreateShMem(&shmid); + if(BC_STS_SUCCESS !=Sts) + return Sts; + + +/* Sts = DtsGetDilShMem(shmid); + if(BC_STS_SUCCESS !=Sts) + return Sts; +*/ + if(!glob_mode_valid) { globMode = DtsGetOPMode(); if(globMode&4) { globMode&=4; } - DebugLog_Trace(LDIL_DBG,"DtsDeviceOpen: New globmode is %d \n",globMode); + DebugLog_Trace(LDIL_DBG,"DtsDeviceOpen:New globmode is %d \n",globMode); } else{ globMode = DtsGetOPMode(); } +#else + globMode = DtsGetOPMode(); +#endif + +#if 0 + if(((globMode & 0x3) && (mode != DTS_MONITOR_MODE)) || + ((globMode & 0x4) && (mode == DTS_MONITOR_MODE)) || + ((globMode & 0x8) && (mode == DTS_HWINIT_MODE))){ + DebugLog_Trace(LDIL_DBG,"DtsDeviceOpen: mode %d already opened\n",mode); +#ifdef _USE_SHMEM_ + DtsDelDilShMem(); +#endif + return BC_STS_DEC_EXIST_OPEN; + } + + if(mode == DTS_PLAYBACK_MODE){ + while(cnt--){ + if(DtsGetHwInitSts() != BC_DIL_HWINIT_IN_PROGRESS) + break; + bc_sleep_ms(100); + } + if(!cnt){ + return BC_STS_TIMEOUT; + } + }else if(mode == DTS_HWINIT_MODE){ + DtsSetHwInitSts(BC_DIL_HWINIT_IN_PROGRESS); + } +#endif if (mode == DTS_HWINIT_MODE) DtsSetHwInitSts(BC_DIL_HWINIT_IN_PROGRESS); @@ -455,7 +519,6 @@ if(drvHandle < 0) { DebugLog_Trace(LDIL_ERR,"DtsDeviceOpen: Create File Failed\n"); - DtsDelDilShMem(); return BC_STS_ERROR; } @@ -464,28 +527,18 @@ if( (Sts = DtsInitInterface(drvHandle,hDevice, mode)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_ERR,"DtsDeviceOpen: Interface Init Failed:%x\n",Sts); close(drvHandle); - DtsReleaseInterface(DtsGetContext(*hDevice)); - DtsDelDilShMem(); return Sts; } if( (Sts = DtsGetHwType(*hDevice,&DeviceID,&VendorID,&RevID))!=BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"Get Hardware Type Failed\n"); close(drvHandle); - DtsReleaseInterface(DtsGetContext(*hDevice)); - DtsDelDilShMem(); return Sts; } // set Ctx->DevId early, other depend on it DtsGetContext(*hDevice)->DevId = DeviceID; - DtsSetgDevID(DeviceID); - /* - * Old layout link cards have issues w/a core clock of 200, so we use - * 180 for all link cards, as we have no way to tell old layout from - * new layout cards. - */ - DtsSetCoreClock(*hDevice, 180); + DtsSetCoreClock(*hDevice, 200); /* * We have to specify the mode to the driver. @@ -495,8 +548,6 @@ if ((Sts = DtsGetVersion(*hDevice, &drvVer, &dilVer)) != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Get drv ver failed\n"); close(drvHandle); - DtsReleaseInterface(DtsGetContext(*hDevice)); - DtsDelDilShMem(); return Sts; } /* If driver minor version is more than 13, enable DTS_SKIP_TX_CHK_CPB feature */ @@ -534,9 +585,6 @@ if( (Sts = DtsNotifyOperatingMode(*hDevice,drvMode)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"Notify Operating Mode Failed\n"); - DtsReleaseInterface(DtsGetContext(*hDevice)); - close(drvHandle); - DtsDelDilShMem(); return Sts; } @@ -579,15 +627,13 @@ } else { - DebugLog_Trace(LDIL_DBG,"DtsSetupHardware: Failed from Open\n"); + DebugLog_Trace(LDIL_DBG,"DtsSetupHardware: Failed\n"); bc_sleep_ms(100); } } if(Sts != BC_STS_SUCCESS ) { DtsReleaseInterface(DtsGetContext(*hDevice)); - close(drvHandle); - DtsDelDilShMem(); goto exit; } } @@ -601,8 +647,6 @@ DtsRstDrvStat(*hDevice); } - DtsGetContext(*hDevice)->ProcessID = processID; - //DtsDevRegisterWr( hDevice,UartSelectA, 3); exit: return Sts; @@ -616,9 +660,6 @@ DTS_LIB_CONTEXT *Ctx; uint32_t globMode = 0; - if(hDevice == NULL) - return BC_STS_SUCCESS; - DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) @@ -1011,6 +1052,8 @@ /* Close the Input dump File */ DumpInputSampleToFile(NULL,0); + + return sts; } @@ -1113,10 +1156,6 @@ if(Ctx->DevId == BC_PCI_DEVID_FLEA) { - if(Ctx->SingleThreadedAppMode) { - pInputFormat->bEnableScaling = true; - pInputFormat->ScalingParams.sWidth = 1280; - } if(pInputFormat->bEnableScaling) { if((pInputFormat->ScalingParams.sWidth > 1920)|| (pInputFormat->ScalingParams.sWidth < 128)) @@ -1334,7 +1373,7 @@ } } -// DebugLog_Trace(LDIL_DBG,"DbgOptions=%x\n", Ctx->RegCfg.DbgOptions); + DebugLog_Trace(LDIL_DBG,"DbgOptions=%x\n", Ctx->RegCfg.DbgOptions); pIocData->u.RxCap.Rsrd = ST_CAP_IMMIDIATE; pIocData->u.RxCap.StartDeliveryThsh = RX_START_DELIVERY_THRESHOLD; @@ -1387,7 +1426,7 @@ } } -// DebugLog_Trace(LDIL_DBG,"DbgOptions=%x\n", Ctx->RegCfg.DbgOptions); + DebugLog_Trace(LDIL_DBG,"DbgOptions=%x\n", Ctx->RegCfg.DbgOptions); pIocData->u.RxCap.Rsrd = NO_PARAM; pIocData->u.RxCap.StartDeliveryThsh = RX_START_DELIVERY_THRESHOLD; @@ -1499,6 +1538,7 @@ savFlags = pOut->PoutFlags; pOut->discCnt = 0; + pOut->b422Mode = Ctx->b422Mode; do { @@ -1613,25 +1653,20 @@ OutBuffs.PoutFlags |= pOut->PoutFlags; width = Ctx->HWOutPicWidth; OutBuffs.b422Mode = Ctx->b422Mode; - pOut->AppCallBack(pOut->hnd, - width, - OutBuffs.PicInfo.height, - 0, - &OutBuffs); + pOut->AppCallBack( pOut->hnd, + width, + OutBuffs.PicInfo.height, + 0, + &OutBuffs); } - if (pOut->PoutFlags & BC_POUT_FLAGS_MODE) { - sts = DtsCopyFormat(Ctx,pOut,&OutBuffs); - } else { - pOut->b422Mode = Ctx->b422Mode; - if(Ctx->b422Mode) { - sts = DtsCopyRawDataToOutBuff(Ctx,pOut,&OutBuffs); - }else{ - if(pOut->PoutFlags & BC_POUT_FLAGS_YV12){ - sts = DtsCopyNV12ToYV12(Ctx,pOut,&OutBuffs); - }else { - sts = DtsCopyNV12(Ctx,pOut,&OutBuffs); - } + if(Ctx->b422Mode) { + sts = DtsCopyRawDataToOutBuff(Ctx,pOut,&OutBuffs); + }else{ + if(pOut->PoutFlags & BC_POUT_FLAGS_YV12){ + sts = DtsCopyNV12ToYV12(Ctx,pOut,&OutBuffs); + }else { + sts = DtsCopyNV12(Ctx,pOut,&OutBuffs); } } @@ -1786,16 +1821,6 @@ return txBufPush(&Ctx->circBuf, pUserData, ulSizeInBytes); } -DRVIFLIB_API uint32_t -DtsTxFreeSize( HANDLE hDevice ) -{ - DTS_LIB_CONTEXT *Ctx = NULL; - - DTS_GET_CTX(hDevice,Ctx); - - return Ctx->circBuf.freeSize; -} - DRVIFLIB_API BC_STATUS DtsSendSPESPkt(HANDLE hDevice , uint64_t timeStamp, @@ -2163,7 +2188,6 @@ return BC_STS_SUCCESS; return BC_STS_ERROR; } - if (Ctx->VidParams.StreamType == BC_STREAM_TYPE_PES || timeStamp == 0) { return DtsAlignSendData(hDevice, pUserData, ulSizeInBytes, timeStamp, encrypted); @@ -2942,6 +2966,7 @@ } } } + // For LINK Pause HW if the RLL is too full. Prevent overflows // Hard coded values for now if(Ctx->DevId == BC_PCI_DEVID_LINK && Ctx->SingleThreadedAppMode) { @@ -2963,9 +2988,6 @@ DTS_LIB_CONTEXT *Ctx; BC_STATUS sts = BC_STS_SUCCESS; uint32_t pciids = 0; - int shmid = 0; - -// DebugLog_Trace(LDIL_DBG,"DtsGetCapabilities: Called\n"); if(hDevice != NULL) { DTS_GET_CTX(hDevice,Ctx); // Called after the HW has been opened @@ -2973,19 +2995,10 @@ } else { // called before HW has been opened - // First make sure no one else has the HW open already - if(BC_STS_SUCCESS == DtsCreateShMem(&shmid)) { - pciids = DtsGetgDevID(); - DtsDelDilShMem(); - if(pciids == BC_PCI_DEVID_INVALID) { - sts = DtsGetHWFeatures(&pciids); - pciids >>= 16; - if(sts != BC_STS_SUCCESS) - return sts; - } - } - else - return BC_STS_INSUFF_RES; + sts = DtsGetHWFeatures(&pciids); + pciids >>= 16; + if(sts != BC_STS_SUCCESS) + return sts; } if (pciids == BC_PCI_DEVID_INVALID) diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_if.h crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_if.h --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_if.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_if.h 2010-08-16 04:38:08.000000000 +0000 @@ -468,7 +468,7 @@ Sets input video's various parameters that would be used by a subsequent call to DtsStartDecoder. - DtsSetInputFormat must always be called before DtsOpenDecoder for the + DtsSetInputFormat must always be called before DtsStartDecoder for the decoder to start processing input data. The device must have been previously opened for this call to succeed. @@ -1508,30 +1508,6 @@ PBC_INFO_CRYSTAL bCrystalInfo ); -/***************************************************************************** - -Function name: - - DtsTxFreeSize - -Description: - - This API returns the amount of free space in the tx circular buffer -Parameters: - - hDevice Handle to device. This is obtained via a prior call to - DtsDeviceOpen. - -Return: - - uint32_t value of number of free bytes in the tx circular buffer - -*****************************************************************************/ -DRVIFLIB_API uint32_t -DtsTxFreeSize( - HANDLE hDevice -); - #ifdef __cplusplus } #endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_int_if.cpp crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_int_if.cpp --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_int_if.cpp 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_int_if.cpp 2010-08-16 04:38:08.000000000 +0000 @@ -33,8 +33,6 @@ #include "libcrystalhd_int_if.h" #include "libcrystalhd_fwcmds.h" -#include - #define SV_MAX_LINE_SZ 128 #define PCI_GLOBAL_CONTROL MISC2_GLOBAL_CTRL #define PCI_INT_STS_REG MISC2_INTERNAL_STATUS @@ -252,7 +250,7 @@ DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId != BC_PCI_DEVID_LINK) { - //DebugLog_Trace(LDIL_DBG,"DtsSetCoreClock is not supported in this device\n"); + DebugLog_Trace(LDIL_DBG,"DtsSetCoreClock is not supported in this device\n"); return BC_STS_ERROR; } @@ -634,12 +632,7 @@ return sts; } - *Value = pciInfo->pci_cfg_space[0] | - (pciInfo->pci_cfg_space[1] << 8)| - (pciInfo->pci_cfg_space[2] << 16)| - (pciInfo->pci_cfg_space[3] << 24); - - //*Value = *(uint32_t *)(pciInfo->pci_cfg_space); + *Value = *(uint32_t *)(pciInfo->pci_cfg_space); DtsRelIoctlData(Ctx,pIocData); @@ -668,12 +661,7 @@ pciInfo->Size = Size; pciInfo->Offset = Offset; - pciInfo->pci_cfg_space[0] = Value & 0xFF; - pciInfo->pci_cfg_space[1] = (Value >> 8) & 0xFF; - pciInfo->pci_cfg_space[2] = (Value >> 16) & 0xFF; - pciInfo->pci_cfg_space[3] = (Value >> 24) & 0xFF; - - //*((uint32_t *)(pciInfo->pci_cfg_space)) = Value; + *((uint32_t *)(pciInfo->pci_cfg_space)) = Value; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_WR_PCI_CFG,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsGetPciConfigSpace: Ioctl failed: %d\n",sts); @@ -741,25 +729,28 @@ BC_STATUS sts = BC_STS_SUCCESS; - DTS_GET_CTX(hDevice, Ctx); + DTS_GET_CTX(hDevice,Ctx); - if (!(pIocData = DtsAllocIoctlData(Ctx))) + if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; reg_acc_wr = (BC_CMD_REG_ACC *) &pIocData->u.regAcc; + // // Prepare the command here. + // reg_acc_wr->Offset = offset; reg_acc_wr->Value = Value; - sts = DtsDrvCmd(Ctx, BCM_IOC_REG_WR, 0, pIocData, FALSE); - - if (sts != BC_STS_SUCCESS) - DebugLog_Trace(LDIL_DBG,"DtsDevRegisterWr: Ioctl failed: %d\n", sts); + if( (sts=DtsDrvCmd(Ctx,BCM_IOC_REG_WR,0,pIocData,FALSE)) != BC_STS_SUCCESS){ + DtsRelIoctlData(Ctx,pIocData); + DebugLog_Trace(LDIL_DBG,"DtsDevRegisterWr: Ioctl failed: %d\n",sts); + return sts; + } DtsRelIoctlData(Ctx,pIocData); - return sts; + return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS @@ -1047,7 +1038,7 @@ *dramOff = pIocData->u.ProcInput.DramOffset; - if( BC_STS_SUCCESS != status && BC_STS_IO_USER_ABORT != status) + if( BC_STS_SUCCESS != status) { DebugLog_Trace(LDIL_DBG,"DtsTxDmaText: DeviceIoControl Failed with Sts %d\n", status); } @@ -1325,7 +1316,7 @@ uint32_t y,lDestStride=0; uint8_t *pSrc = NULL, *pDest=NULL; uint32_t dstWidthInPixels, dstHeightInPixels; - uint32_t srcWidthInPixels = 0, srcHeightInPixels; + uint32_t srcWidthInPixels, srcHeightInPixels; BC_STATUS Sts = BC_STS_SUCCESS; if ( (Sts = DtsChkYUVSizes(Ctx,Vout,Vin)) != BC_STS_SUCCESS) @@ -1349,7 +1340,7 @@ return BC_STS_IO_XFR_ERROR; } #endif - srcWidthInPixels = Ctx->HWOutPicWidth; + srcWidthInPixels = Ctx->HWOutPicWidth; srcHeightInPixels = dstHeightInPixels; } else { dstWidthInPixels = Vin->PicInfo.width; @@ -1387,7 +1378,7 @@ uint8_t *yv12buff = NULL; uint32_t uvbase=0; BC_STATUS Sts = BC_STS_SUCCESS; - uint32_t x,y,lDestStrideY=0, lDestStrideUV=0; + uint32_t x,y,lDestStride=0; uint8_t *pSrc = NULL, *pDest=NULL; uint32_t dstWidthInPixels, dstHeightInPixels; uint32_t srcWidthInPixels, srcHeightInPixels; @@ -1399,9 +1390,7 @@ if(Vout->PoutFlags & BC_POUT_FLAGS_SIZE)// needs to be optimized. { if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE) - lDestStrideUV = (lDestStrideY = Vout->StrideSz)/2; - if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE_UV) - lDestStrideUV = Vout->StrideSzUV; + lDestStride = Vout->StrideSz; // Use DShow provided size for now dstWidthInPixels = Vout->PicInfo.width; @@ -1426,13 +1415,13 @@ for (y = 0; y < dstHeightInPixels; y++) { memcpy(pDest,pSrc,dstWidthInPixels); - pDest += dstWidthInPixels + lDestStrideY; + pDest += dstWidthInPixels + lDestStride; pSrc += srcWidthInPixels; } //copy chroma pDest = Vout->UVbuff; pSrc = Vin->UVbuff; - uvbase = (dstWidthInPixels + lDestStrideY) * dstHeightInPixels/4 ;//(Vin->UVBuffDoneSz * 4/2); + uvbase = (dstWidthInPixels + lDestStride) * dstHeightInPixels/4 ;//(Vin->UVBuffDoneSz * 4/2); for (y = 0; y < dstHeightInPixels/2; y++) { for(x = 0; x < dstWidthInPixels; x += 2) @@ -1440,7 +1429,7 @@ pDest[x/2] = pSrc[x+1]; pDest[uvbase + x/2] = pSrc[x]; } - pDest += dstWidthInPixels / 2 + lDestStrideUV; + pDest += (dstWidthInPixels + lDestStride) / 2; pSrc += srcWidthInPixels; } } @@ -1470,10 +1459,10 @@ BC_STATUS DtsCopyNV12(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin) { - uint32_t y,lDestStrideY=0,lDestStrideUV=0; + uint32_t y,lDestStride=0; uint8_t *pSrc = NULL, *pDest=NULL; uint32_t dstWidthInPixels, dstHeightInPixels; - uint32_t srcWidthInPixels=0, srcHeightInPixels; + uint32_t srcWidthInPixels, srcHeightInPixels; BC_STATUS Sts = BC_STS_SUCCESS; @@ -1481,9 +1470,7 @@ return Sts; if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE) - lDestStrideUV = lDestStrideY = Vout->StrideSz; - if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE_UV) - lDestStrideUV = Vout->StrideSzUV; + lDestStride = Vout->StrideSz; if(Vout->PoutFlags & BC_POUT_FLAGS_SIZE) { // Use DShow provided size for now @@ -1503,16 +1490,20 @@ dstHeightInPixels = Vin->PicInfo.height; } - // NV12 is planar: Y plane, followed by packed U-V plane. + + + //WidthInPixels = 1280; + //HeightInPixels = 720; + // NV12 is planar: Y plane, followed by packed U-V plane. // Do a strided copy only if the stride is non-zero - if((lDestStrideY != 0) || (lDestStrideUV != 0) || (srcWidthInPixels != dstWidthInPixels)) { + if( (lDestStride != 0) || (srcWidthInPixels != dstWidthInPixels) ) { // Y plane pDest = Vout->Ybuff; pSrc = Vin->Ybuff; for (y = 0; y < dstHeightInPixels; y++){ memcpy(pDest,pSrc,dstWidthInPixels); - pDest += dstWidthInPixels + lDestStrideY; + pDest += dstWidthInPixels + lDestStride; pSrc += srcWidthInPixels; } // U-V plane @@ -1520,7 +1511,7 @@ pSrc = Vin->UVbuff; for (y = 0; y < dstHeightInPixels/2; y++){ memcpy(pDest,pSrc,dstWidthInPixels); - pDest += dstWidthInPixels + lDestStrideUV; + pDest += dstWidthInPixels + lDestStride; pSrc += srcWidthInPixels; } } else { @@ -1534,701 +1525,6 @@ return BC_STS_SUCCESS; } -// TODO: add sse2 detection -static bool gSSE2 = true; // most of the platforms will have it anyway: -// 64 bits: no test necessary -// mac: no test necessary -// linux/windows: we might have to do the test. - -static void fast_memcpy(uint8_t *dst, const uint8_t *src, uint32_t count) -{ - // tested - if (gSSE2) - { - if (((((uintptr_t) dst) & 0xf) == 0) && ((((uintptr_t) src) & 0xf) == 0)) - { - while (count >= (16*4)) - { - _mm_stream_si128((__m128i *) (dst+ 0*16), _mm_load_si128((__m128i *) (src+ 0*16))); - _mm_stream_si128((__m128i *) (dst+ 1*16), _mm_load_si128((__m128i *) (src+ 1*16))); - _mm_stream_si128((__m128i *) (dst+ 2*16), _mm_load_si128((__m128i *) (src+ 2*16))); - _mm_stream_si128((__m128i *) (dst+ 3*16), _mm_load_si128((__m128i *) (src+ 3*16))); - count -= 16*4; - src += 16*4; - dst += 16*4; - } - } - else - { - while (count >= (16*4)) - { - _mm_storeu_si128((__m128i *) (dst+ 0*16), _mm_loadu_si128((__m128i *) (src+ 0*16))); - _mm_storeu_si128((__m128i *) (dst+ 1*16), _mm_loadu_si128((__m128i *) (src+ 1*16))); - _mm_storeu_si128((__m128i *) (dst+ 2*16), _mm_loadu_si128((__m128i *) (src+ 2*16))); - _mm_storeu_si128((__m128i *) (dst+ 3*16), _mm_loadu_si128((__m128i *) (src+ 3*16))); - count -= 16*4; - src += 16*4; - dst += 16*4; - } - } - } - - while (count --) - *dst++ = *src++; -} - -// this is not good. -// if we have 3 buffers, we cannot assume V is after U -static BC_STATUS DtsCopy422ToYV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ // copy YUY2 to YV12 - // TODO - // NOTE: if we want to support this porperly, we will need to add a Vbuffer pointer - // if we have 3 destination buffers, there's no guarantee that V buffer is derivable from UV pointer. - return BC_STS_INV_ARG; -} - -// this is just a memcpy -static BC_STATUS DtsCopy422ToYUY2(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ // copy YUY2 to YUY2 - uint32_t y; - - // TODO: test this - strideY += dstWidth*2; - - for (y = 0; y < height; y++) - { - fast_memcpy(dstY, srcY, srcWidth*2); - srcY += srcWidth*2; - dstY += strideY; - } - return BC_STS_SUCCESS; -} - -// almost a memcpy, we just need to shuffle YUV's around -static BC_STATUS DtsCopy422ToUYVY(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ - // TODO, test this - uint32_t x = 0, __y; - - strideY += dstWidth*2; - - for (__y = 0; __y < height; __y++) - { - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-7) - { - __m128i v = _mm_load_si128((__m128i *)(srcY+x*2)); - __m128i v1 = _mm_srli_epi16(v, 8); - __m128i v2 = _mm_slli_epi16(v, 8); - _mm_stream_si128((__m128i *)(dstY+x*2), _mm_or_si128(v1, v2)); - x += 8; - } - } - else - { - while (x < srcWidth-7) - { - __m128i v = _mm_loadu_si128((__m128i *)(srcY+x*2)); - __m128i v1 = _mm_srli_epi16(v, 8); - __m128i v2 = _mm_slli_epi16(v, 8); - _mm_storeu_si128((__m128i *)(dstY+x*2), _mm_or_si128(v1, v2)); - x += 8; - } - } - } - - while (x < srcWidth-1) - { - dstY[x*2+0] = srcY[x+1]; - dstY[x*2+1] = srcY[x+0]; - dstY[x*2+2] = srcY[x+3]; - dstY[x*2+3] = srcY[x+2]; - x += 2; - } - - srcY += srcWidth*2; - dstY += strideY; - } - return BC_STS_SUCCESS; -} - -// convert to NV12 -static BC_STATUS DtsCopy422ToNV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ - // tested - uint32_t x, __y; - - strideY += dstWidth; - strideUV += dstWidth; - - static __m128i mask = _mm_set_epi16(0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff); - - for (__y = 0; __y < height; __y += 2) - { - x = 0; - - // first line: Y and UV extraction - - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0) && ((((uintptr_t) dstUV) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i s1 = _mm_load_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels - __m128i s2 = _mm_load_si128((__m128i *) (srcY+x*2+16)); // load 8 more - - __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs - __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs - __m128i y = _mm_packus_epi16 (y1, y2); // get the y together - _mm_stream_si128((__m128i *) (dstY+x), y); // store 16 Y - - s1 = _mm_srli_epi16(s1, 8); // get rid of Y - s2 = _mm_srli_epi16(s2, 8); // get rid of Y - __m128i uv = _mm_packus_epi16 (s1, s2); // get the uv together - _mm_stream_si128((__m128i *) (dstUV+x), uv); // store 8 UV pairs - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i s1 = _mm_loadu_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels - __m128i s2 = _mm_loadu_si128((__m128i *) (srcY+x*2+16)); // load 8 more - - __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs - __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs - __m128i y = _mm_packus_epi16 (y1, y2); // get the y together - _mm_storeu_si128((__m128i *) (dstY+x), y); // store 16 Y - - s1 = _mm_srli_epi16(s1, 8); // get rid of Y - s2 = _mm_srli_epi16(s2, 8); // get rid of Y - __m128i uv = _mm_packus_epi16 (s1, s2); // get the uv together - _mm_storeu_si128((__m128i *) (dstUV+x), uv); // store 8 UV pairs - - x += 16; - } - } - } - - - while (x < srcWidth-1) - { - dstY [x+0] = srcY[x*2+0]; // Y - dstUV[x+0] = srcY[x*2+1]; // U - dstY [x+1] = srcY[x*2+2]; // Y - dstUV[x+1] = srcY[x*2+3]; // V - x += 2; - } - - srcY += srcWidth*2; - dstY += strideY; - dstUV += strideUV; - - // second line: just Y - x = 0; - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i s1 = _mm_load_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels - __m128i s2 = _mm_load_si128((__m128i *) (srcY+x*2+16)); // load 8 more - - __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs - __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs - __m128i y = _mm_packus_epi16 (y1, y2); // get the y - _mm_stream_si128((__m128i *) (dstY+x), y); // store 16 Y - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i s1 = _mm_loadu_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels - __m128i s2 = _mm_loadu_si128((__m128i *) (srcY+x*2+16)); // load 8 more - - __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs - __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs - __m128i y = _mm_packus_epi16 (y1, y2); // get the y - _mm_storeu_si128((__m128i *) (dstY+x), y); // store 16 Y - - x += 16; - } - } - } - - while (x < srcWidth-1) - { - dstY [x+0] = srcY[x*2+0]; // Y - dstY [x+1] = srcY[x*2+2]; // Y - x += 2; - } - - srcY += srcWidth*2; - dstY += strideY; - } - return BC_STS_SUCCESS; -} - - -// this is not good. -// if we have 3 textures, we cannot assume V is after U -static BC_STATUS DtsCopy420ToYV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ - // TODO - // NOTE: if we want to support this porperly, we will need to add a Vbuffer pointer - return BC_STS_INV_ARG; -} - -static BC_STATUS DtsCopy420ToYUY2(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ - // TODO, test this - uint32_t x, __y; - - strideY += dstWidth*2; - - __y = 0; - while (__y < height-2) - { - // first line - x = 0; - - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels - _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels - _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels - - x += 16; - } - } - } - - while (x < srcWidth-1) - { - dstY[x*2+0] = srcY [x+0]; - dstY[x*2+1] = srcUV[x+0]; - dstY[x*2+2] = srcY [x+1]; - dstY[x*2+3] = srcUV[x+1]; - - x += 2; - } - - srcY += srcWidth; - dstY += strideY; - - // second line - - x = 0; - - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv1 = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV - __m128i uv2 = _mm_load_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV - __m128i uv = _mm_avg_epu8(uv1, uv2); - _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels - _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv1 = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV - __m128i uv2 = _mm_loadu_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV - __m128i uv = _mm_avg_epu8(uv1, uv2); - _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels - _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels - - x += 16; - } - } - } - - while (x < srcWidth-1) - { - dstY[x*2+0] = srcY [x+0]; - dstY[x*2+1] = (srcUV[x+0] + srcUV[x+0+srcWidth])/2; - dstY[x*2+2] = srcY [x+1]; - dstY[x*2+3] = (srcUV[x+1] + srcUV[x+1+srcWidth])/2; - - x += 2; - } - - srcY += srcWidth; - srcUV += srcWidth; - dstY += strideY; - - __y += 2; - } - - // last 2 lines - while (__y < height) - { - x = 0; - - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels - _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels - _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels - - x += 16; - } - } - } - - while (x < srcWidth-1) - { - dstY[x*2+0] = srcY [x+0]; - dstY[x*2+1] = srcUV[x+0]; - dstY[x*2+2] = srcY [x+1]; - dstY[x*2+3] = srcUV[x+1]; - - x += 2; - } - - srcY += srcWidth; - dstY += strideY; - - __y++; - } - - return BC_STS_SUCCESS; -} - -static BC_STATUS DtsCopy420ToUYVY(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ - // TODO, test this - uint32_t x, __y; - - strideY += dstWidth*2; - - __y = 0; - while (__y < height-2) - { - // first line - x = 0; - - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels - _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels - _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels - - x += 16; - } - } - } - - while (x < srcWidth-1) - { - dstY[x*2+1] = srcY [x+0]; - dstY[x*2+0] = srcUV[x+0]; - dstY[x*2+3] = srcY [x+1]; - dstY[x*2+2] = srcUV[x+1]; - - x += 2; - } - - srcY += srcWidth; - dstY += strideY; - - // second line - - x = 0; - - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv1 = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV - __m128i uv2 = _mm_load_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV - __m128i uv = _mm_avg_epu8(uv1, uv2); - _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels - _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv1 = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV - __m128i uv2 = _mm_loadu_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV - __m128i uv = _mm_avg_epu8(uv1, uv2); - _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels - _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels - - x += 16; - } - } - } - - while (x < srcWidth-1) - { - dstY[x*2+1] = srcY [x+0]; - dstY[x*2+0] = (srcUV[x+0] + srcUV[x+0+srcWidth])/2; - dstY[x*2+3] = srcY [x+1]; - dstY[x*2+2] = (srcUV[x+1] + srcUV[x+1+srcWidth])/2; - - x += 2; - } - - srcY += srcWidth; - srcUV += srcWidth; - dstY += strideY; - } - - // last 2 lines - while (__y < height) - { - x = 0; - - if (gSSE2) - { - if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) - { - while (x < srcWidth-15) - { - __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels - _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels - - x += 16; - } - } - else - { - while (x < srcWidth-15) - { - __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels - __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV - _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels - _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels - - x += 16; - } - } - } - - while (x < srcWidth-1) - { - dstY[x*2+1] = srcY [x+0]; - dstY[x*2+0] = srcUV[x+0]; - dstY[x*2+3] = srcY [x+1]; - dstY[x*2+2] = srcUV[x+1]; - - x += 2; - } - - srcY += srcWidth; - dstY += strideY; - - __y++; - } - - return BC_STS_SUCCESS; -} - -static BC_STATUS DtsCopy420ToNV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) -{ // tested - uint32_t __y; - - strideY += dstWidth; - strideUV += dstWidth; - - // first copy Y - for (__y = 0; __y < height; __y++) - { - fast_memcpy(dstY, srcY, srcWidth); - dstY += strideY; - srcY += srcWidth; - } - - // now copy uvs - height /= 2; - for (__y = 0; __y < height; __y++) - { - fast_memcpy(dstUV, srcUV, srcWidth); - srcUV += srcWidth; - dstUV += strideUV; - - } - return BC_STS_SUCCESS; -} - - -// copy 422/420 ( device format to format specified in Vout) -BC_STATUS DtsCopyFormat(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin) -{ - uint32_t lDestStrideY=0, lDestStrideUV=0; - uint32_t dstHeightInPixels; - - BC_STATUS Sts = BC_STS_SUCCESS; - - if ( (Sts = DtsChkYUVSizes(Ctx,Vout,Vin)) != BC_STS_SUCCESS) - return Sts; - - if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE) - lDestStrideUV = lDestStrideY = Vout->StrideSz; - if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE_UV) - lDestStrideUV = Vout->StrideSzUV; - - if(Vout->PoutFlags & BC_POUT_FLAGS_SIZE) { - // Use application provided size for now - if(!Ctx->VidParams.Progressive) - dstHeightInPixels = Vout->PicInfo.height/2; - else - dstHeightInPixels = Vout->PicInfo.height; - /* Check for Valid data based on the application information */ - // we cannot do that any more.size may vary, we have to suppose them - // ok - // if((Vout->YBuffDoneSz < (dstWidthInPixels * dstHeightInPixels / 4)) || - // (Vout->UVBuffDoneSz < (dstWidthInPixels * dstHeightInPixels/2 / 4))) - // return BC_STS_IO_XFR_ERROR; - } else { - dstHeightInPixels = Vin->PicInfo.height; - } - - // check that we can do the copy properly - if (Ctx->HWOutPicWidth > Vin->PicInfo.width) - return BC_STS_IO_XFR_ERROR; - - //DebugLog_Trace(LDIL_DBG,"Copying from %d to %d\n", Ctx->b422Mode, Vout->b422Mode); - - if (Ctx->b422Mode) { - // input is 422 (YUY2) - switch (Vout->b422Mode) { - case OUTPUT_MODE422_YUY2: - Sts = DtsCopy422ToYUY2( - Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, - Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV - ); - break; - case OUTPUT_MODE422_UYVY: - Sts = DtsCopy422ToUYVY( - Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, - Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV - ); - break; - case OUTPUT_MODE420_NV12: - Sts = DtsCopy422ToNV12( - Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, - Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV - ); - break; - default: - Sts = BC_STS_INV_ARG; - break; - } - }else{ - // input is 420 (NV12) - switch (Vout->b422Mode) { - case OUTPUT_MODE422_YUY2: - Sts = DtsCopy420ToYUY2( - Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Vin->UVbuff, - Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV - ); - break; - case OUTPUT_MODE422_UYVY: - Sts = DtsCopy420ToUYVY( - Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Vin->UVbuff, - Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV - ); - break; - case OUTPUT_MODE420_NV12: - Sts = DtsCopy420ToNV12( - Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Vin->UVbuff, - Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV - ); - break; - default: - Sts = BC_STS_INV_ARG; - break; - } - } - - return Sts; -} - - - - DRVIFLIB_INT_API BC_STATUS DtsPushFwBinToLink( HANDLE hDevice, diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_int_if.h crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_int_if.h --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_int_if.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_int_if.h 2010-08-16 04:38:08.000000000 +0000 @@ -246,10 +246,10 @@ BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin); -BC_STATUS DtsCopyRawDataToOutBuff( - struct _DTS_LIB_CONTEXT *Ctx, - BC_DTS_PROC_OUT *Vout, - BC_DTS_PROC_OUT *Vin); +BC_STATUS +DtsCopyRawDataToOutBuff(struct _DTS_LIB_CONTEXT *Ctx, + BC_DTS_PROC_OUT *Vout, + BC_DTS_PROC_OUT *Vin); BC_STATUS DtsCopyNV12ToYV12( struct _DTS_LIB_CONTEXT *Ctx, @@ -261,11 +261,6 @@ BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin); -BC_STATUS DtsCopyFormat( - struct _DTS_LIB_CONTEXT *Ctx, - BC_DTS_PROC_OUT *Vout, - BC_DTS_PROC_OUT *Vin); - extern DRVIFLIB_INT_API BC_STATUS DtsPushFwBinToLink(HANDLE hDevice, uint32_t *FwBinFile, uint32_t bytesDnld); diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_parser.cpp crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_parser.cpp --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_parser.cpp 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_parser.cpp 2010-08-16 04:38:08.000000000 +0000 @@ -187,8 +187,6 @@ { DTS_LIB_CONTEXT *Ctx = NULL; - int sts = 0; - DTS_GET_CTX(hDevice,Ctx); //Send SPS and PPS @@ -198,9 +196,7 @@ if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA)) { Ctx->PESConvParams.m_iSpsPpsLen = Ctx->VidParams.MetaDataSz; - sts = posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); - if(sts) - return BC_STS_INSUFF_RES; + posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); memcpy(Ctx->PESConvParams.m_pSpsPpsBuf, Ctx->VidParams.pMetaData, Ctx->PESConvParams.m_iSpsPpsLen); } else @@ -210,9 +206,7 @@ if (Ctx->PESConvParams.m_pSpsPpsBuf) free(Ctx->PESConvParams.m_pSpsPpsBuf); Ctx->PESConvParams.m_iSpsPpsLen = 32; - sts = posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); - if(sts) - return BC_STS_INSUFF_RES; + posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); memcpy(Ctx->PESConvParams.m_pSpsPpsBuf, b_asf_vc1_sm_codein_seqhdr, Ctx->PESConvParams.m_iSpsPpsLen); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 17)) = WORD_SWAP((uint16_t)Ctx->VidParams.WidthInPixels); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 19)) = WORD_SWAP((uint16_t)Ctx->VidParams.HeightInPixels); @@ -223,9 +217,7 @@ if (Ctx->PESConvParams.m_pSpsPpsBuf) free(Ctx->PESConvParams.m_pSpsPpsBuf); Ctx->PESConvParams.m_iSpsPpsLen = 12; - sts = posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); - if(sts) - return BC_STS_INSUFF_RES; + posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); memcpy(Ctx->PESConvParams.m_pSpsPpsBuf, b_asf_vc1_sm_seqhdr, Ctx->PESConvParams.m_iSpsPpsLen); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 4)) = WORD_SWAP((uint16_t)Ctx->VidParams.WidthInPixels); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 6)) = WORD_SWAP((uint16_t)Ctx->VidParams.HeightInPixels); @@ -320,8 +312,6 @@ } } Ctx->PESConvParams.m_iSpsPpsLen = iSHSize + (BRCM_START_CODE_SIZE - iStartSize) * (iPktIdx); - if(Ctx->PESConvParams.m_pSpsPpsBuf) - free(Ctx->PESConvParams.m_pSpsPpsBuf); if(!posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen)) { memset(Ctx->PESConvParams.m_pSpsPpsBuf, 0, Ctx->PESConvParams.m_iSpsPpsLen); @@ -365,8 +355,6 @@ pSrc += iSize; } } - else - return BC_STS_INSUFF_RES; } return BC_STS_SUCCESS; } @@ -706,8 +694,11 @@ { uint32_t iCount = 0; - int sts = 0; + //unused BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; + //unused DTS_INPUT_MDATA *im = NULL; + //unused uint8_t *pSPES =NULL; + //unused uint32_t ulSize = 0; DTS_GET_CTX(hDevice,Ctx); @@ -732,9 +723,7 @@ Ctx->PESConvParams.lPendBufferSize = *pUlDataSize * 2; if (Ctx->PESConvParams.lPendBufferSize < 1024) Ctx->PESConvParams.lPendBufferSize = 1024; - sts = posix_memalign((void**)&Ctx->PESConvParams.pStartcodePendBuff, 8, Ctx->PESConvParams.lPendBufferSize); - if(sts) - return BC_STS_INSUFF_RES; + posix_memalign((void**)&Ctx->PESConvParams.pStartcodePendBuff, 8, Ctx->PESConvParams.lPendBufferSize); } //unused uint8_t* pSequenceHeader = Ctx->VidParams.pMetaData; diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_priv.cpp crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_priv.cpp --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_priv.cpp 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_priv.cpp 2010-08-16 04:38:08.000000000 +0000 @@ -39,6 +39,12 @@ #include "libcrystalhd_int_if.h" #include "libcrystalhd_priv.h" +#define BC_EOS_DETECTED 0xffffffff + +uint32_t g_nRefNum = 0; + +uint32_t g_nDrvHandleCnt = 0; + /*============== Global shared area usage ======================*/ /* Global mode settings */ /* @@ -49,9 +55,16 @@ bit 5 - Hwsetup in progress */ +/* struct _bc_dil_glob_s{ + uint32_t gDilOpMode; + uint32_t gHwInitSts; + BC_DTS_STATS stats; +} bc_dil_glob = {0,0,{0,0}};*/ + +#ifdef _USE_SHMEM_ bc_dil_glob_s *bc_dil_glob_ptr=NULL; -bool glob_mode_valid=TRUE; +BOOL glob_mode_valid=TRUE; BC_STATUS DtsCreateShMem(int *shmem_id) { int shmid=-1; @@ -69,7 +82,7 @@ //First Try to create it. if((shmid= shmget(shmkey, 1024, 0644|IPC_CREAT|IPC_EXCL))== -1 ) { if(errno==EEXIST) { - //DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:shmem already exists :%d\n",errno); + DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:shmem lareday exists :%d\n",errno); //shmem segment already exists so get the shmid if((shmid= shmget(shmkey, 1024, 0644))== -1 ) { DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:unable to get shmid :%d\n",errno); @@ -121,23 +134,22 @@ DtsGetDilShMem(shmid); } - *shmem_id =shmid; + *shmem_id =shmid; - return BC_STS_SUCCESS; + return BC_STS_SUCCESS; } BC_STATUS DtsGetDilShMem(uint32_t shmid) { - bc_dil_glob_ptr=(bc_dil_glob_s *)shmat(shmid,(void *)0,0); - if((long)bc_dil_glob_ptr==-1) { + bc_dil_glob_ptr=(bc_dil_glob_s *)shmat(shmid,(void *)0,0); + if((int)bc_dil_glob_ptr==-1) { DebugLog_Trace(LDIL_DBG,"Unable to open shared memory ...\n"); return BC_STS_ERROR; } return BC_STS_SUCCESS; } - BC_STATUS DtsDelDilShMem() { int shmid =0; @@ -165,7 +177,7 @@ if(buf.shm_nattch ==0) { //No process is currently attached to the shmem seg. go ahead and delete it if(-1!=shmctl(shmid,IPC_RMID,NULL)){ - // DebugLog_Trace(LDIL_DBG,"DtsDelDilShMem:deleted shmem segment ...\n"); + DebugLog_Trace(LDIL_DBG,"DtsDelDilShMem:deleted shmem segment ...\n"); return BC_STS_ERROR; } else{ @@ -177,81 +189,77 @@ } +#else +struct _bc_dil_glob_s{ + uint32_t gDilOpMode; + uint32_t gHwInitSts; + BC_DTS_STATS stats; +} bc_dil_glob = {0,0,{0,0}}; +#endif -uint32_t DtsGetgDevID(void) -{ - if(bc_dil_glob_ptr == NULL) - return BC_PCI_DEVID_INVALID; - else - return bc_dil_glob_ptr->DevID; -} - -void DtsSetgDevID(uint32_t DevID) -{ - bc_dil_glob_ptr->DevID = DevID; -} uint32_t DtsGetOPMode( void ) { +#ifdef _USE_SHMEM_ return bc_dil_glob_ptr->gDilOpMode; +#else + return bc_dil_glob.gDilOpMode; +#endif + + } void DtsSetOPMode( uint32_t value ) { +#ifdef _USE_SHMEM_ bc_dil_glob_ptr->gDilOpMode = value; +#else + bc_dil_glob.gDilOpMode = value; +#endif } uint32_t DtsGetHwInitSts( void ) { +#ifdef _USE_SHMEM_ return bc_dil_glob_ptr->gHwInitSts; +#else + return bc_dil_glob.gHwInitSts; +#endif } void DtsSetHwInitSts( uint32_t value ) { +#ifdef _USE_SHMEM_ bc_dil_glob_ptr->gHwInitSts = value; +#else + bc_dil_glob.gHwInitSts = value; +#endif } - void DtsRstStats( void ) { +#ifdef _USE_SHMEM_ memset(&bc_dil_glob_ptr->stats, 0, sizeof(bc_dil_glob_ptr->stats)); +#else + memset(&bc_dil_glob.stats, 0, sizeof(bc_dil_glob.stats)); +#endif } BC_DTS_STATS * DtsGetgStats ( void ) { +#ifdef _USE_SHMEM_ return &bc_dil_glob_ptr->stats; -} - -bool DtsIsDecOpened(pid_t nNewPID) -{ - if(bc_dil_glob_ptr == NULL) - return false; - - if (nNewPID == 0) - return bc_dil_glob_ptr->g_bDecOpened; - - if (nNewPID == bc_dil_glob_ptr->g_nProcID) - return false; +#else + return &bc_dil_glob.stats; +#endif - return bc_dil_glob_ptr->g_bDecOpened; } -bool DtsChkPID(pid_t nCurPID) +uint32_t DtsGetRefNum() { - if (bc_dil_glob_ptr->g_nProcID == 0) - return true; - - return (nCurPID == bc_dil_glob_ptr->g_nProcID); + return g_nRefNum++; } -void DtsSetDecStat(bool bDecOpen, pid_t PID) -{ - if (bDecOpen == true) - bc_dil_glob_ptr->g_nProcID = PID; - else - bc_dil_glob_ptr->g_nProcID = 0; - bc_dil_glob_ptr->g_bDecOpened = bDecOpen; -} /*============== Global shared area usage End.. ======================*/ #define TOP_FIELD_FLAG 0x01 @@ -1020,7 +1028,6 @@ DTS_LIB_CONTEXT * Ctx = DtsGetContext(userHandle); //unused DWORD dwTimeout = 0; - BC_STATUS sts; if( !Ctx ) return FALSE; @@ -1033,11 +1040,8 @@ // WILL need to take care of lb bytes returned. // Check the existing code. // - if(BC_STS_SUCCESS != (sts = DtsDrvCmd(Ctx,dwIoControlCode,Async,(BC_IOCTL_DATA *)lpInBuffer,FALSE))) - { - DebugLog_Trace(LDIL_DBG, "DtsDrvCmd Failed with status %d\n", sts); + if(BC_STS_SUCCESS != DtsDrvCmd(Ctx,dwIoControlCode,Async,(BC_IOCTL_DATA *)lpInBuffer,FALSE)) return FALSE; - } return TRUE; } @@ -1508,13 +1512,12 @@ // Name: DtsInitInterface // Description: Do application specific allocation and other initialization. //------------------------------------------------------------------------ -BC_STATUS DtsInitInterface(int hDevice, HANDLE *RetCtx, uint32_t mode) +BC_STATUS DtsInitInterface(int hDevice,HANDLE *RetCtx, uint32_t mode) { DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; pthread_attr_t thread_attr; - int ret = 0; Ctx = (DTS_LIB_CONTEXT*)malloc(sizeof(*Ctx)); if(!Ctx){ @@ -1548,7 +1551,6 @@ sts = DtsAllocMemPools(Ctx); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsAllocMemPools failed Sts:%d\n",sts); - *RetCtx = (HANDLE)Ctx; return sts; } @@ -1556,7 +1558,6 @@ sts = DtsMapYUVBuffs(Ctx); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsMapYUVBuffs failed Sts:%d\n",sts); - *RetCtx = (HANDLE)Ctx; return sts; } } @@ -1570,9 +1571,7 @@ pthread_create(&Ctx->htxThread, &thread_attr, txThreadProc, Ctx); pthread_attr_destroy(&thread_attr); - ret = posix_memalign((void**)&Ctx->alignBuf, 128, ALIGN_BUF_SIZE); - if(ret) - sts = BC_STS_INSUFF_RES; + posix_memalign((void**)&Ctx->alignBuf, 128, ALIGN_BUF_SIZE); *RetCtx = (HANDLE)Ctx; @@ -1580,43 +1579,6 @@ } //------------------------------------------------------------------------ -// Name: DtsReleaseInterface -// Description: Do application specific Release and other initialization. -//------------------------------------------------------------------------ -BC_STATUS DtsReleaseInterface(DTS_LIB_CONTEXT *Ctx) -{ - - if(!Ctx) - return BC_STS_INV_ARG; - - // Exit TX thread - Ctx->txThreadExit = true; - // wait to make sure the thread exited - pthread_join(Ctx->htxThread, NULL); - // de-Allocate circular buffer - txBufFree(&Ctx->circBuf); - Ctx->htxThread = 0; - if(Ctx->alignBuf) - free(Ctx->alignBuf); - - DtsReleaseMemPools(Ctx); - - if((Ctx->DevHandle != 0) && close(Ctx->DevHandle)!=0) //Zero if success - { - DebugLog_Trace(LDIL_DBG,"DtsDeviceClose: Close Handle Failed with error %d\n",errno); - } - - DtsSetHwInitSts(BC_DIL_HWINIT_NOT_YET); - - DtsDelDilShMem(); - - free(Ctx); - - return BC_STS_SUCCESS; - -} - -//------------------------------------------------------------------------ // Name: DtsNotifyOperatingMode // Description: Notfiy the operating mode to driver. //------------------------------------------------------------------------ @@ -1695,6 +1657,44 @@ } //------------------------------------------------------------------------ +// Name: DtsReleaseInterface +// Description: Do application specific Release and other initialization. +//------------------------------------------------------------------------ +BC_STATUS DtsReleaseInterface(DTS_LIB_CONTEXT *Ctx) +{ + + if(!Ctx) + return BC_STS_INV_ARG; + + DtsReleaseMemPools(Ctx); + + if(close(Ctx->DevHandle)!=0) //Zero if success + { + DebugLog_Trace(LDIL_DBG,"DtsDeviceClose: Close Handle Failed with error %d\n",errno); + + } + + DtsSetHwInitSts(BC_DIL_HWINIT_NOT_YET); + +#ifdef _USE_SHMEM_ + DtsDelDilShMem(); +#endif + + // Exit TX thread + Ctx->txThreadExit = true; + // wait to make sure the thread exited + pthread_join(Ctx->htxThread, NULL); + // de-Allocate circular buffer + txBufFree(&Ctx->circBuf); + Ctx->htxThread = 0; + free(Ctx->alignBuf); + + free(Ctx); + + return BC_STS_SUCCESS; + +} +//------------------------------------------------------------------------ // Name: DtsGetBCRegConfig // Description: Setup Register Sub-Key values. //------------------------------------------------------------------------ @@ -2300,12 +2300,9 @@ BC_STATUS txBufInit(pTXBUFFER txBuf, uint32_t sizeInit) { BC_STATUS sts = BC_STS_SUCCESS; - int ret = 0; if(txBuf->buffer != NULL) return BC_STS_INV_ARG; - ret = posix_memalign((void**)&txBuf->buffer, 128, sizeInit); - if(ret) - return BC_STS_INSUFF_RES; + posix_memalign((void**)&txBuf->buffer, 128, sizeInit); if(txBuf->buffer != NULL) { txBuf->basePointer = txBuf->buffer; @@ -2383,11 +2380,10 @@ if(txBuf == NULL) return BC_STS_INV_ARG; - pthread_mutex_lock(&txBuf->flushLock); - if(sizeToPop > txBuf->busySize) return BC_STS_INV_ARG; + pthread_mutex_lock(&txBuf->flushLock); sizeTop = (uint32_t)(txBuf->endPointer - (txBuf->basePointer + txBuf->readPointer) + 1); if(sizeToPop <= sizeTop) popSz = sizeToPop; @@ -2462,11 +2458,8 @@ uint8_t encrypted = 0; HANDLE hDevice = (HANDLE)Ctx; BC_DTS_STATUS pStat; - int ret = 0; - ret = posix_memalign((void**)&localBuffer, 128, CIRC_TX_BUF_SIZE); - if(ret) - return FALSE; + posix_memalign((void**)&localBuffer, 128, CIRC_TX_BUF_SIZE); while(!Ctx->txThreadExit) { @@ -2494,13 +2487,11 @@ szDataToSend = Ctx->circBuf.busySize; else szDataToSend = pStat.cpbEmptySize; - if(BC_STS_SUCCESS != txBufPop(&Ctx->circBuf, localBuffer, szDataToSend)) { - usleep(5 * 1000); - continue; - } + txBufPop(&Ctx->circBuf, localBuffer, szDataToSend); if(Ctx->VidParams.VideoAlgo == BC_VID_ALGO_VC1MP) encrypted |= 0x2; sts = DtsTxDmaText(hDevice, localBuffer, szDataToSend, &dramOff, encrypted); + if(sts == BC_STS_SUCCESS) DtsUpdateInStats(Ctx, szDataToSend); else @@ -2542,11 +2533,7 @@ } if(pIo.RetSts == BC_STS_SUCCESS) { - *pciids = pIo.u.pciCfg.pci_cfg_space[0] | - (pIo.u.pciCfg.pci_cfg_space[0] << 8) | - (pIo.u.pciCfg.pci_cfg_space[0] << 16) | - (pIo.u.pciCfg.pci_cfg_space[0] << 24); - //*pciids = *(uint32_t*)pIo.u.pciCfg.pci_cfg_space; + *pciids = *(uint32_t*)pIo.u.pciCfg.pci_cfg_space; close(drvHandle); return BC_STS_SUCCESS; } diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_priv.h crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_priv.h --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/libcrystalhd_priv.h 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/libcrystalhd_priv.h 2010-08-16 04:38:08.000000000 +0000 @@ -124,9 +124,6 @@ #define ALIGN_BUF_SIZE (512*1024) #define CIRC_TX_BUF_SIZE (4096*1024) - -#define BC_EOS_DETECTED 0xffffffff - typedef struct _DTS_MPOOL_TYPE { uint32_t type; uint32_t sz; @@ -362,59 +359,73 @@ /* Internal helper function */ uint32_t DtsGetWidthfromResolution(DTS_LIB_CONTEXT *Ctx, uint32_t Resolution); +#ifdef _DYNAMIC_BUFFERS_ +BC_STATUS DtsAddBuffsWithFmtChInfo(DTS_LIB_CONTEXT *Ctx); + +BC_STATUS DtsAllocNewRxBuffs(DTS_LIB_CONTEXT *Ctx, uint32_t BuffSz, uint32_t BuffCnt); + +BC_STATUS DtsFreeRxBuffs(DTS_LIB_CONTEXT *Ctx); + +void DtsGetMaxSize(DTS_LIB_CONTEXT *Ctx, U32 *Sz); + +BC_STATUS DtsHandleTimingMrkr(DTS_LIB_CONTEXT *Ctx); + +#if 0 +BC_STATUS DtsWaitForFlushDone(DTS_LIB_CONTEXT *Ctx, HANDLE hDevice, uint8_t *EOSDetected); +#endif + +#endif /*====================== Performance Counter Routines ============================*/ void DtsUpdateInStats(DTS_LIB_CONTEXT *Ctx, uint32_t size); void DtsUpdateOutStats(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); +/*====================== Debug Routines ========================================*/ +void DtsTestMdata(DTS_LIB_CONTEXT *gCtx); +BOOL DtsDbgCheckPointers(DTS_LIB_CONTEXT *Ctx,BC_IOCTL_DATA *pIo); + +BOOL DtsCheckRptPic(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); +BC_STATUS DtsUpdateVidParams(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); + /*============== Global shared area usage ======================*/ + #define BC_DIL_HWINIT_NOT_YET 0 #define BC_DIL_HWINIT_IN_PROGRESS 1 #define BC_DIL_HWINIT_DONE 2 +#ifdef _USE_SHMEM_ #define BC_DIL_SHMEM_KEY 0xBABEFACE typedef struct _bc_dil_glob_s{ - uint32_t gDilOpMode; - uint32_t gHwInitSts; - BC_DTS_STATS stats; - pid_t g_nProcID; - bool g_bDecOpened; - uint32_t DevID; + uint32_t gDilOpMode; + uint32_t gHwInitSts; + BC_DTS_STATS stats; } bc_dil_glob_s; BC_STATUS DtsGetDilShMem(uint32_t shmid); BC_STATUS DtsDelDilShMem(void); BC_STATUS DtsCreateShMem(int *shmem_id); - +#endif /* DTS Global Parameters Utility functions */ -uint32_t DtsGetOPMode(void); -void DtsSetOPMode(uint32_t value); -uint32_t DtsGetHwInitSts(void); -void DtsSetHwInitSts(uint32_t value); -void DtsRstStats(void); -BC_DTS_STATS * DtsGetgStats (void); -uint32_t DtsGetgDevID(void); -void DtsSetgDevID(uint32_t DevID); +uint32_t DtsGetOPMode( void ); +void DtsSetOPMode( uint32_t value ); +uint32_t DtsGetHwInitSts( void ); +void DtsSetHwInitSts( uint32_t value ); +void DtsRstStats( void ) ; +BC_DTS_STATS * DtsGetgStats ( void ); +uint32_t DtsGetRefNum(); BC_STATUS DtsGetDevType(uint32_t *pDevID, uint32_t *pVendID, uint32_t *pRevID); uint32_t DtsGetDevID(); -bool DtsIsDecOpened(pid_t nNewPID); +uint8_t DtsIsDecOpened(pid_t nNewPID); void DtsSetDecStat(bool bDecOpen, pid_t PID); bool DtsChkPID(pid_t nCurPID); void DtsLock(DTS_LIB_CONTEXT *Ctx); void DtsUnLock(DTS_LIB_CONTEXT *Ctx); -/*====================== Debug Routines ========================================*/ -void DtsTestMdata(DTS_LIB_CONTEXT *gCtx); -BOOL DtsDbgCheckPointers(DTS_LIB_CONTEXT *Ctx,BC_IOCTL_DATA *pIo); - -BOOL DtsCheckRptPic(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); -BC_STATUS DtsUpdateVidParams(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); - #ifdef __cplusplus } #endif diff -Nru crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/Makefile crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/Makefile --- crystalhd-0.0~git20101012.a3a83b8/linux_lib/libcrystalhd/Makefile 2010-10-12 20:47:14.000000000 +0000 +++ crystalhd-0.0~git20101029.6df10a0/linux_lib/libcrystalhd/Makefile 2010-08-16 04:38:08.000000000 +0000 @@ -2,7 +2,7 @@ # Broadcom "BCM970012/BCM970015" Crystal HD device interface library. # # -BCLIB_MINOR=6 +BCLIB_MINOR=5 BCLIB_MAJOR=3 BCLIB_NAME=libcrystalhd.so BCLIB_SL=$(BCLIB_NAME).$(BCLIB_MAJOR) @@ -24,7 +24,7 @@ # -D_USE_SHMEM_ CPPFLAGS += ${INCLUDES} -CPPFLAGS += -O2 -Wall -fPIC -shared -fstrict-aliasing -msse2 +CPPFLAGS += -g -Wall -fPIC -shared LDFLAGS = -Wl,-soname,${BCLIB_SL} -pthread SRCFILES = libcrystalhd_if.cpp \