diff -Nru tiomapconf-1.52.0/CHANGELOG tiomapconf-1.61.1/CHANGELOG --- tiomapconf-1.52.0/CHANGELOG 2012-11-14 16:36:23.000000000 +0000 +++ tiomapconf-1.61.1/CHANGELOG 2012-12-13 15:13:55.000000000 +0000 @@ -1,3 +1,44 @@ +v1.61: +------- + - [OMAP5][CLKDM][PWRDM][MODULE] complete migration to generic layers and fix some ES2.0 bugs + - [OMAP5][EMIF][MODULE] call genric module_xyz() functions instead of OMAP5-specific mod54xx_xyz() ones + - [OMAP5][SR][MODULE] call generic module_xyz() functions instead of OMAP5-specific mod54xx_xyz() ones + - [DEBUG] better trace memory reads and writes + - [OMAP4][CLKDM][PWRDM] move xyz_config_show to respective libraries + + +v1.60: +------- + - [MODULE][SYSCONFIG][AUDIT] reworked sysconfig audit + - [MODULE][CLKSPEED][AUDIT] reworked clkspeed audit + - [OMAP5][MODULE] rework "show opp" and "show pwst" to use new generic frameworks + - [VOLTDM] handle new OMAP543x ES2.0 voltage domain status registers + - [TRACE][OMAP4470][OMAP5] add EMIF total read and write bandwidth item to trace perf + - [PWRDM][EMU] move EMU domain enable/disable functions to powerdomain lib + - [TRACE][PERF][SETUP] fix segfault when default setup file cannot be created + - [OMAP5][PRCM] handle ES2.0 module changes in CM_xyz_CLKCTRL registers + - [OMAP5][PRCM] handle ES2.0 changes in CM_xyz_CLKSTCTRL registers + - [OMAP5][MODULE] handle OMAP543x ES2.x PRCM registers changes in module info list + - [OMAP5][MODULE][OPP] handle OMAP543x ES2.0 MPU and GPU frequency changes + - [OMAP5][PRCM][CLOCK] handle OMAP543x ES2.0 clock tree changes + - [OMAP5][DPLL] handle OMAP543x ES2.0 DPLLs changes + - [OMAP5][CTRLMOD] handle OMAP543x ES2.0 Control Module changes + - [OMAP5][EMIF] handle OMAP543x ES2.0 EMIF changes + - [OMAP5][SYSCONFIG][MODULE] fix BB2D sysconfig register + - [OMAP5][PRCM] handle OMAP543x ES2.0 PRM changes + - [OMAP5][PRCM] handle OMAP543x ES2.0 CM changes + - [OMAP5][MODULE] handle added/removed modules in OMAP543x ES2.0 + - [OMAP5][MODULE] fix missing PoR OPP rate for GPIO modules + - [OMAP5] handle no L4PER power domain in OMAP543x ES2.0 + - [OMAP5][CPUDETECT] allow user to select forced OMAP543x ES1.0 or ES2.0 + - [OMAP5] OMAP543x ES2.0 DIEID detection + - [REGRESSIONTESTSUITE] add EMIF test, remove kernel clock test, do not use register import + - [MODULE] introduce generic module layer + - [PWRDM] introduce generic power domain layer + - [CLKDM] introduce generic clock domain layer + - [I2C] update to I2C Tools library v3.1.0 + + v1.52: ------- - [OMAP5][CLKSPEED][AUDIT] fix missing BANDGAPTS expected clock rate diff -Nru tiomapconf-1.52.0/Makefile tiomapconf-1.61.1/Makefile --- tiomapconf-1.52.0/Makefile 2012-11-14 16:36:23.000000000 +0000 +++ tiomapconf-1.61.1/Makefile 2012-12-13 15:13:55.000000000 +0000 @@ -44,139 +44,301 @@ CC = $(CROSS_COMPILE)gcc -DEF_INC := $(shell $(CROSS_COMPILE)gcc -print-file-name=include) -MYCFLAGS+=$(CFLAGS) -D_OMAP5430 -D_SC_VER_1_16 -c -Wall -Wextra -Wno-missing-field-initializers -I. -Icommon -Ipmic -Iaudioic -Ilinux -Istatcoll -Iomap4 -Iomap5 -Ii2c-tools -I$(DEF_INC) -static -DESTDIR ?= target - - -OMAP4SOURCES= omap4/clock44xx.c omap4/clkdm44xx.c omap4/pwrdm44xx.c\ - omap4/voltdm44xx.c omap4/module44xx.c omap4/cpuinfo44xx.c\ - omap4/lib44xx.c omap4/gfx44xx.c omap4/ivahd44xx.c\ - omap4/abe44xx.c omap4/wkup44xx.c omap4/audit44xx.c\ - omap4/l3init44xx.c omap4/mpuss44xx.c omap4/alwon44xx.c\ - omap4/emu44xx.c omap4/smartreflex44xx.c omap4/main44xx.c\ - omap4/dpll44xx.c omap4/mpu44xx.c omap4/wkdep44xx.c\ - omap4/core44xx.c omap4/per44xx.c omap4/dsp44xx.c\ - omap4/dss44xx.c omap4/cam44xx.c omap4/hwobs44xx.c\ - omap4/abb44xx.c omap4/temperature44xx.c omap4/ctt44xx.c\ - omap4/pct44xx.c omap4/emif44xx.c omap4/coresight44xx.c\ - omap4/stm44xx.c omap4/pmi44xx.c omap4/pmi44xx_pwrdm.c\ - omap4/counters44xx.c omap4/l2cc44xx.c\ - omap4/pmi44xx_voltdm.c omap4/power_trace44xx.c\ - omap4/display44xx.c omap4/prcm44xx.c omap4/camera44xx.c\ - omap4/dep44xx.c omap4/uc_audit44xx.c\ - omap4/help44xx.c omap4/module44xx-data.c\ - omap4/vc44xx.c omap4/sr44xx-data.c omap4/vp44xx.c\ - omap4/vp44xx-data.c omap4/dpll44xx-data.c\ - omap4/dpll4470-data-38_4MHz.c\ - omap4/dpll4460-data-38_4MHz.c\ - omap4/dpll4430-data-38_4MHz.c omap4/pads44xx.c\ - omap4/opp44xx.c - - -OMAP4OBJECTS= $(OMAP4SOURCES:.c=.o) - - -OMAP5SOURCES= omap5/cpuinfo54xx.c omap5/main54xx.c omap5/cm54xx-defs.c\ - omap5/cm54xx.c omap5/prm54xx-defs.c omap5/prm54xx.c\ - omap5/sr54xx-defs.c omap5/sr54xx.c omap5/dss54xx.c\ - omap5/wkupaon54xx.c omap5/cam54xx.c omap5/dsp54xx.c\ - omap5/abe54xx.c omap5/gpu54xx.c omap5/coreaon54xx.c\ - omap5/iva54xx.c omap5/mpu54xx.c omap5/l3init54xx.c\ - omap5/core54xx.c omap5/l4per54xx.c omap5/prmdevice54xx.c\ - omap5/emu54xx.c omap5/ckgen54xx.c omap5/instr54xx.c\ - omap5/help54xx.c omap5/dpll54xx.c omap5/prcm54xx.c\ - omap5/clock54xx.c omap5/voltdm54xx.c omap5/pwrdm54xx.c\ - omap5/clkdm54xx.c omap5/module54xx-data.c\ - omap5/module54xx.c omap5/dpll54xx-data.c\ - omap5/dpll54xx-data-19_2MHz.c\ - omap5/dpll54xx-data-38_4MHz.c\ - omap5/audit54xx.c omap5/lib54xx.c\ - omap5/ctrlmod_core54xx-defs.c\ - omap5/ctrlmod_core_pad54xx-defs.c\ - omap5/ctrlmod_wkup54xx-defs.c\ - omap5/ctrlmod_wkup_pad54xx-defs.c omap5/ctrlmod54xx.c\ - omap5/ctrlmod54xx-data.c omap5/temp54xx.c\ - omap5/sysconfig54xx-defs.c omap5/hwobs54xx.c\ - omap5/abb54xx.c omap5/emif54xx-defs.c omap5/emif54xx.c\ - omap5/clkdm_dependency54xx-data.c\ - omap5/clkdm_dependency54xx.c omap5/ctt54xx.c\ - omap5/vp54xx.c omap5/vc54xx.c omap5/opp54xx.c -OMAP5OBJECTS= $(OMAP5SOURCES:.c=.o) +DEF_INC := $(shell $(CROSS_COMPILE)gcc -print-file-name=include) -SOURCES= omapconf.c builddate.c common/lib.c common/reg.c\ - common/autoadjust_table.c common/genlist.c common/abb.c\ - common/module.c common/clkdm.c common/pwrdm.c pmic/pmic.c\ - common/cpuinfo.c common/dpll.c i2c-tools/i2cbusses.c\ - i2c-tools/i2cget.c i2c-tools/i2cset.c i2c-tools/util.c\ - common/help.c common/clkdm_dependency.c\ - common/vp.c common/vc.c common/sr.c common/audit.c\ - statcoll/sci_swcapture.c statcoll/sci.c\ - statcoll/cToolsHelper.c common/timestamp_32k.c\ - common/lib_android.c common/mem.c common/emif.c\ - common/trace.c common/opp.c common/voltdm.c\ - common/temperature.c - -OBJECTS= $(SOURCES:.c=.o) +DEF_INC_PATH = -I. -Icommon -Ipmic -Iaudioic -Ilinux -Ii2c-tools\ + -Iarch/arm/mach-omap/common\ + -Iarch/arm/mach-omap/common/prcm\ + -Iarch/arm/mach-omap/common/statcoll\ + -Iarch/arm/mach-omap/omap4\ + -Iarch/arm/mach-omap/omap4/prcm\ + -Iarch/arm/mach-omap/omap4/dpll\ + -Iarch/arm/mach-omap/omap4/pmi\ + -Iarch/arm/mach-omap/omap5\ + -Iarch/arm/mach-omap/omap5/prcm\ + -Iarch/arm/mach-omap/omap5/dpll\ + -Iarch/arm/mach-omap/omap5/ctrlmod -PMICSOURCES= pmic/twl603x.c pmic/tps62361.c pmic/twl603x_lib.c +MYCFLAGS+=$(CFLAGS) -D_OMAP5430 -D_SC_VER_1_16 -c -Wall -Wextra\ + -Wno-missing-field-initializers -I$(DEF_INC) $(DEF_INC_PATH) -static -PMICOBJECTS= $(PMICSOURCES:.c=.o) +DESTDIR ?= target -AUDIOICSOURCES= audioic/twl6040.c audioic/twl6040_lib.c -AUDIOICOBJECTS= $(AUDIOICSOURCES:.c=.o) +OMAPSOURCES=\ + arch/arm/mach-omap/common/prcm/prcm-module.c\ + arch/arm/mach-omap/common/prcm/clkdm.c\ + arch/arm/mach-omap/common/prcm/pwrdm.c\ + arch/arm/mach-omap/common/prcm/abb.c\ + arch/arm/mach-omap/common/prcm/clkdm_dependency.c\ + arch/arm/mach-omap/common/prcm/vp.c\ + arch/arm/mach-omap/common/prcm/vc.c\ + arch/arm/mach-omap/common/dpll.c\ + arch/arm/mach-omap/common/sr.c\ + arch/arm/mach-omap/common/emif.c\ + arch/arm/mach-omap/common/module.c\ + arch/arm/mach-omap/common/clockdomain.c\ + arch/arm/mach-omap/common/powerdomain.c\ + arch/arm/mach-omap/common/voltdomain.c\ + arch/arm/mach-omap/common/statcoll/sci_swcapture.c\ + arch/arm/mach-omap/common/statcoll/sci.c\ + arch/arm/mach-omap/common/statcoll/cToolsHelper.c\ + arch/arm/mach-omap/common/timestamp_32k.c + +OMAPOBJECTS= $(OMAPSOURCES:.c=.o) + + + + +OMAP4SOURCES=\ + arch/arm/mach-omap/omap4/prcm/module44xx-data.c\ + arch/arm/mach-omap/omap4/prcm/clock44xx.c\ + arch/arm/mach-omap/omap4/prcm/clkdm44xx.c\ + arch/arm/mach-omap/omap4/prcm/pwrdm44xx.c\ + arch/arm/mach-omap/omap4/prcm/voltdm44xx.c\ + arch/arm/mach-omap/omap4/prcm/abb44xx.c\ + arch/arm/mach-omap/omap4/prcm/vp44xx.c\ + arch/arm/mach-omap/omap4/prcm/vp44xx-data.c\ + arch/arm/mach-omap/omap4/prcm/vc44xx.c\ + arch/arm/mach-omap/omap4/prcm/gfx44xx.c\ + arch/arm/mach-omap/omap4/prcm/ivahd44xx.c\ + arch/arm/mach-omap/omap4/prcm/abe44xx.c\ + arch/arm/mach-omap/omap4/prcm/l3init44xx.c\ + arch/arm/mach-omap/omap4/prcm/mpu44xx.c\ + arch/arm/mach-omap/omap4/prcm/wkdep44xx.c\ + arch/arm/mach-omap/omap4/prcm/core44xx.c\ + arch/arm/mach-omap/omap4/prcm/per44xx.c\ + arch/arm/mach-omap/omap4/prcm/dsp44xx.c\ + arch/arm/mach-omap/omap4/prcm/prcm44xx.c\ + arch/arm/mach-omap/omap4/prcm/camera44xx.c\ + arch/arm/mach-omap/omap4/prcm/dep44xx.c\ + arch/arm/mach-omap/omap4/prcm/alwon44xx.c\ + arch/arm/mach-omap/omap4/prcm/emu44xx.c\ + arch/arm/mach-omap/omap4/prcm/dss44xx.c\ + arch/arm/mach-omap/omap4/prcm/cam44xx.c\ + arch/arm/mach-omap/omap4/prcm/wkup44xx.c\ + arch/arm/mach-omap/omap4/dpll/dpll44xx.c\ + arch/arm/mach-omap/omap4/dpll/dpll44xx-data.c\ + arch/arm/mach-omap/omap4/dpll/dpll4470-data-38_4MHz.c\ + arch/arm/mach-omap/omap4/dpll/dpll4460-data-38_4MHz.c\ + arch/arm/mach-omap/omap4/dpll/dpll4430-data-38_4MHz.c\ + arch/arm/mach-omap/omap4/pmi/coresight44xx.c\ + arch/arm/mach-omap/omap4/pmi/stm44xx.c\ + arch/arm/mach-omap/omap4/pmi/pmi44xx.c\ + arch/arm/mach-omap/omap4/pmi/pmi44xx_pwrdm.c\ + arch/arm/mach-omap/omap4/pmi/pmi44xx_voltdm.c\ + arch/arm/mach-omap/omap4/pmi/power_trace44xx.c\ + arch/arm/mach-omap/omap4/module44xx.c\ + arch/arm/mach-omap/omap4/cpuinfo44xx.c\ + arch/arm/mach-omap/omap4/lib44xx.c\ + arch/arm/mach-omap/omap4/audit44xx.c\ + arch/arm/mach-omap/omap4/mpuss44xx.c\ + arch/arm/mach-omap/omap4/smartreflex44xx.c\ + arch/arm/mach-omap/omap4/main44xx.c\ + arch/arm/mach-omap/omap4/hwobs44xx.c\ + arch/arm/mach-omap/omap4/temperature44xx.c\ + arch/arm/mach-omap/omap4/ctt44xx.c\ + arch/arm/mach-omap/omap4/pct44xx.c\ + arch/arm/mach-omap/omap4/emif44xx.c\ + arch/arm/mach-omap/omap4/counters44xx.c\ + arch/arm/mach-omap/omap4/l2cc44xx.c\ + arch/arm/mach-omap/omap4/display44xx.c\ + arch/arm/mach-omap/omap4/uc_audit44xx.c\ + arch/arm/mach-omap/omap4/help44xx.c\ + arch/arm/mach-omap/omap4/sr44xx-data.c\ + arch/arm/mach-omap/omap4/pads44xx.c\ + arch/arm/mach-omap/omap4/opp44xx.c + + +OMAP4OBJECTS= $(OMAP4SOURCES:.c=.o) + + + + +OMAP5SOURCES=\ + arch/arm/mach-omap/omap5/prcm/cm54xxes1-defs.c\ + arch/arm/mach-omap/omap5/prcm/cm54xx-defs.c\ + arch/arm/mach-omap/omap5/prcm/cm54xx.c\ + arch/arm/mach-omap/omap5/prcm/prm54xxes1-defs.c\ + arch/arm/mach-omap/omap5/prcm/prm54xx-defs.c\ + arch/arm/mach-omap/omap5/prcm/prm54xx.c\ + arch/arm/mach-omap/omap5/prcm/clock54xx.c\ + arch/arm/mach-omap/omap5/prcm/abb54xx.c\ + arch/arm/mach-omap/omap5/prcm/vp54xx.c\ + arch/arm/mach-omap/omap5/prcm/vc54xx.c\ + arch/arm/mach-omap/omap5/prcm/clkdm_dependency54xx.c\ + arch/arm/mach-omap/omap5/prcm/clkdm_dependency54xxes1-data.c\ + arch/arm/mach-omap/omap5/prcm/clkdm_dependency54xx-data.c\ + arch/arm/mach-omap/omap5/prcm/dss54xx.c\ + arch/arm/mach-omap/omap5/prcm/wkupaon54xx.c\ + arch/arm/mach-omap/omap5/prcm/cam54xx.c\ + arch/arm/mach-omap/omap5/prcm/dsp54xx.c\ + arch/arm/mach-omap/omap5/prcm/abe54xx.c\ + arch/arm/mach-omap/omap5/prcm/gpu54xx.c\ + arch/arm/mach-omap/omap5/prcm/coreaon54xx.c\ + arch/arm/mach-omap/omap5/prcm/iva54xx.c\ + arch/arm/mach-omap/omap5/prcm/mpu54xx.c\ + arch/arm/mach-omap/omap5/prcm/l3init54xx.c\ + arch/arm/mach-omap/omap5/prcm/core54xx.c\ + arch/arm/mach-omap/omap5/prcm/l4per54xx.c\ + arch/arm/mach-omap/omap5/prcm/prmdevice54xx.c\ + arch/arm/mach-omap/omap5/prcm/emu54xx.c\ + arch/arm/mach-omap/omap5/prcm/ckgen54xx.c\ + arch/arm/mach-omap/omap5/prcm/instr54xx.c\ + arch/arm/mach-omap/omap5/prcm/prcm54xx.c\ + arch/arm/mach-omap/omap5/prcm/voltdm54xx.c\ + arch/arm/mach-omap/omap5/prcm/pwrdm54xx.c\ + arch/arm/mach-omap/omap5/prcm/clkdm54xx.c\ + arch/arm/mach-omap/omap5/prcm/module54xx.c\ + arch/arm/mach-omap/omap5/dpll/dpll54xx.c\ + arch/arm/mach-omap/omap5/dpll/dpll54xx-data.c\ + arch/arm/mach-omap/omap5/dpll/dpll54xx-data-19_2MHz.c\ + arch/arm/mach-omap/omap5/dpll/dpll54xx-data-38_4MHz.c\ + arch/arm/mach-omap/omap5/ctrlmod/ctrlmod_core54xx-defs.c\ + arch/arm/mach-omap/omap5/ctrlmod/ctrlmod_core_pad54xx-defs.c\ + arch/arm/mach-omap/omap5/ctrlmod/ctrlmod_wkup54xx-defs.c\ + arch/arm/mach-omap/omap5/ctrlmod/ctrlmod_wkup_pad54xx-defs.c\ + arch/arm/mach-omap/omap5/ctrlmod/ctrlmod54xx.c\ + arch/arm/mach-omap/omap5/ctrlmod/ctrlmod54xx-data.c\ + arch/arm/mach-omap/omap5/cpuinfo54xx.c\ + arch/arm/mach-omap/omap5/main54xx.c\ + arch/arm/mach-omap/omap5/sr54xx-defs.c\ + arch/arm/mach-omap/omap5/sr54xx.c\ + arch/arm/mach-omap/omap5/help54xx.c\ + arch/arm/mach-omap/omap5/audit54xx.c\ + arch/arm/mach-omap/omap5/lib54xx.c\ + arch/arm/mach-omap/omap5/temp54xx.c\ + arch/arm/mach-omap/omap5/sysconfig54xx-defs.c\ + arch/arm/mach-omap/omap5/hwobs54xx.c\ + arch/arm/mach-omap/omap5/emif54xxes1-defs.c\ + arch/arm/mach-omap/omap5/emif54xx-defs.c\ + arch/arm/mach-omap/omap5/emif54xx.c\ + arch/arm/mach-omap/omap5/ctt54xx.c\ + arch/arm/mach-omap/omap5/opp54xx.c + +OMAP5OBJECTS= $(OMAP5SOURCES:.c=.o) + + + + +SOURCES=\ + omapconf.c\ + builddate.c\ + common/lib.c\ + common/reg.c\ + common/autoadjust_table.c\ + common/genlist.c\ + common/cpuinfo.c\ + common/help.c\ + common/audit.c\ + common/lib_android.c\ + common/mem.c\ + common/trace.c\ + common/opp.c\ + common/temperature.c\ + pmic/pmic.c + +OBJECTS= $(SOURCES:.c=.o) + + + + +PMICSOURCES= pmic/twl603x.c pmic/tps62361.c pmic/twl603x_lib.c + +PMICOBJECTS= $(PMICSOURCES:.c=.o) + + + + +AUDIOICSOURCES= audioic/twl6040.c audioic/twl6040_lib.c + +AUDIOICOBJECTS= $(AUDIOICSOURCES:.c=.o) + + + + +LINUXSOURCES= linux/cpufreq.c linux/cstate.c linux/interrupts.c\ + linux/timer_stats.c linux/linux_mem.c + + +LINUXOBJECTS= $(LINUXSOURCES:.c=.o) + + + + +I2CSOURCES=\ + i2c-tools/i2cbusses.c\ + i2c-tools/i2cget.c\ + i2c-tools/i2cset.c\ + i2c-tools/util.c\ + +I2COBJECTS= $(I2CSOURCES:.c=.o) + + + + +ALLOBJECTS= $(OBJECTS) $(OMAPOBJECTS) $(OMAP4OBJECTS) $(OMAP5OBJECTS) $(LINUXOBJECTS) $(PMICOBJECTS) $(AUDIOICOBJECTS) $(I2COBJECTS) + + + + +EXECUTABLE= omapconf + + + + +all: $(SOURCES) $(ALLOBJECTS) $(EXECUTABLE) + + + + +$(EXECUTABLE): $(ALLOBJECTS) + $(CC) -static $(LDFLAGS) $(ALLOBJECTS) -lrt -o $@ + rm -f builddate.c -LINUXSOURCES= linux/cpufreq.c linux/cstate.c linux/interrupts.c\ - linux/timer_stats.c linux/linux_mem.c -LINUXOBJECTS= $(LINUXSOURCES:.c=.o) +.c.o: + $(CC) $(MYCFLAGS) $< -o $@ -ALLOBJECTS= $(OBJECTS) $(OMAP4OBJECTS) $(OMAP5OBJECTS) $(LINUXOBJECTS) $(PMICOBJECTS) $(AUDIOICOBJECTS) -EXECUTABLE= omapconf +builddate.c: + echo 'char *builddate="'`date`'";' > builddate.c -all: $(SOURCES) $(ALLOBJECTS) $(EXECUTABLE) -$(EXECUTABLE): $(ALLOBJECTS) - $(CC) -static $(LDFLAGS) $(ALLOBJECTS) -lrt -o $@ - rm -f builddate.c -.c.o: - $(CC) $(MYCFLAGS) $< -o $@ +install: omapconf + install -d $(DESTDIR) + install omapconf $(DESTDIR) -builddate.c: - echo 'char *builddate="'`date`'";' > builddate.c -install: omapconf - install -d $(DESTDIR) - install omapconf $(DESTDIR) +install_android: omapconf + adb push omapconf /data/ -install_android: omapconf - adb push omapconf /data/ clean: - rm -f omapconf *.o builddate.c - rm -f $(OBJECTS) - rm -f $(LINUXOBJECTS) - rm -f $(OMAP4OBJECTS) - rm -f $(OMAP5OBJECTS) - rm -f $(PMICOBJECTS) - rm -f $(AUDIOICOBJECTS) + rm -f omapconf *.o builddate.c + rm -f $(OBJECTS) + rm -f $(LINUXOBJECTS) + rm -f $(OMAPOBJECTS) + rm -f $(OMAP4OBJECTS) + rm -f $(OMAP5OBJECTS) + rm -f $(PMICOBJECTS) + rm -f $(AUDIOICOBJECTS) + rm -f $(I2COBJECTS) diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/clockdomain.c tiomapconf-1.61.1/arch/arm/mach-omap/common/clockdomain.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/clockdomain.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/clockdomain.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,435 @@ +/* + * + * @Component OMAPCONF + * @Filename clockdomain.c + * @Description Clock Domain Generic Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define CLOCKDM_DEBUG */ +#ifdef CLOCKDM_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +static int _clockdm_info_get(const char *clockdm, clockdm_info *data); + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_init + * @BRIEF initialize internal data + * @DESCRIPTION initialize internal data (architecture dependent) + *//*------------------------------------------------------------------------ */ +void clockdm_init(void) +{ + #ifdef CLOCKDM_DEBUG + int i, count; + const genlist *clkdm_list; + clockdm_info clkdm; + #endif + + if (cpu_is_omap44xx()) { + clkdm44xx_init(); + } else if (cpu_is_omap54xx()) { + clkdm54xx_init(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } + + #ifdef CLOCKDM_DEBUG + clkdm_list = clockdm_list_get(); + count = genlist_getcount((genlist *) clkdm_list); + printf("Clock Domain List:\n"); + for (i = 0; i < count; i++) { + genlist_get((genlist *) clkdm_list, i, (clockdm_info *) &clkdm); + printf(" %s:\n", clkdm.name); + printf(" ID:%d (%s)\n", clkdm.id, + clkdm54xx_name_get(clkdm.id)); + printf(" PwrDM: %s\n", clkdm.powerdm); + printf(" VoltDM: %s\n", clkdm.voltdm); + printf(" CLKSTCTRL REG: %s\n", (clkdm.clkstctrl)->name); + printf(" Properties: %d\n", clkdm.properties); + printf("\n\n"); + } + printf("Clock Domain count: %d\n\n", count); + #endif +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_deinit + * @BRIEF free dynamically allocated internal data. + * @DESCRIPTION free dynamically allocated internal data. + * MUST BE CALLED AT END OF EXECUTION. + *//*------------------------------------------------------------------------ */ +void clockdm_deinit(void) +{ + if (cpu_is_omap44xx()) { + clkdm44xx_deinit(); + } else if (cpu_is_omap54xx()) { + clkdm54xx_deinit(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_list_get + * @BRIEF return the list of clock domains + * @RETURNS list of clock domains in case of success + * NULL in case of error + * @DESCRIPTION return the list of clock domains + *//*------------------------------------------------------------------------ */ +const genlist *clockdm_list_get(void) +{ + if (cpu_is_omap44xx()) { + return clkdm44xx_list_get(); + } else if (cpu_is_omap54xx()) { + return clkdm54xx_list_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return NULL; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_count_get + * @BRIEF return the number of clock domains + * @RETURNS number of clock domains (> 0) in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @DESCRIPTION return the number of clock domains + *//*------------------------------------------------------------------------ */ +int clockdm_count_get(void) +{ + if (cpu_is_omap44xx()) { + return clkdm44xx_count_get(); + } else if (cpu_is_omap54xx()) { + return clkdm54xx_count_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION _clockdm_info_get + * @BRIEF return the saved informations of a given clock domain. + * @RETURNS 0 in case of success + * -1 in case of error + * @param[in] clockdm: clock domain name + * @param[in,out] data:clock domain details + * @DESCRIPTION return the saved informations of a given clock domain. + *//*------------------------------------------------------------------------ */ +static int _clockdm_info_get(const char *clockdm, clockdm_info *data) +{ + const genlist *clkdm_list; + int i, count; + + CHECK_NULL_ARG(clockdm, -1); + CHECK_NULL_ARG(data, -1); + + clkdm_list = clockdm_list_get(); + count = genlist_getcount((genlist *) clkdm_list); + for (i = 0; i < count; i++) { + genlist_get((genlist *) clkdm_list, i, (void *) data); + if (strcmp(data->name, clockdm) == 0) { + dprintf("%s(%s): found.\n", __func__, clockdm); + return 0; + } + } + + dprintf("%s(%s): not found!\n", __func__, clockdm); + return -1; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_id_get + * @BRIEF return the unique ID of a given clock domain. + * @RETURNS >= 0 clock domain ID + * -1 in case of error + * @param[in] clockdm: clock domain name + * @DESCRIPTION return the unique ID of a given clock domain. + *//*------------------------------------------------------------------------ */ +int clockdm_id_get(const char *clockdm) +{ + int id; + clockdm_info data; + + CHECK_NULL_ARG(clockdm, -1); + + id = _clockdm_info_get(clockdm, &data); + if (id == 0) + id = data.id; + + dprintf("%s(%s) = %d\n", __func__, clockdm, id); + return id; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_powerdm_get + * @BRIEF return the power domain name a clock domain is part of + * @RETURNS power domain name on success. + * NULL in case of error + * @param[in] clockdm: clock domain name + * @DESCRIPTION return the power domain name a clock domain is part of + *//*------------------------------------------------------------------------ */ +const char *clockdm_powerdm_get(const char *clockdm) +{ + int ret; + clockdm_info data; + + CHECK_NULL_ARG(clockdm, NULL); + + ret = _clockdm_info_get(clockdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve clockdm_info struct!\n", + __func__, clockdm); + return NULL; + } + + dprintf("%s(%s) = %s\n", __func__, clockdm, data.powerdm); + return data.powerdm; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_voltdm_get + * @BRIEF return the voltage domain name a clock domain is part of + * @RETURNS voltage domain name on success. + * NULL in case of error (not found) + * @param[in] clockdm: clock domain name + * @DESCRIPTION return the voltage domain name a clock domain is part of + *//*------------------------------------------------------------------------ */ +const char *clockdm_voltdm_get(const char *clockdm) +{ + int ret; + clockdm_info data; + + CHECK_NULL_ARG(clockdm, NULL); + + ret = _clockdm_info_get(clockdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve clockdm_info struct!\n", + __func__, clockdm); + return NULL; + } + + dprintf("%s(%s) = %s\n", __func__, clockdm, data.voltdm); + return data.voltdm; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_clkstctrl_get + * @BRIEF return the CLKSTCTRL register of a given clock domain + * @RETURNS CLKSTCTRL register on success + * NULL in case of error (not found) + * @param[in] clockdm: clock domain name + * @DESCRIPTION return the CLKSTCTRL register of a given clock domain + *//*------------------------------------------------------------------------ */ +reg *clockdm_clkstctrl_get(const char *clockdm) +{ + int ret; + clockdm_info data; + + CHECK_NULL_ARG(clockdm, NULL); + + ret = _clockdm_info_get(clockdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve clockdm_info struct!\n", + __func__, clockdm); + return NULL; + } + + if (data.clkstctrl != NULL) { + dprintf("%s(%s): CM_CLKSTCTRL=%s\n", __func__, + clockdm, reg_name_get(data.clkstctrl)); + return data.clkstctrl; + } else { + dprintf("%s(%s): CM_CLKSTCTRL==NULL\n", __func__, clockdm); + return NULL; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_status_get + * @BRIEF return the status of a given clock domain + * @RETURNS clock domain status on success + * CLKDM_STATUS_MAX in case of error + * @param[in] clockdm: clock domain name + * @DESCRIPTION return the status of a given clock domain + *//*------------------------------------------------------------------------ */ +clkdm_status clockdm_status_get(const char *clockdm) +{ + reg *clkstctrl_reg; + unsigned int clkstctrl; + clkdm_status st; + + CHECK_NULL_ARG(clockdm, CLKDM_STATUS_MAX); + + clkstctrl_reg = clockdm_clkstctrl_get(clockdm); + if (clkstctrl_reg != NULL) { + clkstctrl = reg_read(clkstctrl_reg); + st = clkdm_status_get(clkstctrl); + dprintf("%s(%s): CM_CLKSTCTRL=%s status=%s\n", __func__, + clockdm, reg_name_get(clkstctrl_reg), + clkdm_status_name_get(st)); + return st; + } else { + dprintf("%s(%s): CM_CLKSTCTRL==NULL\n", __func__, clockdm); + return CLKDM_STATUS_MAX; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_ctrl_mode_get + * @BRIEF return the control mode of a given clock domain + * @RETURNS control mode on success + * CLKM_CTRL_MODE_MAX in case of error + * @param[in] clockdm: clock domain name + * @DESCRIPTION return the control mode of a given clock domain + *//*------------------------------------------------------------------------ */ +clkdm_ctrl_mode clockdm_ctrl_mode_get(const char *clockdm) +{ + reg *clkstctrl_reg; + unsigned int clkstctrl; + clkdm_ctrl_mode mode; + + CHECK_NULL_ARG(clockdm, CLKM_CTRL_MODE_MAX); + + clkstctrl_reg = clockdm_clkstctrl_get(clockdm); + if (clkstctrl_reg != NULL) { + clkstctrl = reg_read(clkstctrl_reg); + mode = clkdm_ctrl_mode_get(clkstctrl); + dprintf("%s(%s): CM_CLKSTCTRL=%s ctrl mode=%s\n", __func__, + clockdm, reg_name_get(clkstctrl_reg), + clkdm_ctrl_mode_name_get(mode)); + return mode; + } else { + dprintf("%s(%s): CM_CLKSTCTRL==NULL\n", __func__, clockdm); + return CLKM_CTRL_MODE_MAX; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clockdm_config_show + * @BRIEF display clock domain configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in,out] stream: output file + * @param[in] clockdm: clock domain name + * @DESCRIPTION display clock domain configuration + *//*------------------------------------------------------------------------ */ +int clockdm_config_show(FILE *stream, const char *clockdm) +{ + clockdm_info data; + unsigned int cm_clkstctrl; + char s[64]; + int ret; + + CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(clockdm, OMAPCONF_ERR_ARG); + + ret = _clockdm_info_get(clockdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve clockdm_info struct!\n", + __func__, clockdm); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + /* Read CLKSTCTRL register if not NULL */ + if (data.clkstctrl == NULL) /* Nothing to show */ + return 0; + cm_clkstctrl = reg_read(data.clkstctrl); + + /* Decode and display clock domain's configuration */ + fprintf(stream, + "|----------------------------------------------------------------|\n"); + strcpy(s, data.name); + strcat(s, " Clock Domain Configuration"); + fprintf(stream, "| %-62s |\n", s); + fprintf(stream, + "|--------------------------------------|-------------------------|\n"); + fprintf(stream, "| %-36s | %-23s |\n", "Clock State Transition control", + clkdm_ctrl_mode_name_get(clkdm_ctrl_mode_get(cm_clkstctrl))); + + if (cpu_is_omap44xx()) { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + ret = OMAPCONF_ERR_CPU; /* FIXME */ + } else if (cpu_is_omap54xx()) { + ret = clkdm54xx_config_show(stream, data); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + ret = OMAPCONF_ERR_CPU; + } + + fprintf(stream, + "|----------------------------------------------------------------|\n\n"); + + return ret; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/clockdomain.h tiomapconf-1.61.1/arch/arm/mach-omap/common/clockdomain.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/clockdomain.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/clockdomain.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,112 @@ +/* + * + * @Component OMAPCONF + * @Filename clockdomain.h + * @Description Clock Domain Generic Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __CLOCKDOMAIN_H__ +#define __CLOCKDOMAIN_H__ + + +#include +#include +#include +#include + + +#define CLKDM_MAX_NAME_LENGTH 16 + + +#define CLKDM_EMU ((const char *) "EMU") +#define CLKDM_WKUPAON ((const char *) "WKUPAON") +#define CLKDM_COREAON ((const char *) "COREAON") +#define CLKDM_CAM ((const char *) "CAM") +#define CLKDM_L4_CFG ((const char *) "L4CFG") +#define CLKDM_EMIF ((const char *) "EMIF") +#define CLKDM_IPU ((const char *) "IPU") +#define CLKDM_L3_MAIN2 ((const char *) "L3MAIN2") +#define CLKDM_L3_INSTR ((const char *) "L3INSTR") +#define CLKDM_L3_MAIN1 ((const char *) "L3MAIN1") +#define CLKDM_C2C ((const char *) "C2C") +#define CLKDM_DMA ((const char *) "DMA") +#define CLKDM_MIPIEXT ((const char *) "MIPIEXT") +#define CLKDM_DSS ((const char *) "DSS") +#define CLKDM_CUST_EFUSE ((const char *) "CUSTEFUSE") +#define CLKDM_L3_INIT ((const char *) "L3INIT") +#define CLKDM_L4_PER ((const char *) "L4PER") +#define CLKDM_L4_SEC ((const char *) "L4SEC") +#define CLKDM_ABE ((const char *) "ABE") +#define CLKDM_DSP ((const char *) "DSP") +#define CLKDM_GPU ((const char *) "GPU") +#define CLKDM_IVA ((const char *) "IVA") +#define CLKDM_MPU ((const char *) "MPU") +#define CLKDM_NONE ((const char *) "NONE") +#define CLKDM_UNKNOWN ((const char *) "UNKNOWN") + + +typedef struct { + const char *name; + int id; + const char *powerdm; + const char *voltdm; + reg *clkstctrl; + int properties; +} clockdm_info; + + +void clockdm_init(void); +void clockdm_deinit(void); + +int clockdm_count_get(void); +const genlist *clockdm_list_get(void); + +int clockdm_id_get(const char *clockdm); +const char *clockdm_powerdm_get(const char *clockdm); +const char *clockdm_voltdm_get(const char *clockdm); +reg *clockdm_clkstctrl_get(const char *clockdm); + +clkdm_status clockdm_status_get(const char *clockdm); +clkdm_ctrl_mode clockdm_ctrl_mode_get(const char *clockdm); + +int clockdm_config_show(FILE *stream, const char *clockdm); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/dpll.c tiomapconf-1.61.1/arch/arm/mach-omap/common/dpll.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/dpll.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/dpll.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,487 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll.c + * @Description OMAP DPLL Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2006 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include + + +/* #define DPLL_DEBUG */ +#ifdef DPLL_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +static const char + dpll_mode_names[DPLL_MODE_MAX][DPLL_MODE_MAX_NAME_LENGTH] = { + "RESERVED", + "LPST", + "FRST", + "RESERVED", + "MNBP", + "LPBP", + "FRBP", + "Lock"}; + + +static const char + dpll_ramp_level_names[DPLL_RAMP_LEVEL_MAX][DPLL_RAMP_LEVEL_MAX_NAME_LENGTH] = { + "No Ramp", + "8,4,2", + "4,2,1.5", + "RESERVED"}; + + +static const char + dpll_autoidle_mode_names[DPLL_AUTOIDLE_MODE_MAX][DPLL_AUTOIDLE_MODE_MAX_NAME_LENGTH] = { + "Disabled", + "Auto LPST", + "Auto FRST", + "RESERVED", + "RESERVED", + "Auto LPBP", + "Auto FRBP", + "RESERVED"}; + + +static const char + dpll_status_names[DPLL_STATUS_MAX][DPLL_STATUS_MAX_NAME_LENGTH] = { + "Bypassed", + "Locked", + "Stopped", + "Reserved"}; + + +static const char + dpll_bp_clk_src_names[DPLL_BP_CLK_SRC_ID_MAX][DPLL_BP_CLK_SRC_MAX_NAME_LENGTH] = { + "CLKINP", + "CLKINPULOW"}; + + +static const char + dpll_clkouthif_src_names[DPLL_CLKOUTHIF_SRC_ID_MAX][DPLL_CLKOUTHIF_SRC_MAX_NAME_LENGTH] = { + "DCO", + "CLKINPHIF"}; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_mode_name_get + * @BRIEF return DPLL mode name + * @RETURNS pointer towards const string containing DPLL mode name + * "RESERVED" in case of 'mode' is invalid + * @param[in] mode: dpll mode extracted from register + * @DESCRIPTION return DPLL mode name + *//*------------------------------------------------------------------------ */ +const char *dpll_mode_name_get(dpll_mode mode) +{ + if (mode >= DPLL_MODE_MAX) { + fprintf(stderr, "%s(): bad mode! (%u)\n", __func__, mode); + return (char *) dpll_mode_names[DPLL_RESERVED_0]; + } + + return (char *) dpll_mode_names[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_ramp_level_name_get + * @BRIEF return RAMP LEVEL string + * @RETURNS pointer towards const string containing + * DPLL RAMP LEVEL name + * "RESERVED" in case of 'mode' is invalid + * @param[in] level: RAMP LEVEL mode extracted from register + * @DESCRIPTION return RAMP LEVEL string + *//*------------------------------------------------------------------------ */ +const char *dpll_ramp_level_name_get(dpll_ramp_level level) +{ + if (level >= DPLL_RAMP_LEVEL_MAX) { + fprintf(stderr, "%s(): bad level! (%u)\n", __func__, level); + return (char *) dpll_ramp_level_names[DPLL_RAMP_RESERVED]; + } + + return (char *) dpll_ramp_level_names[level]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_autoidle_mode_name_get + * @BRIEF return DPLL autoidle mode name + * @RETURNS pointer towards const string containing + * DPLL autoidle mode name + * "RESERVED" in case of 'mode' is invalid + * @param[in] mode: dpll autoidle mode extracted from register + * @DESCRIPTION return DPLL autoidle mode name + *//*------------------------------------------------------------------------ */ +const char *dpll_autoidle_mode_name_get(dpll_autoidle_mode mode) +{ + if (mode >= DPLL_AUTOIDLE_MODE_MAX) { + fprintf(stderr, "%s(): bad mode! (%u)\n", __func__, mode); + return (char *) dpll_autoidle_mode_names[DPLL_AUTO_RESERVED_7]; + } + + return (char *) dpll_autoidle_mode_names[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_status_name_get + * @BRIEF return DPLL status name + * @RETURNS pointer towards const string containing DPLL status name + * "RESERVED" in case of 'status' is invalid + * @param[in] status: dpll status extracted from register + * @DESCRIPTION return DPLL status name + *//*------------------------------------------------------------------------ */ +const char *dpll_status_name_get(dpll_status status) +{ + if (status >= DPLL_STATUS_MAX) { + fprintf(stderr, "%s(): bad status! (%u)\n", __func__, status); + return (char *) dpll_status_names[DPLL_STATUS_RESERVED]; + } + + return (char *) dpll_status_names[status]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_bp_clk_src_name_get + * @BRIEF return DPLL bypass source clock name + * @RETURNS bypass source clock name on success + * NULL in case of error + * @param[in] id: valid DPLL bypass source clock ID + * @DESCRIPTION return DPLL bypass source clock name + *//*------------------------------------------------------------------------ */ +const char *dpll_bp_clk_src_name_get(dpll_bp_clk_src id) +{ + CHECK_ARG_LESS_THAN(id, DPLL_BP_CLK_SRC_ID_MAX, NULL); + + return (char *) dpll_bp_clk_src_names[id]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_clkouthif_src_name_get + * @BRIEF return DPLL clkouthif source clock name + * @RETURNS clkouthif source clock name on success + * NULL in case of error + * @param[in] id: valid DPLL clkouthif source clock ID + * @DESCRIPTION return DPLL clkouthif source clock name + *//*------------------------------------------------------------------------ */ +const char *dpll_clkouthif_src_name_get(dpll_clkouthif_src id) +{ + CHECK_ARG_LESS_THAN(id, DPLL_CLKOUTHIF_SRC_ID_MAX, NULL); + + return (char *) dpll_clkouthif_src_names[id]; +} + + +#ifndef DPLL_DEBUG +/* #define DPLL_SETTINGS_EXTRACT_DEBUG */ +#ifdef DPLL_SETTINGS_EXTRACT_DEBUG +#undef dprintf +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif +#endif +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_settings_extract + * @BRIEF extract DPLL settings from registers + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * @param[in] id: valid DPLL ID + * @param[in] type: DPLL type + * @param[in] dpll_regs: dpll registers to extract settings from + * @param[in,out] settings: struct with extracted DPLL settings + * @DESCRIPTION extract DPLL settings from registers + *//*------------------------------------------------------------------------ */ +int dpll_settings_extract(unsigned int id, dpll_type type, + dpll_settings_regs *dpll_regs, dpll_settings *settings) +{ + unsigned int val; + CHECK_NULL_ARG(dpll_regs, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(settings, OMAPCONF_ERR_ARG); + + settings->id = id; + settings->type = type; + + /* Extract data from CM_CLKMODE_DPLL_xyz */ + val = reg_read(dpll_regs->cm_clkmode_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_clkmode_dpll)->name, val); + + settings->mode = extract_bitfield(val, 0, 3); + (settings->ramp).ramp_level = extract_bitfield(val, 3, 2); + (settings->ramp).ramp_rate = 1 << (extract_bitfield(val, + 5, 3) + 1); + settings->driftguard_en = extract_bit(val, 8); + (settings->ramp).relock_ramp_en = extract_bit(val, 9); + settings->lpmode_en = extract_bit(val, 10); + settings->regm4xen = extract_bit(val, 11); + (settings->SSC).mode = extract_bit(val, 12); + (settings->SSC).ack = extract_bit(val, 13); + (settings->SSC).downspread = extract_bit(val, 14); + + dprintf("%s(): mode=0x%X (%s), lp_mode=%u, REGM4XEN=%u, " + "DRIFTGUARD_EN=%u\n", __func__, settings->mode, + dpll_mode_name_get(settings->mode), settings->lpmode_en, + settings->regm4xen, settings->driftguard_en); + dprintf("%s(): RAMP_EN=%u, RAMP_RATE=%uxREFCLK, RAMP_LEVEL=%u (%s)\n", + __func__, (settings->ramp).relock_ramp_en, + (settings->ramp).ramp_rate, (settings->ramp).ramp_level, + dpll_ramp_level_name_get((settings->ramp).ramp_level)); + dprintf("%s(): SSC_EN=%u, SSC_ACK=%u, SSC_DOWNSPREAD=%u\n", + __func__, (settings->SSC).mode, + (settings->SSC).ack, (settings->SSC).downspread); + + /* Extract data from CM_IDLEST_DPLL_xyz */ + val = reg_read(dpll_regs->cm_idlest_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_idlest_dpll)->name, val); + + settings->lock_status = extract_bit(val, 0); + settings->mn_bypass_status = extract_bit(val, 8); + + dprintf("%s(): ST_DPLL_CLK=%u, ST_MN_BYPASS=%u\n", + __func__, settings->lock_status, settings->mn_bypass_status); + + /* Extract data from CM_AUTOIDLE_DPLL_xyz */ + val = reg_read(dpll_regs->cm_autoidle_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_autoidle_dpll)->name, val); + + settings->autoidle_mode = extract_bitfield(val, 0, 3); + + dprintf("%s(): AUTO_DPLL_MODE=%u (%s)\n", __func__, + settings->autoidle_mode, + dpll_autoidle_mode_name_get(settings->autoidle_mode)); + + /* Extract data from CM_CLKSEL_DPLL_xyz */ + val = reg_read(dpll_regs->cm_clksel_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_clksel_dpll)->name, val); + + if (settings->type == DPLL_TYPE_A) { + (settings->MN).N = extract_bitfield(val, 0, 7); + (settings->MN).M = extract_bitfield(val, 8, 11); + settings->clkouthif_src = extract_bit(val, 20); + if (!cpu_is_omap4430()) { + (settings->DCC).en = extract_bit(val, 22); + (settings->DCC).count = extract_bitfield(val, 24, 8); + } else { + (settings->DCC).en = 0; + (settings->DCC).count = 0; + } + settings->bypass_clk = extract_bit(val, 23); + } else { + (settings->MN).N = extract_bitfield(val, 0, 8); + (settings->MN).M = extract_bitfield(val, 8, 12); + settings->selfreqdco = extract_bit(val, 21); + settings->sd_div = extract_bitfield(val, 24, 8); + dprintf("%s(): SELFREQDCO=%u, SD_DIV=%u\n", __func__, + settings->selfreqdco, settings->sd_div); + } + dprintf("%s(): M=%u, N=%u, CLKOUTHIF_CLK=%u, BP_CLK=%u\n", __func__, + (settings->MN).M, (settings->MN).N, settings->clkouthif_src, + settings->bypass_clk); + dprintf("%s(): DCC_EN=%u, DCC_COUNT=%u\n", __func__, + (settings->DCC).en, (settings->DCC).count); + + /* Extract data from CM_BYPCLK_DPLL_XYZ */ + if ((void *) dpll_regs->cm_bypclk_dpll != NULL) { + val = reg_read(dpll_regs->cm_bypclk_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_bypclk_dpll)->name, val); + + settings->bypass_clk_div = 1 << extract_bitfield(val, 0, 2); + + dprintf("%s(): BP_CLK_DIV=%u\n", __func__, + settings->bypass_clk_div); + + } else { + settings->bypass_clk_div = 1; + + dprintf("%s(): BYPCLK register does not exist.\n", __func__); + } + + /* Extract data from CM_DIV_M2_DPLL_XYZ */ + if ((void *) dpll_regs->cm_div_m2_dpll != NULL) { + val = reg_read(dpll_regs->cm_div_m2_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_div_m2_dpll)->name, val); + + (settings->MN).M2_present = 1; + if (settings->type == DPLL_TYPE_A) { + (settings->MN).M2 = extract_bitfield(val, 0, 5); + (settings->MN).X2_M2_autogating = + !extract_bit(val, 10); + (settings->MN).X2_M2_clkout_st = extract_bit(val, 11); + } else { + (settings->MN).M2 = extract_bitfield(val, 0, 7); + } + (settings->MN).M2_autogating = !extract_bit(val, 8); + (settings->MN).M2_clkout_st = extract_bit(val, 9); + + dprintf("%s(): M2 DIV=%u, AUTOGATING=%u, CLKST=%u\n", + __func__, (settings->MN).M2, + (settings->MN).M2_autogating, + (settings->MN).M2_clkout_st); + if (settings->type == DPLL_TYPE_A) { + dprintf("%s(): X2_M2 AUTOGATING=%u, CLKST=%u\n", + __func__, (settings->MN).X2_M2_autogating, + (settings->MN).X2_M2_clkout_st); + } + } else { + (settings->MN).M2_present = 0; + + dprintf("%s(): DIV_M2 register does not exist.\n", __func__); + } + + /* Extract data from CM_DIV_M3_DPLL_XYZ */ + if ((void *) dpll_regs->cm_div_m3_dpll != NULL) { + val = reg_read(dpll_regs->cm_div_m3_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_div_m3_dpll)->name, val); + + (settings->MN).M3_present = 1; + (settings->MN).M3 = extract_bitfield(val, 0, 5); + (settings->MN).X2_M3_autogating = !extract_bit(val, 8); + (settings->MN).X2_M3_clkout_st = extract_bit(val, 9); + + dprintf("%s(): X2_M3 DIV=%u, AUTOGATING=%u, CLKST=%u\n", + __func__, (settings->MN).M3, + (settings->MN).X2_M3_autogating, + (settings->MN).X2_M3_clkout_st); + } else { + (settings->MN).M3_present = 0; + + dprintf("%s(): DIV_M3 register does not exist.\n", __func__); + } + + /* Extract data from CM_DELTAMSTEP_DPLL_xyz */ + val = reg_read(dpll_regs->cm_ssc_deltamstep_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_ssc_deltamstep_dpll)->name, val); + + (settings->SSC).deltaMStep = extract_bitfield(val, 0, 20); + + dprintf("%s(): deltaMStep=0x%X\n", __func__, + (settings->SSC).deltaMStep); + + /* Extract data from CM_MODFREQDIV_DPLL_xyz */ + val = reg_read(dpll_regs->cm_ssc_modfreqdiv_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_ssc_modfreqdiv_dpll)->name, val); + + (settings->SSC).mantissa = extract_bitfield(val, 0, 7); + (settings->SSC).exponent = extract_bitfield(val, 8, 3); + + dprintf("%s(): mantissa=0x%X, exponent=0x%X\n", __func__, + (settings->SSC).mantissa, (settings->SSC).exponent); + + /* Extract data from CM_CLKDCOLDO_DPLL_xyz */ + if ((void *) dpll_regs->cm_clkdcoldo_dpll != NULL) { + val = reg_read(dpll_regs->cm_clkdcoldo_dpll); + dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, + (dpll_regs->cm_clkdcoldo_dpll)->name, val); + + (settings->MN).clkdcoldo_autogating = !extract_bit(val, 8); + (settings->MN).clkdcoldo_clkout_st = extract_bit(val, 9); + + dprintf("%s(): CLKDCOLDO AUTOGATING=%u, CLKST=%u\n", + __func__, + (settings->MN).clkdcoldo_autogating, + (settings->MN).clkdcoldo_clkout_st); + } + return 0; +} +#ifdef DPLL_SETTINGS_EXTRACT_DEBUG +#undef dprintf +#define dprintf(format, ...) +#endif + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll_lock_freq_calc + * @BRIEF compute DPLL lock frequency (in MHz) + * @RETURNS lock frequency in case of success (in MHz) + * 0.0 in case of error. + * @param[in] settings: DPLL settings with fields + * regm4xen, fref, MN.M, MN.N INITIALIZED + * @DESCRIPTION compute DPLL lock frequency (in MHz) + *//*------------------------------------------------------------------------ */ +double dpll_lock_freq_calc(dpll_settings *settings) +{ + CHECK_NULL_ARG(settings, 0.0); + + if (settings->type == DPLL_TYPE_A) { + if (settings->regm4xen == 0) + settings->fdpll = + (settings->fref * 2.0 * (double) (settings->MN).M) / + ((double) (settings->MN).N + 1.0); + else + settings->fdpll = + (settings->fref * 8.0 * (double) (settings->MN).M) / + ((double) (settings->MN).N + 1.0); + dprintf("%s(%u): type=A regm4xen=%u fref=%lfMHz M=%u N=%u => " + "fdpll=%lfMHz\n", __func__, settings->id, + settings->regm4xen, settings->fref, (settings->MN).M, + (settings->MN).N, settings->fdpll); + } else { + settings->fdpll = + (settings->fref * (double) (settings->MN).M) / + ((double) (settings->MN).N + 1.0); + dprintf("%s(%u): type=B fref=%lfMHz M=%u N=%u => " + "fdpll=%lfMHz\n", __func__, settings->id, + settings->fref, (settings->MN).M, + (settings->MN).N, settings->fdpll); + } + + return settings->fdpll; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/dpll.h tiomapconf-1.61.1/arch/arm/mach-omap/common/dpll.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/dpll.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/dpll.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,246 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll.h + * @Description OMAP DPLL Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2006 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __DPLL_H__ +#define __DPLL_H__ + + +#include + + +#define DPLL_MAX_NAME_LENGTH 16 +#define DPLL_OUTPUT_MAX_NAME_LENGTH 16 +#define HSDIV_MAX_NAME_LENGTH 4 +#define DPLL_MODE_MAX_NAME_LENGTH 10 +#define DPLL_RAMP_LEVEL_MAX_NAME_LENGTH 10 +#define DPLL_AUTOIDLE_MODE_MAX_NAME_LENGTH 10 +#define DPLL_STATUS_MAX_NAME_LENGTH 10 +#define DPLL_BP_CLK_SRC_MAX_NAME_LENGTH 12 +#define DPLL_CLKOUTHIF_SRC_MAX_NAME_LENGTH 12 + + +typedef enum { + DPLL_TYPE_A, /* DPLLs MPU, IVA, ABE, CORE, PER */ + DPLL_TYPE_B, /* DPLLs USB, UNIPRO[1-2]) */ + DPLL_TYPE_MAX +} dpll_type; + + +typedef enum { + DPLL_RESERVED_0 = 0, + DPLL_LOW_POWER_STOP = 1, + DPLL_FAST_RELOCK_STOP = 2, + DPLL_RESERVED_3 = 3, + DPLL_MN_BYPASS = 4, + DPLL_LOW_POWER_BYPASS = 5, + DPLL_FAST_RELOCK_BYPASS = 6, + DPLL_LOCK = 7, + DPLL_MODE_MAX = 8 +} dpll_mode; + + +typedef enum { + DPLL_DISABLED = 0, + DPLL_AUTO_LOW_POWER_STOP = 1, + DPLL_AUTO_FAST_RELOCK_STOP = 2, + DPLL_AUTO_RESERVED_3 = 3, + DPLL_AUTO_RESERVED_4 = 4, + DPLL_AUTO_BYPASS_LOW_POWER = 5, + DPLL_AUTO_BYPASS_FAST_RELOCK = 6, + DPLL_AUTO_RESERVED_7 = 7, + DPLL_AUTOIDLE_MODE_MAX +} dpll_autoidle_mode; + + +typedef enum { + DPLL_STATUS_BYPASSED = 0, + DPLL_STATUS_LOCKED = 1, + DPLL_STATUS_STOPPED = 2, + DPLL_STATUS_RESERVED = 3, + DPLL_STATUS_MAX +} dpll_status; + + +typedef enum { + DPLL_RAMP_NO = 0, + DPLL_RAMP_8_4_2_1 = 1, + DPLL_RAMP_4_2_1_5 = 2, + DPLL_RAMP_RESERVED = 3, + DPLL_RAMP_LEVEL_MAX = 4 +} dpll_ramp_level; + + +typedef enum { + DPLL_BP_CLK_SRC_CLKINP = 0, + DPLL_BP_CLK_SRC_CLKINPULOW = 1, + DPLL_BP_CLK_SRC_ID_MAX +} dpll_bp_clk_src; + + +typedef enum { + DPLL_CLKOUTHIF_SRC_DCO = 0, + DPLL_CLKOUTHIF_SRC_CLKINPHIF = 1, + DPLL_CLKOUTHIF_SRC_ID_MAX +} dpll_clkouthif_src; + + +typedef struct { + reg *cm_clkmode_dpll; + reg *cm_idlest_dpll; + reg *cm_autoidle_dpll; + reg *cm_clksel_dpll; + reg *cm_bypclk_dpll; + reg *cm_div_m2_dpll; + reg *cm_div_m3_dpll; + reg *cm_ssc_deltamstep_dpll; + reg *cm_ssc_modfreqdiv_dpll; + reg *cm_clkdcoldo_dpll; +} dpll_settings_regs; + + +typedef struct { + unsigned int relock_ramp_en; /* CM_CLKMODE_DPLL.DPLL_RELOCK_RAMP_EN */ + unsigned int ramp_rate; /* CM_CLKMODE_DPLL.DPLL_RAMP_RATE */ + unsigned int ramp_level; /* CM_CLKMODE_DPLL.DPLL_RAMP_LEVEL */ +} dpll_ramp_settings; + + +typedef struct { + /* Common DPLL types A & B */ + unsigned int M; /* CM_CLKSEL_DPLL.DPLL_MULT */ + unsigned int N; /* CM_CLKSEL_DPLL.DPLL_DIV */ + unsigned short M2_present; /* 0 if does not exist in CM_DIV_M2_DPLL, 1 otherwise */ + unsigned int M2; /* CM_DIV_M2_DPLL.DPLL_CLKOUT_DIV */ + double M2_rate; /* in MHz (== CLKOUT for DPLL type B */ + /* DPLL type A only */ + unsigned short M2_clkout_st; /* CM_DIV_M2_DPLL.ST_DPLL_CLKOUT */ + unsigned short M2_autogating; /* CM_DIV_M2_DPLL.DPLL_CLKOUT_GATE_CTRL */ + unsigned short X2_M2_present; /* 0 if does not exist in CM_DIV_M2_DPLL, 1 otherwise */ + double X2_M2_rate; /* in MHz */ + unsigned short X2_M2_clkout_st; /* CM_DIV_M2_DPLL.ST_DPLL_CLKOUTX2 */ + unsigned short X2_M2_autogating; /* CM_DIV_M2_DPLL.DPLL_CLKOUTX2_GATE_CTRL */ + unsigned short M3_present; /* 0 if does not exist in CM_DIV_M3_DPLL, 1 otherwise */ + unsigned int M3; /* CM_DIV_M3_DPLL.DPLL_CLKOUT_DIV */ + double X2_M3_rate; /* in MHz */ + unsigned short X2_M3_clkout_st; /* CM_DIV_M3_DPLL.ST_DPLL_CLKOUT */ + unsigned short X2_M3_autogating; /* CM_DIV_M3_DPLL.DPLL_CLKOUT_GATE_CTRL */ + /* DPLL type B only */ + unsigned short clkdcoldo_clkout_st; /* CM_CLKDCOLDO_DPLL.ST_DPLL_CLKDCOLDO */ + unsigned short clkdcoldo_autogating; /* CM_CLKDCOLDO_DPLL.DPLL_CLKDCOLDO_GATE_CTRL */ + double clkdcoldo_rate; /* in MHz */ +} dpll_MN_settings; + + +typedef struct { + char type[12]; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_TYPE */ + unsigned short downspread; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_DOWNSPREAD */ + unsigned short mode; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_EN */ + unsigned short ack; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_ACK */ + unsigned int deltaMStep; /* CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP */ + unsigned int exponent; /* CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDIV_MANTISSA */ + unsigned int mantissa; /* CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDIV_MANTISSA */ + double fm; /* Modulation Frequency = [DPLL_REFCLK/4]/MODFREQDIV */ + /* MODFREQDIV = MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT */ +} dpll_SSC_settings; /* Spread Spectrum Clocking */ + + +typedef struct { + unsigned int en; /* CM_CLKSEL_DPLL.DCC_EN */ + unsigned int count; /* CM_CLKSEL_DPLL.DCC_COUNT_MAX */ +} dpll_DCC_settings; /* Duty Cycle Correction */ + + +typedef struct { + /* Common DPLL type A & B */ + unsigned int id; /* DPLL ID */ + unsigned short initialized; + dpll_type type; /* A or B */ + dpll_mode mode; /* CM_CLKMODE_DPLL.DPLL_EN */ + dpll_autoidle_mode autoidle_mode; /* CM_AUTOIDLE_DPLL.AUTO_DPLL_MODE */ + dpll_MN_settings MN; + dpll_SSC_settings SSC; + double fref; /* REF_CLK, in MHz */ + double fbyp_clk_m2; /* M2 output bypass clock, in MHz */ + double fdpll; /* in MHz */ + unsigned short lock_status; /* CM_IDLEST_DPLL.ST_DPLL_CLK */ + unsigned short mn_bypass_status; /* CM_IDLEST_DPLL.ST_MN_BYPASS */ + /* DPLL type A only */ + dpll_DCC_settings DCC; + dpll_ramp_settings ramp; + unsigned int lpmode_en; /* CM_CLKMODE_DPLL.DPLL_LPMODE_EN */ + unsigned int driftguard_en; /* CM_CLKMODE_DPLL.DPLL_DRIFTGUARD_EN */ + unsigned short regm4xen; /* CM_CLKMODE_DPLL.DPLL_REGM4XEN */ + double fbyp_clk_m3; /* M3 output bypass clock, in MHz */ + double fbyp_clk_hsdiv; /* HS dividers output bypass clock, in MHz */ + unsigned short bypass_clk_div; /* CM_BYPCLK_DPLL.CLKSEL */ + unsigned short bypass_clk; /* CM_CLKSEL_DPLL.DPLL_BYP_CLKSEL */ + unsigned short clkouthif_src; /* CM_CLKSEL_DPLL.DPLL_CLKOUTHIF_CLKSEL */ + /* DPLL type B only */ + unsigned int sd_div; /* CM_CLKSEL_DPLL.DPLL_SD_DIV */ + unsigned short selfreqdco; /* CM_CLKSEL_DPLL.SELFREQDCO */ +} dpll_settings; + + +typedef struct { + unsigned int ref_clk; + unsigned int byp_clk_m2; + unsigned int byp_clk_m3; + unsigned int byp_clk_hsdiv; +} dpll_clk_sources; + + +const char *dpll_mode_name_get(dpll_mode mode); +const char *dpll_ramp_level_name_get(dpll_ramp_level level); +const char *dpll_autoidle_mode_name_get(dpll_autoidle_mode mode); +const char *dpll_status_name_get(dpll_status status); +const char *dpll_bp_clk_src_name_get(dpll_bp_clk_src id); +const char *dpll_clkouthif_src_name_get(dpll_clkouthif_src id); + +double dpll_lock_freq_calc(dpll_settings *settings); + +int dpll_settings_extract(unsigned int id, dpll_type type, + dpll_settings_regs *dpll_regs, dpll_settings *settings); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/emif.c tiomapconf-1.61.1/arch/arm/mach-omap/common/emif.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/emif.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/emif.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,115 @@ +/* + * + * @Component OMAPCONF + * @Filename emif.c + * @Description EMIF Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include + + +/* #define EMIF_DEBUG */ +#ifdef EMIF_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +static const char + emif_mr4_code_table_c[EMIF_TEMP_RESERVED + 1][EMIF_TEMP_MAX_NAME_LENGTH] = { + "FIXME", + "FIXME", + "FIXME", + "< 85", + "FIXME", + ">= 85 & <= 105", + "FIXME", + "> 105", + "FIXME"}; + + +static const char + emif_mr4_code_table_f[EMIF_TEMP_RESERVED + 1][EMIF_TEMP_MAX_NAME_LENGTH] = { + "FIXME", + "FIXME", + "FIXME", + "< 185", + "FIXME", + ">= 185 & <= 221", + "FIXME", + "> 221", + "FIXME"}; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif_mr4_convert + * @BRIEF convert LPDDR2 MR4 code into string + * @RETURNS MR4 code as a string indicating temperature range + * "FIXME" string in case of error + * @param[in] mr4: LPDDR2 MR4 code + * @param[in] unit: select celcius ou fahrenheit + * @DESCRIPTION convert LPDDR2 MR4 code into string. MR4 code is not a + * temperature, but a temperature range, that cannot be + * converted to integer. Hence return it a string. + *//*------------------------------------------------------------------------ */ +const char *emif_mr4_convert(emif_mr4_code mr4, temperature_unit unit) +{ + if (mr4 > EMIF_TEMP_RESERVED) + mr4 = EMIF_TEMP_RESERVED; + + if (unit == TEMP_CELCIUS_DEGREES) { + dprintf("%s(%d) = %s\n", __func__, + mr4, emif_mr4_code_table_c[mr4]); + return emif_mr4_code_table_c[mr4]; + } else if (unit == TEMP_FAHRENHEIT_DEGREES) { + dprintf("%s(%d) = %s\n", __func__, + mr4, emif_mr4_code_table_f[mr4]); + return emif_mr4_code_table_f[mr4]; + } else { + fprintf(stderr, + "omapconf: %s() called with incorrect unit ""(%d), " + "defaulting to celcius degrees.\n", __func__, unit); + dprintf("%s(%d) = %s\n", __func__, + mr4, emif_mr4_code_table_c[mr4]); + return emif_mr4_code_table_c[mr4]; + } +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/emif.h tiomapconf-1.61.1/arch/arm/mach-omap/common/emif.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/emif.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/emif.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,66 @@ +/* + * + * @Component OMAPCONF + * @Filename emif.h + * @Description EMIF Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __EMIF_H__ +#define __EMIF_H__ + + +#include + + +#define EMIF_TEMP_MAX_NAME_LENGTH 16 + + +typedef enum { + EMIF_TEMP_BELOW_85C = 0x3, + EMIF_TEMP_ABOVE_85C = 0x5, + EMIF_TEMP_EXCEED_105C = 0x7, + EMIF_TEMP_RESERVED = 0x8 +} emif_mr4_code; + + +const char *emif_mr4_convert(emif_mr4_code mr4, temperature_unit unit); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/module.c tiomapconf-1.61.1/arch/arm/mach-omap/common/module.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/module.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/module.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,2151 @@ +/* + * + * @Component OMAPCONF + * @Filename module.c + * @Description OMAP Generic Module Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define MODULE_DEBUG */ +#ifdef MODULE_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_init + * @BRIEF initialize internal data + * @DESCRIPTION initialize internal data (architecture dependent) + *//*------------------------------------------------------------------------ */ +void module_init(void) +{ + #ifdef MODULE_DEBUG + int i, j, count, count_opp; + const genlist *mod_list; + mod_info mod; + mod_opp opp; + #endif + + if (cpu_is_omap44xx()) { + mod44xx_init(); + } else if (cpu_is_omap54xx()) { + mod54xx_init(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } + + #ifdef MODULE_DEBUG + mod_list = module_list_get(); + count = genlist_getcount((genlist *) mod_list); + printf("Module List:\n"); + for (i = 0; i < count; i++) { + genlist_get((genlist *) mod_list, i, (mod_info *) &mod); + printf(" %s:\n", mod.name); + printf(" ID:%d\n", mod.id); + printf(" ClkDM: %s\n", mod.clkdm); + printf(" PwrDM: %s\n", mod.pwrdm); + printf(" VoltDM: %s\n", mod.voltdm); + printf(" F-Clk:%d\n", mod.clk); + printf(" SYSCONFIG REG: %s\n", (mod.sysconfig)->name); + printf(" CLKCTRL REG: %s\n", (mod.clkctrl)->name); + printf(" CONTEXT REG: %s\n", (mod.context)->name); + printf(" Properties: %d\n", mod.properties); + printf(" OPP List: "); + count_opp = genlist_getcount((genlist *) &(mod.mod_opp_list)); + for (j = 0; j < count_opp; j++) { + genlist_get(&(mod.mod_opp_list), j, + (mod_opp *) &opp); + printf("(%s, %dKHz) ", opp.name, opp.rate); + } + printf("\n\n"); + } + printf("Module count: %d\n\n", count); + #endif +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_deinit + * @BRIEF free dynamically allocated internal data. + * @DESCRIPTION free dynamically allocated internal data. + * MUST BE CALLED AT END OF EXECUTION. + *//*------------------------------------------------------------------------ */ +void module_deinit(void) +{ + if (cpu_is_omap44xx()) { + mod44xx_deinit(); + } else if (cpu_is_omap54xx()) { + mod54xx_deinit(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_list_get + * @BRIEF return the list of modules + * @RETURNS list of modules in case of success + * NULL in case of error + * @DESCRIPTION return the list of modules + *//*------------------------------------------------------------------------ */ +const genlist *module_list_get(void) +{ + if (cpu_is_omap44xx()) { + return mod44xx_list_get(); + } else if (cpu_is_omap54xx()) { + return mod54xx_list_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return NULL; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_count_get + * @BRIEF return the number of modules + * @RETURNS number of modules (> 0) in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @DESCRIPTION return the number of modules + *//*------------------------------------------------------------------------ */ +int module_count_get(void) +{ + if (cpu_is_omap44xx()) { + return mod44xx_count_get(); + } else if (cpu_is_omap54xx()) { + return mod54xx_count_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION _module_info_get + * @BRIEF return the saved informations of a given module. + * @RETURNS 0 in case of success + * -1 in case of error + * @param[in] mod: module name + * @param[in,out] data: module details + * @DESCRIPTION return the saved informations of a given module. + *//*------------------------------------------------------------------------ */ +static int _module_info_get(const char *mod, mod_info *data) +{ + const genlist *mod_list; + int i, count; + + CHECK_NULL_ARG(mod, -1); + CHECK_NULL_ARG(data, -1); + + mod_list = module_list_get(); + count = genlist_getcount((genlist *) mod_list); + for (i = 0; i < count; i++) { + genlist_get((genlist *) mod_list, i, (void *) data); + if (strcmp(data->name, mod) == 0) { + dprintf("%s(%s): found.\n", __func__, mod); + return 0; + } + } + + dprintf("%s(%s): not found!\n", __func__, mod); + return -1; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION _module_properties_get + * @BRIEF return the properties of a given module. + * @RETURNS >= 0 module properties + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in] mod: module name + * @param[in,out] properties: module properties + * @DESCRIPTION return the properties of a given module. + *//*------------------------------------------------------------------------ */ +static int _module_properties_get(const char *mod, unsigned int *properties) +{ + const genlist *mod_list; + mod_info data; + int i, count; + + CHECK_NULL_ARG(mod, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(properties, OMAPCONF_ERR_ARG); + + mod_list = module_list_get(); + count = genlist_getcount((genlist *) mod_list); + for (i = 0; i < count; i++) { + genlist_get((genlist *) mod_list, i, (void *) &data); + if (strcmp(data.name, mod) == 0) { + *properties = data.properties; + dprintf("%s(%s): properties found (%u).\n", + __func__, mod, *properties); + return 0; + } + } + + *properties = 0; + dprintf("%s(%s): not found!\n", __func__, mod); + return OMAPCONF_ERR_NOT_AVAILABLE; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_sysconfig_register + * @BRIEF return 1 if module has a SYSCONFIG register. + * @RETURNS 1 if module has a SYSCONFIG register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module has a SYSCONFIG register. + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_sysconfig_register(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_SYSCONFIG) != 0) { + dprintf("%s(%s): HAS SYSCONFIG register\n", __func__, mod); + return 1; + } else { + dprintf("%s(%s): does NOT have SYSCONFIG register\n", + __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_autoidle_bit + * @BRIEF return 1 if module has autoidle bit in sysconfig. + * @RETURNS 1 if module has autoidle bit in sysconfig register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module has autoidle bit in sysconfig. + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_autoidle_bit(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_AUTOIDLE_BIT0) != 0) { + dprintf("%s(%s): HAS autoidle bit (0)\n", __func__, mod); + return 1; + } else if ((properties & MOD_HAS_AUTOIDLE_BIT8) != 0) { + dprintf("%s(%s): HAS autoidle bit (8)\n", __func__, mod); + return 1; + } else { + dprintf("%s(%s): does NOT have autoidle bit\n", __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_idle_mode + * @BRIEF return 1 if module has idle mode in sysconfig register. + * @RETURNS 1 if module has idle mode in sysconfig register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module has idle mode in sysconfig register. + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_idle_mode(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_IDLE_MODE1) != 0) { + dprintf("%s(%s): HAS idle mode (1-0)\n", __func__, mod); + return 1; + } else if ((properties & MOD_HAS_IDLE_MODE3) != 0) { + dprintf("%s(%s): HAS idle mode (3-2)\n", __func__, mod); + return 1; + } else if ((properties & MOD_HAS_IDLE_MODE4) != 0) { + dprintf("%s(%s): HAS idle mode (4-3)\n", __func__, mod); + return 1; + } else { + dprintf("%s(%s): does NOT have idle mode\n", __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_idle_status + * @BRIEF return 1 if module has idle mode in sysconfig register. + * @RETURNS 1 if module has idle status in CM_CLKCTRL register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module has idle mode in sysconfig register. + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_idle_status(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_NO_IDLE_STATUS) != 0) { + dprintf("%s(%s): HAS NO idle status\n", __func__, mod); + return 0; + } else { + dprintf("%s(%s): HAS idle status\n", __func__, mod); + return 1; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_smart_idle_wakeup_mode + * @BRIEF return 1 if module implements "smart-idle wakeup" mode + * @RETURNS 1 if module implements "smart-idle wakeup" mode. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module implements "smart-idle wakeup" mode + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_smart_idle_wakeup_mode(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_SMART_IDLE_WAKEUP_MODE) != 0) { + dprintf("%s(%s): HAS smart-idle wakeup mode\n", __func__, mod); + return 1; + } else { + dprintf("%s(%s): does NOT have smart-idle wakeup mode\n", + __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_enawakeup_bit + * @BRIEF return 1 if module has ENAWAKEUP bit in sysconfig + * @RETURNS 1 if module has ENAWAKEUP bit in sysconfig register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module has ENAWAKEUP bit in sysconfig + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_enawakeup_bit(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_ENAWAKEUP_BIT) != 0) { + dprintf("%s(%s): HAS ENAWAKEUP bit\n", __func__, mod); + return 1; + } else { + dprintf("%s(%s): does NOT have ENAWAKEUP bit\n", __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_standby_mode + * @BRIEF return 1 if module has STANDBY mode in sysconfig + * @RETURNS 1 if module has STANDBY mode in sysconfig register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module has STANDBY mode in sysconfig + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_standby_mode(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_STANDBY_MODE5) != 0) { + dprintf("%s(%s): HAS STANDBY mode (5-4)\n", __func__, mod); + return 1; + } else if ((properties & MOD_HAS_STANDBY_MODE13) != 0) { + dprintf("%s(%s): HAS STANDBY mode (13-12)\n", __func__, mod); + return 1; + } else { + dprintf("%s(%s): does NOT have STANDBY mode\n", __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_standby_status + * @BRIEF return 1 if module has STANDBY status field in + * CM_xyz_CLKCTRL register. + * @RETURNS 1 if module has STANDBY status field in + * CM_xyz_CLKCTRL register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module has STANDBY status field in + * CM_xyz_CLKCTRL register. + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_standby_status(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_STANDBY_STATUS) != 0) { + dprintf("%s(%s): HAS STANDBY status\n", __func__, mod); + return 1; + } else { + dprintf("%s(%s): does NOT have STANDBY status\n", + __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_smart_standby_wakeup_mode + * @BRIEF return 1 if module implements "smart-standby wakeup" + * mode + * @RETURNS 1 if module implements "smart-standby wakeup" mode. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION return 1 if module implements "smart-standby wakeup" + * mode + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_smart_standby_wakeup_mode(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_SMART_STANDBY_WAKEUP_MODE) != 0) { + dprintf("%s(%s): HAS smart-standby wakeup mode\n", + __func__, mod); + return 1; + } else { + dprintf( + "%s(%s): does NOT have smart-standby wakeup mode\n", + __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_has_clock_activity_mode + * @BRIEF check if omap module has clock activity mode in + * sysconfig register + * @RETURNS 1 if omap module has clock activity mode in + * sysconfig register. + * 0 if not available or in case of error. + * @param[in] id: valid module ID + * @DESCRIPTION check if omap module has clock activity mode in + * sysconfig register + * (not all modules feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int module_has_clock_activity_mode(const char *mod) +{ + int ret; + unsigned int properties; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_properties_get(mod, &properties); + if (ret != 0) { + dprintf("%s(%s): could not retrieve properties!!! (%d)\n", + __func__, mod, ret); + return 0; + } + + if ((properties & MOD_HAS_CLOCK_ACTIVITY_MODE) != 0) { + dprintf("%s(%s): HAS clock activity mode\n", __func__, + mod); + return 1; + } else { + dprintf("%s(%s): does NOT have clock activity mode\n", + __func__, mod); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_id_get + * @BRIEF return the unique ID of a given module. + * @RETURNS >= 0 module ID + * -1 in case of error + * @param[in] mod: module name + * @DESCRIPTION return the unique ID of a given module. + *//*------------------------------------------------------------------------ */ +int module_id_get(const char *mod) +{ + int id; + mod_info data; + + CHECK_NULL_ARG(mod, -1); + + id = _module_info_get(mod, &data); + if (id == 0) + id = data.id; + + dprintf("%s(%s) = %d\n", __func__, mod, id); + return id; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_is_accessible + * @BRIEF check omap module's registers accessibility + * @RETURNS 1 if omap module's registers accessible + * 0 if omap module's registers NOT accessible + * (or in case of error) + * @param[in] mod: module name + * @DESCRIPTION check omap module's registers accessibility + *//*------------------------------------------------------------------------ */ +unsigned short int module_is_accessible(const char *mod) +{ + int ret; + mod_info data; + unsigned int cm_clkctrl; + + CHECK_NULL_ARG(mod, 0); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + return 0; + } + + if (data.clkctrl == NULL) { + dprintf("%s(%s): cm_clkctrl_reg == NULL!!!\n", __func__, mod); + return 0; + } + + cm_clkctrl = reg_read(data.clkctrl); + dprintf("%s(%s) = %d\n", __func__, mod, mod_is_accessible(cm_clkctrl)); + return mod_is_accessible(cm_clkctrl); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_mode_get + * @BRIEF retrieve module mode from CM register + * @RETURNS module mode on success + * MOD_MODULE_MODE_MAX in case of error or not available + * @param[in] mod: module name + * @DESCRIPTION retrieve module mode from CM register + *//*------------------------------------------------------------------------ */ +mod_module_mode module_mode_get(const char *mod) +{ + int ret; + mod_info data; + unsigned int cm_clkctrl; + mod_module_mode mmode; + + CHECK_NULL_ARG(mod, MOD_MODULE_MODE_MAX); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + mmode = MOD_MODULE_MODE_MAX; + } else if (data.clkctrl == NULL) { + /* Module is not SW-Controlled via PRCM */ + dprintf("%s(%s): CM_CLKCTRL ADDR = NULL\n", __func__, mod); + mmode = MOD_MODULE_MODE_MAX; + } else { + /* Retrieve module mode */ + cm_clkctrl = reg_read(data.clkctrl); + mmode = mod_module_mode_get(cm_clkctrl); + } + + dprintf("%s(%s) = %s\n", __func__, mod, + mod_module_mode_name_get(mmode)); + return mmode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_autoidle_mode_get + * @BRIEF retrieve module autoidle mode + * @RETURNS module autoidle mode + * MOD_AUTOIDLE_MODE_MAX in case of error + * @param[in] mod: module name + * @DESCRIPTION retrieve module autoidle mode + *//*------------------------------------------------------------------------ */ +mod_autoidle_mode module_autoidle_mode_get(const char *mod) +{ + int ret; + mod_info data; + unsigned int sysconfig; + mod_autoidle_mode mode; + + CHECK_NULL_ARG(mod, MOD_AUTOIDLE_MODE_MAX); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + mode = MOD_AUTOIDLE_MODE_MAX; + } else if (data.sysconfig == NULL) { + dprintf("%s(%s): sysconfig == NULL!!!\n", __func__, mod); + mode = MOD_AUTOIDLE_MODE_MAX; + } else if (!module_is_accessible(mod)) { + dprintf("%s(%s): module is not accessible.\n", __func__, mod); + mode = MOD_AUTOIDLE_MODE_MAX; + } else { + sysconfig = reg_read(data.sysconfig); + mode = mod_autoidle_mode_get(sysconfig, data.properties); + dprintf("%s(%s)=%u (%s)\n", __func__, mod, mode, + mod_autoidle_mode_name_get(mode)); + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_idle_mode_get + * @BRIEF retrieve omap module's idle mode + * @RETURNS module's idle mode + * MOD_IDLE_MODE_MAX in case of error + * @param[in] mod: module name + * @DESCRIPTION retrieve omap module's idle mode + *//*------------------------------------------------------------------------ */ +mod_idle_mode module_idle_mode_get(const char *mod) +{ + int ret; + mod_info data; + unsigned int sysconfig; + mod_idle_mode mode; + + CHECK_NULL_ARG(mod, MOD_IDLE_MODE_MAX); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + mode = MOD_IDLE_MODE_MAX; + } else if (data.sysconfig == NULL) { + dprintf("%s(%s): sysconfig == NULL!!!\n", __func__, mod); + mode = MOD_IDLE_MODE_MAX; + } else if (!module_is_accessible(mod)) { + dprintf("%s(%s): module is not accessible.\n", __func__, mod); + mode = MOD_IDLE_MODE_MAX; + } else { + sysconfig = reg_read(data.sysconfig); + mode = mod_idle_mode_get(sysconfig, data.properties); + dprintf("%s(%s)=%u (%s)\n", __func__, mod, mode, + mod_idle_mode_name_get(mode)); + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_idle_status_get + * @BRIEF retrieve module's idle status from CM_xxx_xxx_CLKCTRL + * @RETURNS module idle status + * MOD_IDLE_STATUS_MAX in case of error + * @param[in] mod: module name + * @DESCRIPTION retrieve module's idle status from CM_xxx_xxx_CLKCTRL + *//*------------------------------------------------------------------------ */ +mod_idle_status module_idle_status_get(const char *mod) +{ + int ret; + mod_info data; + unsigned int clkctrl; + mod_idle_status mstatus; + + CHECK_NULL_ARG(mod, MOD_IDLE_STATUS_MAX); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + mstatus = MOD_IDLE_STATUS_MAX; + } else if (data.clkctrl == NULL) { + dprintf("%s(%s): clkctrl == NULL!!!\n", __func__, mod); + mstatus = MOD_IDLE_STATUS_MAX; + } else { + clkctrl = reg_read(data.clkctrl); + mstatus = mod_idle_status_get(clkctrl, data.properties); + dprintf("%s(%s)=%u (%s)\n", __func__, mod, mstatus, + mod_idle_status_name_get(mstatus)); + } + + return mstatus; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_standby_mode_get + * @BRIEF retrieve omap module's standby mode + * @RETURNS module's standby mode + * MOD_STANDBY_MODE_MAX in case of error + * @param[in] mod: module name + * @DESCRIPTION retrieve omap module's standby mode + *//*------------------------------------------------------------------------ */ +mod_standby_mode module_standby_mode_get(const char *mod) +{ + int ret; + mod_info data; + unsigned int sysconfig; + mod_standby_mode mode; + + CHECK_NULL_ARG(mod, MOD_STANDBY_MODE_MAX); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + return MOD_STANDBY_MODE_MAX; + } else if (data.sysconfig == NULL) { + dprintf("%s(%s): sysconfig == NULL!!!\n", __func__, mod); + mode = MOD_STANDBY_MODE_MAX; + } else if (!module_is_accessible(mod)) { + dprintf("%s(%s): module is not accessible.\n", __func__, mod); + return MOD_STANDBY_MODE_MAX; + } else { + sysconfig = reg_read(data.sysconfig); + mode = mod_standby_mode_get(sysconfig, data.properties); + dprintf("%s(%s)=%u (%s)\n", __func__, mod, mode, + mod_standby_mode_name_get(mode)); + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_standby_status_get + * @BRIEF retrieve module standby status from CM_xxx_xxx_CLKCTRL + * @RETURNS module standby status + * MOD_STANDBY_STATUS_MAX in case of error + * @param[in] mod: module name + * @DESCRIPTION retrieve module standby status from CM_xxx_xxx_CLKCTRL + *//*------------------------------------------------------------------------ */ +mod_standby_status module_standby_status_get(const char *mod) +{ + int ret; + mod_info data; + unsigned int clkctrl; + mod_standby_status mstatus; + + CHECK_NULL_ARG(mod, MOD_STANDBY_STATUS_MAX); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + return MOD_STANDBY_STATUS_MAX; + } else if (data.clkctrl == NULL) { + dprintf("%s(%s): clkctrl == NULL!!!\n", __func__, mod); + mstatus = MOD_STANDBY_STATUS_MAX; + } else { + clkctrl = reg_read(data.clkctrl); + mstatus = mod_standby_status_get(clkctrl, data.properties); + dprintf("%s(%s)=%u (%s)\n", __func__, mod, mstatus, + mod_standby_status_name_get(mstatus)); + } + + return mstatus; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_context_is_lost + * @BRIEF check if module's context was retained or lost + * during last power transition + * @RETURNS 1 if module's context was LOST during last power + * transition (or in case of error) + * 0 if module's context was RETAINED during last power + * transition + * -1 in case of error or module has no context register + * @param[in] mod: module name + * @DESCRIPTION check if module's context was retained or lost + * during last power transition + *//*------------------------------------------------------------------------ */ +int module_context_is_lost(const char *mod) +{ + int ret; + mod_info data; + unsigned int rm_context; + short lost; + + CHECK_NULL_ARG(mod, -1); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + lost = -1; + } else if (data.context == NULL) { + dprintf("%s(%s): RM_CONTEXT addr==NULL\n", __func__, mod); + lost = -1; + } else { + rm_context = reg_read(data.context); + lost = mod_context_is_lost(rm_context); + dprintf("%s(%s)=%d\n", __func__, mod, lost); + } + + return lost; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_clock_activity_mode_get + * @BRIEF retrieve omap module's clock activity mode + * @RETURNS module's clock activity mode + * MOD_CLOCK_ACTIVITY_MODE_MAX in case of error + * @param[in] mod: module name + * @DESCRIPTION retrieve omap module's clock activity mode + *//*------------------------------------------------------------------------ */ +mod_clock_activity_mode module_clock_activity_mode_get(const char *mod) +{ + int ret; + mod_info data; + unsigned int sysconfig; + mod_clock_activity_mode mode; + + CHECK_NULL_ARG(mod, MOD_CLOCK_ACTIVITY_MODE_MAX); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + return MOD_CLOCK_ACTIVITY_MODE_MAX; + } else if (data.sysconfig == NULL) { + dprintf("%s(%s): sysconfig == NULL!!!\n", __func__, mod); + mode = MOD_CLOCK_ACTIVITY_MODE_MAX; + } else if (!module_is_accessible(mod)) { + dprintf("%s(%s): module is not accessible.\n", __func__, mod); + mode = MOD_CLOCK_ACTIVITY_MODE_MAX; + } else { + sysconfig = reg_read(data.sysconfig); + mode = mod_clock_activity_mode_get(sysconfig, data.properties); + dprintf("%s(%s)=%u (%s)\n", __func__, mod, mode, + mod_clock_activity_mode_name_get(mode)); + + + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_por_clk_rate_get + * @BRIEF return the recommended module functional clock rate, + * in KHz, for a given OPerating Point (OPP), + * as defined in Data Manual. + * @RETURNS module recommended functional clock rate, in KHz. + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in] mod: module name, as defined in module.h + * @DESCRIPTION return the recommended module functional clock rate, + * in KHz, for a given OPerating Point (OPP), + * as defined in Data Manual. + *//*------------------------------------------------------------------------ */ +int module_por_clk_rate_get(const char *mod, const char *opp) +{ + mod_info data; + mod_opp data_opp; + int ret, i, opp_count, rate_khz; + + CHECK_NULL_ARG(mod, OMAPCONF_ERR_ARG); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + rate_khz = OMAPCONF_ERR_NOT_AVAILABLE; + goto module_por_clk_rate_get_end; + } + + opp_count = genlist_getcount((genlist *) &(data.mod_opp_list)); + for (i = 0; i < opp_count; i++) { + genlist_get(&(data.mod_opp_list), i, + (mod_opp *) &data_opp); + if (strcmp(data_opp.name, opp) != 0) + continue; + + /* Module OPP details found */ + rate_khz = data_opp.rate; + goto module_por_clk_rate_get_end; + } + + dprintf("%s(%s): Module OPP details could not be found!\n", + __func__, opp); + rate_khz = OMAPCONF_ERR_NOT_AVAILABLE; + + + + +#if 0 + opp_id = opp_s2id(opp); + if (opp_id < 0) { + dprintf("%s(%s): could not retrieve OPP ID! (%d)\n", + __func__, mod, opp_id); + rate_khz = opp_id; + goto mod_por_clk_rate_get_end; + } + + if (cpu_is_omap44xx()) { + ret = mod44xx_get_por_clk_speed((mod44xx_id) mod_id, + (unsigned short) opp_id, &rate_mhz); + if (ret < 0) { + dprintf( + "%s(%s): could not retrieve module POR rate! (%d)\n", + __func__, mod, ret); + rate_khz = ret; + } else { + rate_khz = mhz2khz(rate_mhz); + } + } else if (cpu_is_omap54xx()) { + rate_mhz = mod54xx_por_clk_rate_get( + (mod54xx_id) mod_id, (opp54xx_id) opp_id); + if (rate_mhz < 0) { + rate_khz = (int) rate_mhz; + dprintf( + "%s(%s): could not retrieve module POR rate! (%d)\n", + __func__, mod, rate_khz); + } else { + rate_khz = mhz2khz(rate_mhz); + } + } else { + fprintf(stderr, "omapconf: %s(): cpu not supported!!!\n", + __func__); + rate_khz = OMAPCONF_ERR_CPU; + } +#endif + + +module_por_clk_rate_get_end: + dprintf("%s(%s) = %d KHz\n", __func__, mod, rate_khz); + return rate_khz; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_clk_get + * @BRIEF return module functional clock ID + * @RETURNS module functional clock source in case of success (>= 0) + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in] id: valid module ID + * @DESCRIPTION return module functional clock ID + *//*------------------------------------------------------------------------ */ +int module_clk_get(const char *mod) +{ + mod_info data; + int ret, clk_id; + + CHECK_NULL_ARG(mod, OMAPCONF_ERR_ARG); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + clk_id = OMAPCONF_ERR_NOT_AVAILABLE; + } else if (data.clk < 0) { + dprintf("%s(%s): could not retrieve module clock ID!\n", + __func__, mod); + clk_id = OMAPCONF_ERR_NOT_AVAILABLE; + } else { + clk_id = data.clk; + } + + dprintf("%s(%s)=%d KHz\n", __func__, mod, clk_id); + return clk_id; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_clk_rate_get + * @BRIEF return the module functional clock rate, in KHz. + * @RETURNS module functional clock rate, in KHz. + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in] mod: module name, as defined in module.h + * @param[in] ignore: do not consider DPLL status (if any). + * @DESCRIPTION return the module functional clock rate, in KHz. + *//*------------------------------------------------------------------------ */ +int module_clk_rate_get(const char *mod, unsigned short ignore) +{ + mod_info data; + int ret, rate_khz; + double rate_mhz; + + CHECK_NULL_ARG(mod, OMAPCONF_ERR_ARG); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + rate_khz = OMAPCONF_ERR_NOT_AVAILABLE; + } else if (data.clk < 0) { + dprintf("%s(%s): could not retrieve module clock ID!\n", + __func__, mod); + rate_khz = OMAPCONF_ERR_NOT_AVAILABLE; + } else { + rate_mhz = clk54xx_rate_get(data.clk, ignore); + if (rate_mhz < 0.0) { + rate_khz = (int) rate_mhz; + dprintf( + "%s(%s): could not retrieve module rate! (%d)\n", + __func__, mod, rate_khz); + } else { + rate_khz = mhz2khz(rate_mhz); + } + } + + dprintf("%s(%s)=%d KHz\n", __func__, mod, rate_khz); + return rate_khz; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_status_show + * @BRIEF show OMAP5 power status + * @RETURNS 0 on success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in,out] stream: output file stream (!= NULL) + * @DESCRIPTION show OMAP5 power status + *//*------------------------------------------------------------------------ */ +int module_status_show(FILE *stream) +{ + int voltdm_count; + const genlist *voltdm_list; + voltdm_info voltdm; + const char *opp; + char s_voltdm_name[VOLTDM_MAX_NAME_LENGTH + 10]; + int powerdm_count; + const genlist *powerdm_list; + powerdm_info pwrdm; + int clockdm_count; + const genlist *clockdm_list; + clockdm_info clkdm; + int mod_count; + const genlist *mod_list; + mod_info mod; + int v, p, c, m; + mod_idle_status idlest; + mod_standby_status stbyst; + char s_idlest[MODULE_MODES_MAX_NAME_LENGTH]; + char s_stbyst[MODULE_MODES_MAX_NAME_LENGTH]; + pwrdm_state pwst, pwtgst; + char s_pwst[PWRDM_STATE_MAX_NAME_LENGTH]; + char s_pwtgst[PWRDM_STATE_MAX_NAME_LENGTH]; + char s_pwrdm_name[PWRDM_MAX_NAME_LENGTH]; + clkdm_status clkst; + char s_clkst[CLKDM_STATUS_MAX_NAME_LENGTH]; + char s_clkdm_name[CLKDM_MAX_NAME_LENGTH]; + double clk_rate; + char s_clk_rate[12]; + char s_current_opp[OPP_MAX_NAME_LENGTH]; + unsigned short first_mod, first_clkdm, first_pwrdm; + double volt; + + /* Retrieve voltage domain list and count */ + voltdm_list = voltdm_list_get(); + if (voltdm_list == NULL) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve VDD List!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + voltdm_count = voltdm_count_get(); + if (voltdm_count <= 0) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve VDD count!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + /* Retrieve power domain list and count */ + powerdm_list = powerdm_list_get(); + if (powerdm_list == NULL) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve PWRDM List!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + powerdm_count = powerdm_count_get(); + if (powerdm_count <= 0) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve PWRDM count!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + /* Retrieve clock domain list and count */ + clockdm_list = clockdm_list_get(); + if (clockdm_list == NULL) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve CLKDM List!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + clockdm_count = clockdm_count_get(); + if (clockdm_count <= 0) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve CLKDM count!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + /* Retrieve module domain list and count */ + mod_list = module_list_get(); + if (mod_list == NULL) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve MODULE List!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + mod_count = module_count_get(); + if (mod_count <= 0) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve MODULE count!\n", + __func__); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + + /* For each voltage domain, retrieve the current OPP */ + fprintf(stream, + "|---------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"); + fprintf(stream, + "| OMAP Power Status |\n"); + fprintf(stream, + "|---------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"); + fprintf(stream, + "| Voltage Domain | Power Domain | Clock Domain | Module Status |\n"); + fprintf(stream, + "| Name | OPP | Name | Curr. | Target | Name | Status | Name | Rate (MHz) | Idle | Standby |\n"); + /* For each domain, retrieve the clock & power domain status */ + for (v = 0; v < voltdm_count; v++) { + fprintf(stream, + "|---------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"); + genlist_get((genlist *) voltdm_list, v, (void *) &voltdm); + + opp = opp_get(voltdm.name, 1); + if (opp != NULL) + strncpy(s_current_opp, opp, OPP_MAX_NAME_LENGTH); + else + strncpy(s_current_opp, "NOT FOUND", OPP_MAX_NAME_LENGTH); + + volt = (double) voltdm_voltage_get(voltdm.name) / 1000000.0; + if (volt > 0) + sprintf(s_voltdm_name, "%s (%.3lfV)", + voltdm.name, volt); + else + strcpy(s_voltdm_name, voltdm.name); + + for (p = 0, first_pwrdm = 1; p < powerdm_count; p++) { + genlist_get( + (genlist *) powerdm_list, p, (void *) &pwrdm); + + if (strcmp(pwrdm.voltdm, voltdm.name) != 0) + continue; + /* Ignore these power domains (and modules) */ + else if (strcmp(pwrdm.name, "MMAON") == 0) + continue; + else if (strcmp(pwrdm.name, "MPUAON") == 0) + continue; + else if (strcmp(pwrdm.name, "CUSTEFUSE") == 0) + continue; + + *s_pwst = '\0'; + pwst = powerdm_state_get(pwrdm.name, + PWRDM_STATE_CURRENT); + pwrdm_state2string(s_pwst, pwst); + + *s_pwtgst = '\0'; + pwtgst = powerdm_state_get(pwrdm.name, + PWRDM_STATE_TARGET); + pwrdm_state2string(s_pwtgst, pwtgst); + strncpy(s_pwrdm_name, pwrdm.name, + PWRDM_MAX_NAME_LENGTH); + + for (c = 0, first_clkdm = 1; c < clockdm_count; c++) { + genlist_get((genlist *) clockdm_list, c, + (void *) &clkdm); + + if (strcmp(clkdm.powerdm, pwrdm.name) != 0) + continue; + if ((strcmp(clkdm.name, CLKDM_L4_SEC) == 0) && + cpu_is_gp_device()) + continue; + if (strcmp(clkdm.name, CLKDM_NONE) == 0) + continue; + + if ((!first_pwrdm) && (first_clkdm)) + fprintf(stream, + "| %-17s | %-9s |-------------------------------------------------------------------------------------------------------------------------------|\n", + "", ""); + *s_clkst = '\0'; + clkst = clockdm_status_get(clkdm.name); + if (clkst != CLKDM_STATUS_MAX) + strcpy(s_clkst, + clkdm_status_name_get(clkst)); + + strncpy(s_clkdm_name, clkdm.name, + CLKDM_MAX_NAME_LENGTH); + + /* For each module, retrieve status */ + for (m = 0, first_mod = 1; m < mod_count; m++) { + genlist_get((genlist *) mod_list, m, + (void *) &mod); + + if (strcmp(mod.clkdm, clkdm.name) != 0) + continue; + + *s_idlest = '\0'; + *s_stbyst = '\0'; + + idlest = module_idle_status_get( + mod.name); + if (idlest != MOD_IDLE_STATUS_MAX) { + strcpy(s_idlest, mod_idle_status_name_get(idlest)); + } else if (idlest != MOD_DISABLED) { + stbyst = module_standby_status_get(mod.name); + if (stbyst != MOD_STANDBY_STATUS_MAX) + strcpy(s_stbyst, mod_standby_status_name_get(stbyst)); + } + clk_rate = (double) module_clk_rate_get( + mod.name, 0) / 1000.0; + if (clk_rate < 0.0) + strcpy(s_clk_rate, "Error"); + else + snprintf(s_clk_rate, 12, + "%.3lf", clk_rate); + if ((first_mod) && (!first_clkdm)) + fprintf(stream, + "| %-17s | %-9s | %-10s | %-6s | %-6s |------------------------------------------------------------------------------------------------|\n", + "", "", "", "", ""); + fprintf(stream, + "| %-17s | %-9s | %-10s | %-6s | %-6s | %-10s | %-8s | %-21s | %-10s | %-20s | %-10s |\n", + s_voltdm_name, + s_current_opp, + s_pwrdm_name, + s_pwst, + s_pwtgst, + s_clkdm_name, + s_clkst, + mod.name, + s_clk_rate, + s_idlest, + s_stbyst); + if (first_mod) { + *s_clkdm_name = '\0'; + *s_pwrdm_name = '\0'; + *s_voltdm_name = '\0'; + *s_current_opp = '\0'; + *s_pwst = '\0'; + *s_pwtgst = '\0'; + *s_clkst = '\0'; + first_mod = 0; + } + } + first_clkdm = 0; + } + first_pwrdm = 0; + } + + } + fprintf(stream, + "|---------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_clk_rate_audit + * @BRIEF Modules functional clock rate audit. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in,out] stream: output file - NULL: no output (silent) + * @param[in,out] err_nbr: pointer to return audit error number + * @param[in,out] wng_nbr: pointer to return audit warning number + * @DESCRIPTION Modules functional clock rate audit. + *//*------------------------------------------------------------------------ */ +int module_clk_rate_audit(FILE *stream, + unsigned int *err_nbr, unsigned int *wng_nbr) +{ + const char *opp; + int mod_count, m; + const genlist *mod_list; + mod_info mod; + + double speed_curr = 0.0, speed_por = 0.0; + const char pass1[10] = "pass (1)"; + const char fail2[10] = "FAIL (2)"; + const char fail3[10] = "FAIL (3)"; + const char warning4[10] = "warn (4)"; + const char warning5[10] = "warn (5)"; + const char warning6[10] = "warn (6)"; + const char warning7[10] = "warn (7)"; + const char ignore8[10] = "ign. (8)"; + const char warning9[10] = "warn (9)"; + const char fixme[10] = "FIXME"; + char *status; + char s_speed_curr[16], s_speed_por[16]; + char src_clk_name[CLK54XX_MAX_NAME_LENGTH]; + char opp_name[OPP_MAX_NAME_LENGTH]; + char prev_gov[CPUFREQ_GOV_MAX_NAME_LENGTH]; + char prev_gov2[CPUFREQ_GOV_MAX_NAME_LENGTH]; + mod_module_mode mmode; + + CHECK_CPU(54xx, OMAPCONF_ERR_CPU); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + + *err_nbr = 0; + *wng_nbr = 0; + + /* Switch to userspace governor temporarily, + * so that OPP cannot change during audit and does not false it. + */ + cpufreq_scaling_governor_set("userspace", prev_gov); + + /* Retrieve module domain list and count */ + mod_list = module_list_get(); + if (mod_list == NULL) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve MODULE List!\n", + __func__); + (*wng_nbr)++; + goto module_clk_rate_audit_end; + } + mod_count = module_count_get(); + if (mod_count <= 0) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve MODULE count!\n", + __func__); + (*wng_nbr)++; + goto module_clk_rate_audit_end; + } + + if (stream == NULL) + goto module_clk_rate_audit_loop; + + fprintf(stream, + "|----------------------------------------------------------------------------------------------------------|\n"); + fprintf(stream, "| %-21s | %-24s | %-9s | %-27s | %-11s |\n", + " CLOCK SPEED AUDIT", "", "", " Clock Rate (MHz)", + ""); + fprintf(stream, + "| %-21s | %-24s | %-9s | %-12s | %-12s | %-11s |\n", + "Module", "Source Clock", "OPP", "Current", "Expected", + "STATUS"); + fprintf(stream, + "|----------------------------------------------------------------------------------------------------------|\n"); + +module_clk_rate_audit_loop: + for (m = 0; m < mod_count; m++) { + genlist_get((genlist *) mod_list, m, + (void *) &mod); + dprintf("\n\n%s():Auditing module %s\n", __func__, mod.name); + + /* Filter based on module name */ + if (cpu_is_gp_device()) { + if ((strcmp(mod.name, MOD_TIMER12) == 0) || + (strcmp(mod.name, MOD_WD_TIMER1) == 0) || + (strcmp(mod.name, MOD_DMA_CRYPTO) == 0) || + (strcmp(mod.name, MOD_AES1) == 0) || + (strcmp(mod.name, MOD_AES2) == 0) || + (strcmp(mod.name, MOD_SHA2MD5) == 0) || + (strcmp(mod.name, MOD_RNG) == 0) || + (strcmp(mod.name, MOD_DES3DES) == 0) || + (strcmp(mod.name, MOD_PKA) == 0)) { + dprintf("\tGP device, skip it.\n"); + continue; + } + } + + /* init variables */ + status = (char *) fixme; + speed_curr = -1.0; + snprintf(s_speed_curr, 16, "%s", "NOT FOUND"); + snprintf(src_clk_name, CLK54XX_MAX_NAME_LENGTH, "%s", + "NOT FOUND"); + strcpy(opp_name, "NOT FOUND"); + speed_por = -2.0; + snprintf(s_speed_por, 16, "%s", "NOT FOUND"); + + /* Get module's functional source clock */ + if (mod.clk < 0) { + dprintf("%s(): src_clk not found!\n", __func__); + status = (char *) warning4; + (*wng_nbr)++; + goto module_clk_rate_audit_opp_fill; + } + snprintf(src_clk_name, CLK54XX_MAX_NAME_LENGTH, "%s", + clk54xx_name_get(mod.clk)); /* FIXME */ + + /* Get module's functional clock rate*/ + speed_curr = + (double) module_clk_rate_get(mod.name, 1) / 1000.0; + if (speed_curr < 0.0) { + dprintf("%s(): speed not found!\n", __func__); + status = (char *) warning5; + (*wng_nbr)++; + goto module_clk_rate_audit_opp_fill; + } + dprintf("%s(): speed=%lfMHz\n", __func__, speed_curr); + mhz2string(speed_curr, s_speed_curr); + + /* Get OPP */ + opp = opp_get(mod.voltdm, 1); + if (opp == NULL) { + dprintf("%s(): opp not found!\n", __func__); + status = (char *) fail3; + (*err_nbr)++; + goto module_clk_rate_audit_opp_fill; + } + strncpy(opp_name, opp, OPP_MAX_NAME_LENGTH); + + /* + * Get Plan Of Record (POR) module's functional + * source clock rate + */ + + if ((strcmp(mod.name, MOD_TIMER2) == 0) || + (strcmp(mod.name, MOD_TIMER3) == 0) || + (strcmp(mod.name, MOD_TIMER4) == 0) || + (strcmp(mod.name, MOD_TIMER5) == 0) || + (strcmp(mod.name, MOD_TIMER6) == 0) || + (strcmp(mod.name, MOD_TIMER7) == 0) || + (strcmp(mod.name, MOD_TIMER8) == 0) || + (strcmp(mod.name, MOD_TIMER9) == 0) || + (strcmp(mod.name, MOD_TIMER10) == 0) || + (strcmp(mod.name, MOD_TIMER11) == 0) || + (strcmp(mod.name, MOD_MCASP) == 0) || + (strcmp(mod.name, MOD_MCBSP1) == 0) || + (strcmp(mod.name, MOD_MCBSP2) == 0) || + (strcmp(mod.name, MOD_MCBSP3) == 0) || + (strcmp(mod.name, MOD_SLIMBUS1) == 0) || + (strcmp(mod.name, MOD_SLIMBUS2) == 0)) { + /* + * These modules are out of interest or + * there is no mandatory clock speed + */ + snprintf(s_speed_por, 16, "%s", "Undefined"); + status = (char *) ignore8; + goto module_clk_rate_audit_opp_fill; + } + + mmode = module_mode_get(mod.name); + speed_por = (double) module_por_clk_rate_get( + mod.name, opp) / 1000.0; + if (speed_por < 0.0) { + dprintf("\tWarning: %s POR speed not yet defined!\n", + mod.name); + status = (char *) warning6; + (*wng_nbr)++; + goto module_clk_rate_audit_opp_fill; + } + dprintf("\tPOR rate is %lfMHz\n", speed_por); + snprintf(s_speed_por, 16, "%.3lf", speed_por); + + /* Keep only 1 decimal for comparison */ + if (speed_curr > 1.0) + speed_curr = (double) ((int) + (speed_curr * 10.0)) / 10.0; + dprintf("%s(): rounded current speed=%lfMHz\n", + __func__, speed_curr); + if (speed_por > 1.0) + speed_por = (double) ((int) + (speed_por * 10.0)) / 10.0; + dprintf("%s(): rounded POR speed=%lfMHz\n", + __func__, speed_por); + + if (speed_curr == speed_por) { + status = (char *) pass1; + dprintf("%s(): pass!\n", __func__); + } else if (mmode == MOD_DISABLED_MODE) { + /* + * may not be a true failure when + * module is disabled (not configured). + * Does not impact power. + */ + dprintf("%s(): disabled module.\n", + __func__); + status = (char *) warning7; + (*wng_nbr)++; + } else if (speed_curr == 0.0) { + dprintf("%s(): speed_curr == 0.0.\n", + __func__); + status = (char *) warning7; + (*wng_nbr)++; + } else if (speed_curr < speed_por) { + dprintf("%s(): curr < por.\n", + __func__); + status = (char *) warning9; + (*wng_nbr)++; + } else { + dprintf("%s(): FAILED!\n", __func__); + status = (char *) fail2; + (*err_nbr)++; + } + +module_clk_rate_audit_opp_fill: + if (stream == NULL) + break; + + fprintf(stream, + "| %-21s | %-24s | %-9s | %-12s | %-12s | %-11s |\n", + mod.name, src_clk_name, opp_name, s_speed_curr, + s_speed_por, status); + } + + if (stream == NULL) + goto module_clk_rate_audit_end; + + fprintf(stream, + "|----------------------------------------------------------------------------------------------------------|\n\n"); + + fprintf(stream, + "Notes:\n"); + fprintf(stream, + " (1) Current module rate IS the expected (PoR) one.\n"); + fprintf(stream, + " (2) Current module rate is NOT the expected (PoR) one.\n"); + fprintf(stream, + " (3) Current OPP could not be detected.\n"); + fprintf(stream, + " (4) Current module source clock could not be retrieved.\n"); + fprintf(stream, + " (5) Current module source clock rate could not be retrieved.\n"); + fprintf(stream, + " (6) Current module source clock PoR rate could not be retrieved.\n"); + fprintf(stream, + " (7) Clock rate does no match PoR rate, but module is disabled (no power impact).\n"); + fprintf(stream, + " (8) Optional module, not used on reference platform.\n"); + fprintf(stream, + " (9) Current module rate is lower than the expected (PoR) one.\n"); + + if (*err_nbr == 0) + fprintf(stream, + "\nSUCCESS! Clock Speed audit completed with 0 error (%d warning(s))\n\n", + *wng_nbr); + else + fprintf(stream, + "\nFAILED! Clock Speed audit completed with %d error and %d warning.\n\n", + *err_nbr, *wng_nbr); + +module_clk_rate_audit_end: + /* Restore CPUFreq governor */ + cpufreq_scaling_governor_set(prev_gov, prev_gov2); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_sysconfig_audit + * @BRIEF Modules SYSCONFIG registers audit. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in,out] stream: output file - NULL: no output (silent) + * @param[in,out] err_nbr: pointer to return audit error number + * @param[in,out] wng_nbr: pointer to return audit warning number + * @DESCRIPTION Modules SYSCONFIG registers audit. + *//*------------------------------------------------------------------------ */ +int module_sysconfig_audit(FILE *stream, unsigned int *err_nbr, + unsigned int *wng_nbr) +{ + int mod_count, m; + const genlist *mod_list; + mod_info mod; + const char pass[5] = "Pass"; + const char fail[5] = "FAIL"; + const char ignore[12] = "Ignored (1)"; + const char warning[8] = "Warning"; + mod_autoidle_mode autoidle_mode; + mod_idle_mode idle_mode; + mod_standby_mode standby_mode; + mod_clock_activity_mode clock_activity_mode; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row; + char element[TABLE_MAX_ELT_LEN]; + + CHECK_CPU(54xx, OMAPCONF_ERR_CPU); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + + *err_nbr = 0; + *wng_nbr = 0; + + /* Retrieve module domain list and count */ + mod_list = module_list_get(); + if (mod_list == NULL) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve MODULE List!\n", + __func__); + (*wng_nbr)++; + goto module_sysconfig_audit_end; + } + mod_count = module_count_get(); + if (mod_count <= 0) { + fprintf(stderr, + "omapconf: %s(): failed to retrieve MODULE count!\n", + __func__); + (*wng_nbr)++; + goto module_sysconfig_audit_end; + } + + autoadjust_table_init(table); + + row = 0; + strncpy(table[row][0], "MODULES SYSCONFIG AUDIT", TABLE_MAX_ELT_LEN); + strncpy(table[row][1], "AUTOIDLE Mode", TABLE_MAX_ELT_LEN); + strncpy(table[row][2], "IDLE Mode", TABLE_MAX_ELT_LEN); + strncpy(table[row][3], "STANDBY Mode", TABLE_MAX_ELT_LEN); + strncpy(table[row][4], "CLOCK ACTIVITY Mode", TABLE_MAX_ELT_LEN); + row++; + + for (m = 0; m < mod_count; m++) { + genlist_get((genlist *) mod_list, m, + (void *) &mod); + dprintf("\n%s(): Module name = %s\n", __func__, mod.name); + + autoadjust_table_strncpy(table, row, 0, (char *) mod.name); + if (mod.sysconfig == NULL) { + dprintf("\t%s(): no sysconfig\n", __func__); + continue; + } + + if (!module_is_accessible(mod.name)) { + dprintf("\t%s(): module is not accessible\n", __func__); + autoadjust_table_strncpy(table, row, 1, + (char *) ignore); + autoadjust_table_strncpy(table, row, 2, + (char *) ignore); + autoadjust_table_strncpy(table, row, 3, + (char *) ignore); + autoadjust_table_strncpy(table, row, 4, + (char *) ignore); + row++; + continue; + } + + /* Audit module's autoidle bit (if any) */ + autoidle_mode = module_autoidle_mode_get(mod.name); + if (autoidle_mode == MOD_AUTOIDLE_MODE_MAX) { + dprintf("\t%s(): module does not have autoidle bit\n", + __func__); + goto module_sysconfig_audit_idle_mode; + } + dprintf("\t%s(): autoidle=%u (%s)\n", __func__, autoidle_mode, + mod_autoidle_mode_name_get(autoidle_mode)); + if (autoidle_mode == MOD_AUTOGATING) { + autoadjust_table_strncpy(table, row, 1, (char *) pass); + } else { + snprintf(element, TABLE_MAX_ELT_LEN, "%s (%s)", + fail, mod_autoidle_mode_name_get( + autoidle_mode)); + autoadjust_table_strncpy(table, row, 1, element); + (*err_nbr)++; + } + +module_sysconfig_audit_idle_mode: + /* Audit module's IDLE mode */ + idle_mode = module_idle_mode_get(mod.name); + if (idle_mode == MOD_IDLE_MODE_MAX) { + dprintf("\t%s(): module does not have idle mode\n", + __func__); + goto module_sysconfig_audit_standby_mode; + } + dprintf("\t%s(): idle mode=%u (%s)\n", __func__, idle_mode, + mod_idle_mode_name_get(idle_mode)); + switch (idle_mode) { + case MOD_SMART_IDLE_WAKEUP: + autoadjust_table_strncpy(table, row, 2, (char *) pass); + break; + case MOD_SMART_IDLE: + if (!module_has_smart_idle_wakeup_mode(mod.name)) { + autoadjust_table_strncpy(table, row, 2, + (char *) pass); + } else { + snprintf(element, TABLE_MAX_ELT_LEN, + "%s (%s) (3)", fail, + mod_idle_mode_name_get(idle_mode)); + autoadjust_table_strncpy(table, row, 2, + element); + (*err_nbr)++; + } + break; + case MOD_FORCE_IDLE: + snprintf(element, TABLE_MAX_ELT_LEN, "%s (%s)", + warning, mod_idle_mode_name_get(idle_mode)); + autoadjust_table_strncpy(table, row, 2, element); + (*wng_nbr)++; + break; + default: + if ((strcmp(mod.name, MOD_UART1) == 0) || + (strcmp(mod.name, MOD_UART2) == 0) || + (strcmp(mod.name, MOD_UART3) == 0) || + (strcmp(mod.name, MOD_UART4) == 0) || + (strcmp(mod.name, MOD_UART5) == 0) || + (strcmp(mod.name, MOD_UART6) == 0)) { + /* + * UART IP idle management is buggy + * (cf errata). When active, + * must be used in no-idle mode. + */ + autoadjust_table_strncpy(table, row, 2, + (char *) pass); + } else { + snprintf(element, TABLE_MAX_ELT_LEN, + "%s (%s)", fail, mod_idle_mode_name_get( + idle_mode)); + autoadjust_table_strncpy(table, row, 2, + element); + (*err_nbr)++; + } + } + +module_sysconfig_audit_standby_mode: + /* Audit module's STANDBY mode */ + standby_mode = module_standby_mode_get(mod.name); + if (standby_mode == MOD_STANDBY_MODE_MAX) { + goto module_sysconfig_audit_clock_activity_mode; + dprintf("\t%s(): module does not have standby mode\n", + __func__); + } + dprintf("\t%s(): standby mode=%u (%s)\n", __func__, + standby_mode, mod_standby_mode_name_get(standby_mode)); + switch (standby_mode) { + case MOD_STANDBY_MODE_RESERVED: + autoadjust_table_strncpy(table, row, 3, (char *) pass); + break; + case MOD_SMART_STANDBY: + if (!module_has_smart_standby_wakeup_mode(mod.name)) { + autoadjust_table_strncpy(table, row, 2, + (char *) pass); + } else { + snprintf(element, TABLE_MAX_ELT_LEN, + "%s (%s) (4)", fail, + mod_standby_mode_name_get(idle_mode)); + autoadjust_table_strncpy(table, row, 2, + element); + (*err_nbr)++; + } + break; + case MOD_FORCE_STANDBY: + snprintf(element, TABLE_MAX_ELT_LEN, "%s (%s)", + warning, mod_standby_mode_name_get( + standby_mode)); + autoadjust_table_strncpy(table, row, 3, element); + (*wng_nbr)++; + break; + default: + snprintf(element, TABLE_MAX_ELT_LEN, "%s (%s)", + fail, mod_standby_mode_name_get(standby_mode)); + autoadjust_table_strncpy(table, row, 3, element); + (*err_nbr)++; + } + +module_sysconfig_audit_clock_activity_mode: + /* Audit module's CLOCK ACTIVITY mode */ + clock_activity_mode = module_clock_activity_mode_get(mod.name); + if (clock_activity_mode == MOD_CLOCK_ACTIVITY_MODE_MAX) { + dprintf( + "\t%s(): module does not have clock activity mode\n", + __func__); + goto module_sysconfig_audit_next_row; + } + dprintf("\t%s(): clock activity mode=%u (%s)\n", + __func__, clock_activity_mode, + mod_clock_activity_mode_name_get(clock_activity_mode)); + switch (clock_activity_mode) { + case MOD_FCLK_AUTO_ICLK_AUTO: + /* + * Functional clock can be switched-off. + * L4 clock can be switched-off. + */ + autoadjust_table_strncpy(table, row, 4, (char *) pass); + break; + case MOD_FCLK_AUTO_ICLK_ON: + /* + * Functional clock can be switched-off. + * L4 clock is maintained during wake-up period. + */ + case MOD_FCLK_ON_ICLK_AUTO: + /* + * Functional clock is maintained during wake-up + * period. + * L4 clock can be switched-off. + */ + snprintf(element, TABLE_MAX_ELT_LEN, "%s (%s)", + warning, mod_clock_activity_mode_name_get( + clock_activity_mode)); + autoadjust_table_strncpy(table, row, 4, element); + (*wng_nbr)++; + break; + case MOD_FCLK_ON_ICLK_ON: + /* + * Functional clock is maintained during wake-up + * period. + * L4 clock is maintained during wake-up period. + */ + default: + snprintf(element, TABLE_MAX_ELT_LEN, "%s (%s)", + fail, mod_clock_activity_mode_name_get( + clock_activity_mode)); + autoadjust_table_strncpy(table, row, 4, element); + (*err_nbr)++; + } +module_sysconfig_audit_next_row: + row++; + } + + if (stream != NULL) { + autoadjust_table_fprint(stream, table, row, 5); + fprintf(stream, + "NB:\n"); + fprintf(stream, + " (1) - Show 'Ignored' when module is disabled (registers not accessible).\n"); + fprintf(stream, + " (2) - Show empty cell(s) when module does not feature this mode.\n"); + fprintf(stream, + " - AUTOIDLE MODE:\n"); + fprintf(stream, + " - Report Pass if enabled, FAIL otherwise.\n"); + fprintf(stream, + " - IDLE MODE:\n"); + fprintf(stream, + " - Report Pass if set to \"Smart-Idle\" or \"Smart-Idle Wakeup\" (when available).\n"); + fprintf(stream, + " - (3) Modules featuring \"Smart-Idle Wakeup\" mode must be programmed in this mode. Audit will report FAIL even with \"Smart-Idle\" mode.\n"); + fprintf(stream, + " - Report Warning (with setting) in case of \"Force-Idle\" mode.\n"); + fprintf(stream, + " - Report FAIL (with incorrect setting) otherwise.\n"); + fprintf(stream, + " - STANDBY MODE:\n"); + fprintf(stream, + " - Report Pass if set to \"Smart-Standby\" or \"Smart-Standby Wakeup\" (when available).\n"); + fprintf(stream, + " - (4) Modules featuring \"Smart-Standby Wakeup\" mode must be programmed in this mode. Audit will report FAIL even with \"Smart-Standby\" mode.\n"); + fprintf(stream, + " - Report Warning (with setting) in case of \"Force-Standby\" mode.\n"); + fprintf(stream, + " - Report FAIL (with incorrect setting) otherwise.\n"); + fprintf(stream, + " - CLOCKACTIVITY MODE:\n"); + fprintf(stream, + " - Report Pass if both I-CLK and F-CLK are set to AUTO mode.\n"); + fprintf(stream, + " - Report Warning if one of I-CLK or F-CLK is set to ON mode.\n"); + fprintf(stream, + " - Report FAIL (with incorrect setting) otherwise.\n\n"); + +module_sysconfig_audit_end: + if (*err_nbr == 0) { + fprintf(stream, + "SUCCESS! Modules SYSCONFIG registers audit completed with 0 error (%d warning(s))\n\n", + *wng_nbr); + } else { + fprintf(stream, + "FAILED! Modules SYSCONFIG registers audit completed with %d error and %d warning.\n\n", + *err_nbr, *wng_nbr); + } + } + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_config_show + * @BRIEF analyze module power configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in,out] stream: output file + * @param[in] mod: module name + * @DESCRIPTION analyze module power configuration + *//*------------------------------------------------------------------------ */ +int module_config_show(FILE *stream, const char *mod) +{ + int ret; + mod_info data; + + unsigned int cm_clkctrl, rm_context; + char s[72]; + mod_idle_status idlest; + mod_standby_status standbyst; + double rate; + + CHECK_NULL_ARG(mod, OMAPCONF_ERR_ARG); + CHECK_CPU(54xx, OMAPCONF_ERR_NOT_AVAILABLE); + + ret = _module_info_get(mod, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve mod_info struct!\n", + __func__, mod); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + if (data.clkctrl == NULL) { + /* Nothing to show */ + return 0; + } + + /* Read register */ + cm_clkctrl = reg_read(data.clkctrl); + + /* Decode and display module's power configuration */ + fprintf(stream, + "|------------------------------------------------------------------------|\n"); + strcpy(s, data.name); + strcat(s, " Module Configuration"); + fprintf(stream, + "| %-70s |\n", s); + fprintf(stream, + "|----------------------------------|-------------------------------------|\n"); + + /* F-Clock Source & Rate */ + if (data.clk >= 0) { + fprintf(stream, + "| %-32s | %-35s |\n", "Source Clock", + clk54xx_name_get(data.clk)); /* FIXME */ + + rate = (double) module_clk_rate_get(data.name, 1) / 1000.0; + if (rate < 0.0) + strcpy(s, "Unknown"); + else + sprintf(s, "%.3lfMHz", rate); + fprintf(stream, "| %-32s | %-35s |\n", "Source Clock Rate", s); + } else { + fprintf(stream, "| %-32s | %-35s |\n", "Source Clock", + "Unknown"); + fprintf(stream, "| %-32s | %-35s |\n", "Source Clock Rate", + "Unknown"); + } + + /* Module Mode */ + fprintf(stream, "| %-32s | %-35s |\n", "Mode", + mod_module_mode_name_get(module_mode_get(data.name))); + + /* Idle Status */ + idlest = module_idle_status_get(data.name); + if (idlest == MOD_IDLE_STATUS_MAX) + fprintf(stream, "| %-32s | %-35s |\n", "Idle Status", + "Not Available (does not exist)"); + else + fprintf(stream, "| %-32s | %-35s |\n", "Idle Status", + mod_idle_status_name_get(idlest)); + + /* Standby Status */ + standbyst = module_standby_status_get(data.name); + if (standbyst == MOD_STANDBY_STATUS_MAX) + fprintf(stream, "| %-32s | %-35s |\n", "Standby Status", + "Not Available (does not exist)"); + else + fprintf(stream, "| %-32s | %-35s |\n", "Standby Status", + mod_standby_status_name_get(standbyst)); + + /* FCLK Source / Optional Clocks (architecture-specific) */ + if (cpu_is_omap44xx()) { + rm_context = reg_read(data.context); + ret = mod44xx_config_show(stream, data.name, + reg_addr_get(data.clkctrl), cm_clkctrl, + reg_addr_get(data.context), rm_context); + } else if (cpu_is_omap54xx()) { + ret = mod54xx_config_show(stream, data.id, cm_clkctrl); + } else { + dprintf("omapconf: %s(): cpu not yet supported.\n", + __func__); + fprintf(stream, "| %-32s | %-35s |\n", + "Func. / Opt. Clocks", "UNKNOWN ARCH."); + } + + /* Module Context */ + ret = module_context_is_lost(data.name); + if (ret == -1) + fprintf(stream, "| %-32s | %-35s |\n", "Context", + "Not Available (does not exist)"); + else if (ret == 0) + fprintf(stream, "| %-32s | %-35s |\n", "Context", "Retained"); + else + fprintf(stream, "| %-32s | %-35s |\n", "Context", "Lost"); + + + fprintf(stream, + "|------------------------------------------------------------------------|\n\n"); + + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/module.h tiomapconf-1.61.1/arch/arm/mach-omap/common/module.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/module.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/module.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,273 @@ +/* + * + * @Component OMAPCONF + * @Filename module.h + * @Description OMAP Generic Module Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __MODULE_H__ +#define __MODULE_H__ + + +#include +#include +#include +#include + + +#define MOD_UNKNOWN ((const char *) "UNKNOWN") +#define MOD_DSP ((const char *) "DSP") +#define MOD_GPU ((const char *) "GPU") +#define MOD_IVA ((const char *) "IVA") +#define MOD_SL2 ((const char *) "SL2") +#define MOD_MPU ((const char *) "MPU") +#define MOD_DEBUGSS ((const char *) "DEBUGSS") +#define MOD_CTRL_MODULE_WKUP ((const char *) "CTRL_MODULE_WKUP") +#define MOD_CTRL_MODULE_CORE ((const char *) "CTRL_MODULE_CORE") +#define MOD_CTRL_MODULE_BANDGAP ((const char *) "CTRL_MODULE_BANDGAP") +#define MOD_L3_MAIN1_INTERCONNECT ((const char *) "L3_MAIN1_INTERCONNECT") +#define MOD_L3_MAIN2_INTERCONNECT ((const char *) "L3_MAIN2_INTERCONNECT") +#define MOD_L3_MAIN3_INTERCONNECT ((const char *) "L3_MAIN3_INTERCONNECT") +#define MOD_L3_INSTR_INTERCONNECT ((const char *) "L3_INSTR_INTERCONNECT") +#define MOD_L4_PER_INTERCONNECT ((const char *) "L4_PER_INTERCONNECT") +#define MOD_L4_WKUP_INTERCONNECT ((const char *) "L4_WKUP_INTERCONNECT") +#define MOD_L4_CFG_INTERCONNECT ((const char *) "L4_CFG_INTERCONNECT") +#define MOD_L4_ABE_INTERCONNECT ((const char *) "L4_ABE_INTERCONNECT") +#define MOD_GPIO1 ((const char *) "GPIO1") +#define MOD_GPIO2 ((const char *) "GPIO2") +#define MOD_GPIO3 ((const char *) "GPIO3") +#define MOD_GPIO4 ((const char *) "GPIO4") +#define MOD_GPIO5 ((const char *) "GPIO5") +#define MOD_GPIO6 ((const char *) "GPIO6") +#define MOD_GPIO7 ((const char *) "GPIO7") +#define MOD_GPIO8 ((const char *) "GPIO8") +#define MOD_TIMER1 ((const char *) "TIMER1") +#define MOD_TIMER2 ((const char *) "TIMER2") +#define MOD_TIMER3 ((const char *) "TIMER3") +#define MOD_TIMER4 ((const char *) "TIMER4") +#define MOD_TIMER5 ((const char *) "TIMER5") +#define MOD_TIMER6 ((const char *) "TIMER6") +#define MOD_TIMER7 ((const char *) "TIMER7") +#define MOD_TIMER8 ((const char *) "TIMER8") +#define MOD_TIMER9 ((const char *) "TIMER9") +#define MOD_TIMER10 ((const char *) "TIMER10") +#define MOD_TIMER11 ((const char *) "TIMER11") +#define MOD_TIMER12 ((const char *) "TIMER12") +#define MOD_WD_TIMER1 ((const char *) "WD_TIMER1") +#define MOD_WD_TIMER2 ((const char *) "WD_TIMER2") +#define MOD_WD_TIMER3 ((const char *) "WD_TIMER3") +#define MOD_SARRAM ((const char *) "SARRAM") +#define MOD_COUNTER_32K ((const char *) "COUNTER_32K") +#define MOD_KEYBOARD ((const char *) "KEYBOARD") +#define MOD_IO_SRCOMP_WKUP ((const char *) "IO_SRCOMP_WKUP") +#define MOD_IO_SRCOMP_CORE ((const char *) "IO_SRCOMP_CORE") +#define MOD_SMARTREFLEX_MPU ((const char *) "SMARTREFLEX_MPU") +#define MOD_SMARTREFLEX_IVA ((const char *) "SMARTREFLEX_IVA") +#define MOD_SMARTREFLEX_MM ((const char *) "SMARTREFLEX_MM") +#define MOD_SMARTREFLEX_CORE ((const char *) "SMARTREFLEX_CORE") +#define MOD_BANDGAPTS ((const char *) "BANDGAPTS") +#define MOD_FDIF ((const char *) "FDIF") +#define MOD_ISS ((const char *) "ISS") +#define MOD_CAL ((const char *) "CAL") +#define MOD_SPINLOCK ((const char *) "SPINLOCK") +#define MOD_MAILBOX ((const char *) "MAILBOX") +#define MOD_SARROM ((const char *) "SARROM") +#define MOD_OCP2SCP2 ((const char *) "OCP2SCP2") +#define MOD_OCPSCP3 ((const char *) "OCPSCP3") +#define MOD_PHY_EMIF ((const char *) "PHY_EMIF") +#define MOD_DLL_EMIF ((const char *) "DLL_EMIF") +#define MOD_DMM ((const char *) "DMM") +#define MOD_EMIF1 ((const char *) "EMIF1") +#define MOD_EMIF2 ((const char *) "EMIF2") +#define MOD_EMIF_OCP_FW ((const char *) "EMIF_OCP_FW") +#define MOD_IPU ((const char *) "IPU") +#define MOD_GPMC ((const char *) "GPMC") +#define MOD_OCMC_RAM ((const char *) "OCMC_RAM") +#define MOD_OCP_WP_NOC ((const char *) "OCP_WP_NOC") +#define MOD_C2C ((const char *) "C2C") +#define MOD_C2C_OCP_FW ((const char *) "C2C_OCP_FW") +#define MOD_MODEM_ICR ((const char *) "MODEM_ICR") +#define MOD_DMA_SYSTEM ((const char *) "DMA_SYSTEM") +#define MOD_LLI ((const char *) "LLI") +#define MOD_LLI_OCP_FW ((const char *) "LLI_OCP_FW") +#define MOD_MPHY ((const char *) "MPHY") +#define MOD_DSS ((const char *) "DSS") +#define MOD_BB2D ((const char *) "BB2D") +#define MOD_HSI ((const char *) "HSI") +#define MOD_IEEE1500_2_OCP ((const char *) "IEEE1500_2_OCP") +#define MOD_MMC1 ((const char *) "MMC1") +#define MOD_MMC2 ((const char *) "MMC2") +#define MOD_MMC3 ((const char *) "MMC3") +#define MOD_MMC4 ((const char *) "MMC4") +#define MOD_MMC5 ((const char *) "MMC5") +#define MOD_OCPSCP1 ((const char *) "OCPSCP1") +#define MOD_USB_HOST_HS ((const char *) "USB_HOST_HS") +#define MOD_USB_OTG_SS ((const char *) "USB_OTG_SS") +#define MOD_USB_TLL_HS ((const char *) "USB_TLL_HS") +#define MOD_USB_PHY_CORE ((const char *) "USB_PHY_CORE") +#define MOD_USB2PHY ((const char *) "USB2PHY") +#define MOD_SATA ((const char *) "SATA") +#define MOD_UNIPRO1 ((const char *) "UNIPRO1") +#define MOD_UNIPRO2 ((const char *) "UNIPRO2") +#define MOD_MPHY_UNIPRO2 ((const char *) "MPHY_UNIPRO2") +#define MOD_ELM ((const char *) "ELM") +#define MOD_HDQ1W ((const char *) "HDQ1W") +#define MOD_I2C1 ((const char *) "I2C1") +#define MOD_I2C2 ((const char *) "I2C2") +#define MOD_I2C3 ((const char *) "I2C3") +#define MOD_I2C4 ((const char *) "I2C4") +#define MOD_I2C5 ((const char *) "I2C5") +#define MOD_MCSPI1 ((const char *) "MCSPI1") +#define MOD_MCSPI2 ((const char *) "MCSPI2") +#define MOD_MCSPI3 ((const char *) "MCSPI3") +#define MOD_MCSPI4 ((const char *) "MCSPI4") +#define MOD_UART1 ((const char *) "UART1") +#define MOD_UART2 ((const char *) "UART2") +#define MOD_UART3 ((const char *) "UART3") +#define MOD_UART4 ((const char *) "UART4") +#define MOD_UART5 ((const char *) "UART5") +#define MOD_UART6 ((const char *) "UART6") +#define MOD_DMA_CRYPTO ((const char *) "DMA_CRYPTO") +#define MOD_AES1 ((const char *) "AES1") +#define MOD_AES2 ((const char *) "AES2") +#define MOD_SHA2MD5 ((const char *) "SHA2MD5") +#define MOD_RNG ((const char *) "RNG") +#define MOD_DES3DES ((const char *) "DES3DES") +#define MOD_PKA ((const char *) "PKA") +#define MOD_AESS ((const char *) "AESS") +#define MOD_DMIC ((const char *) "DMIC") +#define MOD_MCASP ((const char *) "MCASP") +#define MOD_MCBSP1 ((const char *) "MCBSP1") +#define MOD_MCBSP2 ((const char *) "MCBSP2") +#define MOD_MCBSP3 ((const char *) "MCBSP3") +#define MOD_MCPDM ((const char *) "MCPDM") +#define MOD_SLIMBUS1 ((const char *) "SLIMBUS1") +#define MOD_SLIMBUS2 ((const char *) "SLIMBUS2") + + + +#define MOD_CONTROL_GEN_WKUP ((const char *) "CONTROL_GEN_WKUP") +#define MOD_CONTROL_PADCONF_WKUP ((const char *) "CONTROL_PADCONF_WKUP") +#define MOD_CONTROL_GEN_CORE ((const char *) "CONTROL_GEN_CORE") +#define MOD_CONTROL_PADCONF_CORE ((const char *) "CONTROL_PADCONF_CORE") +#define MOD_SYNCTIMER ((const char *) "SYNCTIMER") +#define MOD_USIM ((const char *) "USIM") +#define MOD_WDT3 ((const char *) "WDT3") +#define MOD_IVAHD ((const char *) "IVAHD") +#define MOD_C2C_FW ((const char *) "C2C_FW") +#define MOD_MPU_ICR ((const char *) "MPU_ICR") +#define MOD_SDMA ((const char *) "SDMA") +#define MOD_MPU_M3 ((const char *) "MPU_M3") +#define MOD_OCP_WP1 ((const char *) "OCP_WP1") +#define MOD_EMIF_FW ((const char *) "EMIF_FW") +#define MOD_DLL ((const char *) "DLL") +#define MOD_DDRPHY ((const char *) "DDRPHY") +#define MOD_DISPC ((const char *) "DISPC") +#define MOD_FSUSBHOST ((const char *) "FSUSBHOST") +#define MOD_HSUSBOTG ((const char *) "HSUSBOTG") +#define MOD_USBPHY ((const char *) "USBPHY") +#define MOD_USBTLL ((const char *) "USBTLL") +#define MOD_P1500 ((const char *) "P1500") +#define MOD_MCBSP4 ((const char *) "MCBSP4") + + +typedef struct { + const char *name; /* Module Name */ + int id; /* Module ID (invalid if < 0) */ + const char *clkdm; /* Name of Clock Domain module is part of */ + const char *pwrdm; /* Name of Power Domain module is part of */ + const char *voltdm; /* Name of Voltage Domain module is part of */ + int clk; /* Functional Clock of the module (invalid if < 0) */ + reg *sysconfig; /* SYSCONFIG register of the module */ + reg *clkctrl; /* CLKCTRL register of the module */ + reg *context; /* CONTEXT register of the module */ + genlist mod_opp_list; /* List of OPP (as defined in opp.h) supported by the module */ + unsigned int properties; /* Module properties flags */ +} mod_info; + + +typedef struct { + const char *name; /* OPP Name */ + int rate; /* in KHz */ +} mod_opp; + + +void module_init(void); +void module_deinit(void); + +int module_count_get(void); +const genlist *module_list_get(void); + + +unsigned int module_has_sysconfig_register(const char *mod); +unsigned int module_has_autoidle_bit(const char *mod); +unsigned int module_has_idle_mode(const char *mod); +unsigned int module_has_idle_status(const char *mod); +unsigned int module_has_smart_idle_wakeup_mode(const char *mod); +unsigned int module_has_enawakeup_bit(const char *mod); +unsigned int module_has_standby_mode(const char *mod); +unsigned int module_has_standby_status(const char *mod); +unsigned int module_has_smart_standby_wakeup_mode(const char *mod); +unsigned int module_has_clock_activity_mode(const char *mod); + + +int module_id_get(const char *mod); +unsigned short int module_is_accessible(const char *mod); +mod_module_mode module_mode_get(const char *mod); +mod_autoidle_mode module_autoidle_mode_get(const char *mod); +mod_idle_mode module_idle_mode_get(const char *mod); +mod_idle_status module_idle_status_get(const char *mod); +mod_standby_mode module_standby_mode_get(const char *mod); +mod_standby_status module_standby_status_get(const char *mod); +mod_clock_activity_mode module_clock_activity_mode_get(const char *mod); +int module_context_is_lost(const char *mod); +int module_clk_get(const char *mod); +int module_clk_rate_get(const char *mod, unsigned short ignore); +int module_por_clk_rate_get(const char *mod, const char *opp); + +int module_status_show(FILE *stream); +int module_clk_rate_audit(FILE *stream, + unsigned int *err_nbr, unsigned int *wng_nbr); +int module_sysconfig_audit(FILE *stream, unsigned int *err_nbr, + unsigned int *wng_nbr); +int module_config_show(FILE *stream, const char *mod); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/powerdomain.c tiomapconf-1.61.1/arch/arm/mach-omap/common/powerdomain.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/powerdomain.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/powerdomain.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,692 @@ +/* + * + * @Component OMAPCONF + * @Filename powerdomain.c + * @Description OMAP Generic Power Domain Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define PWRDM_DEBUG */ +#ifdef PWRDM_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +static int _powerdm_info_get(const char *powerdm, powerdm_info *data); + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_init + * @BRIEF initialize internal data + * @DESCRIPTION initialize internal data (architecture dependent) + *//*------------------------------------------------------------------------ */ +void powerdm_init(void) +{ + #ifdef PWRDM_DEBUG + int i, count; + const genlist *pwrdm_list; + powerdm_info pwrdm; + #endif + + if (cpu_is_omap44xx()) { + pwrdm44xx_init(); + } else if (cpu_is_omap54xx()) { + pwrdm54xx_init(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } + + #ifdef PWRDM_DEBUG + pwrdm_list = powerdm_list_get(); + count = genlist_getcount((genlist *) pwrdm_list); + printf("Power Domain List:\n"); + for (i = 0; i < count; i++) { + genlist_get((genlist *) pwrdm_list, i, (powerdm_info *) &pwrdm); + printf(" %s:\n", pwrdm.name); + printf(" ID:%d\n", pwrdm.id); + printf(" VoltDM: %s\n", pwrdm.voltdm); + printf(" PWRSTCTRL REG: %s\n", (pwrdm.pwrstctrl)->name); + printf(" PWRSTST REG: %s\n", (pwrdm.pwrstst)->name); + printf(" Properties: %d\n", pwrdm.properties); + printf("\n\n"); + } + printf("Power Domain count: %d\n\n", count); + #endif +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_deinit + * @BRIEF free dynamically allocated internal data. + * @DESCRIPTION free dynamically allocated internal data. + * MUST BE CALLED AT END OF EXECUTION. + *//*------------------------------------------------------------------------ */ +void powerdm_deinit(void) +{ + if (cpu_is_omap44xx()) { + pwrdm44xx_deinit(); + } else if (cpu_is_omap54xx()) { + pwrdm54xx_deinit(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_list_get + * @BRIEF return the list of power domains + * @RETURNS list of power domains in case of success + * NULL in case of error + * @DESCRIPTION return the list of power domains + *//*------------------------------------------------------------------------ */ +const genlist *powerdm_list_get(void) +{ + if (cpu_is_omap44xx()) { + return pwrdm44xx_list_get(); + } else if (cpu_is_omap54xx()) { + return pwrdm54xx_list_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return NULL; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_count_get + * @BRIEF return the number of power domains + * @RETURNS number of power domains (> 0) in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @DESCRIPTION return the number of power domains + *//*------------------------------------------------------------------------ */ +int powerdm_count_get(void) +{ + if (cpu_is_omap44xx()) { + return pwrdm44xx_count_get(); + } else if (cpu_is_omap54xx()) { + return pwrdm54xx_count_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION _powerdm_info_get + * @BRIEF return the saved informations of a given power domain. + * @RETURNS 0 in case of success + * -1 in case of error + * @param[in] powerdm: power domain name + * @param[in,out] data: power domain details + * @DESCRIPTION return the saved informations of a given power domain. + *//*------------------------------------------------------------------------ */ +static int _powerdm_info_get(const char *powerdm, powerdm_info *data) +{ + const genlist *pwrdm_list; + int i, count; + + CHECK_NULL_ARG(powerdm, -1); + CHECK_NULL_ARG(data, -1); + + pwrdm_list = powerdm_list_get(); + count = genlist_getcount((genlist *) pwrdm_list); + for (i = 0; i < count; i++) { + genlist_get((genlist *) pwrdm_list, i, (void *) data); + if (strcmp(data->name, powerdm) == 0) { + dprintf("%s(%s): found.\n", __func__, powerdm); + return 0; + } + } + + dprintf("%s(%s): not found!\n", __func__, powerdm); + return -1; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_has_last_power_state + * @BRIEF return 1 if power domain has LASTPOWERSTATEENTERED + * @RETURNS 1 if power domain has a LASTPOWERSTATEENTERED bitfield. + * 0 if not available or in case of error. + * @param[in] powerdm: power domain name + * @DESCRIPTION return 1 if power domain has LASTPOWERSTATEENTERED + * in PM_xyz_PWRSTST register (not all power domains + * feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int powerdm_has_last_power_state(const char *powerdm) +{ + int ret; + powerdm_info data; + + CHECK_NULL_ARG(powerdm, 0); + + ret = _powerdm_info_get(powerdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve powerdm_info struct!\n", + __func__, powerdm); + return 0; + } + + if ((data.properties & PWRDM_HAS_LAST_STATE) != 0) { + dprintf("%s(%s): HAS LASTPOWERSTATEENTERED bitfield\n", + __func__, powerdm); + return 1; + } else { + dprintf( + "%s(%s): does NOT have LASTPOWERSTATEENTERED bitfield\n", + __func__, powerdm); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_has_logic_ret_state_ctrl_bit + * @BRIEF return 1 if power domain has LOGICRETSTATE bitfield + * @RETURNS 1 if power domain has a LOGICRETSTATE bitfield. + * 0 if not available or in case of error. + * @param[in] powerdm: power domain name + * @DESCRIPTION return 1 if power domain has LOGICRETSTATE bitfield + * in PM_xyz_PWRSTCTRL register (not all power domains + * feature it). + * Return 0 if not available or in case of error. + * Does not make any access to any register. + *//*------------------------------------------------------------------------ */ +unsigned int powerdm_has_logic_ret_state_ctrl_bit(const char *powerdm) +{ + int ret; + powerdm_info data; + + CHECK_NULL_ARG(powerdm, 0); + + ret = _powerdm_info_get(powerdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve powerdm_info struct!\n", + __func__, powerdm); + return 0; + } + + if ((data.properties & PWRDM_HAS_LOGIC_RET_STATE_CTRL_BIT) != 0) { + dprintf("%s(%s): HAS LOGICRETSTATE bitfield\n", + __func__, powerdm); + return 1; + } else { + dprintf("%s(%s): does NOT have LOGICRETSTATE bitfield\n", + __func__, powerdm); + return 0; + } +} + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_id_get + * @BRIEF return the unique ID of a given power domain. + * @RETURNS >= 0 power domain ID + * -1 in case of error + * @param[in] powerdm: power domain name + * @DESCRIPTION return the unique ID of a given power domain. + *//*------------------------------------------------------------------------ */ +int powerdm_id_get(const char *powerdm) +{ + int id; + powerdm_info data; + + CHECK_NULL_ARG(powerdm, -1); + + id = _powerdm_info_get(powerdm, &data); + if (id == 0) + id = data.id; + + dprintf("%s(%s) = %d\n", __func__, powerdm, id); + return id; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_voltdm_get + * @BRIEF return the voltage domain name a power domain is part of + * @RETURNS voltage domain name on success. + * NULL in case of error + * @param[in] powerdm: power domain name + * @DESCRIPTION return the voltage domain name a power domain is part of + *//*------------------------------------------------------------------------ */ +const char *powerdm_voltdm_get(const char *powerdm) +{ + int ret; + powerdm_info data; + + CHECK_NULL_ARG(powerdm, NULL); + + ret = _powerdm_info_get(powerdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve powerdm_info struct!\n", + __func__, powerdm); + return NULL; + } + + dprintf("%s(%s) = %s\n", __func__, powerdm, data.voltdm); + return data.voltdm; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_pwrstctrl_reg_get + * @BRIEF return the PWRSTCTRL register of a given power domain + * @RETURNS PWRSTCTRL register on success + * NULL in case of error + * @param[in] powerdm: power domain name + * @DESCRIPTION return the PWRSTCTRL register of a given power domain + *//*------------------------------------------------------------------------ */ +reg *powerdm_pwrstctrl_reg_get(const char *powerdm) +{ + int ret; + powerdm_info data; + + CHECK_NULL_ARG(powerdm, NULL); + + ret = _powerdm_info_get(powerdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve powerdm_info struct!\n", + __func__, powerdm); + return NULL; + } + + if (data.pwrstctrl != NULL) { + dprintf("%s(%s): PM_PWRSTCTRL=%s\n", __func__, + powerdm, reg_name_get(data.pwrstctrl)); + return data.pwrstctrl; + } else { + dprintf("%s(%s): PM_PWRSTCTRL==NULL\n", __func__, powerdm); + return NULL; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_pwrstst_reg_get + * @BRIEF return the PWRSTST register of a given power domain + * @RETURNS PWRSTST register on success + * NULL in case of error + * @param[in] powerdm: power domain name + * @DESCRIPTION return the PWRSTST register of a given power domain + *//*------------------------------------------------------------------------ */ +reg *powerdm_pwrstst_reg_get(const char *powerdm) +{ + int ret; + powerdm_info data; + + CHECK_NULL_ARG(powerdm, NULL); + + ret = _powerdm_info_get(powerdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve powerdm_info struct!\n", + __func__, powerdm); + return NULL; + } + + if (data.pwrstst != NULL) { + dprintf("%s(%s): PM_PWRSTST=%s\n", __func__, + powerdm, reg_name_get(data.pwrstst)); + return data.pwrstst; + } else { + dprintf("%s(%s): PM_PWRSTST==NULL\n", __func__, powerdm); + return NULL; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_target_logic_ret_state_get + * @BRIEF return the programmed target logic retention state + * of a given power domain + * @RETURNS programmed target logic retention state on success + * PWRDM_STATE_MAX in case of error + * @param[in] powerdm: power domain name + * @DESCRIPTION return the programmed target logic retention state + * of a given power domain + *//*------------------------------------------------------------------------ */ +pwrdm_state powerdm_target_logic_ret_state_get(const char *powerdm) +{ + reg *pm_pwrstctrl; + pwrdm_state state; + + CHECK_NULL_ARG(powerdm, PWRDM_STATE_MAX); + + if (!powerdm_has_logic_ret_state_ctrl_bit(powerdm)) { + dprintf("%s(%s): domain doesn't have RET state control bit.\n", + __func__, powerdm); + return PWRDM_STATE_MAX; + } + + pm_pwrstctrl = powerdm_pwrstctrl_reg_get(powerdm); + if (pm_pwrstctrl == NULL) { + dprintf("%s(%s): PM_PWRSTCTRL==NULL!\n", __func__, powerdm); + return PWRDM_STATE_MAX; + } + + state = pwrdm_target_logic_ret_state_get(pm_pwrstctrl); + dprintf("%s(%s) = %s\n", __func__, powerdm, + pwrdm_state_name_get(state)); + return state; +} + + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_logic_state_get + * @BRIEF return the current logic state of a given power domain + * @RETURNS current logic state on success + * PWRDM_STATE_MAX in case of error + * @param[in] powerdm: power domain name + * @DESCRIPTION return the current logic state of a given power domain + *//*------------------------------------------------------------------------ */ +pwrdm_state powerdm_logic_state_get(const char *powerdm) +{ + reg *pm_pwrstst; + pwrdm_state state; + + CHECK_NULL_ARG(powerdm, PWRDM_STATE_MAX); + + pm_pwrstst = powerdm_pwrstst_reg_get(powerdm); + if (pm_pwrstst == NULL) { + dprintf("%s(%s): PM_PWRSTST==NULL!\n", __func__, powerdm); + return PWRDM_STATE_MAX; + } + + state = pwrdm_logic_state_get(pm_pwrstst); + dprintf("%s(%s) = %s\n", __func__, powerdm, + pwrdm_state_name_get(state)); + return state; +} + + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_state_get + * @BRIEF return the previous/current/target state of + * a given power domain + * @RETURNS domain previous/current/target state on success + * PWRDM_STATE_MAX in case of error + * @param[in] powerdm: power domain name + * @param[in] type: power domain state type + * @DESCRIPTION return the previous/current/target state of + * a given power domain + *//*------------------------------------------------------------------------ */ +pwrdm_state powerdm_state_get(const char *powerdm, pwrdm_state_type type) +{ + reg *pm_reg; + pwrdm_state state; + + CHECK_NULL_ARG(powerdm, PWRDM_STATE_MAX); + CHECK_ARG_LESS_THAN(type, PWRDM_STATE_TYPE_MAX, PWRDM_STATE_MAX); + + /* Retrieve registers address */ + switch (type) { + case PWRDM_STATE_TARGET: + pm_reg = powerdm_pwrstctrl_reg_get(powerdm); + break; + case PWRDM_STATE_CURRENT: + case PWRDM_STATE_PREVIOUS: + pm_reg = powerdm_pwrstst_reg_get(powerdm); + break; + default: + fprintf(stderr, + "omapconf: %s(%s): invalid type (%d)!\n", + __func__, powerdm, type); + return PWRDM_STATE_MAX; + } + + if (pm_reg == NULL) { + /* Always ON domain */ + dprintf("%s(%s): Always ON domain\n", __func__, powerdm); + return PWRDM_ON_STATE; + } + + /* Retrieve power domain state */ + state = pwrdm_state_get(pm_reg, type); + dprintf("%s(%s, %s) = %s\n", __func__, powerdm, + pwrdm_state_type_name_get(type), + pwrdm_state_name_get(state)); + return state; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_in_transition + * @BRIEF return 1 if a power transition is ongoing + * on a given power domain + * @RETURNS 1 if a power transition is ongoing + * 0 if NO power transition is ongoing (or error) + * @param[in] powerdm: power domain name + * @DESCRIPTION return 1 if a power transition is ongoing + * on a given power domain + *//*------------------------------------------------------------------------ */ +unsigned int powerdm_in_transition(const char *powerdm) +{ + int in_transition; + reg *pm_pwrstst; + + CHECK_NULL_ARG(powerdm, 0); + + pm_pwrstst = powerdm_pwrstst_reg_get(powerdm); + if (pm_pwrstst == NULL) { + dprintf("%s(%s): PM_PWRSTST==NULL!\n", __func__, powerdm); + return 0; + } + + in_transition = pwrdm_in_transition(pm_pwrstst); + #ifdef PWRDM_DEBUG + if (in_transition) + printf("%s(%s): power transition ONGOING.\n", + __func__, powerdm); + else + printf("%s(%s): NO power transition ongoing.\n", + __func__, powerdm); + #endif + + return in_transition; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_config_show + * @BRIEF decode and display power domain configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in,out] stream: output file + * @param[in] powerdm: power domain name + * @DESCRIPTION decode and display power domain configuration + *//*------------------------------------------------------------------------ */ +int powerdm_config_show(FILE *stream, const char *powerdm) +{ + int ret; + powerdm_info data; + pwrdm_state st_last, st_curr, st_tgt; + reg *pm_pwrstctrl; + reg *pm_pwrstst; + char s[64]; + char s1[32], s2[32]; + + CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(powerdm, OMAPCONF_ERR_ARG); + + ret = _powerdm_info_get(powerdm, &data); + if (ret != 0) { + dprintf("%s(%s): could not retrieve powerdm_info struct!\n", + __func__, powerdm); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + fprintf(stream, + "|----------------------------------------------------------------|\n"); + strcpy(s, powerdm); + strcat(s, " Power Domain Configuration"); + fprintf(stream, "| %-62s |\n", s); + fprintf(stream, + "|----------------------------------------------------------------|\n"); + fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", "Power State", + "Current", "Target", "Last"); + fprintf(stream, + "|----------------------------------|---------|---------|---------|\n"); + + st_last = powerdm_state_get(powerdm, PWRDM_STATE_PREVIOUS); + st_curr = powerdm_state_get(powerdm, PWRDM_STATE_CURRENT); + st_tgt = powerdm_state_get(powerdm, PWRDM_STATE_TARGET); + fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", + "Domain", pwrdm_state_name_get(st_curr), + pwrdm_state_name_get(st_tgt), pwrdm_state_name_get(st_last)); + + if ((!powerdm_has_logic_ret_state_ctrl_bit(powerdm)) && + (data.pwrstst == NULL)) + goto powerdm_config_show_mem; + + st_tgt = powerdm_target_logic_ret_state_get(powerdm); + if (st_tgt != PWRDM_STATE_MAX) + strcpy(s1, pwrdm_state_name_get(st_tgt)); + else + strcpy(s1, ""); + st_curr = powerdm_logic_state_get(powerdm); + if (st_curr != PWRDM_STATE_MAX) + strcpy(s2, pwrdm_state_name_get(st_curr)); + else + strcpy(s2, ""); + fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Logic", s2, s1); + +powerdm_config_show_mem: + if (cpu_is_omap44xx()) { + pm_pwrstctrl = powerdm_pwrstctrl_reg_get(powerdm); + pm_pwrstst = powerdm_pwrstst_reg_get(powerdm); + ret = pwrdm44xx_config_show(stream, powerdm, + reg_addr_get(pm_pwrstctrl), + reg_read(pm_pwrstctrl), + reg_addr_get(pm_pwrstst), + reg_read(pm_pwrstst)); + } else if (cpu_is_omap54xx()) { + ret = pwrdm54xx_config_show(stream, data); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + ret = OMAPCONF_ERR_CPU; + } + + if (data.pwrstst != NULL) { + fprintf(stream, + "|----------------------------------------------------------------|\n"); + + fprintf(stream, "| %-32s | %-27s |\n", + "Ongoing Power Transition?", + ((powerdm_in_transition(powerdm) == 1) ? "YES" : "NO")); + } + fprintf(stream, + "|----------------------------------------------------------------|\n\n"); + + return ret; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_emu_enable + * @BRIEF Power ON EMU domain and clocks. + * @DESCRIPTION Power ON EMU domain and clocks. + *//*------------------------------------------------------------------------ */ +void powerdm_emu_enable(void) +{ + if (cpu_is_omap44xx()) { + mem_write(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 0x1); + } else if (cpu_is_omap54xx()) { + if (cpu_revision_get() == REV_ES1_0) + mem_write(OMAP5430ES1_CM_L3INSTR_L3_MAIN_3_CLKCTRL, + 0x1); + else + mem_write(OMAP5430_CM_L3INSTR_L3_MAIN_3_CLKCTRL, 0x1); + } else { + fprintf(stderr, + "omapconf: %s(): warning: cpu not supported, skipping it.\n", + __func__); + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION powerdm_emu_disable + * @BRIEF Power OFF EMU domain and clocks. + * @DESCRIPTION Power OFF EMU domain and clocks. + *//*------------------------------------------------------------------------ */ +void powerdm_emu_disable(void) +{ + if (cpu_is_omap44xx()) { + mem_write(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 0); + } else if (cpu_is_omap54xx()) { + if (cpu_revision_get() == REV_ES1_0) + mem_write(OMAP5430ES1_CM_L3INSTR_L3_MAIN_3_CLKCTRL, + 0x0); + else + mem_write(OMAP5430_CM_L3INSTR_L3_MAIN_3_CLKCTRL, 0x0); + } else { + fprintf(stderr, + "omapconf: %s(): warning: cpu not supported, skipping it.\n", + __func__); + } +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/powerdomain.h tiomapconf-1.61.1/arch/arm/mach-omap/common/powerdomain.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/powerdomain.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/powerdomain.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,111 @@ +/* + * + * @Component OMAPCONF + * @Filename powerdomain.h + * @Description OMAP Generic Power Domain Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __POWERDOMAIN_H__ +#define __POWERDOMAIN_H__ + + +#include +#include +#include +#include + + +#define PWRDM_MAX_NAME_LENGTH 16 + + +#define PWRDM_EMU ((const char *) "EMU") +#define PWRDM_WKUPAON ((const char *) "WKUPAON") +#define PWRDM_COREAON ((const char *) "COREAON") +#define PWRDM_CAM ((const char *) "CAM") +#define PWRDM_CORE ((const char *) "CORE") +#define PWRDM_DSS ((const char *) "DSS") +#define PWRDM_CUST_EFUSE ((const char *) "CUSTEFUSE") +#define PWRDM_L3_INIT ((const char *) "L3INIT") +#define PWRDM_L4_PER ((const char *) "L4PER") +#define PWRDM_ABE ((const char *) "ABE") +#define PWRDM_DSP ((const char *) "DSP") +#define PWRDM_GPU ((const char *) "GPU") +#define PWRDM_MMAON ((const char *) "MMAON") +#define PWRDM_IVA ((const char *) "IVA") +#define PWRDM_MPUAON ((const char *) "MPUAON") +#define PWRDM_MPU ((const char *) "MPU") +#define PWRDM_UNKNOWN ((const char *) "UNKNOWN") + + +typedef struct { + const char *name; + int id; + const char *voltdm; + reg *pwrstctrl; + reg *pwrstst; + int properties; +} powerdm_info; + + +void powerdm_init(void); +void powerdm_deinit(void); + +int powerdm_count_get(void); +const genlist *powerdm_list_get(void); + +int powerdm_id_get(const char *powerdm); +const char *powerdm_voltdm_get(const char *powerdm); +reg *powerdm_pwrstctrl_reg_get(const char *powerdm); +reg *powerdm_pwrstst_reg_get(const char *powerdm); +unsigned int powerdm_has_logic_ret_state_ctrl_bit(const char *powerdm); +pwrdm_state powerdm_target_logic_ret_state_get(const char *powerdm); +pwrdm_state powerdm_logic_state_get(const char *powerdm); +unsigned int powerdm_has_last_power_state(const char *powerdm); +pwrdm_state powerdm_state_get(const char *powerdm, pwrdm_state_type type); +unsigned int powerdm_in_transition(const char *powerdm); + +int powerdm_config_show(FILE *stream, const char *powerdm); + + +void powerdm_emu_enable(void); +void powerdm_emu_disable(void); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/abb.c tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/abb.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/abb.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/abb.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,307 @@ +/* + * + * @Component OMAPCONF + * @Filename abb.c + * @Description PRCM ABB Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include + + +/* #define ABB_DEBUG */ +#ifdef ABB_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION abb_status2string + * @BRIEF convert bitfield value from register into string + * @RETURNS 0 on success + * OMAPCONF_ERR_ARG + * @param[in,out] s: destination string (pre-allocated) + * @param[in] status: bitfield value + * @DESCRIPTION convert bitfield value from register into string + *//*------------------------------------------------------------------------ */ +int abb_status2string(char s[9], unsigned int status) +{ + if (s == NULL) + return OMAPCONF_ERR_ARG; + + switch (status) { + case 0: + strcpy(s, "Bypass"); + break; + case 1: + strcpy(s, "RBB"); + break; + case 2: + strcpy(s, "FBB"); + break; + case 3: + strcpy(s, "Reserved"); + break; + default: + return OMAPCONF_ERR_ARG; + } + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION abb_opp_sel2string + * @BRIEF convert bitfield value from register into string + * @RETURNS 0 on success + * OMAPCONF_ERR_ARG + * @param[in,out] s: destination string (pre-allocated) + * @param[in] opp_sel: bitfield value + * @DESCRIPTION convert bitfield value from register into string + *//*------------------------------------------------------------------------ */ +int abb_opp_sel2string(char s[8], unsigned int opp_sel) +{ + if (s == NULL) + return OMAPCONF_ERR_ARG; + + switch (opp_sel) { + case 0: + case 2: + strcpy(s, "Nominal"); + break; + case 1: + strcpy(s, "Fast"); + break; + case 3: + strcpy(s, "Slow"); + break; + default: + return OMAPCONF_ERR_ARG; + } + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION abb_config_show + * @BRIEF analyze power configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * @param[in,out] stream: output file + * @param[in] sysclk_rate: system_clock rate (MHz) + * @param[in] abb_mpu_setup: PRM_LDO_ABB_MPU_SETUP register content + * @param[in] abb_mpu_ctrl: PRM_LDO_ABB_MPU_CTRL register content + * @param[in] abb_iva_setup: PRM_LDO_ABB_IVA_SETUP register content + * @param[in] abb_iva_ctrl: PRM_LDO_ABB_IVA_CTRL register content + * @DESCRIPTION analyze power configuration + *//*------------------------------------------------------------------------ */ +int abb_config_show(FILE *stream, double sysclk_rate, + unsigned int abb_mpu_setup, unsigned int abb_mpu_ctrl, + unsigned int abb_iva_setup, unsigned int abb_iva_ctrl) +{ + unsigned short int abb_mpu_en, abb_iva_en; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row = 0; + char s[9]; + + CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG); + if (sysclk_rate <= 0.0) { + fprintf(stderr, "%s(): sysclk_rate (%lf) <= 0!!!\n", __func__, + sysclk_rate); + return OMAPCONF_ERR_ARG; + } + + dprintf("%s(): sysclk_rate=%lfMHz abb_mpu_setup=0x%08X, " + "abb_mpu_ctrl=0x%08X, abb_iva_setup=0x%08X, " + "abb_iva_ctrl=0x%08X\n", sysclk_rate, + abb_mpu_setup, abb_mpu_ctrl, abb_iva_setup, abb_iva_ctrl); + + abb_mpu_en = extract_bit(abb_mpu_setup, 0); + abb_iva_en = extract_bit(abb_iva_setup, 0); + + autoadjust_table_init(table); + row = 0; + + strncpy(table[row][0], "ABB Configuration", TABLE_MAX_ELT_LEN); + strncpy(table[row][1], "MPU Voltage Domain", TABLE_MAX_ELT_LEN); + if (cpu_is_omap44xx()) + strncpy(table[row][2], "IVAHD Voltage Domain", + TABLE_MAX_ELT_LEN); + else + strncpy(table[row][2], "MM Voltage Domain", + TABLE_MAX_ELT_LEN); + + row++; + + strncpy(table[row][0], "Mode", TABLE_MAX_ELT_LEN); + strncpy(table[row][1], + ((abb_mpu_en == 1) ? "Enabled" : "Disabled"), + TABLE_MAX_ELT_LEN); + strncpy(table[row][2], + ((abb_iva_en == 1) ? "Enabled" : "Disabled"), + TABLE_MAX_ELT_LEN); + row++; + + strncpy(table[row][0], "Status", TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) { + abb_status2string(s, + extract_bitfield(abb_mpu_ctrl, 3, 2)); + strncpy(table[row][1], + s, + TABLE_MAX_ELT_LEN); + } + if (abb_iva_en == 1) { + abb_status2string(s, + extract_bitfield(abb_iva_ctrl, 3, 2)); + strncpy(table[row][2], + s, + TABLE_MAX_ELT_LEN); + } + row++; + + strncpy(table[row][0], "In Transition?", TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) + strncpy(table[row][1], + ((extract_bit(abb_mpu_ctrl, 6) == 1) ? "YES" : "No"), + TABLE_MAX_ELT_LEN); + if (abb_iva_en == 1) + strncpy(table[row][2], + ((extract_bit(abb_iva_ctrl, 6) == 1) ? "YES" : "No"), + TABLE_MAX_ELT_LEN); + row++; + + strncpy(table[row][0], "Selected OPP", TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) { + abb_opp_sel2string(s, + extract_bitfield(abb_mpu_ctrl, 0, 2)); + strncpy(table[row][1], + s, + TABLE_MAX_ELT_LEN); + } + if (abb_iva_en == 1) { + abb_opp_sel2string(s, + extract_bitfield(abb_iva_ctrl, 0, 2)); + strncpy(table[row][2], + s, + TABLE_MAX_ELT_LEN); + } + row++; + + strncpy(table[row][0], "LDO ABB Mode When Voltage is:", + TABLE_MAX_ELT_LEN); + row++; + strncpy(table[row][0], " Slow OPP (ACTIVE_RBB_SEL)", + TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) + strncpy(table[row][1], + ((extract_bit(abb_mpu_setup, + 1) == 1) ? "RBB" : "Bypass"), + TABLE_MAX_ELT_LEN); + if (abb_iva_en == 1) + strncpy(table[row][2], + ((extract_bit(abb_iva_setup, + 1) == 1) ? "RBB" : "Bypass"), + TABLE_MAX_ELT_LEN); + row++; + + strncpy(table[row][0], " Fast OPP (ACTIVE_FBB_SEL)", + TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) + strncpy(table[row][1], + ((extract_bit(abb_mpu_setup, + 2) == 1) ? "FBB" : "Bypass"), + TABLE_MAX_ELT_LEN); + if (abb_iva_en == 1) + strncpy(table[row][2], + ((extract_bit(abb_iva_setup, + 2) == 1) ? "FBB" : "Bypass"), + TABLE_MAX_ELT_LEN); + row++; + + strncpy(table[row][0], " Sleep Volt. (SLEEP_RBB_SEL)", + TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) + strncpy(table[row][1], + ((extract_bit(abb_mpu_setup, + 3) == 1) ? "RBB" : "Bypass"), + TABLE_MAX_ELT_LEN); + if (abb_iva_en == 1) + strncpy(table[row][2], + ((extract_bit(abb_iva_setup, + 3) == 1) ? "RBB" : "Bypass"), + TABLE_MAX_ELT_LEN); + row++; + strncpy(table[row][0], "LDO Settling Time", TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%d (%fus)", + extract_bitfield(abb_mpu_setup, 8, 8), + extract_bitfield(abb_mpu_setup, 8, 8) * + (16.0 / sysclk_rate)); + if (abb_iva_en == 1) + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%d (%fus)", + extract_bitfield(abb_iva_setup, 8, 8), + extract_bitfield(abb_iva_setup, 8, 8) * + (16.0 / sysclk_rate)); + row++; + strncpy(table[row][0], " (Target is 50us)", TABLE_MAX_ELT_LEN); + row++; + + strncpy(table[row][0], "Stat", TABLE_MAX_ELT_LEN); + if (abb_mpu_en == 1) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%d (%.3fus)", + extract_bitfield(abb_mpu_setup, 8, 8), + extract_bitfield(abb_mpu_setup, 8, 8) * + (16.0 / sysclk_rate)); + if (abb_iva_en == 1) + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%d (%.3fus)", + extract_bitfield(abb_iva_setup, 8, 8), + extract_bitfield(abb_iva_setup, 8, 8) * + (16.0 / sysclk_rate)); + + autoadjust_table_print(table, row, 3); + + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/abb.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/abb.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/abb.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/abb.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,57 @@ +/* + * + * @Component OMAPCONF + * @Filename abb.h + * @Description PRCM ABB Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __PRCM_ABB_H__ +#define __PRCM_ABB_H__ + + +#include + + +int abb_config_show(FILE *stream, double sysclk_rate, + unsigned int abb_mpu_setup, unsigned int abb_mpu_ctrl, + unsigned int abb_iva_setup, unsigned int abb_iva_ctrl); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm.c tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,150 @@ +/* + * + * @Component OMAPCONF + * @Filename clkdm.c + * @Description Clock Domain Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include + + +/* #define PRCM_CLKDM_DEBUG */ +#ifdef PRCM_CLKDM_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +static const char + clkdm_ctrl_mode_names[CLKM_CTRL_MODE_MAX][CLKDM_CTRL_MODE_MAX_NAME_LENGTH] = { + "NO SLEEP", + "SW-Forced Sleep", + "SW-Forced Wakeup", + "HW-Auto"}; + + +static const char + clkdm_status_names[CLKDM_STATUS_MAX][CLKDM_STATUS_MAX_NAME_LENGTH] = { + "Gated", + "Running"}; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkdm_ctrl_mode_name_get + * @BRIEF return clock domain transition control mode name + * @RETURNS clock domain transition control mode name on success + * "FIXME" in case of error + * @param[in] mode: valid clock domain transition control mode + * @DESCRIPTION return clock domain transition control mode name + *//*------------------------------------------------------------------------ */ +const char *clkdm_ctrl_mode_name_get(clkdm_ctrl_mode mode) +{ + CHECK_ARG_LESS_THAN(mode, CLKM_CTRL_MODE_MAX, "FIXME"); + + return clkdm_ctrl_mode_names[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkdm_ctrl_mode_get + * @BRIEF return clock domain transition control mode + * @RETURNS clock domain transition control mode on success + * CLKM_CTRL_MODE_MAX in case of error + * @param[in] cm_clkstctrl: CM_xyz_CLKSTCTRL register content + * @DESCRIPTION return clock domain transition control mode + *//*------------------------------------------------------------------------ */ +clkdm_ctrl_mode clkdm_ctrl_mode_get(unsigned int cm_clkstctrl) +{ + clkdm_ctrl_mode mode; + + /* Retrieve clock domain transition control mode */ + mode = (clkdm_ctrl_mode) extract_bitfield(cm_clkstctrl, 0, 2); + dprintf("%s(): cm_clkstctrl=0x%08X => mode=%u (%s) (bit [1-0])\n", + __func__, cm_clkstctrl, mode, clkdm_ctrl_mode_name_get(mode)); + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkdm_status_name_get + * @BRIEF return clock domain status name + * @RETURNS clock domain status name on success + * "FIXME" in case of error + * @param[in] st: valid clock domain status + * @DESCRIPTION return clock domain status name + *//*------------------------------------------------------------------------ */ +const char *clkdm_status_name_get(clkdm_status st) +{ + CHECK_ARG_LESS_THAN(st, CLKDM_STATUS_MAX, "FIXME"); + + return clkdm_status_names[st]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkdm_status_get + * @BRIEF return clock domain status + * @RETURNS clock domain status on success + * CLKDM_STATUS_MAX in case of error + * @param[in] cm_clkstctrl: CM_xyz_CLKSTCTRL register content + * @DESCRIPTION return clock domain status + *//*------------------------------------------------------------------------ */ +clkdm_status clkdm_status_get(unsigned int cm_clkstctrl) +{ + clkdm_status clkdmst; + unsigned int val; + + /* Retrieve clock domain status */ + val = extract_bitfield(cm_clkstctrl, 8, 24); + if (val == 0) + clkdmst = CLKDM_GATED; + else + clkdmst = CLKDM_RUNNING; + dprintf("%s(): cm_clkstctrl=0x%08X => clkst=%u (%s) (bits [31-8])\n", + __func__, cm_clkstctrl, clkdmst, + clkdm_status_name_get(clkdmst)); + + return clkdmst; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,75 @@ +/* + * + * @Component OMAPCONF + * @Filename clkdm.h + * @Description Clock Domain Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __PRCM_CLKDM_H__ +#define __PRCM_CLKDM_H__ + + +#define CLKDM_CTRL_MODE_MAX_NAME_LENGTH 24 +#define CLKDM_STATUS_MAX_NAME_LENGTH 8 + + +typedef enum { + CLKM_NO_SLEEP_MODE = 0, + CLKM_SW_SLEEP_MODE = 1, + CLKM_SW_WKUP_MODE = 2, + CLKM_HW_AUTO_MODE = 3, + CLKM_CTRL_MODE_MAX +} clkdm_ctrl_mode; + + +typedef enum { + CLKDM_GATED = 0, + CLKDM_RUNNING = 1, + CLKDM_STATUS_MAX +} clkdm_status; + + +clkdm_status clkdm_status_get(unsigned int cm_clkstctrl); +const char *clkdm_status_name_get(clkdm_status st); +clkdm_ctrl_mode clkdm_ctrl_mode_get(unsigned int cm_clkstctrl); +const char *clkdm_ctrl_mode_name_get(clkdm_ctrl_mode mode); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm_dependency.c tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm_dependency.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm_dependency.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm_dependency.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,114 @@ +/* + * + * @Component OMAPCONF + * @Filename clkdm_dependency.c + * @Description Clock Domain Dependencies Common Definitions & + * Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include + + +static const char + clkdmdep_type_names_table[CLKDMDEP_TYPE_MAX][CLKDMDEP_TYPE_MAX_NAME_LENGTH] = { + "Static", + "Dynamic"}; + + +static const char + clkdmdep_ctrl_type_names_table[CLKDMDEP_CONTROL_TYPE_MAX][CLKDMDEP_CTRL_TYPE_MAX_NAME_LENGTH] = { + "NA", + "R/W", + "RO"}; + + +static const char + clkdmdep_status_names_table[CLKDMDEP_STATUS_MAX][CLKDMDEP_STATUS_MAX_NAME_LENGTH] = { + "Disabled", + "Enabled"}; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkdmdep_type_name_get + * @BRIEF return type name + * @RETURNS name on success + * NULL in case of error + * @param[in] type: dependency type (static/dynamic) + * @DESCRIPTION return type name + *//*------------------------------------------------------------------------ */ +const char *clkdmdep_type_name_get(clkdmdep_type type) +{ + CHECK_ARG_LESS_THAN(type, CLKDMDEP_TYPE_MAX, NULL); + + return clkdmdep_type_names_table[type]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkdmdep_ctrl_type_name_get + * @BRIEF return control type name + * @RETURNS name on success + * NULL in case of error + * @param[in] type: dependency control type (RW/RO/...) + * @DESCRIPTION return control type name + *//*------------------------------------------------------------------------ */ +const char *clkdmdep_ctrl_type_name_get(clkdmdep_ctrl_type type) +{ + CHECK_ARG_LESS_THAN(type, CLKDMDEP_CONTROL_TYPE_MAX, NULL); + + return clkdmdep_ctrl_type_names_table[type]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkdmdep_status_name_get + * @BRIEF return status name + * @RETURNS name on success + * NULL in case of error + * @param[in] st: status (en/dis) + * @DESCRIPTION return status name + *//*------------------------------------------------------------------------ */ +const char *clkdmdep_status_name_get(clkdmdep_status st) +{ + CHECK_ARG_LESS_THAN(st, CLKDMDEP_STATUS_MAX, NULL); + + return clkdmdep_status_names_table[st]; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm_dependency.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm_dependency.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/clkdm_dependency.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/clkdm_dependency.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,86 @@ +/* + * + * @Component OMAPCONF + * @Filename clkdm_dependency.h + * @Description Clock Domain Dependencies Common Definitions & + * Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __PRCM_CLKDM_DEPENDENCY_H__ +#define __PRCM_CLKDM_DEPENDENCY_H__ + + +#include + + +#define CLKDMDEP_TYPE_MAX_NAME_LENGTH 8 +#define CLKDMDEP_CTRL_TYPE_MAX_NAME_LENGTH 4 +#define CLKDMDEP_STATUS_MAX_NAME_LENGTH 9 + + +typedef enum { + CLKDMDEP_STATIC, + CLKDMDEP_DYNAMIC, + CLKDMDEP_TYPE_MAX +} clkdmdep_type; + + +typedef enum { + CLKDMDEP_NA, /* not available, does not exist */ + CLKDMDEP_RW, /* available, SW-configurable */ + CLKDMDEP_RO, /* available, not configurable (hard-coded) */ + CLKDMDEP_CONTROL_TYPE_MAX +} clkdmdep_ctrl_type; + + +typedef enum { + CLKDMDEP_DIS, /* dependency is disabled */ + CLKDMDEP_EN, /* dependency is enabled */ + CLKDMDEP_STATUS_MAX +} clkdmdep_status; + + + +const char *clkdmdep_type_name_get(clkdmdep_type type); +const char *clkdmdep_ctrl_type_name_get(clkdmdep_ctrl_type type); +const char *clkdmdep_status_name_get(clkdmdep_status st); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/prcm-common.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/prcm-common.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/prcm-common.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/prcm-common.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,473 @@ +/* ======================================================================= *//** + * @Component OMAPCONF + * @Filename prcm-common.h + * @Description OMAP2/3 PRCM base and module definitions + * @Copyright GPL version 2 + *//*======================================================================== */ +/* + * OMAP2/3 PRCM base and module definitions + * + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation + * + * Written by Paul Walmsley + * OMAP4 defines in this file are automatically generated from the OMAP hardware + * databases. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H +#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H + +/* Module offsets from both CM_BASE & PRM_BASE */ + +/* + * Offsets that are the same on 24xx and 34xx + * + * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is + * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. + */ +#define OCP_MOD 0x000 +#define MPU_MOD 0x100 +#define CORE_MOD 0x200 +#define GFX_MOD 0x300 +#define WKUP_MOD 0x400 +#define PLL_MOD 0x500 + + +/* Chip-specific module offsets */ +#define OMAP24XX_GR_MOD OCP_MOD +#define OMAP24XX_DSP_MOD 0x800 + +#define OMAP2430_MDM_MOD 0xc00 + +/* IVA2 module is < base on 3430 */ +#define OMAP3430_IVA2_MOD -0x800 +#define OMAP3430ES2_GFX_MOD GFX_MOD +#define OMAP3430_CCR_MOD PLL_MOD +#define OMAP3430_DSS_MOD 0x600 +#define OMAP3430_CAM_MOD 0x700 +#define OMAP3430_PER_MOD 0x800 +#define OMAP3430_EMU_MOD 0x900 +#define OMAP3430_GR_MOD 0xa00 +#define OMAP3430_NEON_MOD 0xb00 +#define OMAP3430ES2_USBHOST_MOD 0xc00 + +#define BITS(n_bit) \ + (((1 << n_bit) - 1) | (1 << n_bit)) + +#define BITFIELD(l_bit, u_bit) \ + (BITS(u_bit) & ~((BITS(l_bit)) >> 1)) + +/* OMAP44XX specific module offsets */ + +/* CM1 instances */ + +#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000 +#define OMAP4430_CM1_CKGEN_MOD 0x0100 +#define OMAP4430_CM1_MPU_MOD 0x0300 +#define OMAP4430_CM1_DSP_MOD 0x0400 +#define OMAP4430_CM1_ABE_MOD 0x0500 +#define OMAP4430_CM1_RESTORE_MOD 0x0e00 +#define OMAP4430_CM1_INSTR_MOD 0x0f00 + +/* CM2 instances */ + +#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000 +#define OMAP4430_CM2_CKGEN_MOD 0x0100 +#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600 +#define OMAP4430_CM2_CORE_MOD 0x0700 +#define OMAP4430_CM2_IVAHD_MOD 0x0f00 +#define OMAP4430_CM2_CAM_MOD 0x1000 +#define OMAP4430_CM2_DSS_MOD 0x1100 +#define OMAP4430_CM2_GFX_MOD 0x1200 +#define OMAP4430_CM2_L3INIT_MOD 0x1300 +#define OMAP4430_CM2_L4PER_MOD 0x1400 +#define OMAP4430_CM2_CEFUSE_MOD 0x1600 +#define OMAP4430_CM2_RESTORE_MOD 0x1e00 +#define OMAP4430_CM2_INSTR_MOD 0x1f00 + +/* PRM instances */ + +#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 +#define OMAP4430_PRM_CKGEN_MOD 0x0100 +#define OMAP4430_PRM_MPU_MOD 0x0300 +#define OMAP4430_PRM_DSP_MOD 0x0400 +#define OMAP4430_PRM_ABE_MOD 0x0500 +#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 +#define OMAP4430_PRM_CORE_MOD 0x0700 +#define OMAP4430_PRM_IVAHD_MOD 0x0f00 +#define OMAP4430_PRM_CAM_MOD 0x1000 +#define OMAP4430_PRM_DSS_MOD 0x1100 +#define OMAP4430_PRM_GFX_MOD 0x1200 +#define OMAP4430_PRM_L3INIT_MOD 0x1300 +#define OMAP4430_PRM_L4PER_MOD 0x1400 +#define OMAP4430_PRM_CEFUSE_MOD 0x1600 +#define OMAP4430_PRM_WKUP_MOD 0x1700 +#define OMAP4430_PRM_WKUP_CM_MOD 0x1800 +#define OMAP4430_PRM_EMU_MOD 0x1900 +#define OMAP4430_PRM_EMU_CM_MOD 0x1a00 +#define OMAP4430_PRM_DEVICE_MOD 0x1b00 +#define OMAP4430_PRM_INSTR_MOD 0x1f00 + +/* SCRM instances */ + +#define OMAP4430_SCRM_SCRM_MOD 0x0000 + +/* CHIRONSS instances */ + +#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000 +#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200 +#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 +#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 + +/* Base Addresses for the OMAP4 */ + +#define OMAP4430_CM1_BASE 0x4a004000 +#define OMAP4430_CM2_BASE 0x4a008000 +#define OMAP4430_PRM_BASE 0x4a306000 +#define OMAP4430_SCRM_BASE 0x4a30a000 +#define OMAP4430_CHIRONSS_BASE 0x48243000 + + +/* 24XX register bits shared between CM & PRM registers */ + +/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ +#define OMAP2420_EN_MMC_SHIFT 26 +#define OMAP2420_EN_MMC (1 << 26) +#define OMAP24XX_EN_UART2_SHIFT 22 +#define OMAP24XX_EN_UART2 (1 << 22) +#define OMAP24XX_EN_UART1_SHIFT 21 +#define OMAP24XX_EN_UART1 (1 << 21) +#define OMAP24XX_EN_MCSPI2_SHIFT 18 +#define OMAP24XX_EN_MCSPI2 (1 << 18) +#define OMAP24XX_EN_MCSPI1_SHIFT 17 +#define OMAP24XX_EN_MCSPI1 (1 << 17) +#define OMAP24XX_EN_MCBSP2_SHIFT 16 +#define OMAP24XX_EN_MCBSP2 (1 << 16) +#define OMAP24XX_EN_MCBSP1_SHIFT 15 +#define OMAP24XX_EN_MCBSP1 (1 << 15) +#define OMAP24XX_EN_GPT12_SHIFT 14 +#define OMAP24XX_EN_GPT12 (1 << 14) +#define OMAP24XX_EN_GPT11_SHIFT 13 +#define OMAP24XX_EN_GPT11 (1 << 13) +#define OMAP24XX_EN_GPT10_SHIFT 12 +#define OMAP24XX_EN_GPT10 (1 << 12) +#define OMAP24XX_EN_GPT9_SHIFT 11 +#define OMAP24XX_EN_GPT9 (1 << 11) +#define OMAP24XX_EN_GPT8_SHIFT 10 +#define OMAP24XX_EN_GPT8 (1 << 10) +#define OMAP24XX_EN_GPT7_SHIFT 9 +#define OMAP24XX_EN_GPT7 (1 << 9) +#define OMAP24XX_EN_GPT6_SHIFT 8 +#define OMAP24XX_EN_GPT6 (1 << 8) +#define OMAP24XX_EN_GPT5_SHIFT 7 +#define OMAP24XX_EN_GPT5 (1 << 7) +#define OMAP24XX_EN_GPT4_SHIFT 6 +#define OMAP24XX_EN_GPT4 (1 << 6) +#define OMAP24XX_EN_GPT3_SHIFT 5 +#define OMAP24XX_EN_GPT3 (1 << 5) +#define OMAP24XX_EN_GPT2_SHIFT 4 +#define OMAP24XX_EN_GPT2 (1 << 4) +#define OMAP2420_EN_VLYNQ_SHIFT 3 +#define OMAP2420_EN_VLYNQ (1 << 3) + +/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ +#define OMAP2430_EN_GPIO5_SHIFT 10 +#define OMAP2430_EN_GPIO5 (1 << 10) +#define OMAP2430_EN_MCSPI3_SHIFT 9 +#define OMAP2430_EN_MCSPI3 (1 << 9) +#define OMAP2430_EN_MMCHS2_SHIFT 8 +#define OMAP2430_EN_MMCHS2 (1 << 8) +#define OMAP2430_EN_MMCHS1_SHIFT 7 +#define OMAP2430_EN_MMCHS1 (1 << 7) +#define OMAP24XX_EN_UART3_SHIFT 2 +#define OMAP24XX_EN_UART3 (1 << 2) +#define OMAP24XX_EN_USB_SHIFT 0 +#define OMAP24XX_EN_USB (1 << 0) + +/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ +#define OMAP2430_EN_MDM_INTC_SHIFT 11 +#define OMAP2430_EN_MDM_INTC (1 << 11) +#define OMAP2430_EN_USBHS_SHIFT 6 +#define OMAP2430_EN_USBHS (1 << 6) + +/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ +#define OMAP2420_ST_MMC_SHIFT 26 +#define OMAP2420_ST_MMC_MASK (1 << 26) +#define OMAP24XX_ST_UART2_SHIFT 22 +#define OMAP24XX_ST_UART2_MASK (1 << 22) +#define OMAP24XX_ST_UART1_SHIFT 21 +#define OMAP24XX_ST_UART1_MASK (1 << 21) +#define OMAP24XX_ST_MCSPI2_SHIFT 18 +#define OMAP24XX_ST_MCSPI2_MASK (1 << 18) +#define OMAP24XX_ST_MCSPI1_SHIFT 17 +#define OMAP24XX_ST_MCSPI1_MASK (1 << 17) +#define OMAP24XX_ST_GPT12_SHIFT 14 +#define OMAP24XX_ST_GPT12_MASK (1 << 14) +#define OMAP24XX_ST_GPT11_SHIFT 13 +#define OMAP24XX_ST_GPT11_MASK (1 << 13) +#define OMAP24XX_ST_GPT10_SHIFT 12 +#define OMAP24XX_ST_GPT10_MASK (1 << 12) +#define OMAP24XX_ST_GPT9_SHIFT 11 +#define OMAP24XX_ST_GPT9_MASK (1 << 11) +#define OMAP24XX_ST_GPT8_SHIFT 10 +#define OMAP24XX_ST_GPT8_MASK (1 << 10) +#define OMAP24XX_ST_GPT7_SHIFT 9 +#define OMAP24XX_ST_GPT7_MASK (1 << 9) +#define OMAP24XX_ST_GPT6_SHIFT 8 +#define OMAP24XX_ST_GPT6_MASK (1 << 8) +#define OMAP24XX_ST_GPT5_SHIFT 7 +#define OMAP24XX_ST_GPT5_MASK (1 << 7) +#define OMAP24XX_ST_GPT4_SHIFT 6 +#define OMAP24XX_ST_GPT4_MASK (1 << 6) +#define OMAP24XX_ST_GPT3_SHIFT 5 +#define OMAP24XX_ST_GPT3_MASK (1 << 5) +#define OMAP24XX_ST_GPT2_SHIFT 4 +#define OMAP24XX_ST_GPT2_MASK (1 << 4) +#define OMAP2420_ST_VLYNQ_SHIFT 3 +#define OMAP2420_ST_VLYNQ_MASK (1 << 3) + +/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ +#define OMAP2430_ST_MDM_INTC_SHIFT 11 +#define OMAP2430_ST_MDM_INTC_MASK (1 << 11) +#define OMAP2430_ST_GPIO5_SHIFT 10 +#define OMAP2430_ST_GPIO5_MASK (1 << 10) +#define OMAP2430_ST_MCSPI3_SHIFT 9 +#define OMAP2430_ST_MCSPI3_MASK (1 << 9) +#define OMAP2430_ST_MMCHS2_SHIFT 8 +#define OMAP2430_ST_MMCHS2_MASK (1 << 8) +#define OMAP2430_ST_MMCHS1_SHIFT 7 +#define OMAP2430_ST_MMCHS1_MASK (1 << 7) +#define OMAP2430_ST_USBHS_SHIFT 6 +#define OMAP2430_ST_USBHS_MASK (1 << 6) +#define OMAP24XX_ST_UART3_SHIFT 2 +#define OMAP24XX_ST_UART3_MASK (1 << 2) +#define OMAP24XX_ST_USB_SHIFT 0 +#define OMAP24XX_ST_USB_MASK (1 << 0) + +/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP24XX_EN_GPIOS_SHIFT 2 +#define OMAP24XX_EN_GPIOS (1 << 2) +#define OMAP24XX_EN_GPT1_SHIFT 0 +#define OMAP24XX_EN_GPT1 (1 << 0) + +/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ +#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) +#define OMAP24XX_ST_GPIOS_MASK 2 +#define OMAP24XX_ST_GPT1_SHIFT (1 << 0) +#define OMAP24XX_ST_GPT1_MASK 0 + +/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ +#define OMAP2430_ST_MDM_SHIFT (1 << 0) + + +/* 3430 register bits shared between CM & PRM registers */ + +/* CM_REVISION, PRM_REVISION shared bits */ +#define OMAP3430_REV_SHIFT 0 +#define OMAP3430_REV_MASK (0xff << 0) + +/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ +#define OMAP3430_AUTOIDLE (1 << 0) + +/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ +#define OMAP3430_EN_MMC2 (1 << 25) +#define OMAP3430_EN_MMC2_SHIFT 25 +#define OMAP3430_EN_MMC1 (1 << 24) +#define OMAP3430_EN_MMC1_SHIFT 24 +#define OMAP3430_EN_MCSPI4 (1 << 21) +#define OMAP3430_EN_MCSPI4_SHIFT 21 +#define OMAP3430_EN_MCSPI3 (1 << 20) +#define OMAP3430_EN_MCSPI3_SHIFT 20 +#define OMAP3430_EN_MCSPI2 (1 << 19) +#define OMAP3430_EN_MCSPI2_SHIFT 19 +#define OMAP3430_EN_MCSPI1 (1 << 18) +#define OMAP3430_EN_MCSPI1_SHIFT 18 +#define OMAP3430_EN_I2C3 (1 << 17) +#define OMAP3430_EN_I2C3_SHIFT 17 +#define OMAP3430_EN_I2C2 (1 << 16) +#define OMAP3430_EN_I2C2_SHIFT 16 +#define OMAP3430_EN_I2C1 (1 << 15) +#define OMAP3430_EN_I2C1_SHIFT 15 +#define OMAP3430_EN_UART2 (1 << 14) +#define OMAP3430_EN_UART2_SHIFT 14 +#define OMAP3430_EN_UART1 (1 << 13) +#define OMAP3430_EN_UART1_SHIFT 13 +#define OMAP3430_EN_GPT11 (1 << 12) +#define OMAP3430_EN_GPT11_SHIFT 12 +#define OMAP3430_EN_GPT10 (1 << 11) +#define OMAP3430_EN_GPT10_SHIFT 11 +#define OMAP3430_EN_MCBSP5 (1 << 10) +#define OMAP3430_EN_MCBSP5_SHIFT 10 +#define OMAP3430_EN_MCBSP1 (1 << 9) +#define OMAP3430_EN_MCBSP1_SHIFT 9 +#define OMAP3430_EN_FSHOSTUSB (1 << 5) +#define OMAP3430_EN_FSHOSTUSB_SHIFT 5 +#define OMAP3430_EN_C2C (1 << 3) +#define OMAP3430_EN_C2C_SHIFT 3 + +/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ +#define OMAP3430_EN_HSOTGUSB (1 << 4) +#define OMAP3430_EN_HSOTGUSB_SHIFT 4 + +/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ +#define OMAP3430_ST_MMC2_SHIFT 25 +#define OMAP3430_ST_MMC2_MASK (1 << 25) +#define OMAP3430_ST_MMC1_SHIFT 24 +#define OMAP3430_ST_MMC1_MASK (1 << 24) +#define OMAP3430_ST_MCSPI4_SHIFT 21 +#define OMAP3430_ST_MCSPI4_MASK (1 << 21) +#define OMAP3430_ST_MCSPI3_SHIFT 20 +#define OMAP3430_ST_MCSPI3_MASK (1 << 20) +#define OMAP3430_ST_MCSPI2_SHIFT 19 +#define OMAP3430_ST_MCSPI2_MASK (1 << 19) +#define OMAP3430_ST_MCSPI1_SHIFT 18 +#define OMAP3430_ST_MCSPI1_MASK (1 << 18) +#define OMAP3430_ST_I2C3_SHIFT 17 +#define OMAP3430_ST_I2C3_MASK (1 << 17) +#define OMAP3430_ST_I2C2_SHIFT 16 +#define OMAP3430_ST_I2C2_MASK (1 << 16) +#define OMAP3430_ST_I2C1_SHIFT 15 +#define OMAP3430_ST_I2C1_MASK (1 << 15) +#define OMAP3430_ST_UART2_SHIFT 14 +#define OMAP3430_ST_UART2_MASK (1 << 14) +#define OMAP3430_ST_UART1_SHIFT 13 +#define OMAP3430_ST_UART1_MASK (1 << 13) +#define OMAP3430_ST_GPT11_SHIFT 12 +#define OMAP3430_ST_GPT11_MASK (1 << 12) +#define OMAP3430_ST_GPT10_SHIFT 11 +#define OMAP3430_ST_GPT10_MASK (1 << 11) +#define OMAP3430_ST_MCBSP5_SHIFT 10 +#define OMAP3430_ST_MCBSP5_MASK (1 << 10) +#define OMAP3430_ST_MCBSP1_SHIFT 9 +#define OMAP3430_ST_MCBSP1_MASK (1 << 9) +#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 +#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) +#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 +#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) +#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 +#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) +#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 +#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) +#define OMAP3430_ST_C2C_SHIFT 3 +#define OMAP3430_ST_C2C_MASK (1 << 3) + +/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP3430_EN_GPIO1 (1 << 3) +#define OMAP3430_EN_GPIO1_SHIFT 3 +#define OMAP3430_EN_GPT12 (1 << 1) +#define OMAP3430_EN_GPT12_SHIFT 1 +#define OMAP3430_EN_GPT1 (1 << 0) +#define OMAP3430_EN_GPT1_SHIFT 0 + +/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP3430_EN_SR2 (1 << 7) +#define OMAP3430_EN_SR2_SHIFT 7 +#define OMAP3430_EN_SR1 (1 << 6) +#define OMAP3430_EN_SR1_SHIFT 6 + +/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP3430_EN_GPT12 (1 << 1) +#define OMAP3430_EN_GPT12_SHIFT 1 + +/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ +#define OMAP3430_ST_SR2_SHIFT 7 +#define OMAP3430_ST_SR2_MASK (1 << 7) +#define OMAP3430_ST_SR1_SHIFT 6 +#define OMAP3430_ST_SR1_MASK (1 << 6) +#define OMAP3430_ST_GPIO1_SHIFT 3 +#define OMAP3430_ST_GPIO1_MASK (1 << 3) +#define OMAP3430_ST_GPT12_SHIFT 1 +#define OMAP3430_ST_GPT12_MASK (1 << 1) +#define OMAP3430_ST_GPT1_SHIFT 0 +#define OMAP3430_ST_GPT1_MASK (1 << 0) + +/* + * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, + * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, + * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits + */ +#define OMAP3430_EN_MPU (1 << 1) +#define OMAP3430_EN_MPU_SHIFT 1 + +/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ +#define OMAP3430_EN_GPIO6 (1 << 17) +#define OMAP3430_EN_GPIO6_SHIFT 17 +#define OMAP3430_EN_GPIO5 (1 << 16) +#define OMAP3430_EN_GPIO5_SHIFT 16 +#define OMAP3430_EN_GPIO4 (1 << 15) +#define OMAP3430_EN_GPIO4_SHIFT 15 +#define OMAP3430_EN_GPIO3 (1 << 14) +#define OMAP3430_EN_GPIO3_SHIFT 14 +#define OMAP3430_EN_GPIO2 (1 << 13) +#define OMAP3430_EN_GPIO2_SHIFT 13 +#define OMAP3430_EN_UART3 (1 << 11) +#define OMAP3430_EN_UART3_SHIFT 11 +#define OMAP3430_EN_GPT9 (1 << 10) +#define OMAP3430_EN_GPT9_SHIFT 10 +#define OMAP3430_EN_GPT8 (1 << 9) +#define OMAP3430_EN_GPT8_SHIFT 9 +#define OMAP3430_EN_GPT7 (1 << 8) +#define OMAP3430_EN_GPT7_SHIFT 8 +#define OMAP3430_EN_GPT6 (1 << 7) +#define OMAP3430_EN_GPT6_SHIFT 7 +#define OMAP3430_EN_GPT5 (1 << 6) +#define OMAP3430_EN_GPT5_SHIFT 6 +#define OMAP3430_EN_GPT4 (1 << 5) +#define OMAP3430_EN_GPT4_SHIFT 5 +#define OMAP3430_EN_GPT3 (1 << 4) +#define OMAP3430_EN_GPT3_SHIFT 4 +#define OMAP3430_EN_GPT2 (1 << 3) +#define OMAP3430_EN_GPT2_SHIFT 3 + +/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ +/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits + * be ST_* bits instead? */ +#define OMAP3430_EN_MCBSP4 (1 << 2) +#define OMAP3430_EN_MCBSP4_SHIFT 2 +#define OMAP3430_EN_MCBSP3 (1 << 1) +#define OMAP3430_EN_MCBSP3_SHIFT 1 +#define OMAP3430_EN_MCBSP2 (1 << 0) +#define OMAP3430_EN_MCBSP2_SHIFT 0 + +/* CM_IDLEST_PER, PM_WKST_PER shared bits */ +#define OMAP3430_ST_GPIO6_SHIFT 17 +#define OMAP3430_ST_GPIO6_MASK (1 << 17) +#define OMAP3430_ST_GPIO5_SHIFT 16 +#define OMAP3430_ST_GPIO5_MASK (1 << 16) +#define OMAP3430_ST_GPIO4_SHIFT 15 +#define OMAP3430_ST_GPIO4_MASK (1 << 15) +#define OMAP3430_ST_GPIO3_SHIFT 14 +#define OMAP3430_ST_GPIO3_MASK (1 << 14) +#define OMAP3430_ST_GPIO2_SHIFT 13 +#define OMAP3430_ST_GPIO2_MASK (1 << 13) +#define OMAP3430_ST_UART3_SHIFT 11 +#define OMAP3430_ST_UART3_MASK (1 << 11) +#define OMAP3430_ST_GPT9_SHIFT 10 +#define OMAP3430_ST_GPT9_MASK (1 << 10) +#define OMAP3430_ST_GPT8_SHIFT 9 +#define OMAP3430_ST_GPT8_MASK (1 << 9) +#define OMAP3430_ST_GPT7_SHIFT 8 +#define OMAP3430_ST_GPT7_MASK (1 << 8) +#define OMAP3430_ST_GPT6_SHIFT 7 +#define OMAP3430_ST_GPT6_MASK (1 << 7) +#define OMAP3430_ST_GPT5_SHIFT 6 +#define OMAP3430_ST_GPT5_MASK (1 << 6) +#define OMAP3430_ST_GPT4_SHIFT 5 +#define OMAP3430_ST_GPT4_MASK (1 << 5) +#define OMAP3430_ST_GPT3_SHIFT 4 +#define OMAP3430_ST_GPT3_MASK (1 << 4) +#define OMAP3430_ST_GPT2_SHIFT 3 +#define OMAP3430_ST_GPT2_MASK (1 << 3) + +/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ +#define OMAP3430_EN_CORE_SHIFT 0 +#define OMAP3430_EN_CORE_MASK (1 << 0) + +#endif + diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/prcm-module.c tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/prcm-module.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/prcm-module.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/prcm-module.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,569 @@ +/* + * + * @Component OMAPCONF + * @Filename prcm-module.c + * @Description OMAP PRCM Module APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include + + +/* #define MOD_DEBUG */ +#ifdef MOD_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +static const char + mod_autoidle_mode_names_table[MOD_AUTOIDLE_MODE_MAX + 1][MODULE_MODES_MAX_NAME_LENGTH] = { + "Free Running", + "Autogating", + "FIXME"}; + + +static const char + mod_idle_mode_names_table[MOD_IDLE_MODE_MAX + 1][MODULE_MODES_MAX_NAME_LENGTH] = { + "Force-Idle", + "No Idle", + "Smart-Idle", + "Smart-Idle Wakeup", + "FIXME"}; + + +static const char + mod_idle_status_names_table[MOD_IDLE_STATUS_MAX + 1][MODULE_MODES_MAX_NAME_LENGTH] = { + "Full ON", + "In Transition", + "OCP-ONLY Idle", + "Disabled (NO ACCESS)", + "FIXME"}; + + +static const char + mod_standby_mode_names_table[MOD_STANDBY_MODE_MAX + 1][MODULE_MODES_MAX_NAME_LENGTH] = { + "Force-standby", + "No standby", + "Smart-Standby", + "Reserved", + "FIXME"}; + + +static const char + mod_standby_status_names_table[MOD_STANDBY_STATUS_MAX + 1][MODULE_MODES_MAX_NAME_LENGTH] = { + "Functional", + "In Standby", + "FIXME"}; + + +static const char + mod_module_mode_names_table[MOD_MODULE_MODE_MAX + 1][MODULE_MODES_MAX_NAME_LENGTH] = { + "Disabled (NO ACCESS)", + "HW-Auto", + "Enabled (EXPLICITLY)", + "Reserved", + "FIXME"}; + + +static const char + mod_clock_activity_mode_names_table[MOD_CLOCK_ACTIVITY_MODE_MAX + 1][MODULE_MODES_MAX_NAME_LENGTH] = { + "F-CLK AUTO / I-CLK AUTO", + "F-CLK AUTO / I-CLK ON", + "F-CLK ON / I-CLK AUTO", + "F-CLK ON / I-CLK ON", + "FIXME"}; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_module_mode_name_get + * @BRIEF return module mode name + * @RETURNS module mode name on success + * "FIXME" otherwise + * @param[in] mode: valid module mode + * @DESCRIPTION return module mode name + *//*------------------------------------------------------------------------ */ +const char *mod_module_mode_name_get(mod_module_mode mode) +{ + if (mode > MOD_MODULE_MODE_MAX) + mode = MOD_MODULE_MODE_MAX; + + return mod_module_mode_names_table[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_autoidle_mode_name_get + * @BRIEF return autoidle mode name + * @RETURNS autoidle mode name on success + * "FIXME" otherwise + * @param[in] mode: valid autoidle mode + * @DESCRIPTION return autoidle mode name + *//*------------------------------------------------------------------------ */ +const char *mod_autoidle_mode_name_get(mod_autoidle_mode mode) +{ + if (mode > MOD_AUTOIDLE_MODE_MAX) + mode = MOD_AUTOIDLE_MODE_MAX; + + return mod_autoidle_mode_names_table[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_idle_mode_name_get + * @BRIEF return idle mode name + * @RETURNS idle mode name on success + * "FIXME" otherwise + * @param[in] mode: valid idle mode + * @DESCRIPTION return idle mode name + *//*------------------------------------------------------------------------ */ +const char *mod_idle_mode_name_get(mod_idle_mode mode) +{ + if (mode > MOD_IDLE_MODE_MAX) + mode = MOD_IDLE_MODE_MAX; + + return mod_idle_mode_names_table[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_standby_mode_name_get + * @BRIEF return standby mode name + * @RETURNS standby mode name on success + * "FIXME" otherwise + * @param[in] mode: valid standby mode + * @DESCRIPTION return standby mode name + *//*------------------------------------------------------------------------ */ +const char *mod_standby_mode_name_get(mod_standby_mode mode) +{ + if (mode > MOD_STANDBY_MODE_MAX) + mode = MOD_STANDBY_MODE_MAX; + + return mod_standby_mode_names_table[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_clock_activity_mode_name_get + * @BRIEF return clock activity mode name + * @RETURNS clock activity mode name on success + * "FIXME" otherwise + * @param[in] mode: valid clock activity mode + * @DESCRIPTION return clock activity mode name + *//*------------------------------------------------------------------------ */ +const char *mod_clock_activity_mode_name_get(mod_clock_activity_mode mode) +{ + if (mode > MOD_CLOCK_ACTIVITY_MODE_MAX) + mode = MOD_CLOCK_ACTIVITY_MODE_MAX; + + return mod_clock_activity_mode_names_table[mode]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_idle_status_name_get + * @BRIEF return module idle status name + * @RETURNS module idle status name on success + * "FIXME" otherwise + * @param[in] status: valid module idle status + * @DESCRIPTION return module idle status name + *//*------------------------------------------------------------------------ */ +const char *mod_idle_status_name_get(mod_idle_status status) +{ + if (status > MOD_IDLE_STATUS_MAX) + status = MOD_IDLE_STATUS_MAX; + + return mod_idle_status_names_table[status]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_standby_status_name_get + * @BRIEF return module standby status name + * @RETURNS module standby status name on success + * "FIXME" otherwise + * @param[in] status: valid module standby status + * @DESCRIPTION return module standby status name + *//*------------------------------------------------------------------------ */ +const char *mod_standby_status_name_get(mod_standby_status status) +{ + if (status > MOD_STANDBY_STATUS_MAX) + status = MOD_STANDBY_STATUS_MAX; + + return mod_standby_status_names_table[status]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_is_accessible + * @BRIEF return 1 if module is running, 0 otherwise + * @RETURNS 1 if module is running, 0 otherwise + * @param[in] cm_clkctrl: CM_xxx_xxx_CLKCTRL register content + * @DESCRIPTION return 1 if module is running, 0 otherwise + *//*------------------------------------------------------------------------ */ +unsigned int mod_is_accessible(unsigned int cm_clkctrl) +{ + mod_module_mode mmode; + mod_idle_status mstatus; + + /* Retrieve module mode */ + mmode = (mod_module_mode) extract_bitfield(cm_clkctrl, 0, 2); + dprintf("%s(): CM_CLKCTRL=0x%08X MODULEMODE (bit [1-0])=%u (%s)\n", + __func__, cm_clkctrl, mmode, + mod_module_mode_name_get(mmode)); + + if (mmode == MOD_DISABLED_MODE) { + dprintf("%s(): module mode is disabled => NOT accessible\n", + __func__); + return 0; + } + + /* Retrieve module idle status */ + mstatus = (mod_idle_status) extract_bitfield(cm_clkctrl, 16, 2); + dprintf("%s(): IDLEST (bit [17-16]) = %u (%s)\n", __func__, mstatus, + mod_idle_status_name_get(mstatus)); + switch (mstatus) { + case MOD_FULL_ON: + /* Module is fully functional, including OCP */ + dprintf("%s(): module is fully functional => accessible\n", + __func__); + return 1; + + case MOD_IN_TRANSITION: + /* + * Module is performing transition: wakeup, or sleep, + * or sleep abortion. + * In case of sleep transition, transition may complete before + * the module is tentatively accessed, so it is safer to always + * consider module as non-accessible. + */ + dprintf( + "%s(): module is performing transition: wakeup, or sleep, or sleep abortion => NOT accessible\n", + __func__); + return 0; + + case MOD_OCP_ONLY_IDLE: + /* + * Module is in Idle mode (only OCP part). OCP clock can be + * re-enabled on access, so module is accessible. + */ + dprintf( + "%s(): module is in Idle mode (only OCP part) => accessible\n", + __func__); + return 1; + + case MOD_DISABLED: + /* Module is disabled and cannot be accessed. */ + dprintf( + "%s(): module is disabled and cannot be accessed => NOT accessible\n", + __func__); + return 0; + + default: + fprintf(stderr, "%s(): ?!?!?!?! => NOT accessible\n", __func__); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_module_mode_get + * @BRIEF return the module module mode. + * @RETURNS module mode in case of success + * MOD_MODULE_MODE_MAX otherwise + * @param[in] cm_clkctrl: CM_XYZ_CLKCTRL register content + * @DESCRIPTION return the module module mode. + *//*------------------------------------------------------------------------ */ +mod_module_mode mod_module_mode_get(unsigned int cm_clkctrl) +{ + mod_module_mode mmode; + + mmode = (mod_module_mode) extract_bitfield(cm_clkctrl, 0, 2); + dprintf( + "%s(): CM_CLKCTRL=0x%08X MODULEMODE (bit [1-0])=%u (%s)\n", + __func__, cm_clkctrl, mmode, + mod_module_mode_name_get(mmode)); + + return mmode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_idle_status_get + * @BRIEF retrieve module's idle status from CM_xxx_xxx_CLKCTRL + * @RETURNS module idle status + * MOD_IDLE_STATUS_MAX in case of error + * @param[in] cm_clkctrl: CM_xxx_xxx_CLKCTRL register content + * @param[in] properties: module properties + * @DESCRIPTION retrieve module's idle status from CM_xxx_xxx_CLKCTRL + *//*------------------------------------------------------------------------ */ +mod_idle_status mod_idle_status_get( + unsigned int cm_clkctrl, unsigned int properties) +{ + mod_idle_status mstatus; + + if ((properties & MOD_HAS_NO_IDLE_STATUS) != 0) { + dprintf("%s(): module HAS NO idle status (prop=%u)\n", + __func__, properties); + mstatus = MOD_IDLE_STATUS_MAX; + } else { + mstatus = (mod_idle_status) extract_bitfield(cm_clkctrl, 16, 2); + dprintf( + "%s(): CM_CLKCTRL=0x%08X, IDLEST (bit [17-16])=%u (%s)\n", + __func__, cm_clkctrl, mstatus, + mod_idle_status_name_get(mstatus)); + } + + return mstatus; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_standby_status_get + * @BRIEF retrieve module standby status from CM_xxx_xxx_CLKCTRL + * @RETURNS module standby status + * MOD_STANDBY_STATUS_MAX in case of error + * @param[in] cm_clkctrl: CM_xxx_xxx_CLKCTRL register content + * @param[in] properties: module properties + * @DESCRIPTION retrieve module standby status from CM_xxx_xxx_CLKCTRL + *//*------------------------------------------------------------------------ */ +mod_standby_status mod_standby_status_get( + unsigned int cm_clkctrl, unsigned int properties) +{ + mod_standby_status mstatus; + + if ((properties & MOD_HAS_STANDBY_STATUS) != 0) { + mstatus = (mod_standby_status) extract_bit(cm_clkctrl, 18); + dprintf( + "%s(): CM_CLKCTRL=0x%08X, STANDBYST (bit 18)=%u (%s)\n", + __func__, cm_clkctrl, mstatus, + mod_standby_status_name_get(mstatus)); + } else { + dprintf("%s(): module does NOT have STANDBY status bit\n", + __func__); + mstatus = MOD_STANDBY_STATUS_MAX; + } + + return mstatus; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_autoidle_mode_get + * @BRIEF retrieve module autoidle mode + * @RETURNS module autoidle mode + * MOD_AUTOIDLE_MODE_MAX in case of error + * @param[in] sysconfig: SYSCONFIG register content + * @param[in] properties: module properties + * @DESCRIPTION retrieve module autoidle mode + *//*------------------------------------------------------------------------ */ +mod_autoidle_mode mod_autoidle_mode_get( + unsigned int sysconfig, unsigned int properties) +{ + mod_autoidle_mode mode; + + if ((properties & MOD_HAS_AUTOIDLE_BIT0) != 0) { + mode = (mod_autoidle_mode) extract_bit(sysconfig, 0); + dprintf( + "%s(): SYSCONFIG=0x%08X POS=0 AUTOIDLE MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_autoidle_mode_name_get(mode)); + } else if ((properties & MOD_HAS_AUTOIDLE_BIT8) != 0) { + /* + * NB: AUTOGATINGDISABLE instead of AUTOGATING, + * bit is inverted compared to other modules ... + */ + mode = (mod_autoidle_mode) !extract_bit(sysconfig, 8); + dprintf("%s(): SYSCONFIG=0x%08X POS=8 AUTOIDLE MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_autoidle_mode_name_get(mode)); + } else { + dprintf("%s(): MODULE DOES NOT HAVE AUTOIDLE MODE?! (%u)\n", + __func__, properties); + mode = MOD_AUTOIDLE_MODE_MAX; + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_idle_mode_get + * @BRIEF retrieve omap module's idle mode + * @RETURNS module's idle mode + * MOD_IDLE_MODE_MAX in case of error + * @param[in] sysconfig: SYSCONFIG register content + * @param[in] properties: module properties + * @DESCRIPTION retrieve omap module's idle mode + *//*------------------------------------------------------------------------ */ +mod_idle_mode mod_idle_mode_get( + unsigned int sysconfig, unsigned int properties) +{ + mod_idle_mode mode; + + if ((properties & MOD_HAS_IDLE_MODE1) != 0) { + mode = (mod_idle_mode) extract_bitfield(sysconfig, 0, 2); + dprintf( + "%s(): SYSCONFIG=0x%08X POS=[1-0] IDLE MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_idle_mode_name_get(mode)); + } else if ((properties & MOD_HAS_IDLE_MODE3) != 0) { + mode = (mod_idle_mode) extract_bitfield(sysconfig, 2, 2); + dprintf("%s(): SYSCONFIG=0x%08X POS=[3-2] IDLE MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_idle_mode_name_get(mode)); + } else if ((properties & MOD_HAS_IDLE_MODE4) != 0) { + mode = (mod_idle_mode) extract_bitfield(sysconfig, 3, 2); + dprintf("%s(): SYSCONFIG=0x%08X POS=[4-3] IDLE MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_idle_mode_name_get(mode)); + } else { + dprintf("%s(): MODULE DOES NOT HAVE IDLE MODE?! (%u)\n", + __func__, properties); + mode = MOD_IDLE_MODE_MAX; + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_standby_mode_get + * @BRIEF retrieve omap module's standby mode + * @RETURNS module's standby mode + * MOD_STANDBY_MODE_MAX in case of error + * @param[in] sysconfig: SYSCONFIG register content + * @param[in] properties: module properties + * @DESCRIPTION retrieve omap module's standby mode + *//*------------------------------------------------------------------------ */ +mod_standby_mode mod_standby_mode_get( + unsigned int sysconfig, unsigned int properties) +{ + mod_standby_mode mode; + + if ((properties & MOD_HAS_STANDBY_MODE5) != 0) { + mode = (mod_standby_mode) extract_bitfield(sysconfig, 4, 2); + dprintf( + "%s(): SYSCONFIG=0x%08X POS=[5-4] STANDBY MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_standby_mode_name_get(mode)); + } else if ((properties & MOD_HAS_STANDBY_MODE13) != 0) { + mode = (mod_standby_mode) extract_bitfield(sysconfig, 12, 2); + dprintf( + "%s(): SYSCONFIG=0x%08X POS=[13-12] STANDBY MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_standby_mode_name_get(mode)); + } else { + dprintf("%s(): MODULE DOES NOT HAVE STANDBY MODE?! (%u)\n", + __func__, properties); + mode = MOD_STANDBY_MODE_MAX; + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_clock_activity_mode_get + * @BRIEF retrieve omap module's clock activity mode + * @RETURNS module's clock activity mode + * MOD_CLOCK_ACTIVITY_MODE_MAX in case of error + * @param[in] sysconfig: SYSCONFIG register content + * @param[in] properties: module properties + * @DESCRIPTION retrieve omap module's clock activity mode + *//*------------------------------------------------------------------------ */ +mod_clock_activity_mode mod_clock_activity_mode_get( + unsigned int sysconfig, unsigned int properties) +{ + mod_clock_activity_mode mode; + + if ((properties & MOD_HAS_CLOCK_ACTIVITY_MODE) != 0) { + mode = (mod_clock_activity_mode) extract_bitfield(sysconfig, 8, 2); + dprintf( + "%s(): SYSCONFIG=0x%08X POS=[9-8] CLOCK ACTIVITY MODE=%u (%s)\n", + __func__, sysconfig, mode, + mod_clock_activity_mode_name_get(mode)); + } else { + dprintf("%s(): module does NOT have clock activity mode (%u)\n", + __func__, properties); + mode = MOD_CLOCK_ACTIVITY_MODE_MAX; + } + + return mode; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mod_context_is_lost + * @BRIEF check if module's context was retained or lost + * during last power transition + * @RETURNS 1 if module's context was LOST during last power + * transition + * 0 if module's context was RETAINED during last power + * transition + * @param[in] sysconfig: RM_XYZ_CONTEXT register content + * @DESCRIPTION check if module's context was retained or lost + * during last power transition + *//*------------------------------------------------------------------------ */ +int mod_context_is_lost(unsigned int rm_context) +{ + int lost; + if (rm_context == 0) { + /* All memory bank(s) were retained */ + dprintf( + "%s(): RM_CONTEXT=0x%08X => context is RETAINED\n", + __func__, rm_context); + lost = 0; + } else { + /* At least 1 memory bank was lost */ + dprintf( + "%s(): RM_CONTEXT=0x%08X => context is LOST\n", + __func__, rm_context); + lost = 1; + } + + return lost; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/prcm-module.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/prcm-module.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/prcm-module.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/prcm-module.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,166 @@ +/* + * + * @Component OMAPCONF + * @Filename prcm-module.h + * @Description OMAP PRCM Module Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __PRCM_MODULE_H__ +#define __PRCM_MODULE_H__ + + +#define MODULE_MAX_NAME_LENGTH 32 +#define MODULE_MODES_MAX_NAME_LENGTH 32 +#define MOD_INTERFACE_TYPE_MAX_NAME_LENGTH 8 + +#define OPP_MAX 6 + +#define MOD_HAS_SYSCONFIG (1 << 0) +#define MOD_HAS_AUTOIDLE_BIT0 (1 << 1) /* bit 0 */ +#define MOD_HAS_AUTOIDLE_BIT8 (1 << 2) /* bit 8 (for SLIMBUS) */ +#define MOD_HAS_IDLE_MODE3 (1 << 3) /* bits [3-2] */ +#define MOD_HAS_IDLE_MODE4 (1 << 4) /* bits [4-3] */ +#define MOD_HAS_IDLE_MODE1 (1 << 5) /* bits [1-0] */ +#define MOD_HAS_SMART_IDLE_WAKEUP_MODE (1 << 6) /* mode 0x3 */ +#define MOD_HAS_ENAWAKEUP_BIT (1 << 7) /* bit 2 */ +#define MOD_HAS_STANDBY_MODE5 (1 << 8) /* bits [5-4] */ +#define MOD_HAS_STANDBY_MODE13 (1 << 9) /* bits [13-12] */ +#define MOD_HAS_SMART_STANDBY_WAKEUP_MODE (1 << 10) /* mode 0x3 */ +#define MOD_HAS_CLOCK_ACTIVITY_MODE (1 << 11) /* bits [9-8] */ +#define MOD_HAS_STANDBY_STATUS (1 << 12) /* CM_CLKCTRL bit 18 */ +#define MOD_HAS_NO_IDLE_STATUS (1 << 13) /* CM_CLKCTRL bit [17-16] */ + + +typedef enum { + MOD_FREE_RUNNING = 0, + MOD_AUTOGATING = 1, + MOD_AUTOIDLE_MODE_MAX +} mod_autoidle_mode; + + +typedef enum { + MOD_FORCE_IDLE = 0, + MOD_NO_IDLE = 1, + MOD_SMART_IDLE = 2, + MOD_SMART_IDLE_WAKEUP = 3, + MOD_IDLE_MODE_MAX +} mod_idle_mode; + + +typedef enum { + MOD_FULL_ON = 0x0, + MOD_IN_TRANSITION = 0x1, + MOD_OCP_ONLY_IDLE = 0x2, + MOD_DISABLED = 0x3, + MOD_IDLE_STATUS_MAX +} mod_idle_status; + + +typedef enum { + MOD_FORCE_STANDBY = 0, + MOD_NO_STANDBY = 1, + MOD_SMART_STANDBY = 2, + MOD_STANDBY_MODE_RESERVED = 3, + MOD_STANDBY_MODE_MAX +} mod_standby_mode; + + +typedef enum { + MOD_FUNCTIONAL = 0x0, + MOD_IN_STANDBY = 0x1, + MOD_STANDBY_STATUS_MAX +} mod_standby_status; + + +typedef enum { + MOD_DISABLED_MODE = 0, + MOD_HW_AUTO_MODE = 1, + MOD_ENABLED_MODE = 2, + MOD_RESERVED_MODE = 3, + MOD_MODULE_MODE_MAX +} mod_module_mode; + + +typedef enum { + MOD_FCLK_AUTO_ICLK_AUTO = 0, + MOD_FCLK_AUTO_ICLK_ON = 1, + MOD_FCLK_ON_ICLK_AUTO = 2, + MOD_FCLK_ON_ICLK_ON = 3, + MOD_CLOCK_ACTIVITY_MODE_MAX, +} mod_clock_activity_mode; + + +typedef enum { + MOD_INTERFACE_MASTER, + MOD_INTERFACE_SLAVE, + MOD_INTERFACE_DUAL, + MOD_INTERFACE_NONE, /* no SYSCONFIG register or only Autoidle bit */ + MOD_INTERFACE_TYPE_MAX +} mod_interface_type; + + +unsigned int mod_is_accessible(unsigned int cm_clkctrl); +mod_module_mode mod_module_mode_get(unsigned int cm_clkctrl); +mod_idle_status mod_idle_status_get( + unsigned int cm_clkctrl, unsigned int properties); +mod_standby_status mod_standby_status_get( + unsigned int cm_clkctrl, unsigned int properties); + +mod_autoidle_mode mod_autoidle_mode_get( + unsigned int sysconfig, unsigned int properties); +mod_idle_mode mod_idle_mode_get( + unsigned int sysconfig, unsigned int properties); +mod_standby_mode mod_standby_mode_get( + unsigned int sysconfig, unsigned int properties); +mod_clock_activity_mode mod_clock_activity_mode_get( + unsigned int sysconfig, unsigned int properties); + +int mod_context_is_lost(unsigned int rm_context); + +const char *mod_module_mode_name_get(mod_module_mode mode); +const char *mod_autoidle_mode_name_get(mod_autoidle_mode mode); +const char *mod_idle_mode_name_get(mod_idle_mode mode); +const char *mod_standby_mode_name_get(mod_standby_mode mode); +const char *mod_clock_activity_mode_name_get(mod_clock_activity_mode mode); +const char *mod_idle_status_name_get(mod_idle_status status); +const char *mod_standby_status_name_get(mod_standby_status status); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/pwrdm.c tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/pwrdm.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/pwrdm.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/pwrdm.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,329 @@ +/* + * + * @Component OMAPCONF + * @Filename pwrdm.c + * @Description OMAP Power Domain APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include + + +/* #define PRCM_PWRDM_DEBUG */ +#ifdef PRCM_PWRDM_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +static const char + pwrdm_state_names[PWRDM_STATE_MAX][PWRDM_STATE_MAX_NAME_LENGTH] = { + "OFF", + "RET", + "INACT", + "ON"}; + + +static const char + pwrdm_state_type_names[PWRDM_STATE_TYPE_MAX][PWRDM_STATE_MAX_NAME_LENGTH] = { + "PREVIOUS", + "CURRENT", + "TARGET"}; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_state_name_get + * @BRIEF return power domain state name + * @RETURNS power domain state name on success + * NULL in case of error + * @param[in] st: valid power domain state + * @DESCRIPTION return power domain state name + *//*------------------------------------------------------------------------ */ +const char *pwrdm_state_name_get(pwrdm_state st) +{ + CHECK_ARG_LESS_THAN(st, PWRDM_STATE_MAX, NULL); + + return pwrdm_state_names[st]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_state_type_name_get + * @BRIEF return power domain state type name + * @RETURNS power domain state type name on success + * NULL in case of error + * @param[in] type: valid power domain state type + * @DESCRIPTION return power domain state type name + *//*------------------------------------------------------------------------ */ +const char *pwrdm_state_type_name_get(pwrdm_state_type type) +{ + CHECK_ARG_LESS_THAN(type, PWRDM_STATE_TYPE_MAX, NULL); + + return pwrdm_state_type_names[type]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_state_get + * @BRIEF return power domain state + * @RETURNS power domain state on success + * PWRDM_STATE_MAX in case of error + * @param[in] pm_pwrst: PM_xyz_PWRST[CTRL-ST] register + * @param[in] type: pwrdm state type + * @DESCRIPTION return power domain state + *//*------------------------------------------------------------------------ */ +pwrdm_state pwrdm_state_get(reg *pm_pwrst, pwrdm_state_type type) +{ + pwrdm_state st; + unsigned int val; + + CHECK_NULL_ARG(pm_pwrst, PWRDM_STATE_MAX); + + /* Retrieve registers content */ + val = reg_read(pm_pwrst); + dprintf("%s(%s): addr=0x%08X val=0x%08X\n", __func__, + pm_pwrst->name, pm_pwrst->addr, val); + + /* Retrieve power domain state */ + if (type == PWRDM_STATE_PREVIOUS) + st = (pwrdm_state) extract_bitfield(val, 24, 2); + else + st = (pwrdm_state) extract_bitfield(val, 0, 2); + dprintf("%s(%s): state=%u (%s)\n", __func__, + pm_pwrst->name, st, pwrdm_state_name_get(st)); + + return st; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_target_logic_ret_state_get + * @BRIEF return logic target state for this power domain + * when domain is RET + * @RETURNS power domain logic state when domain is RET: + * PWRDM_OFF_STATE or PWRDM_RET_STATE + * PWRDM_STATE_MAX in case of error + * @param[in] pm_pwrstctrl: PM_xyz_PWRSTCTRL register + * @DESCRIPTION return logic target state for this power domain when + * domain is RET + *//*------------------------------------------------------------------------ */ +pwrdm_state pwrdm_target_logic_ret_state_get(reg *pm_pwrstctrl) +{ + pwrdm_state st; + unsigned int val; + + CHECK_NULL_ARG(pm_pwrstctrl, PWRDM_STATE_MAX); + + /* Retrieve registers content */ + val = reg_read(pm_pwrstctrl); + /* Retrieve power domain state */ + if (extract_bit(val, 2) == 1) + st = PWRDM_RET_STATE; + else + st = PWRDM_OFF_STATE; + dprintf( + "%s(%s): addr=0x%08X val=0x%08X LOGICRETSTATE (bit 2)=%u logic target RET state=%s\n", + __func__, + pm_pwrstctrl->name, pm_pwrstctrl->addr, val, + extract_bit(val, 2), pwrdm_state_name_get(st)); + + return st; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_logic_state_get + * @BRIEF return logic state for this power domain + * @RETURNS power domain logic state: + * PWRDM_OFF_STATE or PWRDM_ON_STATE + * PWRDM_STATE_MAX in case of error + * @param[in] pm_pwrstst: PM_xyz_PWRSTST register + * @DESCRIPTION return logic state for this power domain + *//*------------------------------------------------------------------------ */ +pwrdm_state pwrdm_logic_state_get(reg *pm_pwrstst) +{ + pwrdm_state st; + unsigned int val; + + CHECK_NULL_ARG(pm_pwrstst, PWRDM_STATE_MAX); + + /* Retrieve registers content */ + val = reg_read(pm_pwrstst); + /* Retrieve power domain state */ + if (extract_bit(val, 2) == 1) + st = PWRDM_ON_STATE; + else + st = PWRDM_OFF_STATE; + dprintf( + "%s(%s): addr=0x%08X val=0x%08X LOGICRETSTATE (bit 2)=%u logic state=%s\n", + __func__, + pm_pwrstst->name, pm_pwrstst->addr, val, + extract_bit(val, 2), pwrdm_state_name_get(st)); + + return st; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_in_transition + * @BRIEF return 1 if power domain is in transition, 0 otherwise + * @RETURNS return 1 if power domain is in transition, 0 otherwise + * @param[in] pm_pwrstst: PM_xyz_PWRSTST register + * @DESCRIPTION return 1 if power domain is in transition, 0 otherwise + *//*------------------------------------------------------------------------ */ +unsigned int pwrdm_in_transition(reg *pm_pwrstst) +{ + unsigned int val; + + CHECK_NULL_ARG(pm_pwrstst, 0); + + /* Retrieve registers content */ + val = reg_read(pm_pwrstst); + /* Retrieve power domain intransition status */ + dprintf("%s(%s): addr=0x%08X val=0x%08X INTRANSITION (bit 20)=%u\n", + __func__, pm_pwrstst->name, + pm_pwrstst->addr, val, extract_bit(val, 20)); + return extract_bit(val, 20); +} + + +/* FIXME: DEPRECATED FUNCTION. Update OMAP4 code to use new functions ... */ +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_state2string + * @BRIEF convert powerstate into string + * @RETURNS 0 on success + * OMAPCONF_ERR_ARG + * @param[in,out] s: destination string (pre-allocated) + * @param[in] powerstate: powerstate + * @DESCRIPTION convert powerstate into string + *//*------------------------------------------------------------------------ */ +int pwrdm_state2string(char s[6], pwrdm_state powerstate) +{ + if (s == NULL) + return OMAPCONF_ERR_ARG; + + switch (powerstate) { + case PWRDM_OFF_STATE: + strcpy(s, "OFF"); + break; + case PWRDM_RET_STATE: + strcpy(s, "RET"); + break; + case PWRDM_INACTIVE_STATE: + strcpy(s, "INACT"); + break; + case PWRDM_ON_STATE: + strcpy(s, "ON"); + break; + default: + strcpy(s, "FIXME"); + return OMAPCONF_ERR_ARG; + } + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION pwrdm_states_get + * @BRIEF extract power domain states (current, target) + * @RETURNS 0 on success + * OMAPCONF_ERR_ARG + * @param[in] name: domain name (MPU, CORE, PER, ...) + * @param[in,out] pwst: domain current state string + * (must be pre-allocated) + * @param[in,out] pwtgst: domain target state string + * (must be pre-allocated) + * @DESCRIPTION extract power domain states (current, target) + * from register into strings. + *//*------------------------------------------------------------------------ */ +int pwrdm_states_get(char *name, char pwst[6], char pwtgst[6]) +{ + unsigned int pwrstst, pwrstctrl; + + char pm_pwrstst_name[OMAPCONF_REG_NAME_MAX_LENGTH] = "PM_"; + char pm_pwrstctrl_name[OMAPCONF_REG_NAME_MAX_LENGTH] = "PM_"; + unsigned int pm_pwrstst_addr; + unsigned int pm_pwrstctrl_addr; + + if ((name == NULL) || + (pwst == NULL) || + (pwtgst == NULL)) + return OMAPCONF_ERR_ARG; + + /* Retrieve register names */ + strcat(pm_pwrstst_name, name); + strcat(pm_pwrstst_name, "_PWRSTST"); + strcat(pm_pwrstctrl_name, name); + strcat(pm_pwrstctrl_name, "_PWRSTCTRL"); + dprintf("pm_pwrstst_name=%s pm_pwrstctrl_name=%s\n", + pm_pwrstst_name, pm_pwrstctrl_name); + + /* Retrieve registers address */ + if (find_reg_addr(pm_pwrstst_name, &pm_pwrstst_addr) != 0) { + printf("pm_pwrstst_name = %s not found!\n", + pm_pwrstst_name); + return OMAPCONF_ERR_ARG; + } + if (find_reg_addr(pm_pwrstctrl_name, &pm_pwrstctrl_addr) != 0) { + printf("pm_pwrstctrl_name = %s not found!\n", + pm_pwrstctrl_name); + return OMAPCONF_ERR_ARG; + } + dprintf("pm_pwrstst_addr=0x%08X pm_pwrstctrl_addr=0x%08X\n", + pm_pwrstst_addr, pm_pwrstctrl_addr); + + /* Retrieve registers content */ + mem_read(pm_pwrstst_addr, &pwrstst); + mem_read(pm_pwrstctrl_addr, &pwrstctrl); + + /* Retrieve power domain current & target states */ + pwrdm_state2string(pwst, + (pwrdm_state) extract_bitfield(pwrstst, 0, 2)); + pwrdm_state2string(pwtgst, + (pwrdm_state) extract_bitfield(pwrstctrl, 0, 2)); + dprintf("pwst=%s pwtgst=%s\n", pwst, pwtgst); + + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/pwrdm.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/pwrdm.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/pwrdm.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/pwrdm.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,88 @@ +/* + * + * @Component OMAPCONF + * @Filename pwrdm.h + * @Description OMAP Power Domain Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __PRCM_PWRDM_H__ +#define __PRCM_PWRDM_H__ + + +#include + + +#define PWRDM_STATE_MAX_NAME_LENGTH 8 + + +#define PWRDM_HAS_LAST_STATE (1 << 0) /* bits [25-24] */ +#define PWRDM_HAS_LOGIC_RET_STATE_CTRL_BIT (1 << 1) /* bit 2 */ + + +typedef enum { + PWRDM_OFF_STATE = 0, + PWRDM_RET_STATE = 1, + PWRDM_INACTIVE_STATE = 2, + PWRDM_ON_STATE = 3, + PWRDM_STATE_MAX +} pwrdm_state; + + +typedef enum { + PWRDM_STATE_PREVIOUS, + PWRDM_STATE_CURRENT, + PWRDM_STATE_TARGET, + PWRDM_STATE_TYPE_MAX +} pwrdm_state_type; + + +pwrdm_state pwrdm_state_get(reg *pm_pwrst, pwrdm_state_type type); +pwrdm_state pwrdm_target_logic_ret_state_get(reg *pm_pwrstctrl); +pwrdm_state pwrdm_logic_state_get(reg *pm_pwrstst); +unsigned int pwrdm_in_transition(reg *pm_pwrstst); +const char *pwrdm_state_name_get(pwrdm_state st); +const char *pwrdm_state_type_name_get(pwrdm_state_type type); + +/* FIXME: DEPRECATED FUNCTION. Update OMAP4 code to use new functions ... */ +int pwrdm_state2string(char s[6], pwrdm_state powerstate); +int pwrdm_states_get(char *name, char pwst[6], char pwtgst[6]); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vc.c tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vc.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vc.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vc.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,357 @@ +/* + * + * @Component OMAPCONF + * @Filename vc.c + * @Description VOLTAGE CONTROLLER (VC) Common Definitions & + * Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2006 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include + + +#define VC_ON_POS 24 +#define VC_ON_LEN 8 +#define VC_ONLP_POS 16 +#define VC_ONLP_LEN 8 +#define VC_RET_POS 8 +#define VC_RET_LEN 8 +#define VC_OFF_POS 0 +#define VC_OFF_LEN 8 + +#define VC_DFILTEREN_POS 6 +#define VC_SRMODEEN_POS 4 +#define VC_HSMODEEN_POS 3 +#define VC_HSMCODE_POS 0 +#define VC_HSMCODE_LEN 3 + +#define VC_HSSCLL_POS 24 +#define VC_HSSCLL_LEN 8 +#define VC_HSSCLH_POS 16 +#define VC_HSSCLH_LEN 8 +#define VC_SCLL_POS 8 +#define VC_SCLL_LEN 8 +#define VC_SCLH_POS 0 +#define VC_SCLH_LEN 8 + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vc_cmd_values_get + * @BRIEF return ON/ONLP/RET/OFF command values + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * @param[in] prm_vc_val_cmd: PRM_VC_VAL_CMD register content + * @param[in,out] cmd_on: ON command value (RETURNED) + * @param[in,out] cmd_onlp: ONLP command value (RETURNED) + * @param[in,out] cmd_ret: RET command value (RETURNED) + * @param[in,out] cmd_off: OFF command value (RETURNED) + * @DESCRIPTION return ON/ONLP/RET/OFF command values + *//*------------------------------------------------------------------------ */ +short int vc_cmd_values_get(unsigned int prm_vc_val_cmd, + unsigned char *cmd_on, unsigned char *cmd_onlp, + unsigned char *cmd_ret, unsigned char *cmd_off) +{ + CHECK_NULL_ARG(cmd_on, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(cmd_onlp, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(cmd_ret, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(cmd_off, OMAPCONF_ERR_ARG); + + *cmd_on = extract_bitfield(prm_vc_val_cmd, VC_ON_POS, VC_ON_LEN); + *cmd_onlp = extract_bitfield(prm_vc_val_cmd, VC_ONLP_POS, VC_ONLP_LEN); + *cmd_ret = extract_bitfield(prm_vc_val_cmd, VC_RET_POS, VC_RET_LEN); + *cmd_off = extract_bitfield(prm_vc_val_cmd, VC_OFF_POS, VC_OFF_LEN); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sri2c_is_double_filtering_enabled + * @BRIEF check if double filtering is enabled + * @RETURNS 1 if double filtering is enabled + * 0 if double filtering is disabled + * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register + * content + * @DESCRIPTION check if double filtering is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sri2c_is_double_filtering_enabled( + unsigned int prm_vc_cfg_i2c_mode) +{ + return extract_bit(prm_vc_cfg_i2c_mode, VC_DFILTEREN_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sri2c_is_sr_mode_enabled + * @BRIEF check if I2C repeated start operation mode is enabled + * @RETURNS 1 if I2C repeated start operation mode is enabled + * 0 if I2C repeated start operation mode is disabled + * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register + * content + * @DESCRIPTION check if I2C repeated start operation mode is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sri2c_is_sr_mode_enabled(unsigned int prm_vc_cfg_i2c_mode) +{ + return extract_bit(prm_vc_cfg_i2c_mode, VC_SRMODEEN_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sri2c_is_hs_mode_enabled + * @BRIEF check if I2C high speed mode is enabled + * @RETURNS 1 if I2C high speed mode is enabled + * 0 if I2C high speed mode is disabled + * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register + * content + * @DESCRIPTION check if I2C high speed mode is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sri2c_is_hs_mode_enabled(unsigned int prm_vc_cfg_i2c_mode) +{ + return extract_bit(prm_vc_cfg_i2c_mode, VC_HSMODEEN_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sri2c_master_code_get + * @BRIEF return the master code value for I2C High Speed preamble + * transmission + * @RETURNS master code value for I2C High Speed preamble + * transmission + * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register + * content + * @DESCRIPTION return the master code value for I2C High Speed preamble + * transmission + *//*------------------------------------------------------------------------ */ +unsigned char sri2c_master_code_get(unsigned int prm_vc_cfg_i2c_mode) +{ + return extract_bitfield(prm_vc_cfg_i2c_mode, + VC_HSMCODE_POS, VC_HSMCODE_LEN); +} + + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sri2c_low_clock_cycles_count_get + * @BRIEF return the system clock cycles, necessary to count + * the low period of the I2C clock signal + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register + * content + * @param[in] prm_vc_cfg_i2c_clk: PRM_VC_CFG_I2C_CLK register content + * @param[in,out] cycles: I2C clock signal low period (in SYSCLK cycles) + * (RETURNED) + * @param[in,out] us: I2C clock signal low period (in micro-second) + * (RETURNED) + * @DESCRIPTION return the system clock cycles, necessary to count + * the low period of the I2C clock signal + *//*------------------------------------------------------------------------ */ +int sri2c_low_clock_cycles_count_get(unsigned int prm_vc_cfg_i2c_mode, + unsigned int prm_vc_cfg_i2c_clk, + unsigned char *cycles, double *us) +{ + double sysclk; + + CHECK_NULL_ARG(cycles, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(us, OMAPCONF_ERR_ARG); + + if (cpu_is_omap44xx()) { + sysclk = clk44xx_get_system_clock_speed(); + } else if (cpu_is_omap54xx()) { + sysclk = clk54xx_sysclk_rate_get(); + } else { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode)) + *cycles = extract_bitfield(prm_vc_cfg_i2c_clk, + VC_HSSCLL_POS, VC_HSSCLL_LEN); + else + *cycles = extract_bitfield(prm_vc_cfg_i2c_clk, + VC_SCLL_POS, VC_SCLL_LEN); + *us = ((double) *cycles) / sysclk; + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sri2c_high_clock_cycles_count_get + * @BRIEF return the system clock cycles, necessary to count + * the high period of the I2C clock signal + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register + * content + * @param[in] prm_vc_cfg_i2c_clk: PRM_VC_CFG_I2C_CLK register content + * @param[in,out] cycles: I2C clock signal high period (in SYSCLK cycles) + * (RETURNED) + * @param[in,out] us: I2C clock signal low period (in micro-second) + * (RETURNED) + * @DESCRIPTION return the system clock cycles, necessary to count + * the high period of the I2C clock signal + *//*------------------------------------------------------------------------ */ +int sri2c_high_clock_cycles_count_get(unsigned int prm_vc_cfg_i2c_mode, + unsigned int prm_vc_cfg_i2c_clk, + unsigned char *cycles, double *us) +{ + double sysclk; + + CHECK_NULL_ARG(cycles, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(us, OMAPCONF_ERR_ARG); + + if (cpu_is_omap44xx()) { + sysclk = clk44xx_get_system_clock_speed(); + } else if (cpu_is_omap54xx()) { + sysclk = clk54xx_sysclk_rate_get(); + } else { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode)) + *cycles = extract_bitfield(prm_vc_cfg_i2c_clk, + VC_HSSCLH_POS, VC_HSSCLH_LEN); + else + *cycles = extract_bitfield(prm_vc_cfg_i2c_clk, + VC_SCLH_POS, VC_SCLH_LEN); + *us = ((double) *cycles) / sysclk; + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sri2c_config_show + * @BRIEF decode and show VC SR I2C current configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @param[in,out] stream: output file (NULL: no output (silent)) + * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register + * content + * @param[in] prm_vc_cfg_i2c_clk: PRM_VC_CFG_I2C_CLK register content + * @DESCRIPTION decode and show VC SR I2C current configuration + *//*------------------------------------------------------------------------ */ +int sri2c_config_show(FILE *stream, unsigned int prm_vc_cfg_i2c_mode, + unsigned int prm_vc_cfg_i2c_clk) +{ + unsigned char low_cycles, high_cycles; + double low_us, high_us; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row = 0; + + if (!cpu_is_omap44xx() && !cpu_is_omap54xx()) { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + row = 0; + autoadjust_table_init(table); + autoadjust_table_strncpy(table, row++, 0, "SR HS-I2C Configuration"); + + + autoadjust_table_strncpy(table, row, 0, "Double Filtering"); + if (sri2c_is_double_filtering_enabled(prm_vc_cfg_i2c_mode)) + autoadjust_table_strncpy(table, row, 1, + "Enabled (rejects glitches < 2 SYSCLK cycle)"); + else + autoadjust_table_strncpy(table, row, 1, + "Disabled (rejects glitches < 1 SYSCLK cycle)"); + row++; + + autoadjust_table_strncpy(table, row, 0, + "Repeated Start Mode (SRMODEEN)"); + if (sri2c_is_sr_mode_enabled(prm_vc_cfg_i2c_mode)) + autoadjust_table_strncpy(table, row, 1, "Enabled"); + else + autoadjust_table_strncpy(table, row, 1, "Disabled"); + row++; + + autoadjust_table_strncpy(table, row, 0, "High-Speed Mode (HSMODEEN)"); + if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode)) { + autoadjust_table_strncpy(table, row, 1, "Enabled"); + row++; + autoadjust_table_strncpy(table, row, 0, + " HS Master Code (HSMCODE)"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X", sri2c_master_code_get(prm_vc_cfg_i2c_mode)); + } else { + autoadjust_table_strncpy(table, row, 1, "Disabled"); + } + row++; + + autoadjust_table_strncpy(table, row++, 0, "I2C Clock Configuration:"); + sri2c_low_clock_cycles_count_get( + prm_vc_cfg_i2c_mode, prm_vc_cfg_i2c_clk, &low_cycles, &low_us); + sri2c_high_clock_cycles_count_get( + prm_vc_cfg_i2c_mode, prm_vc_cfg_i2c_clk, + &high_cycles, &high_us); + if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode)) { + autoadjust_table_strncpy(table, row, 0, + " Low Period (HSSCLL)"); + snprintf(table[row++][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)", + low_cycles, low_us); + autoadjust_table_strncpy(table, row, 0, + " High Period (HSSCLH)"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)", + high_cycles, high_us); + } else { + autoadjust_table_strncpy(table, row, 0, " Low Period (SCLL)"); + snprintf(table[row++][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)", + low_cycles, low_us); + autoadjust_table_strncpy(table, row, 0, " High Period (SCLH)"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)", + high_cycles, high_us); + } + row++; + + if (stream != NULL) + autoadjust_table_fprint(stream, table, row, 2); + + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vc.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vc.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vc.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vc.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,74 @@ +/* + * + * @Component OMAPCONF + * @Filename vc.h + * @Description VOLTAGE CONTROLLER (VC) Common Definitions & + * Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2006 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __PRCM_VC_H__ +#define __PRCM_VC_H__ + + +#include + + +short int vc_cmd_values_get(unsigned int prm_vc_val_cmd, + unsigned char *cmd_on, unsigned char *cmd_onlp, + unsigned char *cmd_ret, unsigned char *cmd_off); + +unsigned char sri2c_is_double_filtering_enabled( + unsigned int prm_vc_cfg_i2c_mode); +unsigned char sri2c_is_sr_mode_enabled(unsigned int prm_vc_cfg_i2c_mode); +unsigned char sri2c_is_hs_mode_enabled(unsigned int prm_vc_cfg_i2c_mode); +unsigned char sri2c_master_code_get(unsigned int prm_vc_cfg_i2c_mode); + +int sri2c_low_clock_cycles_count_get(unsigned int prm_vc_cfg_i2c_mode, + unsigned int prm_vc_cfg_i2c_clk, + unsigned char *cycles, double *us); +int sri2c_high_clock_cycles_count_get(unsigned int prm_vc_cfg_i2c_mode, + unsigned int prm_vc_cfg_i2c_clk, + unsigned char *cycles, double *us); + +int sri2c_config_show(FILE *stream, unsigned int prm_vc_cfg_i2c_mode, + unsigned int prm_vc_cfg_i2c_clk); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vp.c tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vp.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vp.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vp.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,963 @@ +/* + * + * @Component OMAPCONF + * @Filename vp.c + * @Description VOLTAGE PROCESSOR (VP) Common Definitions + * & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include + + +/* #define VP_DEBUG */ +#ifdef VP_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +/* VP bitfields */ +#define VP_ERROROFFSET_POS 24 +#define VP_ERROROFFSET_LEN 8 +#define VP_ERRORGAIN_POS 16 +#define VP_ERRORGAIN_LEN 8 +#define VP_INITVOLTAGE_POS 8 +#define VP_INITVOLTAGE_LEN 8 +#define VP_TIMEOUTEN_POS 3 +#define VP_VPENABLE_POS 0 + +#define VP_VPINIDLE_POS 0 + +#define VP_VDDMAX_POS 24 +#define VP_VDDMAX_LEN 8 +#define VP_VDDMIN_POS 16 +#define VP_VDDMIN_LEN 8 +#define VP_TIMEOUT_POS 0 +#define VP_TIMEOUT_LEN 16 + +#define VP_FORCEUPDATEWAIT_POS 8 +#define VP_FORCEUPDATEWAIT_LEN 24 +#define VP_VPVOLTAGE_POS 0 +#define VP_VPVOLTAGE_LEN 8 + +#define VP_SMPSOFTWAREAITTIMEMAX_POS 8 +#define VP_SMPSOFTWAREAITTIMEMAX_LEN 16 +#define VP_VSTEPMAX_POS 0 +#define VP_VSTEPMAX_LEN 8 + +#define VP_SMPSOFTWAREAITTIMEMIN_POS 8 +#define VP_SMPSOFTWAREAITTIMEMIN_LEN 16 +#define VP_VSTEPMIN_POS 0 +#define VP_VSTEPMIN_LEN 8 + + +#define VP_AUDIT_SHOW_STATUS(curr, golden) \ + if (curr == golden) { \ + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "Pass"); \ + } else { \ + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "FAIL"); \ + (*err_nbr)++; \ + } + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_error_offset_get + * @BRIEF return VP error offset + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * @param[in] vp_config: VP_xyz_CONFIG register content + * @param[in,out] offset_raw: VP error offset RAW HEX value (RETURNED) + * @param[in,out] offset: VP error offset in % (signed) (RETURNED) + * @DESCRIPTION return VP error offset + *//*------------------------------------------------------------------------ */ +int vp_error_offset_get(unsigned int vp_config, + signed char *offset_raw, double *offset) +{ + CHECK_NULL_ARG(offset_raw, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(offset, OMAPCONF_ERR_ARG); + + *offset_raw = (signed char) extract_bitfield(vp_config, + VP_ERROROFFSET_POS, VP_ERROROFFSET_LEN); + *offset = vp_error_offset_hex2percent(*offset_raw); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_error_offset_hex2percent + * @BRIEF convert VP error offset HEX signed value into % + * @RETURNS VP error offset in % + * @param[in] offset: VP error offset RAW HEX value + * @DESCRIPTION convert VP error offset HEX signed value into % + *//*------------------------------------------------------------------------ */ +double vp_error_offset_hex2percent(signed char offset) +{ + return (double) offset * 0.8; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_error_gain_get + * @BRIEF return VP error gain + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * @param[in] vp_config: VP_xyz_CONFIG register content + * @param[in] vdd_id: voltage domain ID + * @param[in,out] gain_raw: VP error gain RAW HEX value (RETURNED) + * @param[in,out] gain: VP error gain in mV/% (signed) (RETURNED) + * @DESCRIPTION return VP error gain + *//*------------------------------------------------------------------------ */ +int vp_error_gain_get(unsigned int vp_config, unsigned short vdd_id, + signed char *gain_raw, double *gain) +{ + CHECK_NULL_ARG(gain_raw, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(gain, OMAPCONF_ERR_ARG); + + *gain_raw = (signed char) extract_bitfield(vp_config, + VP_ERRORGAIN_POS, VP_ERRORGAIN_LEN); + *gain = vp_error_gain_hex2percent(*gain_raw, vdd_id); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_error_gain_hex2percent + * @BRIEF convert VP error gain HEX signed value into mV/% + * @RETURNS VP error gain in mV/% + * @param[in] gain: VP error gain RAW HEX value + * @param[in] vdd_id: voltage domain ID + * @DESCRIPTION convert VP error gain HEX signed value into mV/% + *//*------------------------------------------------------------------------ */ +double vp_error_gain_hex2percent(signed char gain, unsigned short vdd_id) +{ + double step_mv; + + step_mv = (double) smps_step_get(vdd_id2smps_id(vdd_id)) / 1000.0; + + return (double) gain * step_mv / 100.0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_init_voltage_get + * @BRIEF return VP initial voltage + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_config: VP_xyz_CONFIG register content + * @param[in] vdd_id: voltage domain ID + * @param[in,out] init_vsel: initial voltage (vsel command) (RETURNED) + * @param[in,out] init_uv: initial voltage (in micro-volt) (RETURNED) + * @DESCRIPTION return VP initial voltage + *//*------------------------------------------------------------------------ */ +int vp_init_voltage_get(unsigned int vp_config, unsigned short vdd_id, + unsigned char *init_vsel, unsigned int *init_uv) +{ + CHECK_NULL_ARG(init_vsel, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(init_uv, OMAPCONF_ERR_ARG); + + *init_vsel = (unsigned char) extract_bitfield(vp_config, + VP_INITVOLTAGE_POS, VP_INITVOLTAGE_LEN); + *init_uv = smps_vsel2uvolt(vdd_id2smps_id(vdd_id), *init_vsel); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_vc_timeout_is_enabled + * @BRIEF check if VC Timeout is enabled + * @RETURNS 1 if VC Timeout is enabled + * 0 if VC Timeout is disabled + * @param[in] vp_config: VP_xyz_CONFIG register content + * @DESCRIPTION check if VC Timeout is enabled + *//*------------------------------------------------------------------------ */ +unsigned char vp_vc_timeout_is_enabled(unsigned int vp_config) +{ + return extract_bit(vp_config, VP_TIMEOUTEN_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_is_enabled + * @BRIEF check if VP is enabled + * @RETURNS 1 if VP is enabled + * 0 if VP is disabled + * @param[in] vp_config: VP_xyz_CONFIG register content + * @DESCRIPTION check if VP is enabled + *//*------------------------------------------------------------------------ */ +unsigned char vp_is_enabled(unsigned int vp_config) +{ + return extract_bit(vp_config, VP_VPENABLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_is_idle + * @BRIEF check if VP is idle + * @RETURNS 1 if VP is idle + * 0 if VP is not idle (running) + * @param[in] vp_status: VP_xyz_STATUS register content + * @DESCRIPTION check if VP is idle + *//*------------------------------------------------------------------------ */ +unsigned char vp_is_idle(unsigned int vp_status) +{ + return extract_bit(vp_status, VP_VPINIDLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_min_voltage_get + * @BRIEF return VP minimum supply voltage + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_vlimitto: VP_xyz_VLIMITTO register content + * @param[in] vdd_id: voltage domain ID + * @param[in,out] min_vsel: minimum supply voltage (vsel command) + * (RETURNED) + * @param[in,out] min_uv: minimum supply voltage (in micro-volt) + * (RETURNED) + * @DESCRIPTION return VP minimum supply voltage + *//*------------------------------------------------------------------------ */ +int vp_min_voltage_get(unsigned int vp_vlimitto, unsigned short vdd_id, + unsigned char *min_vsel, unsigned int *min_uv) +{ + CHECK_NULL_ARG(min_vsel, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(min_uv, OMAPCONF_ERR_ARG); + + *min_vsel = (unsigned char) extract_bitfield(vp_vlimitto, + VP_VDDMIN_POS, VP_VDDMIN_LEN); + *min_uv = smps_vsel2uvolt(vdd_id2smps_id(vdd_id), *min_vsel); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_max_voltage_get + * @BRIEF return VP maximum supply voltage + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_vlimitto: VP_xyz_VLIMITTO register content + * @param[in] vdd_id: voltage domain ID + * @param[in,out] max_vsel: maximum supply voltage (vsel command) + * (RETURNED) + * @param[in,out] max_uv: maximum supply voltage (in micro-volt) + * (RETURNED) + * @DESCRIPTION return VP maximum supply voltage + *//*------------------------------------------------------------------------ */ +int vp_max_voltage_get(unsigned int vp_vlimitto, unsigned short vdd_id, + unsigned char *max_vsel, unsigned int *max_uv) +{ + CHECK_NULL_ARG(max_vsel, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(max_uv, OMAPCONF_ERR_ARG); + + *max_vsel = (unsigned char) extract_bitfield(vp_vlimitto, + VP_VDDMAX_POS, VP_VDDMAX_LEN); + *max_uv = smps_vsel2uvolt(vdd_id2smps_id(vdd_id), *max_vsel); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_last_voltage_get + * @BRIEF return the last voltage set by the voltage processor + * for a domain. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_voltage: VP_xyz_VOLTAGE register content + * @param[in] vdd_id: voltage domain ID + * @param[in,out] vsel: last supply voltage programmed by VP + * (vsel command) (RETURNED) + * @param[in,out] uv: last supply voltage programmed by VP + * (in micro-volt) (RETURNED) + * @DESCRIPTION return the last voltage set by the voltage processor + * for a domain. + * NB: SR/VP/VC HAVE TO BE AT LEAST INITIALIZED + * (SR COULD BE DISABLED) OTHERWISE THIS VALUE HAS NO SENSE + *//*------------------------------------------------------------------------ */ +int vp_last_voltage_get(unsigned int vp_voltage, unsigned short vdd_id, + unsigned char *vsel, unsigned int *uv) +{ + CHECK_NULL_ARG(vsel, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(uv, OMAPCONF_ERR_ARG); + + *vsel = (unsigned char) extract_bitfield(vp_voltage, 0, + smps_vsel_len_get(vdd_id2smps_id(vdd_id))); + + *uv = smps_vsel2uvolt(vdd_id2smps_id(vdd_id), *vsel); + dprintf("%s(%u): VP_VOLTAGE=0x%08X, vsel=%02X voltage=%uV\n", __func__, + vdd_id, vp_voltage, *vsel, *uv); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_vc_timeout_get + * @BRIEF return VC maximum response wait time + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_vlimitto: VP_xyz_VLIMITTO register content + * @param[in,out] timeout_cycles: maximum response wait time + * (SYSCLK cycles) (RETURNED) + * @param[in,out] timeout_us: maximum response wait time (in micro-second) + * (RETURNED) + * @DESCRIPTION return VC maximum response wait time + *//*------------------------------------------------------------------------ */ +int vp_vc_timeout_get(unsigned int vp_vlimitto, + unsigned int *timeout_cycles, unsigned int *timeout_us) +{ + double sysclk; + + CHECK_NULL_ARG(timeout_cycles, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(timeout_us, OMAPCONF_ERR_ARG); + + if (cpu_is_omap44xx()) { + sysclk = clk44xx_get_system_clock_speed(); + } else if (cpu_is_omap54xx()) { + sysclk = clk54xx_sysclk_rate_get(); + } else { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + *timeout_cycles = extract_bitfield(vp_vlimitto, + VP_TIMEOUT_POS, VP_TIMEOUT_LEN); + *timeout_us = *timeout_cycles / sysclk; + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_force_update_wait_time_get + * @BRIEF return the time voltage processor needs to wait for + * SMPS to be settled after receiving SMPS acknowledge. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_voltage: VP_xyz_VOLTAGE register content + * @param[in,out] time_cycles: time VP needs to wait for SMPS to be + * settled (in SYSCLK cycles) (returned) + * @param[in,out] time VP needs to wait for SMPS to be settled + * (in micro-second) (returned) + * @DESCRIPTION return the time voltage processor needs to wait for + * SMPS to be settled after receiving SMPS acknowledge. + *//*------------------------------------------------------------------------ */ +int vp_force_update_wait_time_get(unsigned int vp_voltage, + unsigned int *time_cycles, unsigned int *time_us) +{ + double sysclk; + + CHECK_NULL_ARG(time_cycles, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(time_us, OMAPCONF_ERR_ARG); + + if (cpu_is_omap44xx()) { + sysclk = clk44xx_get_system_clock_speed(); + } else if (cpu_is_omap54xx()) { + sysclk = clk54xx_sysclk_rate_get(); + } else { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + *time_cycles = extract_bitfield(vp_voltage, + VP_FORCEUPDATEWAIT_POS, VP_FORCEUPDATEWAIT_LEN); + *time_us = *time_cycles / sysclk; + + return 0; + +} + + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_max_step_get + * @BRIEF return VP maximum voltage step + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * @param[in] vp_vstepmax: VP_xyz_VSTEPMAX register content + * @param[in] vdd_id: voltage domain ID + * @param[in,out] max_step: maximum voltage step (vsel command) (RETURNED) + * @param[in,out] max_uv: maximum voltage step (in micro-volt) (RETURNED) + * @DESCRIPTION return VP maximum voltage step + *//*------------------------------------------------------------------------ */ +int vp_max_step_get(unsigned int vp_vstepmax, unsigned short vdd_id, + unsigned int *max_step, unsigned int *max_uv) +{ + CHECK_NULL_ARG(max_step, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(max_uv, OMAPCONF_ERR_ARG); + + *max_step = extract_bitfield(vp_vstepmax, + VP_VSTEPMAX_POS, VP_VSTEPMAX_LEN); + *max_uv = *max_step * smps_step_get(vdd_id2smps_id(vdd_id)); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_min_step_get + * @BRIEF return VP minimum voltage step + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * @param[in] vp_vstepmin: VP_xyz_VSTEPMIN register content + * @param[in] vdd_id: voltage domain ID + * @param[in,out] min_step: minimum voltage step (vsel command) (RETURNED) + * @param[in,out] min_uv: minimum voltage step (in micro-volt) (RETURNED) + * @DESCRIPTION return VP minimum voltage step + *//*------------------------------------------------------------------------ */ +int vp_min_step_get(unsigned int vp_vstepmin, unsigned short vdd_id, + unsigned int *min_step, unsigned int *min_uv) +{ + CHECK_NULL_ARG(min_step, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(min_uv, OMAPCONF_ERR_ARG); + + *min_step = extract_bitfield(vp_vstepmin, + VP_VSTEPMIN_POS, VP_VSTEPMIN_LEN); + *min_uv = *min_step * smps_step_get(vdd_id2smps_id(vdd_id)); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_positive_slew_rate_get + * @BRIEF return VP slew rate for positive voltage step + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_vstepmax: VP_xyz_VSTEPMAX register content + * @param[in,out] cycles: VP slew rate for positive voltage step + * in number of cycles per step (RETURNED) + * @param[in,out] us: VP slew rate for positive voltage step + * in micro-seconds per step (RETURNED) + * @DESCRIPTION return VP slew rate for positive voltage step + *//*------------------------------------------------------------------------ */ +int vp_positive_slew_rate_get(unsigned int vp_vstepmax, + unsigned int *cycles, unsigned int *us) +{ + int ret; + + CHECK_NULL_ARG(cycles, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(us, OMAPCONF_ERR_ARG); + + *cycles = extract_bitfield(vp_vstepmax, + VP_SMPSOFTWAREAITTIMEMAX_POS, VP_SMPSOFTWAREAITTIMEMAX_LEN); + ret = vp_slew_rate_cycles2us(*cycles); + if (ret >= 0) { + *us = ret; + return 0; + } else { + *us = 0; + return ret; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_negative_slew_rate_get + * @BRIEF return VP slew rate for negative voltage step + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * @param[in] vp_vstepmin: VP_xyz_VSTEPMIN register content + * @param[in,out] cycles: VP slew rate for negative voltage step + * in number of cycles per step (RETURNED) + * @param[in,out] us: VP slew rate for negative voltage step + * in micro-seconds per step (RETURNED) + * @DESCRIPTION return VP slew rate for negative voltage step + *//*------------------------------------------------------------------------ */ +int vp_negative_slew_rate_get(unsigned int vp_vstepmin, + unsigned int *cycles, unsigned int *us) +{ + int ret; + + CHECK_NULL_ARG(cycles, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(us, OMAPCONF_ERR_ARG); + + *cycles = extract_bitfield(vp_vstepmin, + VP_SMPSOFTWAREAITTIMEMIN_POS, VP_SMPSOFTWAREAITTIMEMIN_LEN); + ret = vp_slew_rate_cycles2us(*cycles); + if (ret >= 0) { + *us = ret; + return 0; + } else { + *us = 0; + return ret; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_slew_rate_cycles2us + * @BRIEF convert VP slew rate HEX value into micro-seconds + * @RETURNS VP slew rate in micro-seconds + * OMAPCONF_ERR_CPU + * @param[in] cycles: VP slew rate for negative voltage step in + * number of cycles per step + * @DESCRIPTION convert VP slew rate HEX value into micro-seconds + *//*------------------------------------------------------------------------ */ +int vp_slew_rate_cycles2us(unsigned int cycles) +{ + double sysclk; + + if (cpu_is_omap44xx()) { + sysclk = clk44xx_get_system_clock_speed(); + } else if (cpu_is_omap54xx()) { + sysclk = clk54xx_sysclk_rate_get(); + } else { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + return (unsigned int) ((cycles / sysclk) + 1); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_config_show + * @BRIEF decode and show VP current configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @param[in,out] stream: output file (NULL: no output (silent)) + * @param[in,out] vp_regs: VP registers content for the 3 VP instances + * (MPU, IVA/MM, CORE) + * @DESCRIPTION decode and show VP current configuration + *//*------------------------------------------------------------------------ */ +int vp_config_show(FILE *stream, vp_registers vp_regs[3]) +{ + unsigned int cycles, us, step, uv; + unsigned char vsel; + + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int i, row = 0; + signed char vp_offset_raw, vp_gain_raw; + double vp_offset, vp_gain; + + CHECK_NULL_ARG(vp_regs, OMAPCONF_ERR_ARG); + if (!cpu_is_omap44xx() && !cpu_is_omap54xx()) { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + + #ifdef VP_DEBUG + autoadjust_table_init(table); + autoadjust_table_strncpy(table, row, 0, "VP Registers"); + autoadjust_table_strncpy(table, row, 1, "VP MPU"); + if (cpu_is_omap44xx()) + autoadjust_table_strncpy(table, row, 2, "VP MM"); + else + autoadjust_table_strncpy(table, row, 2, "VP MM"); + autoadjust_table_strncpy(table, row, 3, "VP CORE"); + row++; + for (i = 0; i < 3; i++) { + row = 1; + autoadjust_table_strncpy(table, row, 0, "VP_CONFIG"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + vp_regs[i].vp_config); + autoadjust_table_strncpy(table, row, 0, "VP_STATUS"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + vp_regs[i].vp_status); + autoadjust_table_strncpy(table, row, 0, "VP_VLIMITTO"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + vp_regs[i].vp_vlimitto); + autoadjust_table_strncpy(table, row, 0, "VP_VOLTAGE"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + vp_regs[i].vp_voltage); + autoadjust_table_strncpy(table, row, 0, "VP_VSTEPMAX"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + vp_regs[i].vp_vstepmax); + autoadjust_table_strncpy(table, row, 0, "VP_VSTEPMIN"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + vp_regs[i].vp_vstepmin); + } + autoadjust_table_print(table, row, 4); + #endif + + + row = 0; + autoadjust_table_init(table); + autoadjust_table_strncpy(table, row, 0, "PRM VP Configuration"); + autoadjust_table_strncpy(table, row, 1, "VP_MPU"); + if (cpu_is_omap44xx()) + autoadjust_table_strncpy(table, row, 2, "VP_IVA"); + else + autoadjust_table_strncpy(table, row, 2, "VP_MM"); + autoadjust_table_strncpy(table, row++, 3, "VP_CORE"); + + for (i = 0; i < 3; i++) { + row = 1; + autoadjust_table_strncpy(table, row, 0, "Mode"); + if (vp_is_enabled(vp_regs[i].vp_config) == 1) + autoadjust_table_strncpy(table, row, i + 1, "Enabled"); + else + autoadjust_table_strncpy(table, row, i + 1, "Disabled"); + row++; + + autoadjust_table_strncpy(table, row, 0, "Status"); + if (vp_is_idle(vp_regs[i].vp_status) == 1) + autoadjust_table_strncpy(table, row, i + 1, "Idle"); + else + autoadjust_table_strncpy(table, row, i + 1, + "Processing"); + row++; + + autoadjust_table_strncpy(table, row, 0, "VC Response Timeout"); + if (vp_vc_timeout_is_enabled(vp_regs[i].vp_config) == 1) { + autoadjust_table_strncpy(table, row, i + 1, "Enabled"); + row++; + autoadjust_table_strncpy(table, row, 0, + " Timeout (SysClk cycles, us)"); + vp_vc_timeout_get(vp_regs[i].vp_vlimitto, &cycles, &us); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%u (%uus)", cycles, us); + } else { + autoadjust_table_strncpy(table, row, i + 1, "Disabled"); + } + row++; + + autoadjust_table_strncpy(table, row, 0, + "Error Gain (hex, mV/%%)"); + vp_error_gain_get(vp_regs[i].vp_config, vp_regs[i].vdd_id, + &vp_gain_raw, &vp_gain); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV/%%)", vp_gain_raw, vp_gain); + row++; + + autoadjust_table_strncpy(table, row, 0, + "Error Offset (hex, %%)"); + vp_error_offset_get(vp_regs[i].vp_config, + &vp_offset_raw, &vp_offset); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lf%%)", vp_offset_raw, vp_offset); + row++; + + autoadjust_table_strncpy(table, row, 0, + "Initial Voltage (step, V)"); + vp_init_voltage_get(vp_regs[i].vp_config, vp_regs[i].vdd_id, + &vsel, &uv); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", vsel, (double) uv / 1000000.0); + row++; + + autoadjust_table_strncpy(table, row, 0, + "MAX Voltage (step, V)"); + vp_max_voltage_get(vp_regs[i].vp_vlimitto, vp_regs[i].vdd_id, + &vsel, &uv); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", vsel, (double) uv / 1000000.0); + row++; + + autoadjust_table_strncpy(table, row, 0, + "MIN Voltage (step, V)"); + vp_min_voltage_get(vp_regs[i].vp_vlimitto, vp_regs[i].vdd_id, + &vsel, &uv); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", vsel, (double) uv / 1000000.0); + row++; + + autoadjust_table_strncpy(table, row, 0, + "Current Voltage (step, V)"); + vp_last_voltage_get(vp_regs[i].vp_voltage, vp_regs[i].vdd_id, + &vsel, &uv); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", vsel, (double) uv / 1000000.0); + row++; + + autoadjust_table_strncpy(table, row, 0, + "Force Update Wait (cycles, us)"); + vp_force_update_wait_time_get(vp_regs[i].vp_voltage, + &cycles, &us); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "%u (%uus)", + cycles, us); + row++; + + autoadjust_table_strncpy(table, row, 0, "MAX Voltage Step"); + vp_max_step_get(vp_regs[i].vp_vstepmax, vp_regs[i].vdd_id, + &step, &uv); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV)", step, (double) uv / 1000.0); + row++; + + autoadjust_table_strncpy(table, row, 0, + "SMPSWAITTIMEMAX (cycles/step, us)"); + vp_positive_slew_rate_get(vp_regs[i].vp_vstepmax, &cycles, &us); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "%u (%uus)", + cycles, us); + row++; + + autoadjust_table_strncpy(table, row, 0, "MIN Voltage Step"); + vp_min_step_get(vp_regs[i].vp_vstepmin, vp_regs[i].vdd_id, + &step, &uv); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV)", step, (double) uv / 1000.0); + row++; + + autoadjust_table_strncpy(table, row, 0, + "SMPSWAITTIMEMIN (cycles/step, us)"); + vp_negative_slew_rate_get(vp_regs[i].vp_vstepmin, &cycles, &us); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "%u (%uus)", + cycles, us); + row++; + } + + + if (stream != NULL) + autoadjust_table_fprint(stream, table, row, 4); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION vp_config_audit + * @BRIEF audit Voltage Processor (VP) configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in] stream: output file (NULL: no output (silent)) + * @param[in] vp_name: voltage processor name + * @param[in] opp_name: OPP name + * @param[in] vp_regs: VP registers content + * @param[in] vp_golden_settings: expected ("golden") VP settings + * @param[in,out] err_nbr: audit error number + * @param[in,out] wng_nbr: audit warning number + * @DESCRIPTION audit Voltage Processor (VP) configuration by comparison + * with expected ("golden") settings + *//*------------------------------------------------------------------------ */ +int vp_config_audit(FILE *stream, const char *vp_name, const char *opp_name, + vp_registers *vp_regs, const vp_audit_settings *vp_golden_settings, + unsigned int *err_nbr, unsigned int *wng_nbr) +{ + signed char errgain_curr, errgain_expected; + double errgain_curr2, errgain_expected2; + signed char erroffset_curr, erroffset_expected; + double erroffset_curr2, erroffset_expected2; + unsigned int current, expected; + unsigned int current2, expected2; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row; + static const char mode_table[2][16] = { + "Disabled ", + "Enabled "}; + + CHECK_NULL_ARG(vp_name, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(vp_regs, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(vp_golden_settings, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + if (!cpu_is_omap44xx() && !cpu_is_omap54xx()) { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + *err_nbr = 0; + *wng_nbr = 0; + row = 0; + autoadjust_table_init(table); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "PRM %s Configuration AUDIT (@%s)", vp_name, opp_name); + autoadjust_table_strncpy(table, row, 1, "Current"); + autoadjust_table_strncpy(table, row, 2, "Expected"); + autoadjust_table_strncpy(table, row, 3, "STATUS"); + row++; + + autoadjust_table_strncpy(table, row, 0, "Mode"); + current = vp_is_enabled(vp_regs->vp_config); + expected = vp_golden_settings->mode; + autoadjust_table_strncpy(table, row, 1, (char *) mode_table[current]); + autoadjust_table_strncpy(table, row, 2, (char *) mode_table[expected]); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, "VC Response Timeout"); + current = vp_vc_timeout_is_enabled(vp_regs->vp_config); + expected = vp_golden_settings->vc_timeout_mode; + autoadjust_table_strncpy(table, row, 1, (char *) mode_table[current]); + autoadjust_table_strncpy(table, row, 2, (char *) mode_table[expected]); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, " Timeout (SysClk cycles)"); + vp_vc_timeout_get(vp_regs->vp_vlimitto, + ¤t, ¤t2); + expected = vp_golden_settings->vc_timeout_cycles; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u", current); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u", expected); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, + "Force Update Wait (SysClk cycles)"); + vp_force_update_wait_time_get(vp_regs->vp_voltage, + ¤t, ¤t2); + expected = vp_golden_settings->force_update_wait_time; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u", current); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u", expected); + VP_AUDIT_SHOW_STATUS(current, expected); + + + autoadjust_table_strncpy(table, row, 0, "MAX Voltage Step"); + vp_max_step_get(vp_regs->vp_vstepmax, vp_regs->vdd_id, + ¤t, ¤t2); + expected = vp_golden_settings->vstepmax; + expected2 = expected * smps_step_get(vdd_id2smps_id(vp_regs->vdd_id)); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV)", current, (double) current2 / 1000.0); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV)", expected, (double) expected2 / 1000.0); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, + "SMPSWAITTIMEMAX (cycles/step, us)"); + vp_positive_slew_rate_get(vp_regs->vp_vstepmax, ¤t, ¤t2); + expected = vp_golden_settings->positive_slew_rate; + expected2 = vp_slew_rate_cycles2us(expected); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u (%uus)", + current, current2); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u (%uus)", + expected, expected2); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, "MIN Voltage Step"); + vp_min_step_get(vp_regs->vp_vstepmin, vp_regs->vdd_id, + ¤t, ¤t2); + expected = vp_golden_settings->vstepmin; + expected2 = expected * smps_step_get(vdd_id2smps_id(vp_regs->vdd_id)); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV)", current, (double) current2 / 1000.0); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV)", expected, (double) expected2 / 1000.0); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, + "SMPSWAITTIMEMIN (cycles/step, us)"); + vp_negative_slew_rate_get(vp_regs->vp_vstepmin, ¤t, ¤t2); + expected = vp_golden_settings->negative_slew_rate; + expected2 = vp_slew_rate_cycles2us(expected); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u (%uus)", + current, current2); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u (%uus)", + expected, expected2); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, "Initial Voltage (step, V)"); + vp_init_voltage_get(vp_regs->vp_config, vp_regs->vdd_id, + (unsigned char *) ¤t, ¤t2); + expected = vp_golden_settings->init_voltage; + expected2 = smps_vsel2uvolt(vdd_id2smps_id(vp_regs->vdd_id), expected); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", current, (double) current2 / 1000000.0); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", expected, (double) expected2 / 1000000.0); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, "MAX Voltage (step, V)"); + vp_max_voltage_get(vp_regs->vp_vlimitto, vp_regs->vdd_id, + (unsigned char *) ¤t, ¤t2); + expected = vp_golden_settings->max_voltage; + expected2 = smps_vsel2uvolt(vdd_id2smps_id(vp_regs->vdd_id), expected); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", current, (double) current2 / 1000000.0); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", expected, (double) expected2 / 1000000.0); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, "MIN Voltage (step, V)"); + vp_min_voltage_get(vp_regs->vp_vlimitto, vp_regs->vdd_id, + (unsigned char *) ¤t, ¤t2); + expected = vp_golden_settings->min_voltage; + expected2 = smps_vsel2uvolt(vdd_id2smps_id(vp_regs->vdd_id), expected); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", current, (double) current2 / 1000000.0); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.6lfV)", expected, (double) expected2 / 1000000.0); + VP_AUDIT_SHOW_STATUS(current, expected); + + autoadjust_table_strncpy(table, row, 0, "Error Gain (hex, mV/%)"); + vp_error_gain_get(vp_regs->vp_config, vp_regs->vdd_id, + &errgain_curr, &errgain_curr2); + errgain_expected = vp_golden_settings->error_gain; + errgain_expected2 = vp_error_gain_hex2percent(errgain_expected, + vp_regs->vdd_id); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV/%%)", errgain_curr, errgain_curr2); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lfmV/%%)", errgain_expected, errgain_expected2); + VP_AUDIT_SHOW_STATUS(errgain_curr, errgain_expected); + + autoadjust_table_strncpy(table, row, 0, "Error Offset (hex, %)"); + vp_error_offset_get(vp_regs->vp_config, + &erroffset_curr, &erroffset_curr2); + erroffset_expected = vp_golden_settings->error_offset; + erroffset_expected2 = vp_error_offset_hex2percent(erroffset_expected); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lf%%)", erroffset_curr, erroffset_curr2); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.3lf%%)", erroffset_expected, erroffset_expected2); + VP_AUDIT_SHOW_STATUS(erroffset_curr, erroffset_expected); + + if (stream != NULL) { + autoadjust_table_fprint(stream, table, row, 4); + fprintf(stream, "NB:\n"); + fprintf(stream, " - Report 'FAIL' when current setting is " + "different than golden setting.\n"); + fprintf(stream, " - Report 'Pass' when current setting " + "matches golden setting.\n\n"); + } + + return 0; +} + diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vp.h tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vp.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/prcm/vp.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/prcm/vp.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,119 @@ +/* + * + * @Component OMAPCONF + * @Filename vp.h + * @Description VOLTAGE PROCESSOR (VP) Common Definitions + * & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __PRCM_VP_H__ +#define __PRCM_VP_H__ + + +#include + + +typedef struct { + unsigned short vdd_id; + unsigned int vp_config; + unsigned int vp_status; + unsigned int vp_vlimitto; + unsigned int vp_voltage; + unsigned int vp_vstepmax; + unsigned int vp_vstepmin; +} vp_registers; + + +typedef struct { + unsigned char mode; + unsigned char vc_timeout_mode; + unsigned int vc_timeout_cycles; + unsigned char init_voltage; + unsigned char max_voltage; + unsigned char min_voltage; + signed char error_gain; + signed char error_offset; + unsigned int force_update_wait_time; + unsigned int vstepmax; + unsigned int positive_slew_rate; + unsigned int vstepmin; + unsigned int negative_slew_rate; +} vp_audit_settings; + + +int vp_error_offset_get(unsigned int vp_config, + signed char *offset_raw, double *offset); +double vp_error_offset_hex2percent(signed char offset); +int vp_error_gain_get(unsigned int vp_config, unsigned short vdd_id, + signed char *gain_raw, double *gain); +double vp_error_gain_hex2percent(signed char gain, unsigned short vdd_id); +int vp_init_voltage_get(unsigned int vp_config, + unsigned short vdd_id, unsigned char *init_vsel, + unsigned int *init_uv); +unsigned char vp_vc_timeout_is_enabled(unsigned int vp_config); +unsigned char vp_is_enabled(unsigned int vp_config); +unsigned char vp_is_idle(unsigned int vp_status); +int vp_min_voltage_get(unsigned int vp_vlimitto, unsigned short vdd_id, + unsigned char *min_vsel, unsigned int *min_uv); +int vp_max_voltage_get(unsigned int vp_vlimitto, unsigned short vdd_id, + unsigned char *max_vsel, unsigned int *max_uv); +int vp_last_voltage_get(unsigned int vp_voltage, unsigned short vdd_id, + unsigned char *vsel, unsigned int *uv); +int vp_vc_timeout_get(unsigned int vp_vlimitto, + unsigned int *timeout_cycles, unsigned int *timeout_us); +int vp_force_update_wait_time_get(unsigned int vp_voltage, + unsigned int *time_cycles, unsigned int *time_us); +int vp_max_step_get(unsigned int vp_vstepmax, unsigned short vdd_id, + unsigned int *max_step, unsigned int *max_uv); +int vp_min_step_get(unsigned int vp_vstepmin, unsigned short vdd_id, + unsigned int *min_step, unsigned int *min_uv); +int vp_positive_slew_rate_get(unsigned int vp_vstepmax, + unsigned int *cycles, unsigned int *us); +int vp_negative_slew_rate_get(unsigned int vp_vstepmin, + unsigned int *cycles, unsigned int *us); +int vp_slew_rate_cycles2us(unsigned int cycles); + +int vp_config_show(FILE *stream, vp_registers vp_regs[3]); +int vp_config_audit(FILE *stream, const char *vp_name, const char *opp_name, + vp_registers *vp_regs, const vp_audit_settings *vp_golden_settings, + unsigned int *err_nbr, unsigned int *wng_nbr); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/sr.c tiomapconf-1.61.1/arch/arm/mach-omap/common/sr.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/sr.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/sr.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1815 @@ +/* + * + * @Component OMAPCONF + * @Filename sr.c + * @Description SMARTREFLEX Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2006 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define SR_DEBUG */ +#ifdef SR_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +#define SR_ACCUMDATA_POS 22 +#define SR_ACCUMDATA_LEN 10 +#define SR_SRCLKLENGTH_POS 12 +#define SR_SRCLKLENGTH_LEN 10 +#define SR_SRENABLE_POS 11 +#define SR_SENENABLE_POS 10 +#define SR_ERRORGENERATORENABLE_POS 9 +#define SR_MINMAXAVGENABLE_POS 8 +#define SR_LVTSENENABLE_POS 4 +#define SR_LVTSENNENABLE_POS 3 +#define SR_LVTSENPENABLE_POS 2 +#define SR_SENNENABLE_POS 1 +#define SR_SENPENABLE_POS 0 + +#define SR_AVGERRVALID_POS 3 +#define SR_MINMAXAVGVALID_POS 2 +#define SR_ERRORGENERATORVALID_POS 1 +#define SR_MINMAXAVGACCUMVALID_POS 0 + +#define SR_SENPVAL_POS 16 +#define SR_SENPVAL_LEN 16 +#define SR_SENNVAL_POS 0 +#define SR_SENNVAL_LEN 16 + +#define SR_SENPMIN_POS 16 +#define SR_SENPMIN_LEN 16 +#define SR_SENNMIN_POS 0 +#define SR_SENNMIN_LEN 16 + +#define SR_SENPMAX_POS 16 +#define SR_SENPMAX_LEN 16 +#define SR_SENNMAX_POS 0 +#define SR_SENNMAX_LEN 16 + +#define SR_SENPAVG_POS 16 +#define SR_SENPAVG_LEN 16 +#define SR_SENNAVG_POS 0 +#define SR_SENNAVG_LEN 16 + +#define SR_SENPAVGWEIGHT_POS 2 +#define SR_SENPAVGWEIGHT_LEN 2 +#define SR_SENNAVGWEIGHT_POS 0 +#define SR_SENNAVGWEIGHT_LEN 2 + +#define SR_SENPGAIN_POS 20 +#define SR_SENPGAIN_LEN 4 +#define SR_SENNGAIN_POS 16 +#define SR_SENNGAIN_LEN 4 +#define SR_SENPRN_POS 8 +#define SR_SENPRN_LEN 8 +#define SR_SENNRN_POS 0 +#define SR_SENNRN_LEN 8 + +#define SR_MCUACCUMINTSTATRAW_POS 3 +#define SR_MCUVALIDINTSTATRAW_POS 2 +#define SR_MCUBOUNDSINTSTATRAW_POS 1 +#define SR_MCUDISABLEACKINTSTATRAW_POS 0 + +#define SR_MCUACCUMINTSTATENA_POS 3 +#define SR_MCUVALIDINTSTATENA_POS 2 +#define SR_MCUBOUNDSINTSTATENA_POS 1 +#define SR_MCUDISABLEACKINTSTATENA_POS 0 + +#define SR_MCUACCUMINTENASET_POS 3 +#define SR_MCUVALIDINTENASET_POS 2 +#define SR_MCUBOUNDSINTENASET_POS 1 +#define SR_MCUDISABLEACKINTENASET_POS 0 + +#define SR_MCUACCUMINTENACLR_POS 3 +#define SR_MCUVALIDINTENACLR_POS 2 +#define SR_MCUBOUNDSINTENACLR_POS 1 +#define SR_MCUDISABLEACKINTENACLR_POS 0 + +#define SR_AVGERROR_LEN 8 +#define SR_AVGERROR_POS 8 +#define SR_SENERROR_LEN 8 +#define SR_SENERROR_POS 0 + +#define SR_WAKEUPENABLE_POS 26 +#define SR_IDLEMODE_POS 24 +#define SR_IDLEMODE_LEN 2 +#define SR_VPBOUNDSINTSTATENA_POS 23 +#define SR_VPBOUNDSINTENABLE_POS 22 +#define SR_ERRWEIGHT_POS 16 +#define SR_ERRWEIGHT_LEN 3 +#define SR_ERRMAXLIMIT_POS 8 +#define SR_ERRMAXLIMIT_LEN 8 +#define SR_ERRMINLIMIT_POS 0 +#define SR_ERRMINLIMIT_LEN 8 + + +#define SR_AUDIT_SHOW_STATUS(curr, golden) \ + if (curr == golden) { \ + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "Pass"); \ + } else { \ + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "FAIL"); \ + (*err_nbr)++; \ + } + + +static const char + sr_sensor_type_names[SR_SENSOR_TYPE_MAX + 1][SR_SENSOR_TYPE_MAX_LENGTH] = { + "N", + "P", + "FIXME" +}; + + +static const char + sr_sensor_value_type_names[SR_SENSOR_VAL_TYPE_MAX + 1][SR_SENSOR_VAL_TYPE_MAX_LENGTH] = { + "Latest", + "MIN", + "MAX", + "AVG", + "FIXME" +}; + + +static const char + sr_sensor_value_status_names[SR_SENSOR_VAL_STATUS_MAX + 1][SR_SENSOR_VAL_STATUS_MAX_LENGTH] = { + "Invalid", + "Valid", + "Valid & Final", + "FIXME" +}; + + +static const char + sr_interrupt_type_names[SR_IRQ_TYPE_MAX + 1][SR_IRQ_TYPE_MAX_LENGTH] = { + "MCU DisableAck", + "MCU Bounds", + "MCU Valid", + "MCU Accum", + "VP bounds", + "FIXME" +}; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_type_name_get + * @BRIEF return sensor type name + * @RETURNS sensor type name on success + * "FIXME" string in case of error + * @param[in] type: valid sensor type ID + * @DESCRIPTION return sensor type name + *//*------------------------------------------------------------------------ */ +const char *sr_sensor_type_name_get(sr_sensor_type type) +{ + if (type < SR_SENSOR_TYPE_MAX) + return sr_sensor_type_names[type]; + else + return sr_sensor_type_names[SR_SENSOR_TYPE_MAX]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_value_type_name_get + * @BRIEF return sensor value type name + * @RETURNS sensor value type name on success + * "FIXME" string in case of error + * @param[in] type: valid sensor value type ID + * @DESCRIPTION return sensor value type name + *//*------------------------------------------------------------------------ */ +const char *sr_sensor_value_type_name_get(sr_sensor_value_type type) +{ + if (type < SR_SENSOR_VAL_TYPE_MAX) + return sr_sensor_value_type_names[type]; + else + return sr_sensor_value_type_names[SR_SENSOR_VAL_TYPE_MAX]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_value_status_name_get + * @BRIEF return sensor value status name + * @RETURNS sensor value status name on success + * "FIXME" string in case of error + * @param[in] status: valid sensor value status ID + * @DESCRIPTION return sensor value status name + *//*------------------------------------------------------------------------ */ +const char *sr_sensor_value_status_name_get(sr_sensor_value_status status) +{ + if (status < SR_SENSOR_VAL_STATUS_MAX) + return sr_sensor_value_status_names[status]; + else + return sr_sensor_value_status_names[SR_SENSOR_VAL_STATUS_MAX]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_interrupt_type_name_get + * @BRIEF return SR interrupt type name + * @RETURNS interrupt type name on success + * "FIXME" string in case of error + * @param[in] type: valid interrupt type ID + * @DESCRIPTION return SR interrupt type name + *//*------------------------------------------------------------------------ */ +const char *sr_interrupt_type_name_get(sr_interrupt_type type) +{ + if (type < SR_IRQ_TYPE_MAX) + return sr_interrupt_type_names[type]; + else + return sr_interrupt_type_names[SR_IRQ_TYPE_MAX]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_enabled + * @BRIEF check if SR module is enabled by analyzing SRCONFIG + * register content + * @RETURNS 1 if module is enabled, 0 otherwise. + * @param[in] sr_config: SRCONFIG register content + * @DESCRIPTION check if SR module is enabled by analyzing SRCONFIG + * register content + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_enabled(unsigned int sr_config) +{ + return extract_bit(sr_config, SR_SRENABLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_has_converged + * @BRIEF check if SR module has converged + * @RETURNS 1 if module is enabled, 0 otherwise + * @param[in] errconfig: ERRCONFIG register content + * @param[in] senerror: SENERROR register content + * @DESCRIPTION check if SR module has converged + *//*------------------------------------------------------------------------ */ +unsigned char sr_has_converged(unsigned int errconfig, unsigned int senerror) +{ + signed char minlimit, maxlimit, avgerr; + + minlimit = (signed char) sr_error_generator_minlimit_get(errconfig); + maxlimit = (signed char) sr_error_generator_maxlimit_get(errconfig); + avgerr = (signed char) sr_avg_sensor_error_value_get(senerror); + + if ((avgerr <= maxlimit) && (avgerr >= minlimit)) { + dprintf("%s(): minlimit=%d maxlimit=%d avgerr=%d => " + "converged\n", __func__, minlimit, maxlimit, avgerr); + return 1; + } else { + dprintf("%s(): minlimit=%d maxlimit=%d avgerr=%d => " + "NOT converged\n", __func__, minlimit, maxlimit, + avgerr); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_sensors_disabled + * @BRIEF check if SR sensors (N+P) are disabled + * @RETURNS 1 if SR sensors (N+P) are disabled, 0 otherwise + * @param[in] sr_config: SRCONFIG register content + * @DESCRIPTION check if SR sensors (N+P) are disabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_sensors_disabled(unsigned int sr_config) +{ + return !extract_bit(sr_config, SR_SENENABLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_lvt_sensors_disabled + * @BRIEF check if SR LVT sensors (N+P) are disabled + * @RETURNS 1 if SR LVT sensors (N+P) are disabled, 0 otherwise + * @param[in] sr_config: SRCONFIG register content + * @DESCRIPTION check if SR LVT sensors (N+P) are disabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_lvt_sensors_disabled(unsigned int sr_config) +{ + return !extract_bit(sr_config, SR_LVTSENENABLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_sensor_enabled + * @BRIEF check if SR sensor is enabled + * @RETURNS 1 if SR sensor is enabled, 0 otherwise + * @param[in] sr_config: SRCONFIG register content + * @param[in] type: sensor type + * @DESCRIPTION check if SR sensor is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_sensor_enabled(unsigned int sr_config, sr_sensor_type type) +{ + switch (type) { + case SR_SENSOR_N: + return extract_bit(sr_config, SR_SENNENABLE_POS); + case SR_SENSOR_P: + return extract_bit(sr_config, SR_SENPENABLE_POS); + default: + fprintf(stderr, "%s(): incorrect sensor type! (%u)\n", __func__, + type); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_lvt_sensor_enabled + * @BRIEF check if SR LVT sensor is enabled + * @RETURNS 1 if SR LVT sensor is enabled, 0 otherwise + * @param[in] sr_config: SRCONFIG register content + * @param[in] type: sensor type + * @DESCRIPTION check if SR LVT sensor is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_lvt_sensor_enabled(unsigned int sr_config, + sr_sensor_type type) +{ + switch (type) { + case SR_SENSOR_N: + return extract_bit(sr_config, SR_LVTSENNENABLE_POS); + case SR_SENSOR_P: + return extract_bit(sr_config, SR_LVTSENPENABLE_POS); + default: + fprintf(stderr, "%s(): incorrect sensor type! (%u)\n", __func__, + type); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_error_generator_enabled + * @BRIEF check if SR error generator is enabled + * @RETURNS 1 if SR error generator is enabled, 0 otherwise + * @param[in] sr_config: SRCONFIG register content + * @DESCRIPTION check if SR error generator is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_error_generator_enabled(unsigned int sr_config) +{ + return extract_bit(sr_config, SR_ERRORGENERATORENABLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_minmaxavg_detector_enabled + * @BRIEF check if SR min/max/avg detector is enabled + * @RETURNS 1 if SR min/max/avg detector is enabled, 0 otherwise + * @param[in] sr_config: SRCONFIG register content + * @DESCRIPTION check if SR min/max/avg detector is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_minmaxavg_detector_enabled(unsigned int sr_config) +{ + return extract_bit(sr_config, SR_MINMAXAVGENABLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_accumdata_count_get + * @BRIEF return the number of values to accumulate + * @RETURNS number of values to accumulate (ACCUMDATA) + * @param[in] sr_config: SRCONFIG register content + * @DESCRIPTION return the number of values to accumulate + *//*------------------------------------------------------------------------ */ +unsigned char sr_accumdata_count_get(unsigned int sr_config) +{ + return extract_bitfield(sr_config, + SR_ACCUMDATA_POS, SR_ACCUMDATA_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_clk_div_get + * @BRIEF return the value of the internal source clock divider + * @RETURNS value of the internal source clock divider (SRCLKLENGTH) + * @param[in] sr_config: SRCONFIG register content + * @DESCRIPTION return the value of the internal source clock divider + *//*------------------------------------------------------------------------ */ +unsigned char sr_clk_div_get(unsigned int sr_config) +{ + return extract_bitfield(sr_config, + SR_SRCLKLENGTH_POS, SR_SRCLKLENGTH_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_clk_rate_get + * @BRIEF return the rate of the SR clock, considering internal + * divider + * @RETURNS rate of the SR clock, considering internal divider (KHz) + * @param[in] sr_config: SRCONFIG register content + * @param[in] sr_sysclk: smartreflex sysclk rate (MHz) + * @DESCRIPTION return the rate of the SR clock, considering internal + * divider + *//*------------------------------------------------------------------------ */ +double sr_clk_rate_get(unsigned int sr_config, double sr_sysclk) +{ + return (sr_sysclk * 1000.0) / + (2.0 * (double) sr_clk_div_get(sr_config)); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_avg_weighting_factor_get + * @BRIEF return the sensor averaging weighting factor (P & N) + * @RETURNS sensor averaging weighting factor (P & N) + * @param[in] avgweight: AVGWEIGHT register content + * @param[in] type: valid sensor type ID + * @DESCRIPTION return the sensor averaging weighting factor (P & N) + *//*------------------------------------------------------------------------ */ +unsigned char sr_avg_weighting_factor_get(unsigned int avgweight, + sr_sensor_type type) +{ + switch (type) { + case SR_SENSOR_N: + return (unsigned char) extract_bitfield(avgweight, + SR_SENNAVGWEIGHT_POS, SR_SENNAVGWEIGHT_LEN); + case SR_SENSOR_P: + return (unsigned char) extract_bitfield(avgweight, + SR_SENPAVGWEIGHT_POS, SR_SENPAVGWEIGHT_LEN); + default: + fprintf(stderr, "%s(): incorrect sensor type! (%u)\n", __func__, + type); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_gain_get + * @BRIEF return the reciprocal gain (P & N) + * @RETURNS reciprocal gain (P & N) + * @param[in] nvaluereciprocal: NVALUERECIPROCAL register content + * @param[in] type: valid sensor type ID + * @DESCRIPTION return the reciprocal gain (P & N) + *//*------------------------------------------------------------------------ */ +unsigned char sr_gain_get(unsigned int nvaluereciprocal, sr_sensor_type type) +{ + switch (type) { + case SR_SENSOR_N: + return extract_bitfield(nvaluereciprocal, + SR_SENNGAIN_POS, SR_SENNGAIN_LEN); + case SR_SENSOR_P: + return extract_bitfield(nvaluereciprocal, + SR_SENPGAIN_POS, SR_SENPGAIN_LEN); + default: + fprintf(stderr, "%s(): incorrect sensor type! (%u)\n", __func__, + type); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_scale_value_get + * @BRIEF return the reciprocal scale value (P & N) + * @RETURNS reciprocal scale value (P & N) + * @param[in] nvaluereciprocal: NVALUERECIPROCAL register content + * @param[in] type: valid sensor type ID + * @DESCRIPTION return the reciprocal scale value (P & N) + *//*------------------------------------------------------------------------ */ +unsigned char sr_scale_value_get(unsigned int nvaluereciprocal, + sr_sensor_type type) +{ + switch (type) { + case SR_SENSOR_N: + return extract_bitfield(nvaluereciprocal, + SR_SENNRN_POS, SR_SENNRN_LEN); + case SR_SENSOR_P: + return extract_bitfield(nvaluereciprocal, + SR_SENPRN_POS, SR_SENPRN_LEN); + default: + fprintf(stderr, "%s(): incorrect sensor type! (%u)\n", __func__, + type); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_ntarget_get + * @BRIEF return the sensor NTarget (P & N) + * @RETURNS sensor NTarget + * @param[in] nvaluereciprocal: NVALUERECIPROCAL register content + * @param[in] type: valid sensor type ID + * @DESCRIPTION return the sensor NTarget (P & N) + *//*------------------------------------------------------------------------ */ +unsigned int sr_ntarget_get(unsigned int nvaluereciprocal, sr_sensor_type type) +{ + unsigned char gain, scale; + double ntarget; + + gain = sr_gain_get(nvaluereciprocal, type); + scale = sr_scale_value_get(nvaluereciprocal, type); + ntarget = 1.0 / ((double) scale / (double) (1 << (gain + 8))); + dprintf("%s(): NVALUERECIPROCAL=0x%08X gain=%u scale=%u ntarget=%u\n", + __func__, nvaluereciprocal, gain, scale, + 1 + (unsigned int) ntarget); + return 1 + (unsigned int) ntarget; + +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_error_generator_limit_hex2percent + * @BRIEF convert error limit HEX signed value into % + * @RETURNS error limit value in % + * @param[in] limit: error limit HEX signed value + * @DESCRIPTION convert error limit HEX signed value into % + *//*------------------------------------------------------------------------ */ +double sr_error_generator_limit_hex2percent(signed char limit) +{ + return 0.8 * (double) limit; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_error_generator_minlimit_get + * @BRIEF return the RAW lower limit of SenError for interrupt + * generation + * @RETURNS RAW lower limit ("ERRMINLIMIT") + * @param[in] errconfig: ERRCONFIG register content + * @DESCRIPTION return the RAW lower limit of SenError for interrupt + * generation + *//*------------------------------------------------------------------------ */ +unsigned char sr_error_generator_minlimit_get(unsigned int errconfig) +{ + return (unsigned char) extract_bitfield(errconfig, + SR_ERRMINLIMIT_POS, SR_ERRMINLIMIT_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_error_generator_minlimit_percentage_get + * @BRIEF return the percentage of lower limit of SenError + * for interrupt generation + * @RETURNS lower limit ("ERRMINLIMIT") percentage + * @param[in] errconfig: ERRCONFIG register content + * @DESCRIPTION return the percentage of lower limit of SenError + * for interrupt generation + *//*------------------------------------------------------------------------ */ +double sr_error_generator_minlimit_percentage_get(unsigned int errconfig) +{ + return sr_error_generator_limit_hex2percent( + (signed char) sr_error_generator_minlimit_get(errconfig)); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_error_generator_maxlimit_get + * @BRIEF return the RAW upper limit of SenError for interrupt + * generation + * @RETURNS RAW upper limit ("ERRMAXLIMIT") + * @param[in] errconfig: ERRCONFIG register content + * @DESCRIPTION return the RAW upper limit of SenError for interrupt + * generation + *//*------------------------------------------------------------------------ */ +unsigned char sr_error_generator_maxlimit_get(unsigned int errconfig) +{ + return (unsigned char) extract_bitfield(errconfig, + SR_ERRMAXLIMIT_POS, SR_ERRMAXLIMIT_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_error_generator_maxlimit_percentage_get + * @BRIEF return the percentage of upper limit of SenError + * for interrupt generation + * @RETURNS upper limit ("ERRMAXLIMIT") percentage + * @param[in] errconfig: ERRCONFIG register content + * @DESCRIPTION return the percentage of upper limit of SenError + * for interrupt generation + *//*------------------------------------------------------------------------ */ +double sr_error_generator_maxlimit_percentage_get(unsigned int errconfig) +{ + return sr_error_generator_limit_hex2percent( + (signed char) sr_error_generator_maxlimit_get(errconfig)); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_error_generator_weight_get + * @BRIEF return the sensor error weighting factor (ERRWEIGHT) + * @RETURNS AvgSenError weight (ERRWEIGHT) + * @param[in] errconfig: ERRCONFIG register content + * @DESCRIPTION return the sensor error weighting factor (ERRWEIGHT) + *//*------------------------------------------------------------------------ */ +unsigned char sr_error_generator_weight_get(unsigned int errconfig) +{ + return (unsigned char) extract_bitfield(errconfig, + SR_ERRWEIGHT_POS, SR_ERRWEIGHT_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_error_generator_idle_mode_get + * @BRIEF return sensor error generator idle mode + * @RETURNS sensor error generator idle mode + * @param[in] errconfig: ERRCONFIG register content + * @DESCRIPTION return sensor error generator idle mode + *//*------------------------------------------------------------------------ */ +mod_idle_mode sr_error_generator_idle_mode_get(unsigned int errconfig) +{ + return extract_bitfield(errconfig, + SR_IDLEMODE_POS, SR_IDLEMODE_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_is_error_generator_wakeup_enabled + * @BRIEF check if SR error generator module WAKEUP generation + * is enabled + * @RETURNS 1 if module WAKEUP generation is enabled, 0 otherwise + * @param[in] errconfig: ERRCONFIG register content + * @DESCRIPTION check if SR error generator module WAKEUP generation + * is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_is_error_generator_wakeup_enabled(unsigned int errconfig) +{ + return extract_bit(errconfig, SR_WAKEUPENABLE_POS); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_irq_is_enabled + * @BRIEF check if SR interrupt of type 'irq' is enabled + * @RETURNS 1 if interrupt is enabled, 0 otherwise + * @param[in] irqenable_set: IRQENABLE_SET register content + * @param[in] errconfig: ERRCONFIG register content + * @param[in] irq: interrupt type + * @DESCRIPTION check if SR interrupt of type 'irq' is enabled + *//*------------------------------------------------------------------------ */ +unsigned char sr_irq_is_enabled(unsigned int irqenable_set, + unsigned int errconfig, sr_interrupt_type type) +{ + switch (type) { + case SR_IRQ_MCUDISABLEACK: + return extract_bit(irqenable_set, + SR_MCUDISABLEACKINTENASET_POS); + case SR_IRQ_MCUBOUNDS: + return extract_bit(irqenable_set, SR_MCUBOUNDSINTENASET_POS); + case SR_IRQ_MCUVALID: + return extract_bit(irqenable_set, SR_MCUVALIDINTENASET_POS); + case SR_IRQ_MCUACCUM: + return extract_bit(irqenable_set, SR_MCUACCUMINTENASET_POS); + case SR_IRQ_VPBOUNDS: + return extract_bit(errconfig, SR_VPBOUNDSINTENABLE_POS); + default: + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_irq_status_is_set + * @BRIEF check if SR interrupt of type 'irq' status is set + * (pending) + * @RETURNS 1 if interrupt status is set, 0 otherwise + * @param[in] irqstatus: IRQSTATUS register content + * @param[in] errconfig: ERRCONFIG register content + * @param[in] type: interrupt type + * @DESCRIPTION check if SR interrupt of type 'irq' status is set + * (pending) + *//*------------------------------------------------------------------------ */ +unsigned char sr_irq_status_is_set(unsigned int irqstatus, + unsigned int errconfig, sr_interrupt_type type) +{ + switch (type) { + case SR_IRQ_MCUDISABLEACK: + return extract_bit(irqstatus, + SR_MCUDISABLEACKINTSTATENA_POS); + case SR_IRQ_MCUBOUNDS: + return extract_bit(irqstatus, SR_MCUBOUNDSINTSTATENA_POS); + case SR_IRQ_MCUVALID: + return extract_bit(irqstatus, SR_MCUVALIDINTSTATENA_POS); + case SR_IRQ_MCUACCUM: + return extract_bit(irqstatus, SR_MCUACCUMINTSTATENA_POS); + case SR_IRQ_VPBOUNDS: + return extract_bit(errconfig, SR_VPBOUNDSINTSTATENA_POS); + default: + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_irq_raw_status_is_set + * @BRIEF check if SR interrupt of type 'irq' status is set + * (pending). + * NB: VPBOUNDS interrupt has no raw interrupt status flag + * @RETURNS 1 if interrupt raw status is set, 0 otherwise + * @param[in] irqstatus_raw: IRQSTATUS_RAW register content + * @param[in] type: interrupt type + * @DESCRIPTION check if SR interrupt of type 'irq' status is set + * (pending). + * NB: VPBOUNDS interrupt has no raw interrupt status flag + *//*------------------------------------------------------------------------ */ +unsigned char sr_irq_raw_status_is_set(unsigned int irqstatus_raw, + sr_interrupt_type type) +{ + switch (type) { + case SR_IRQ_MCUDISABLEACK: + return extract_bit(irqstatus_raw, + SR_MCUDISABLEACKINTSTATRAW_POS); + case SR_IRQ_MCUBOUNDS: + return extract_bit(irqstatus_raw, SR_MCUBOUNDSINTSTATRAW_POS); + case SR_IRQ_MCUVALID: + return extract_bit(irqstatus_raw, SR_MCUVALIDINTSTATRAW_POS); + case SR_IRQ_MCUACCUM: + return extract_bit(irqstatus_raw, SR_MCUACCUMINTSTATRAW_POS); + case SR_IRQ_VPBOUNDS: + fprintf(stderr, "%s(): error: VPBOUNDS has no raw interrupt " + "status flag.\n", __func__); + default: + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_error_value_status_get + * @BRIEF return the current status of sensor error value + * @RETURNS sensor error value (SenError) status + * @param[in] srstatus: SRSTATUS register content + * @DESCRIPTION return the current status of sensor error value + *//*------------------------------------------------------------------------ */ +sr_sensor_value_status sr_sensor_error_value_status_get( + unsigned int srstatus) +{ + if (extract_bit(srstatus, SR_ERRORGENERATORVALID_POS) == 1) + return SR_SENSOR_VAL_VALID; + else + return SR_SENSOR_VAL_INVALID; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_error_value_get + * @BRIEF return RAW sensor error value from SENERROR register + * @RETURNS RAW sensor error value from SENERROR register + * @param[in] senerror: SENERROR register content + * @DESCRIPTION return RAW sensor error value from SENERROR register + *//*------------------------------------------------------------------------ */ +unsigned char sr_sensor_error_value_get(unsigned int senerror) +{ + return (unsigned char) extract_bitfield(senerror, + SR_SENERROR_POS, SR_SENERROR_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_error_percentage_get + * @BRIEF return sensor error percentage + * @RETURNS percentage of sensor error value + * @param[in] senerror: SENERROR register content + * @DESCRIPTION return sensor error percentage + *//*------------------------------------------------------------------------ */ +double sr_sensor_error_percentage_get(unsigned int senerror) +{ + return 0.8 * (signed char) sr_sensor_error_value_get(senerror); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_avg_sensor_error_value_status_get + * @BRIEF return the current status of avg error value + * @RETURNS avg error value (AvgError) status + * @param[in] srstatus: SRSTATUS register content + * @DESCRIPTION return the current status of avg error value + *//*------------------------------------------------------------------------ */ +sr_sensor_value_status sr_avg_sensor_error_value_status_get( + unsigned int srstatus) +{ + if (extract_bit(srstatus, SR_AVGERRVALID_POS) == 1) + return SR_SENSOR_VAL_VALID; + else + return SR_SENSOR_VAL_INVALID; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_avg_sensor_error_value_get + * @BRIEF return RAW sensor error value from SENERROR register + * @RETURNS RAW sensor error value from SENERROR register + * @param[in] senerror: SENERROR register content + * @DESCRIPTION return RAW sensor error value from SENERROR register + *//*------------------------------------------------------------------------ */ +unsigned char sr_avg_sensor_error_value_get(unsigned int senerror) +{ + return (unsigned char) extract_bitfield(senerror, + SR_AVGERROR_POS, SR_AVGERROR_LEN); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_avg_sensor_error_percentage_get + * @BRIEF return avg sensor error percentage + * @RETURNS avg sensor error value + * @param[in] senerror: SENERROR register content + * @DESCRIPTION return avg sensor error percentage + *//*------------------------------------------------------------------------ */ +double sr_avg_sensor_error_percentage_get(unsigned int senerror) +{ + return 0.8 * (signed char) sr_avg_sensor_error_value_get(senerror); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_value_status_get + * @BRIEF return the current status of selected value type + * (invalid/valid/final) + * @RETURNS sensor values (min/max/avg/latest) status + * @param[in] srstatus: SRSTATUS register content + * @DESCRIPTION return the current status of selected value type + * (invalid/valid/final) + *//*------------------------------------------------------------------------ */ +sr_sensor_value_status sr_sensor_value_status_get(unsigned int srstatus) +{ + if (extract_bit(srstatus, SR_MINMAXAVGACCUMVALID_POS) == 1) + return SR_SENSOR_VAL_FINAL; + else if (extract_bit(srstatus, SR_MINMAXAVGVALID_POS) == 1) + return SR_SENSOR_VAL_VALID; + else + return SR_SENSOR_VAL_INVALID; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_sensor_value_get + * @BRIEF return selected SR sensor value + * NB: use sr_sensor_value_status_get() first to make sure + * value is valid + * @RETURNS SR sensor current (latest) value + * @param[in] sr_regs: SR registers content + * @param[in] sen_type: sensor type + * @param[in] val_type: value type + * @DESCRIPTION return selected SR sensor value + * NB: use sr_sensor_value_status_get() first to make sure + * value is valid + *//*------------------------------------------------------------------------ */ +unsigned int sr_sensor_value_get(sr_registers *sr_regs, sr_sensor_type sen_type, + sr_sensor_value_type val_type) +{ + switch (sen_type) { + case SR_SENSOR_N: + switch (val_type) { + case SR_SENSOR_VAL_LATEST: + return (unsigned int) extract_bitfield(sr_regs->senval, + SR_SENNVAL_POS, SR_SENNVAL_LEN); + case SR_SENSOR_VAL_MIN: + return (unsigned int) extract_bitfield(sr_regs->senmin, + SR_SENNMIN_POS, SR_SENNMIN_LEN); + case SR_SENSOR_VAL_MAX: + return (unsigned int) extract_bitfield(sr_regs->senmax, + SR_SENNMAX_POS, SR_SENNMAX_LEN); + case SR_SENSOR_VAL_AVG: + return (unsigned int) extract_bitfield(sr_regs->senavg, + SR_SENNAVG_POS, SR_SENNAVG_LEN); + default: + fprintf(stderr, "%s(): incorrect value type! (%u)\n", + __func__, val_type); + return 0; + } + + case SR_SENSOR_P: + switch (val_type) { + case SR_SENSOR_VAL_LATEST: + return (unsigned int) extract_bitfield(sr_regs->senval, + SR_SENPVAL_POS, SR_SENPVAL_LEN); + case SR_SENSOR_VAL_MIN: + return (unsigned int) extract_bitfield(sr_regs->senmin, + SR_SENPMIN_POS, SR_SENPMIN_LEN); + case SR_SENSOR_VAL_MAX: + return (unsigned int) extract_bitfield(sr_regs->senmax, + SR_SENPMAX_POS, SR_SENPMAX_LEN); + case SR_SENSOR_VAL_AVG: + return (unsigned int) extract_bitfield(sr_regs->senavg, + SR_SENPAVG_POS, SR_SENPAVG_LEN); + default: + fprintf(stderr, "%s(): incorrect value type! (%u)\n", + __func__, val_type); + return 0; + } + + default: + fprintf(stderr, "%s(): incorrect sensor type! (%u)\n", __func__, + sen_type); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_delta_vdd_get + * @BRIEF return the delta Vdd error in mV + * @RETURNS SR delta Vdd error in mV + * @param[in] freq_error: avegare sensor error (%) + * @param[in] vp_offset: programmed VP error offset (%) + * @param[in] vp_gain: programmed VP error gain (mV/%) + * @DESCRIPTION return the delta Vdd error in mV + *//*------------------------------------------------------------------------ */ +double sr_delta_vdd_get(double freq_error, double vp_offset, double vp_gain) +{ + return (freq_error + vp_offset) * vp_gain; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_lvt_sensor_value_get + * @BRIEF return selected SR sensor value + * NB: use sr_sensor_value_status_get() first to make sure + * value is valid + * @RETURNS SR sensor current (latest) value + * @param[in] sr_regs: SR registers content + * @param[in] sen_type: sensor type + * @param[in] val_type: value type + * @DESCRIPTION return selected SR sensor value + * NB: use sr_sensor_value_status_get() first to make sure + * value is valid + *//*------------------------------------------------------------------------ */ +unsigned int sr_lvt_sensor_value_get(sr_registers *sr_regs, + sr_sensor_type sen_type, sr_sensor_value_type val_type) +{ + switch (sen_type) { + case SR_SENSOR_N: + switch (val_type) { + case SR_SENSOR_VAL_LATEST: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenval, + SR_SENNVAL_POS, SR_SENNVAL_LEN); + case SR_SENSOR_VAL_MIN: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenmin, + SR_SENNMIN_POS, SR_SENNMIN_LEN); + case SR_SENSOR_VAL_MAX: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenmax, + SR_SENNMAX_POS, SR_SENNMAX_LEN); + case SR_SENSOR_VAL_AVG: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenavg, + SR_SENNAVG_POS, SR_SENNAVG_LEN); + default: + fprintf(stderr, "%s(): incorrect value type! (%u)\n", + __func__, val_type); + return 0; + } + + case SR_SENSOR_P: + switch (val_type) { + case SR_SENSOR_VAL_LATEST: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenval, + SR_SENPVAL_POS, SR_SENPVAL_LEN); + case SR_SENSOR_VAL_MIN: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenmin, + SR_SENPMIN_POS, SR_SENPMIN_LEN); + case SR_SENSOR_VAL_MAX: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenmax, + SR_SENPMAX_POS, SR_SENPMAX_LEN); + case SR_SENSOR_VAL_AVG: + return (unsigned int) extract_bitfield( + sr_regs->lvtsenavg, + SR_SENPAVG_POS, SR_SENPAVG_LEN); + default: + fprintf(stderr, "%s(): incorrect value type! (%u)\n", + __func__, val_type); + return 0; + } + + default: + fprintf(stderr, "%s(): incorrect sensor type! (%u)\n", __func__, + sen_type); + return 0; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_config_show + * @BRIEF analyze Smart-Reflex sensor configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in] stream: output file (NULL: no output (silent)) + * @param[in] sr_regs: SR registers content for the 3 SR instances + * (MPU, IVA/MM, CORE) + * @DESCRIPTION analyze Smart-Reflex sensor configuration + *//*------------------------------------------------------------------------ */ +int sr_config_show(FILE *stream, sr_registers sr_regs[3]) +{ + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int i, val, val2, row, maxrow; + sr_sensor_value_status status; + sr_sensor_value_type val_type; + sr_interrupt_type irq_type; + opp44xx_id vdd_core_opp; + double sys_clk, sr_sysclk; + static const char irq_status_table[2][10] = { + "Unchanged", + "Set"}; + static const char mode_table[2][16] = { + "Disabled ", + "Enabled "}; + char *s1, *s2; + unsigned char mode, mode2; + + if (!cpu_is_omap44xx() & !cpu_is_omap54xx()) { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + #ifdef SR_DEBUG + row = 0; + maxrow = 0; + autoadjust_table_init(table); + autoadjust_table_strncpy(table, row, 0, "SR Registers"); + autoadjust_table_strncpy(table, row, 1, "SR MPU"); + if (cpu_is_omap44xx()) + autoadjust_table_strncpy(table, row, 2, "SR IVA"); + else + autoadjust_table_strncpy(table, row, 2, "SR MM"); + autoadjust_table_strncpy(table, row, 3, "SR CORE"); + row++; + for (i = 0; i < 3; i++) { + if (row > maxrow) + maxrow = row; + row = 1; + autoadjust_table_strncpy(table, row, 0, "ACCESSIBLE"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].accessible); + if (sr_regs[i].accessible == 0) + continue; + row++; + autoadjust_table_strncpy(table, row, 0, "SRCONFIG"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].srconfig); + autoadjust_table_strncpy(table, row, 0, "SRSTATUS"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].srstatus); + autoadjust_table_strncpy(table, row, 0, "SENVAL"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].senval); + autoadjust_table_strncpy(table, row, 0, "SENMIN"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].senmin); + autoadjust_table_strncpy(table, row, 0, "SENMAX"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].senmax); + autoadjust_table_strncpy(table, row, 0, "SENAVG"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].senavg); + autoadjust_table_strncpy(table, row, 0, "AVGWEIGHT"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].avgweight); + autoadjust_table_strncpy(table, row, 0, "NVALUERECIPROCAL"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].nvaluereciprocal); + autoadjust_table_strncpy(table, row, 0, "IRQSTATUS_RAW"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].irqstatus_raw); + autoadjust_table_strncpy(table, row, 0, "IRQSTATUS"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].irqstatus); + autoadjust_table_strncpy(table, row, 0, "IRQENABLE_SET"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].irqenable_set); + autoadjust_table_strncpy(table, row, 0, "SENERROR"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].senerror); + autoadjust_table_strncpy(table, row, 0, "ERRCONFIG"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].errconfig); + + if (cpu_is_omap44xx()) + continue; + autoadjust_table_strncpy(table, row, 0, "LVTSENVAL"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].lvtsenval); + autoadjust_table_strncpy(table, row, 0, "LVTSENMIN"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].lvtsenmin); + autoadjust_table_strncpy(table, row, 0, "LVTSENMAX"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].lvtsenmax); + autoadjust_table_strncpy(table, row, 0, "LVTSENAVG"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].lvtsenavg); + autoadjust_table_strncpy(table, row, 0, "LVTNVALUERECIPROCAL"); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, "0x%08X", + sr_regs[i].lvtnvaluereciprocal); + } + autoadjust_table_print(table, maxrow, 4); + #endif + + if (cpu_is_omap44xx()) { + sys_clk = clk44xx_get_system_clock_speed(); + /* Get VDD_CORE OPP to detect DPLL cascading mode */ + voltdm44xx_get_opp(OMAP4_VDD_CORE, &vdd_core_opp); + if (vdd_core_opp == OMAP4_OPPDPLL_CASC) + sr_sysclk = 12.288; /* MHz */ + else + sr_sysclk = sys_clk; + } else { + sr_sysclk = + (double) module_clk_rate_get(MOD_SMARTREFLEX_MPU, 0) / 1000.0; + } + dprintf("%s(): sr_sysclk = %lfMHz\n", __func__, sr_sysclk); + + row = 0; + maxrow = 0; + autoadjust_table_init(table); + autoadjust_table_strncpy(table, row, 0, "SR Configuration"); + autoadjust_table_strncpy(table, row, 1, "SR_MPU"); + if (cpu_is_omap44xx()) + autoadjust_table_strncpy(table, row, 2, "SR_MM"); + else + autoadjust_table_strncpy(table, row, 2, "SR_MM"); + autoadjust_table_strncpy(table, row, 3, "SR_CORE"); + row++; + + for (i = 0; i < 3; i++) { + if (row > maxrow) + maxrow = row; + row = 1; + autoadjust_table_strncpy(table, row, 0, "SR Module"); + if (sr_regs[i].accessible == 0) { + autoadjust_table_strncpy(table, row, i + 1, "Disabled"); + row++; + continue; + } + mode = sr_is_enabled(sr_regs[i].srconfig); + autoadjust_table_strncpy(table, row, i + 1, + (char *) mode_table[mode]); + row++; + autoadjust_table_strncpy(table, row, 0, + "SR_CLK Divider (SRCLKLENGTH)"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "0x%03X (%u)", + sr_clk_div_get(sr_regs[i].srconfig), + sr_clk_div_get(sr_regs[i].srconfig)); + row++; + autoadjust_table_strncpy(table, row, 0, + "SR_CLK Frequency"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "%.3lfKHz", + sr_clk_rate_get(sr_regs[i].srconfig, sr_sysclk)); + row += 2; + + autoadjust_table_strncpy(table, row++, 0, + "Interrupt configuration"); + for (irq_type = SR_IRQ_MCUDISABLEACK; + irq_type < SR_IRQ_TYPE_MAX; irq_type++) { + snprintf(table[row][0], TABLE_MAX_ELT_LEN, " %s", + sr_interrupt_type_name_get(irq_type)); + mode = sr_irq_is_enabled(sr_regs[i].irqenable_set, + sr_regs[i].errconfig, irq_type); + autoadjust_table_strncpy(table, row++, i + 1, + (char *) mode_table[mode]); + if (mode == 0) + continue; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + " Status (Masked | Raw)"); + val = sr_irq_status_is_set(sr_regs[i].irqstatus, + sr_regs[i].errconfig, irq_type); + s1 = (char *) irq_status_table[val]; + if (irq_type != SR_IRQ_VPBOUNDS) { + val2 = sr_irq_raw_status_is_set( + sr_regs[i].irqstatus_raw, irq_type); + s2 = (char *) irq_status_table[val2]; + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%s | %s", s1, s2); + } else { + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%s", s1); + } + row++; + } + row++; + + autoadjust_table_strncpy(table, row, 0, + "SR Sensors (N | P)"); + if (sr_is_sensors_disabled(sr_regs[i].srconfig) == 1) { + autoadjust_table_strncpy(table, row, i + 1, "Disabled"); + row += 2; + goto sr_config_show_minmaxavg; + } + mode = sr_is_sensor_enabled(sr_regs[i].srconfig, SR_SENSOR_N); + mode2 = sr_is_sensor_enabled(sr_regs[i].srconfig, SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "%s | %s", + mode_table[mode], mode_table[mode2]); + row++; + + autoadjust_table_strncpy(table, row, 0, + " Reciprocal Gain (SEN[N-P]GAIN)"); + val = sr_gain_get(sr_regs[i].nvaluereciprocal, SR_SENSOR_N); + val2 = sr_gain_get(sr_regs[i].nvaluereciprocal, SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", val, val, val2, val2); + row++; + + autoadjust_table_strncpy(table, row, 0, + " Reciprocal Scale Value (SEN[N-P]RN)"); + val = sr_scale_value_get(sr_regs[i].nvaluereciprocal, + SR_SENSOR_N); + val2 = sr_scale_value_get(sr_regs[i].nvaluereciprocal, + SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", val, val, val2, val2); + row++; + + autoadjust_table_strncpy(table, row, 0, " NTarget"); + val = sr_ntarget_get(sr_regs[i].nvaluereciprocal, SR_SENSOR_N); + val2 = sr_ntarget_get(sr_regs[i].nvaluereciprocal, SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", val, val, val2, val2); + row++; + if (cpu_is_omap44xx()) { + row++; + goto sr_config_show_minmaxavg; + } + + autoadjust_table_strncpy(table, row, 0, + "SR LVT Sensors (N | P)"); + if (sr_is_lvt_sensors_disabled(sr_regs[i].srconfig) == 1) { + autoadjust_table_strncpy(table, row, i + 1, "Disabled"); + row += 5; + goto sr_config_show_minmaxavg; + } + mode = sr_is_lvt_sensor_enabled(sr_regs[i].srconfig, + SR_SENSOR_N); + mode2 = sr_is_lvt_sensor_enabled(sr_regs[i].srconfig, + SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "%s | %s", + mode_table[mode], mode_table[mode2]); + row++; + + autoadjust_table_strncpy(table, row, 0, + " Reciprocal Gain (SEN[N-P]GAIN)"); + val = sr_gain_get(sr_regs[i].lvtnvaluereciprocal, SR_SENSOR_N); + val2 = sr_gain_get(sr_regs[i].lvtnvaluereciprocal, SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", val, val, val2, val2); + row++; + + autoadjust_table_strncpy(table, row, 0, + " Reciprocal Scale Value (SEN[N-P]RN)"); + val = sr_scale_value_get(sr_regs[i].lvtnvaluereciprocal, + SR_SENSOR_N); + val2 = sr_scale_value_get(sr_regs[i].lvtnvaluereciprocal, + SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", val, val, val2, val2); + row++; + + autoadjust_table_strncpy(table, row, 0, " NTarget"); + val = sr_ntarget_get(sr_regs[i].lvtnvaluereciprocal, + SR_SENSOR_N); + val2 = sr_ntarget_get(sr_regs[i].lvtnvaluereciprocal, + SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", val, val, val2, val2); + row += 2; + +sr_config_show_minmaxavg: + autoadjust_table_strncpy(table, row, 0, + "Min/Max/Avg Detector Module"); + mode = sr_is_minmaxavg_detector_enabled(sr_regs[i].srconfig); + autoadjust_table_strncpy(table, row, i + 1, + (char *) mode_table[mode]); + row++; + if (mode == 0) { + row++; + goto sr_config_show_errgen; + } + autoadjust_table_strncpy(table, row, 0, + " Nbr of Accumulated Values (ACCUMDATA)"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "0x%04X (%05u)", + sr_accumdata_count_get(sr_regs[i].srconfig), + sr_accumdata_count_get(sr_regs[i].srconfig)); + row++; + + autoadjust_table_strncpy(table, row, 0, + " Averager Weighting Factor (N | P)"); + val = sr_avg_weighting_factor_get(sr_regs[i].avgweight, + SR_SENSOR_N); + val2 = sr_avg_weighting_factor_get(sr_regs[i].avgweight, + SR_SENSOR_P); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", + val, val, val2, val2); + row++; + autoadjust_table_strncpy(table, row++, 0, + " Sensor Values (N | P)"); + for (val_type = SR_SENSOR_VAL_LATEST; + val_type < SR_SENSOR_VAL_TYPE_MAX; val_type++) { + snprintf(table[row][0], TABLE_MAX_ELT_LEN, " %s", + sr_sensor_value_type_name_get(val_type)); + status = sr_sensor_value_status_get( + sr_regs[i].srstatus); + if (status == SR_SENSOR_VAL_INVALID) { + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%s", sr_sensor_value_status_name_get( + status)); + } else { + val = sr_sensor_value_get(&(sr_regs[i]), + SR_SENSOR_N, val_type); + val2 = sr_sensor_value_get(&(sr_regs[i]), + SR_SENSOR_P, val_type); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", + val, val, val2, val2); + } + row++; + } + + if (cpu_is_omap44xx()) { + row++; + goto sr_config_show_errgen; + } + autoadjust_table_strncpy(table, row++, 0, + " LVT Sensor Values (N | P)"); + for (val_type = SR_SENSOR_VAL_LATEST; + val_type < SR_SENSOR_VAL_TYPE_MAX; val_type++) { + snprintf(table[row][0], TABLE_MAX_ELT_LEN, " %s", + sr_sensor_value_type_name_get(val_type)); + status = sr_sensor_value_status_get( + sr_regs[i].srstatus); + if (status == SR_SENSOR_VAL_INVALID) { + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%s", sr_sensor_value_status_name_get( + status)); + } else { + val = sr_lvt_sensor_value_get(&(sr_regs[i]), + SR_SENSOR_N, val_type); + val2 = sr_lvt_sensor_value_get(&(sr_regs[i]), + SR_SENSOR_P, val_type); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "0x%04X (%05u) | 0x%04X (%05u)", + val, val, val2, val2); + } + row++; + } + row++; + +sr_config_show_errgen: + autoadjust_table_strncpy(table, row, 0, + "Error Generator Module"); + mode = sr_is_error_generator_enabled(sr_regs[i].srconfig); + autoadjust_table_strncpy(table, row, i + 1, + (char *) mode_table[mode]); + row++; + autoadjust_table_strncpy(table, row, 0, + " Idle Mode"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "%s", + mod_idle_mode_name_get(sr_error_generator_idle_mode_get( + sr_regs[i].errconfig))); + row++; + autoadjust_table_strncpy(table, row, 0, + " WAKEUPENABLE"); + val = sr_is_error_generator_wakeup_enabled( + sr_regs[i].errconfig); + autoadjust_table_strncpy(table, row, i + 1, + (char *) mode_table[mode]); + row++; + + autoadjust_table_strncpy(table, row, 0, + " ERRMINLIMIT"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%.1lf%% (0x%02X)", + sr_error_generator_minlimit_percentage_get( + sr_regs[i].errconfig), + sr_error_generator_minlimit_get(sr_regs[i].errconfig)); + row++; + autoadjust_table_strncpy(table, row, 0, + " ERRMAXLIMIT"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%.1lf%% (0x%02X)", + sr_error_generator_maxlimit_percentage_get( + sr_regs[i].errconfig), + sr_error_generator_maxlimit_get(sr_regs[i].errconfig)); + row++; + autoadjust_table_strncpy(table, row, 0, + " ERRWEIGHT"); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, "0x%1X (%u)", + sr_error_generator_weight_get(sr_regs[i].errconfig), + sr_error_generator_weight_get(sr_regs[i].errconfig)); + row += 2; + + autoadjust_table_strncpy(table, row++, 0, + "Sensor Error"); + autoadjust_table_strncpy(table, row, 0, + " Latest"); + status = sr_sensor_error_value_status_get(sr_regs[i].srstatus); + snprintf(table[row++][i + 1], TABLE_MAX_ELT_LEN, + "%.1lf%% (0x%02X) (%s)", + sr_sensor_error_percentage_get(sr_regs[i].senerror), + sr_sensor_error_value_get(sr_regs[i].senerror), + sr_sensor_value_status_name_get(status)); + autoadjust_table_strncpy(table, row, 0, + " Average"); + status = sr_avg_sensor_error_value_status_get( + sr_regs[i].srstatus); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%.1lf%% (0x%02X) (%s)", + sr_avg_sensor_error_percentage_get(sr_regs[i].senerror), + sr_avg_sensor_error_value_get(sr_regs[i].senerror), + sr_sensor_value_status_name_get(status)); + row++; + } + + if (stream != NULL) + autoadjust_table_fprint(stream, table, maxrow, 4); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_convergence_status_show + * @BRIEF analyze Smart-Reflex convergence status + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in] stream: output file (NULL: no output (silent)) + * @param[in] sr_regs: SR registers content for the 3 SR instances + * (MPU, IVA/MM, CORE) + * @DESCRIPTION analyze Smart-Reflex convergence status + *//*------------------------------------------------------------------------ */ +int sr_convergence_status_show(FILE *stream, sr_status_registers sr_regs[3]) +{ + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int i, row, maxrow; + double volt, freq_error, delta_vdd, vp_offset, vp_gain; + signed char vp_offset_raw, vp_gain_raw; + static const char mode_table[2][16] = { + "Disabled ", + "Enabled "}; + unsigned char mode; + unsigned int opp; + char s_opp[16]; + + if (!cpu_is_omap44xx() & !cpu_is_omap54xx()) { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + + row = 0; + maxrow = 0; + autoadjust_table_init(table); + autoadjust_table_strncpy(table, row, 0, "SR Convergence Status"); + autoadjust_table_strncpy(table, row, 1, "SR MPU"); + if (cpu_is_omap44xx()) + autoadjust_table_strncpy(table, row, 2, "SR IVA"); + else + autoadjust_table_strncpy(table, row, 2, "SR MM"); + autoadjust_table_strncpy(table, row, 3, "SR CORE"); + row++; + + for (i = 0; i < 3; i++) { + if (row > maxrow) + maxrow = row; + row = 1; + autoadjust_table_strncpy(table, row, 0, "SR Module"); + if (sr_regs[i].enabled == 0) { + autoadjust_table_strncpy(table, row, i + 1, "Disabled"); + row++; + continue; + } + mode = sr_is_enabled(sr_regs[i].srconfig); + autoadjust_table_strncpy(table, row, i + 1, + (char *) mode_table[mode]); + row++; + + autoadjust_table_strncpy(table, row, 0, "OPP"); + if (cpu_is_omap44xx()) { + voltdm44xx_get_opp((voltdm44xx_id) i + 1, &opp); + voltdm44xx_opp2string(s_opp, opp, + (voltdm44xx_id) i + 1); + } else if (cpu_is_omap54xx()) { + opp = voltdm54xx_opp_get((voltdm54xx_id) i + 1); + strncpy(s_opp, opp54xx_name_get(opp), 16); + } + autoadjust_table_strncpy(table, row, i + 1, s_opp); + row++; + autoadjust_table_strncpy(table, row, 0, "Converged?"); + if (sr_has_converged( + sr_regs[i].errconfig, sr_regs[i].senerror) == 1) + autoadjust_table_strncpy(table, row, i + 1, "YES"); + else + autoadjust_table_strncpy(table, row, i + 1, "NO"); + row++; + + autoadjust_table_strncpy(table, row, 0, + "Voltage Error (%, mV)"); + freq_error = sr_avg_sensor_error_percentage_get( + sr_regs[i].senerror); + vp_error_offset_get(sr_regs[i].vp_config, + &vp_offset_raw, &vp_offset); + vp_error_gain_get(sr_regs[i].vp_config, i + 1, + &vp_gain_raw, &vp_gain); + delta_vdd = sr_delta_vdd_get(freq_error, vp_offset, vp_gain); + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%.1lf%% (%.3lfmV)", freq_error, delta_vdd); + row++; + + autoadjust_table_strncpy(table, row, 0, + "Converged Voltage (V)"); + if (cpu_is_omap44xx()) { + if (voltdm44xx_get_voltage((voltdm44xx_id) i + 1, + &volt) == 0) + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%.6lfV", volt); + else + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "NA"); + } else if (cpu_is_omap54xx()) { + volt = voltdm54xx_voltage_get((voltdm54xx_id) i + 1); + if (volt > 0.0) + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "%.6lfV", volt); + else + snprintf(table[row][i + 1], TABLE_MAX_ELT_LEN, + "NA"); + } + row++; + + } + + if (stream != NULL) + autoadjust_table_fprint(stream, table, maxrow, 4); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION sr_config_audit + * @BRIEF audit SR settings + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in,out] stream: output file (NULL: no output (silent)) + * @param[in] sr_name: SR module name + * @param[in] opp_name: OPP name + * @param[in] sr_regs: SR registers content + * @param[in] sr_golden_settings: expected ("golden") SR settings + * @param[in,out] err_nbr: error number + * @param[in,out] wng_nbr: warning number + * @DESCRIPTION audit SR settings, by comparing current settings with + * predefined "golden" settings. + *//*------------------------------------------------------------------------ */ +int sr_config_audit(FILE *stream, const char *sr_name, const char *opp_name, + sr_registers *sr_regs, const sr_audit_settings *sr_golden_settings, + unsigned int *err_nbr, unsigned int *wng_nbr) +{ + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row; + double sys_clk, sr_sysclk; + opp44xx_id vdd_core_opp; + sr_interrupt_type irqtype; + mod_idle_mode idle_mode_curr, idle_mode_expected; + static const char mode_table[2][16] = { + "Disabled ", + "Enabled "}; + unsigned char curr, expected; + + if (!cpu_is_omap44xx() /* & !cpu_is_omap54xx() FIXME */) { + fprintf(stderr, "%s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } + CHECK_NULL_ARG(sr_name, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(sr_regs, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(sr_golden_settings, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + + *err_nbr = 0; + *wng_nbr = 0; + + if (cpu_is_omap44xx()) { + sys_clk = clk44xx_get_system_clock_speed(); + /* Get VDD_CORE OPP to detect DPLL cascading mode */ + voltdm44xx_get_opp(OMAP4_VDD_CORE, &vdd_core_opp); + if (vdd_core_opp == OMAP4_OPPDPLL_CASC) + sr_sysclk = 12.288; /* MHz */ + else + sr_sysclk = sys_clk; + } else { + sr_sysclk = + (double) module_clk_rate_get(MOD_SMARTREFLEX_MPU, 0) / 1000.0; + } + dprintf("%s(): sr_sysclk = %lfMHz\n", __func__, sr_sysclk); + + if (sr_regs->accessible == 0) { + if (stream != NULL) + fprintf(stream, "%s is disabled, audit cannot be " + "completed.\n\n", sr_name); + return 0; + } + row = 0; + autoadjust_table_init(table); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "%s AVS Configuration AUDIT (@%s)", sr_name, opp_name); + + autoadjust_table_strncpy(table, row, 1, "Current"); + autoadjust_table_strncpy(table, row, 2, "Expected"); + autoadjust_table_strncpy(table, row, 3, "STATUS"); + row++; + + autoadjust_table_strncpy(table, row, 0, + "SR_CLK Frequency"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%.3lfKHz", + sr_clk_rate_get(sr_regs->srconfig, sr_sysclk)); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.3lfKHz", + sr_golden_settings->sr_sysclk); + SR_AUDIT_SHOW_STATUS( + (unsigned int) sr_clk_rate_get(sr_regs->srconfig, sr_sysclk), + (unsigned int) sr_golden_settings->sr_sysclk); + + autoadjust_table_strncpy(table, row++, 0, + "Interrupt configuration"); + for (irqtype = SR_IRQ_MCUDISABLEACK; irqtype < SR_IRQ_TYPE_MAX; + irqtype++) { + snprintf(table[row][0], TABLE_MAX_ELT_LEN, " %s", + sr_interrupt_type_name_get(irqtype)); + curr = sr_irq_is_enabled( + sr_regs->irqenable_set, + sr_regs->errconfig, irqtype); + autoadjust_table_strncpy(table, row, 1, + (char *) mode_table[curr]); + expected = sr_golden_settings->irqmode[irqtype]; + autoadjust_table_strncpy(table, row, 2, + (char *) mode_table[expected]); + SR_AUDIT_SHOW_STATUS(curr, expected); + } + + autoadjust_table_strncpy(table, row, 0, + "SR Sensor N"); + curr = sr_is_sensor_enabled(sr_regs->srconfig, SR_SENSOR_N); + expected = sr_golden_settings->sensornmode; + autoadjust_table_strncpy(table, row, 1, + (char *) mode_table[curr]); + autoadjust_table_strncpy(table, row, 2, + (char *) mode_table[expected]); + SR_AUDIT_SHOW_STATUS(curr, expected); + + + autoadjust_table_strncpy(table, row, 0, + "SR Sensor P"); + curr = sr_is_sensor_enabled(sr_regs->srconfig, SR_SENSOR_P); + expected = sr_golden_settings->sensorpmode; + autoadjust_table_strncpy(table, row, 1, + (char *) mode_table[curr]); + autoadjust_table_strncpy(table, row, 2, + (char *) mode_table[expected]); + SR_AUDIT_SHOW_STATUS(curr, expected); + + autoadjust_table_strncpy(table, row, 0, + "Min/Max/Avg Detector Module"); + curr = sr_is_minmaxavg_detector_enabled(sr_regs->srconfig); + expected = sr_golden_settings->minmaxavg_detector_mode; + autoadjust_table_strncpy(table, row, 1, + (char *) mode_table[curr]); + autoadjust_table_strncpy(table, row, 2, + (char *) mode_table[expected]); + SR_AUDIT_SHOW_STATUS(curr, expected); + + autoadjust_table_strncpy(table, row, 0, + "Error Generator Module"); + curr = sr_is_error_generator_enabled(sr_regs->srconfig); + expected = sr_golden_settings->errgen_mode; + autoadjust_table_strncpy(table, row, 1, + (char *) mode_table[curr]); + autoadjust_table_strncpy(table, row, 2, + (char *) mode_table[expected]); + SR_AUDIT_SHOW_STATUS(curr, expected); + + autoadjust_table_strncpy(table, row, 0, " Idle Mode"); + idle_mode_curr = + sr_error_generator_idle_mode_get(sr_regs->errconfig); + idle_mode_expected = sr_golden_settings->idle_mode; + autoadjust_table_strncpy(table, row, 1, + (char *) mod_idle_mode_name_get(idle_mode_curr)); + autoadjust_table_strncpy(table, row, 2, + (char *) mod_idle_mode_name_get(idle_mode_expected)); + SR_AUDIT_SHOW_STATUS(idle_mode_curr, idle_mode_expected); + + autoadjust_table_strncpy(table, row, 0, " WAKEUPENABLE"); + curr = sr_is_error_generator_wakeup_enabled( + sr_regs->errconfig); + expected = sr_golden_settings->wakeupenable; + autoadjust_table_strncpy(table, row, 1, + (char *) mode_table[curr]); + autoadjust_table_strncpy(table, row, 2, + (char *) mode_table[expected]); + SR_AUDIT_SHOW_STATUS(curr, expected); + + autoadjust_table_strncpy(table, row, 0, " ERRMINLIMIT"); + curr = sr_error_generator_minlimit_get(sr_regs->errconfig); + expected = sr_golden_settings->errminlimit; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.1lf%%)", curr, + sr_error_generator_limit_hex2percent((signed char) curr)); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.1lf%%)", expected, + sr_error_generator_limit_hex2percent((signed char) expected)); + SR_AUDIT_SHOW_STATUS(curr, expected); + + autoadjust_table_strncpy(table, row, 0, " ERRMAXLIMIT"); + curr = sr_error_generator_maxlimit_get(sr_regs->errconfig); + expected = sr_golden_settings->errmaxlimit; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "0x%02X (%.1lf%%)", curr, + sr_error_generator_limit_hex2percent((signed char) curr)); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "0x%02X (%.1lf%%)", expected, + sr_error_generator_limit_hex2percent((signed char) expected)); + SR_AUDIT_SHOW_STATUS(curr, expected); + + autoadjust_table_strncpy(table, row, 0, + " ERRWEIGHT"); + curr = sr_error_generator_weight_get(sr_regs->errconfig); + expected = sr_golden_settings->errweight; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "0x%1X (%u)", + curr, curr); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "0x%1X (%u)", + expected, expected); + SR_AUDIT_SHOW_STATUS(curr, expected); + + autoadjust_table_strncpy(table, row, 0, "Convergence Status"); + curr = sr_has_converged( + sr_regs->errconfig, sr_regs->senerror); + expected = sr_golden_settings->converged; + if (curr == 1) + autoadjust_table_strncpy(table, row, 1, "Converged"); + else + autoadjust_table_strncpy(table, row, 1, + "Not Converged"); + if (expected == 1) + autoadjust_table_strncpy(table, row, 2, "Converged"); + else + autoadjust_table_strncpy(table, row, 2, + "Not Converged"); + SR_AUDIT_SHOW_STATUS(curr, expected); + + if (stream != NULL) { + autoadjust_table_fprint(stream, table, row, 4); + fprintf(stream, "NB:\n"); + fprintf(stream, " - Report 'FAIL' when current setting is " + "different than golden setting.\n"); + fprintf(stream, " - Report 'Pass' when current setting " + "matches golden setting.\n\n"); + } + + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/sr.h tiomapconf-1.61.1/arch/arm/mach-omap/common/sr.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/sr.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/sr.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,210 @@ +/* + * + * @Component OMAPCONF + * @Filename sr.h + * @Description SMARTREFLEX Common Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2006 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2006 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __SR_H__ +#define __SR_H__ + + +#include +#include + + +#define SR_SENSOR_TYPE_MAX_LENGTH 8 +#define SR_SENSOR_VAL_TYPE_MAX_LENGTH 8 +#define SR_SENSOR_VAL_STATUS_MAX_LENGTH 16 +#define SR_IRQ_TYPE_MAX_LENGTH 16 + + +typedef struct { + unsigned char accessible; + unsigned int srconfig; + unsigned int srstatus; + unsigned int senval; + unsigned int senmin; + unsigned int senmax; + unsigned int senavg; + unsigned int avgweight; + unsigned int nvaluereciprocal; + unsigned int irqstatus_raw; + unsigned int irqstatus; + unsigned int irqenable_set; + unsigned int senerror; + unsigned int errconfig; + /* OMAP5+ only */ + unsigned int lvtsenval; + unsigned int lvtsenmin; + unsigned int lvtsenmax; + unsigned int lvtsenavg; + unsigned int lvtnvaluereciprocal; +} sr_registers; + + +typedef struct { + unsigned char enabled; + unsigned int srconfig; + unsigned int senerror; + unsigned int errconfig; + unsigned int vp_config; +} sr_status_registers; + + +typedef enum { + SR_SENSOR_N, + SR_SENSOR_P, + SR_SENSOR_TYPE_MAX, +} sr_sensor_type; + + +typedef enum { + SR_SENSOR_VAL_LATEST, + SR_SENSOR_VAL_MIN, + SR_SENSOR_VAL_MAX, + SR_SENSOR_VAL_AVG, + SR_SENSOR_VAL_TYPE_MAX, +} sr_sensor_value_type; + + +typedef enum { + SR_SENSOR_VAL_INVALID, + SR_SENSOR_VAL_VALID, + SR_SENSOR_VAL_FINAL, + SR_SENSOR_VAL_STATUS_MAX +} sr_sensor_value_status; + + +typedef enum { + SR_IRQ_MCUDISABLEACK, + SR_IRQ_MCUBOUNDS, + SR_IRQ_MCUVALID, + SR_IRQ_MCUACCUM, + SR_IRQ_VPBOUNDS, + SR_IRQ_TYPE_MAX +} sr_interrupt_type; + + +typedef struct { + double sr_sysclk; /* in KHz */ + unsigned char irqmode[SR_IRQ_TYPE_MAX]; + unsigned char sensornmode; + unsigned char sensorpmode; + unsigned char minmaxavg_detector_mode; + unsigned char errgen_mode; + mod_idle_mode idle_mode; + unsigned char wakeupenable; + signed char errminlimit; + signed char errmaxlimit; + unsigned char errweight; + unsigned char converged; +} sr_audit_settings; + + +int sr_config_show(FILE *stream, sr_registers sr_regs[3]); +int sr_convergence_status_show(FILE *stream, sr_status_registers sr_regs[3]); +int sr_config_audit(FILE *stream, const char *sr_name, const char *opp_name, + sr_registers *sr_regs, const sr_audit_settings *sr_golden_settings, + unsigned int *err_nbr, unsigned int *wng_nbr); + +const char *sr_sensor_type_name_get(sr_sensor_type type); +const char *sr_sensor_value_type_name_get(sr_sensor_value_type type); +const char *sr_sensor_value_status_name_get(sr_sensor_value_status status); +const char *sr_interrupt_type_name_get(sr_interrupt_type type); + +/* Smart-Reflex module-related functions */ +unsigned char sr_is_enabled(unsigned int sr_config); +unsigned char sr_has_converged(unsigned int errconfig, unsigned int senerror); +unsigned char sr_clk_div_get(unsigned int sr_config); +double sr_clk_rate_get(unsigned int sr_config, double sr_sysclk); +unsigned char sr_is_minmaxavg_detector_enabled(unsigned int sr_config); +unsigned char sr_accumdata_count_get(unsigned int sr_config); +unsigned char sr_avg_weighting_factor_get(unsigned int avgweight, + sr_sensor_type type); + +/* Smart-Reflex Error Generator-related functions */ +unsigned char sr_is_error_generator_enabled(unsigned int sr_config); +mod_idle_mode sr_error_generator_idle_mode_get(unsigned int errconfig); +unsigned char sr_is_error_generator_wakeup_enabled(unsigned int errconfig); +double sr_error_generator_limit_hex2percent(signed char limit); +unsigned char sr_error_generator_minlimit_get(unsigned int errconfig); +double sr_error_generator_minlimit_percentage_get(unsigned int errconfig); +unsigned char sr_error_generator_maxlimit_get(unsigned int errconfig); +double sr_error_generator_maxlimit_percentage_get(unsigned int errconfig); +unsigned char sr_error_generator_weight_get(unsigned int errconfig); +sr_sensor_value_status sr_sensor_error_value_status_get( + unsigned int srstatus); +unsigned char sr_sensor_error_value_get(unsigned int senerror); +double sr_sensor_error_percentage_get(unsigned int senerror); +sr_sensor_value_status sr_avg_sensor_error_value_status_get( + unsigned int srstatus); +unsigned char sr_avg_sensor_error_value_get(unsigned int senerror); +double sr_avg_sensor_error_percentage_get(unsigned int senerror); +double sr_delta_vdd_get(double freq_error, double vp_offset, double vp_gain); + +/* Smart-Reflex Sensors-related functions */ +unsigned char sr_is_sensors_disabled(unsigned int sr_config); +unsigned char sr_is_sensor_enabled(unsigned int sr_config, sr_sensor_type type); +unsigned char sr_gain_get(unsigned int nvaluereciprocal, sr_sensor_type type); +unsigned char sr_scale_value_get(unsigned int nvaluereciprocal, + sr_sensor_type type); +unsigned int sr_ntarget_get(unsigned int nvaluereciprocal, sr_sensor_type type); +sr_sensor_value_status sr_sensor_value_status_get(unsigned int srstatus); +unsigned int sr_sensor_value_get(sr_registers *sr_regs, sr_sensor_type sen_type, + sr_sensor_value_type val_type); +unsigned int sr_lvt_sensor_value_get(sr_registers *sr_regs, + sr_sensor_type sen_type, sr_sensor_value_type val_type); + +/* Smart-Reflex IRQ-related functions */ +unsigned char sr_irq_is_enabled(unsigned int irqenable_set, + unsigned int errconfig, sr_interrupt_type type); +unsigned char sr_irq_status_is_set(unsigned int irqstatus, + unsigned int errconfig, sr_interrupt_type type); +unsigned char sr_irq_raw_status_is_set(unsigned int irqstatus_raw, + sr_interrupt_type type); + +/* Smart-Reflex LVT Sensors-related functions */ +unsigned char sr_is_lvt_sensors_disabled(unsigned int sr_config); +unsigned char sr_is_lvt_sensor_enabled(unsigned int sr_config, + sr_sensor_type type); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/cToolsHelper.c tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/cToolsHelper.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/cToolsHelper.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/cToolsHelper.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,259 @@ +/* + * cToolsHelper.c + * + * cTools Helper public functions. + * + * Copyright (C) 2009,2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +//Note this file to be updated for the specific implementation + +#include +#include +#include +#include + +#ifdef __linux__ + #include + #include + + // Mapping paramters + typedef struct _MapObject { + void * vAddr; // Virtural Address + unsigned int mapSize; // Map size in Bytes + struct _MapObject * pPrevMapObj; + struct _MapObject * pNextMapObj; + }MapObject; + + MapObject * pMapObjLL = 0; // Map Object Link List Pointer + + static int fd = 0; + static const unsigned int pageSize = 4096; + static const unsigned int pageMask = 4096-1; +#endif + +// Memory allocation +void * cTools_memAlloc(size_t sizeInBytes) +{ + return((void *)malloc (sizeInBytes)); +} + +// Memory free +void cTools_memFree(void *p) +{ + free(p); +} + +//Returns virtual address to region requested +void * cTools_memMap(unsigned int phyAddr, unsigned int mapSizeInBytes) +{ +#ifdef __linux__ + + void * pVirtualAddress = NULL; + unsigned int mapSize = 0; + MapObject *pMapObj; + + // Only open the /dev/mem device once + if(0 == fd) + { + if((fd = open("/dev/mem", O_RDWR | O_SYNC | O_RSYNC)) == -1) + { + #ifdef _DEBUG + printf("cTools_memMap:: Device '/dev/mem' could not be opened with O_RDWR | O_SYNC attributes.\n"); + #endif + return NULL; + } + } + + // Allocate space for the map object + if ( ( pMapObj = (MapObject *)cTools_memAlloc(sizeof(MapObject))) == NULL ) + { + printf("cTools_memMap:: Unable to create map object, malloc failed\n"); + return NULL; + } + + //Note: phyAddr may need to be aligned to a PAGE_SIZE and mapSizeInBytes may need to be + // a multiple of PAGE_SIZE. Since the STM physical size is either 256KB or 1MB + // this should not be an issue. It is assumed that the Virtual Address returned will + // map to the first location of physical STM space. + + // Adjust mapSizeInBytes to a whole number of pages + if ((mapSizeInBytes % pageSize) != 0 ) + { + mapSize = ((mapSizeInBytes/pageSize) + 1 ) * pageSize; + } + else + { + mapSize = mapSizeInBytes; + } + + pVirtualAddress = mmap(0, mapSize, (PROT_READ|PROT_WRITE), MAP_SHARED, fd, phyAddr & ~pageMask); + + if (pVirtualAddress == (void *) -1) + { + cTools_memFree(pMapObj); + #ifdef _DEBUG + printf("cTools_memMap:: Unable to map physical address 0x%X for %d bytes\n", phyAddr, mapSizeInBytes); + #endif + return NULL; + } + + // Add map object to end of link list + pMapObj->vAddr = pVirtualAddress; + pMapObj->mapSize = mapSize; + pMapObj->pNextMapObj = NULL; + if ( NULL == pMapObjLL ) + { + pMapObjLL = pMapObj; + pMapObj->pPrevMapObj = NULL; + } + else + { + //search the link list for the current last element + MapObject *pThisMapObj = pMapObjLL; + while ( NULL != pThisMapObj->pNextMapObj) { + pThisMapObj = pThisMapObj->pNextMapObj; + } + + pThisMapObj->pNextMapObj = pMapObj; + pMapObj->pPrevMapObj = pThisMapObj; + } + + // Virtual addres must be adjusted with LS 12 bits of the phyAddr + pVirtualAddress += phyAddr & pageMask; + + return pVirtualAddress; + +#else // __linux__ not defined + + #ifdef _DEBUG + printf("cTools_memMap:: Mapping physical address 0x%X for %d bytes\n", phyAddr, mapSizeInBytes); + #endif + return (void *)phyAddr; + +#endif +} + +//Unmap virtual address space of region requested +void cTools_memUnMap(void * vAddr, unsigned int mapSizeInBytes) +{ +#ifdef __linux__ + if( munmap(vAddr, mapSizeInBytes) == -1 ) + { + #ifdef _DEBUG + printf("cTools_memUnMap:: Unable to unmap address 0x%X for %d bytes\n", (unsigned)vAddr, mapSizeInBytes); + #endif + return; + } + + //Mask address and look it up + MapObject * pThisMapObj = pMapObjLL; + + while (( (unsigned int)vAddr & ~pageMask ) != (unsigned int)pThisMapObj->vAddr ) + { + pThisMapObj = pThisMapObj->pNextMapObj; + if ( NULL == pThisMapObj ) + { + #ifdef _DEBUG + printf("cTools_memUnMap:: Failed to find vitural address 0x%X in lookup table\n", (unsigned)vAddr & ~pageMask); + #endif + return; + } + } + + if( munmap(pThisMapObj->vAddr, pThisMapObj->mapSize) == -1 ) + { + #ifdef _DEBUG + printf("cTools_memUnMap:: Unmap failed for address 0x%X for %d bytes\n", (unsigned)pThisMapObj->vAddr, pThisMapObj->mapSize); + #endif + return; + } + + //Fix map object link + // If this is the only object in the list + if ( ( NULL == pThisMapObj->pNextMapObj ) && ( NULL == pThisMapObj->pPrevMapObj ) ) + { + pMapObjLL = NULL; + close(fd); // close memory device handle + fd = 0; + } + + // If first in list need to update list pointer to next element + if ( ( NULL != pThisMapObj->pNextMapObj ) && ( NULL == pThisMapObj->pPrevMapObj ) ) + { + pMapObjLL = pThisMapObj->pNextMapObj; + pThisMapObj->pNextMapObj->pPrevMapObj = NULL; + + } + + // If last object then just need to make the prev map object the last + if ( ( NULL == pThisMapObj->pNextMapObj ) && ( NULL != pThisMapObj->pPrevMapObj ) ) + { + pThisMapObj->pPrevMapObj->pNextMapObj = NULL; + } + + // If in the middle of list then need to remove + if ( ( NULL != pThisMapObj->pNextMapObj ) && ( NULL != pThisMapObj->pPrevMapObj ) ) + { + // - The previous map object's next pointer is updated with this object's next pointer + pThisMapObj->pPrevMapObj->pNextMapObj = pThisMapObj->pNextMapObj; + // - The next map object's previous pointer is updated with this objects previous pointer + pThisMapObj->pNextMapObj->pPrevMapObj = pThisMapObj->pPrevMapObj; + } + + // - Free this object + cTools_memFree(pThisMapObj); + +#endif +#ifdef _DEBUG + printf("cTools_memUnMap:: unmap request for address 0x%X for %d bytes\n", (unsigned)vAddr, mapSizeInBytes); +#endif +} + +int cTools_mutexInit(uint32_t mutexId) +{ + mutexId = mutexId; /* dummy instruction to remove compilation warning */ + return 0; +} + +int cTools_mutexTrylock(uint32_t mutexId) +{ + mutexId = mutexId; /* dummy instruction to remove compilation warning */ + return 0; +} + +int cTools_mutexUnlock(uint32_t mutexId) +{ + mutexId = mutexId; /* dummy instruction to remove compilation warning */ + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci.c tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1656 @@ +/* + * sci.c + * + * Statistic Collector Instrumentation Library + * - Statistic Collector module specific definitions + * - Device specific configurations + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ +#include "sci.h" +#include "sci_common.h" +#ifdef _STM_Logging +#include "StmSupport.h" +#include +#endif +#include +/* + * + * Public external function prototypes + * + */ + +#ifndef _DOXYGEN_IGNORE +extern void * cTools_memAlloc(size_t sizeInBytes); +extern void cTools_memFree(void * ptr); +extern void * cTools_memMap(unsigned int phyAddr, unsigned int mapSizeInBytes); +extern void cTools_memUnMap(void * vAddr, unsigned int mapSizeInBytes); +extern int cTools_mutexInit(uint32_t mutexId); +extern int cTools_mutexTrylock(uint32_t mutexId); +extern int cTools_mutexUnlock(uint32_t mutexId); +extern int mem_read(unsigned int reg_addr, unsigned int *reg_val); +#endif + +/* + * + * Private decarations + * + */ + + +enum sci_state {SCI_MOD_DISABLED, SCI_MOD_ENABLED }; + +struct sci_usecase_key_t { + int module_index; + int num_counters; + int counter_index[2]; + int usecase; /* Either sci_sdram_usecase or sci_mstr_usecase */ + char * pmeta_data_buf; + int meta_data_byte_cnt; + struct sci_usecase_key_t * next; + struct sci_usecase_key_t * prev; +}; + +struct sci_handle_t { + enum sci_state mod_state; + sci_callback psci_callback; + uint32_t sdram_msg_rate; + uint32_t mstr_msg_rate; + bool trigger_enable; + struct sci_usecase_key_t * pusecase_head; /* use case link list pointer */ + enum sci_mode mode; +#ifdef _STM_Logging + bool stm_log_enable; + STMHandle * pstm_handle; + int32_t stm_ch; + uint32_t data_options; +#endif +}; + +struct usecase_parms { + int num_cntr_req; /* Number of SC counters required */ + uint32_t reqevt; + uint32_t rspevt; + int port_type; + uint32_t op_sel[2]; + uint32_t evt_info_sel[2]; +}; + +enum sci_err get_meta_data(psci_handle const phandle, struct sci_usecase_key_t * puc_key, + const char * probe_name, + const char * trans_type, + const char * master_or_slave_name, + uint32_t mask ); +enum sci_err send_meta_data (psci_handle const phandle); +enum sci_err get_usecase_params( int usecase, struct usecase_parms * pusecase_parms); +enum sci_err get_cntr(enum sci_module_type mod_type, int probe_id, int usecase, + int num_filters, int num_cntr_req, + int * mod_index, int * cntr_assigned); +void * get_cntr_addr( int mod, int cnt_index); +void * get_filter_addr ( int mod, int cnt_index, int filter_index); +void put_uckey(psci_handle const phandle, struct sci_usecase_key_t * puc_key); +int sys_to_phys_addr(int sys_addr); + +/* + * sci_open + * + */ +enum sci_err sci_open(psci_handle * const pphandle, struct sci_config * const pcnfg) +{ + int i; + int tmp_cnt = 0; + uint32_t mode = 0; /* Default is SCI_MODE_STM */ + enum sci_err ret_val = SCI_SUCCESS; + + /* If pCPT_Handle is not NULL then return error */ + if (NULL != *pphandle) + ret_val = SCI_ERR_INVALID_HANDLE; + + + /* If config parameters are provided test they are valid */ + if ((SCI_SUCCESS == ret_val) && ( NULL != pcnfg )){ + if ( 0 == pcnfg->sdram_msg_rate ) + ret_val = SCI_ERR_INVALID_PARM; + if ( 0 == pcnfg->mstr_msg_rate ) + ret_val = SCI_ERR_INVALID_PARM; + } + + if (SCI_SUCCESS == ret_val){ + /* Attempt to map the CP Tracer base address of each SC Module*/ + for ( i=0; i < mod_cnt; i++ ) { + mod_map[i]->vbase_addr = (uint32_t *)cTools_memMap(mod_map[i]->base_addr, + mod_map[i]->mod_size); + tmp_cnt++; + } + if ( 0 == tmp_cnt ) + ret_val = SCI_ERR_MAPPING; + } + + /* call sci_get_version to check compatibility with the hw module*/ + if ( SCI_SUCCESS == ret_val) { + uint32_t plib_major_ver; + uint32_t plib_minor_ver; + uint32_t plib_func_id; + uint32_t pmod_func_id; + + ret_val = sci_get_version(*pphandle, &plib_major_ver, &plib_minor_ver, + &plib_func_id, &pmod_func_id ); + } + + /* Malloc the handle */ + if (SCI_SUCCESS == ret_val){ + * pphandle = (struct sci_handle_t *)cTools_memAlloc(sizeof(struct sci_handle_t)); + if ( NULL == * pphandle ) { + ret_val = SCI_ERR_MEM_ALLOC; + } + else { + /* Intialize the handle */ + (*pphandle)->mod_state = SCI_MOD_DISABLED; + (*pphandle)->pusecase_head = NULL; + if (NULL != pcnfg){ + (*pphandle)->psci_callback = pcnfg->errhandler; + (*pphandle)->sdram_msg_rate = pcnfg->sdram_msg_rate; + (*pphandle)->mstr_msg_rate = pcnfg->mstr_msg_rate; + (*pphandle)->trigger_enable = pcnfg->trigger_enable; + (*pphandle)->mode = pcnfg->mode; +#ifdef _STM_Logging + (*pphandle)->stm_log_enable = pcnfg->stm_log_enable; + (*pphandle)->pstm_handle = pcnfg->pstm_handle; + (*pphandle)->stm_ch = pcnfg->stm_ch; + (*pphandle)->data_options = pcnfg->data_options; +#endif + } + else { + (*pphandle)->psci_callback = NULL; + (*pphandle)->sdram_msg_rate = (uint32_t)-1; + (*pphandle)->mstr_msg_rate = (uint32_t)-1; + (*pphandle)->trigger_enable = false; + (*pphandle)->mode = SCI_MODE_STM; +#ifdef _STM_Logging + (*pphandle)->stm_log_enable = false; + (*pphandle)->pstm_handle = NULL; + (*pphandle)->stm_ch = 0; + (*pphandle)->data_options = 0; +#endif + } + + /* Decide on operation mode */ + + /* mode already initialized to the default 0 (for SCI_MODE_STM) */ + if (NULL != pcnfg) { + switch (pcnfg->mode){ + case SCI_MODE_DUMP: + mode = 0x1; + break; +#ifdef _SC_VER_1_16 + case SCI_MODE_STM_COND: + mode = 0x2; + break; + case SCI_MODE_DUMP_COND: + mode = 0x3; + break; + default: + /* + * mode already initialized to the default 0 + * (for SCI_MODE_STM). + * Just to remove compilation warning. + */ + break; +#endif + } + } + + /* Aquire ownership of each module mapped*/ + tmp_cnt = 0; + for ( i=0; i < mod_cnt; i++ ) { + + if (NULL != mod_map[i]->vbase_addr){ + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs; + sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr; + /* Request ownership */ + //if (0 == sc_regs->en) + { + sc_regs->en = 1; + /* Check collection time to confirm ownership */ +//TODO Put ownership conformation check back in +// if (0 == sc_regs->dump_collecttime) + { + sc_regs->dump_collecttime = (*pphandle)->sdram_msg_rate; + mod_map[i]->owner = true; + tmp_cnt++; + sc_regs->dump_manual = mode; + } + /* We are not going to clear sc_regs->en because + * we don't know that the debugger has not set it + * and we just got caught a race condition. + */ + } + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs; + sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr; + /* Request ownership */ + //if (0 == sc_regs->en) + { + sc_regs->en = 1; + /* Check collection time to confirm ownership */ +//TODO Put ownership conformation check back in +// if (0 == sc_regs->dump_collecttime) + { + sc_regs->dump_collecttime = (*pphandle)->mstr_msg_rate; + mod_map[i]->owner = true; + tmp_cnt++; + sc_regs->dump_manual = mode; + } + } + break; + } + } + } + } + if ( 0 == tmp_cnt ) { + ret_val = SCI_ERR_SC_NOT_AVAILABLE; + } + } + } + + //TODO for each module that is owned disable all the counters and filters. + + + + if ( SCI_SUCCESS != ret_val) { + + /* Must be a SCI_ERR_MEM_ALLOC or a SCI_ERR_OWNERSHIP */ + + /* unmap each non-null mod_map[i]->vbase_addr */ + for ( i=0; i < mod_cnt; i++ ) { + if ( NULL != mod_map[i]->vbase_addr ){ + cTools_memUnMap(mod_map[i]->vbase_addr, mod_map[i]->mod_size); + mod_map[i]->vbase_addr = NULL; + } + } + + /* If handle non-null free it and set it back to NULL*/ + if ( NULL != *pphandle ){ + cTools_memFree(*pphandle); + *pphandle = NULL; + } + + /* Call callback - ok to call with NULL handle*/ + if ( NULL != pcnfg->errhandler) + pcnfg->errhandler(*pphandle, __FUNCTION__, ret_val); + + } + + return ret_val; +} +/* + * sci_close + * + */ +enum sci_err sci_close(psci_handle * const pphandle) +{ + int i; + + if ( NULL == *pphandle ) + return SCI_ERR_INVALID_HANDLE; + + /* If any module is running need to disable */ + + if (SCI_MOD_ENABLED == (*pphandle)->mod_state){ + sci_global_disable(*pphandle); + } + + /* Remove any active use cases. + * Note - no error handling on call to sci_remove_usecase because + * we should only be able to add valid usecase pointers to the + * link list. + */ + while ( NULL != (*pphandle)->pusecase_head) { + psci_usecase_key pusecase_key = (*pphandle)->pusecase_head; + sci_remove_usecase (*pphandle, &pusecase_key); + } + + /*Disable and release ownership of modules */ + for ( i=0; i < mod_cnt; i++ ) { + + if ((NULL != mod_map[i]->vbase_addr) && ( true == mod_map[i]->owner )){ + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs; + sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr; + sc_regs->en = 0; + sc_regs->dump_collecttime = 0; + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs; + sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr; + sc_regs->en = 0; + sc_regs->dump_collecttime = 0; + break; + } + }/* end of switch */ + }/* end of if */ + }/* end of for */ + + /* unmap each non-null mod_map[i]->vbase_addr */ + for ( i=0; i < mod_cnt; i++ ) { + if ( NULL != mod_map[i]->vbase_addr ){ + cTools_memUnMap(mod_map[i]->vbase_addr, mod_map[i]->mod_size); + mod_map[i]->vbase_addr = NULL; + } + } + + if ( NULL != *pphandle ) + cTools_memFree(*pphandle); + + *pphandle = NULL; + + return SCI_SUCCESS; +} + +enum sci_err sci_get_version(psci_handle const phandle, uint32_t * const plib_major_ver, + uint32_t * const plib_minor_ver, + uint32_t * const plib_func_id, + uint32_t * const pmod_func_id ) +{ + int i; + int tmp_cnt; + uint32_t pmod_type_id; + enum sci_err ret_err = SCI_SUCCESS; + + /* Note that this function can be called with a NULL handle since + * in this case the handle is used only for error handling + */ + + * plib_major_ver = SCILIB_MAJOR_VERSION; + * plib_minor_ver = SCILIB_MINOR_VERSION; + * plib_func_id = SC_LIB_FUNC; + + + /* We are making the assumption that for a device all the + * SC modules are at least the same func and revision level. + */ + + /* Find the first module that is mapped */ + tmp_cnt = 0; + for ( i=0; i < mod_cnt; i++ ) { + if ( NULL != mod_map[i]->vbase_addr ){ + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr; + /* Request ownership */ + pmod_type_id = *(uint32_t *)(&sc_regs->stdhosthdr_core); + *pmod_func_id = GET_SCMOD_FUNC(*(uint32_t *)(&sc_regs->stdhosthdr_version)); + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr; + /* Request ownership */ + pmod_type_id = *(uint32_t *)(&sc_regs->stdhosthdr_core); + *pmod_func_id = GET_SCMOD_FUNC(*(uint32_t *)(&sc_regs->stdhosthdr_version)); + break; + } + } + + /* since we found a valid module can break out of for loop */ + tmp_cnt++; + break; + } + + } + + if ( 0 == tmp_cnt ) + ret_err = SCI_ERR_ACCESS; + else + if (mod_func_ver[i] != *pmod_func_id) + ret_err = SCI_ERR_REVISION; + if ( pmod_type_id != SC_MOD_TYPE ) + ret_err = SCI_ERR_REVISION; + + if ( (SCI_SUCCESS != ret_err) && (NULL != phandle) + && (NULL != phandle->psci_callback)) + phandle->psci_callback(phandle, __FUNCTION__, ret_err); + + return ret_err; +} + +enum sci_err sci_reg_usecase_sdram(psci_handle const phandle, + struct sci_config_sdram * const pcfg, + psci_usecase_key * pusecase_key ) +{ + int i,j,k; + int cntr_assigned[2] = {-1,-1}; /* free counter assigned */ + int mod; + int num_filters = 1; + struct usecase_parms uc_parms; + struct sc_sdram_regs * sc_regs = NULL; /* SC register pointer */ + struct sdram_filter filter[2]; + enum sci_err ret_err = SCI_SUCCESS; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + if ((NULL != *pusecase_key) || ( NULL == pcfg )) + ret_err = SCI_ERR_INVALID_PARM; + else + { + if (SCI_MOD_ENABLED == phandle->mod_state){ + ret_err = SCI_ERR_MODULE_ENABLED; + } + else + { + get_usecase_params( pcfg->usecase, &uc_parms); + + if (get_cntr(SDRAM, pcfg->probe_id, pcfg->usecase, pcfg->num_filters, + uc_parms.num_cntr_req, &mod, cntr_assigned)){ + ret_err = SCI_ERR_SC_NOT_AVAILABLE; + } + else + { + /* Generate and initialize the usecase key */ + *pusecase_key = (struct sci_usecase_key_t *)cTools_memAlloc(sizeof(struct sci_usecase_key_t)); + if ( NULL == *pusecase_key ) + ret_err = SCI_ERR_MEM_ALLOC; + } + } + } + + if ( SCI_SUCCESS != ret_err ){ + if (NULL != phandle->psci_callback) + phandle->psci_callback(phandle, __FUNCTION__, ret_err); + return ret_err; + } + + /* Note - no more errors possible after this point */ + + (*pusecase_key)->module_index = mod; + (*pusecase_key)->num_counters = uc_parms.num_cntr_req; + (*pusecase_key)->counter_index[0] = cntr_assigned[0]; + (*pusecase_key)->counter_index[1] = cntr_assigned[1]; + (*pusecase_key)->usecase = pcfg->usecase; + + /* put usecase key in the handle's link list */ + put_uckey(phandle, *pusecase_key); + + /* If the number of filters requested by the user is zero + * then setup the default values + */ + if (0 == pcfg->num_filters) { + filter[0].en = 1; + filter[0].mask_mstaddr = 0; /* Don't care - exclude from match */ + filter[0].mask_rd = 0; /* Enable all reads */ + filter[0].mask_wr = 0; /* Enable all writes */ + filter[0].mask_err = 0; /* no errors */ + filter[0].mask_userinfo = 0; /* Don't care - exclude from match */ + filter[0].match_mstaddr = 0; + filter[0].match_rd = 0; + filter[0].match_wr = 0; + filter[0].match_err = 0; + filter[0].match_userinfo = 0; + filter[1].en = 0; + + pcfg->filter[0].trans_qual = SCI_RD_OR_WR_DONTCARE; + } + else { + num_filters = pcfg->num_filters; + for ( i= 0; i< pcfg->num_filters; i++){ +#ifdef _OMAP4430_ES1 + filter[i].match_mstaddr = pcfg->filter[i].mstr_addr_match >>2; +#else + filter[i].match_mstaddr = pcfg->filter[i].mstr_addr_match; +#endif + if ( SCI_MASTID_ALL == pcfg->filter[i].mstr_addr_match) + filter[i].mask_mstaddr = 0; + else + filter[i].mask_mstaddr = pcfg->filter[i].mstr_addr_mask; + + switch (pcfg->filter[i].trans_qual) { + case SCI_RD_ONLY: + filter[i].mask_rd = 1; + filter[i].mask_wr = 1; + filter[i].match_rd = 1; + filter[i].match_wr = 0; + break; + case SCI_WR_ONLY: + filter[i].mask_rd = 1; + filter[i].mask_wr = 1; + filter[i].match_rd = 0; + filter[i].match_wr = 1; + break; + case SCI_RD_OR_WR_NONE: + filter[i].mask_rd = 1; + filter[i].mask_wr = 1; + filter[i].match_rd = 0; + filter[i].match_wr = 0; + break; + case SCI_RD_OR_WR_DONTCARE: + filter[i].mask_rd = 0; + filter[i].mask_wr = 0; + filter[i].match_rd = 0; + filter[i].match_wr = 0; + break; + default: + return SCI_ERR_INVALID_PARM; + } + + switch (pcfg->filter[i].error_qual ) { + case SCI_ERR_ONLY: + filter[i].mask_err = 1; + filter[i].match_err = 1; + break; + case SCI_ERR_NONE: + filter[i].mask_err = 1; + filter[i].match_err = 0; + break; + case SCI_ERR_DONTCARE: + filter[i].mask_err = 0; + filter[i].match_err = 0; + break; + default: + return SCI_ERR_INVALID_PARM; + } + + /* Set userinfo to don't care */ + filter[i].mask_userinfo = 0; + filter[i].match_userinfo = 0; + + /* All done so enable the filter last */ + filter[i].en = 1; + } + } + +#ifdef _STM_Logging + /* Setup the meta data */ + get_meta_data(phandle, *pusecase_key, + sdram_probe_name_table[pcfg->probe_id], + trans_type_table[pcfg->filter[0].trans_qual], + master_name_table[filter[0].match_mstaddr], + filter[0].mask_mstaddr ); +#endif + /* Mark the counters used */ + for ( j= 0; j < uc_parms.num_cntr_req; j++ ){ + (mod_map[mod]->cnt_map)[cntr_assigned[j]].used = true; + } + + /* Set the use case */ + mod_map[mod]->usecase = pcfg->usecase; + mod_map[mod]->usecase_cnt++; + + /* Program the sc module for the use case */ + sc_regs = (struct sc_sdram_regs *)mod_map[mod]->vbase_addr; + + if ( phandle->trigger_enable ) + sc_regs->trigen = 1; + else + sc_regs->trigen = 0; + + sc_regs->reqevt = uc_parms.reqevt; + sc_regs->rspevt = uc_parms.rspevt; + for ( j = 0; j < uc_parms.num_cntr_req; j++){ + sc_regs->evtmux_sel[cntr_assigned[j]] = (sdram_probe_map[pcfg->probe_id] * 2) + uc_parms.port_type; + } + + /* Program the filters + * Note that if two counters are needed for the use case, the filters of + * both counters are set identically + */ + for ( j=0; j < uc_parms.num_cntr_req; j++ ) { + for ( k=0; k < num_filters; k++ ) { + struct sdram_filter * sc_reg_filter = get_filter_addr(mod, cntr_assigned[j],k); + *sc_reg_filter = filter[k]; + } + } + + /*Program the counter */ + for ( k=0; k < uc_parms.num_cntr_req; k++ ) { + int num_filters = sdram_cnt_map[cntr_assigned[k]].num_filters; + if (2 == num_filters){ + struct sdram_cnt_filter2 * sc_cnt_addr = (struct sdram_cnt_filter2 *)get_cntr_addr( mod, cntr_assigned[k]); + sc_cnt_addr->op_sel = uc_parms.op_sel[k]; + sc_cnt_addr->op_evt_info_sel = uc_parms.evt_info_sel[k]; + sc_cnt_addr->globalen = 1; +#ifdef _SC_VER_1_16 + if (true == pcfg->addr_filter_enable){ + sc_cnt_addr->addren = 1; + sc_cnt_addr->addrmax= sys_to_phys_addr(pcfg->addr_filter_max) >> 12; + sc_cnt_addr->addrmin= sys_to_phys_addr(pcfg->addr_filter_min) >> 12; + } + else { + sc_cnt_addr->addren = 0; + sc_cnt_addr->addrmax= 0; + sc_cnt_addr->addrmin= 0; + } +#endif + } + if (1 == num_filters){ + struct sdram_cnt_filter1 * sc_cnt_addr = (struct sdram_cnt_filter1 *)get_cntr_addr( mod, cntr_assigned[k]); + sc_cnt_addr->op_sel = uc_parms.op_sel[k]; + sc_cnt_addr->op_evt_info_sel = uc_parms.evt_info_sel[k]; + sc_cnt_addr->globalen = 1; +#ifdef _SC_VER_1_16 + if (true == pcfg->addr_filter_enable){ + sc_cnt_addr->addren = 1; + sc_cnt_addr->addrmax= sys_to_phys_addr(pcfg->addr_filter_max) >> 12; + sc_cnt_addr->addrmin= sys_to_phys_addr(pcfg->addr_filter_min) >> 12; + } + else { + sc_cnt_addr->addren = 0; + sc_cnt_addr->addrmax= 0; + sc_cnt_addr->addrmin= 0; + } +#endif + } + if (0 == num_filters){ + struct sdram_cnt_filter0 * sc_cnt_addr = (struct sdram_cnt_filter0 *)get_cntr_addr( mod, cntr_assigned[k]); + sc_cnt_addr->op_sel = uc_parms.op_sel[k]; + sc_cnt_addr->op_evt_info_sel = uc_parms.evt_info_sel[k]; + sc_cnt_addr->globalen = 1; +#ifdef _SC_VER_1_16 + if (true == pcfg->addr_filter_enable){ + sc_cnt_addr->addren = 1; + sc_cnt_addr->addrmax= sys_to_phys_addr(pcfg->addr_filter_max) >> 12; + sc_cnt_addr->addrmin= sys_to_phys_addr(pcfg->addr_filter_min) >> 12; + } + else { + sc_cnt_addr->addren = 0; + sc_cnt_addr->addrmax= 0; + sc_cnt_addr->addrmin= 0; + } +#endif + } + } + + return SCI_SUCCESS; +} + + + +enum sci_err sci_reg_usecase_mstr(psci_handle const phandle, + struct sci_config_mstr * const pcfg, + psci_usecase_key * pusecase_key ) +{ + int j,k; + int cntr_assigned[2] = {-1,-1}; /* free counter assigned */ + int mod; + int num_filters = 1; + struct usecase_parms uc_parms; + struct sc_lat_regs * sc_regs = NULL; /* SC register pointer */ + struct lat_filter filter; + enum sci_err ret_err = SCI_SUCCESS; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + if ((NULL != *pusecase_key) || ( NULL == pcfg )) + ret_err = SCI_ERR_INVALID_PARM; + else + { + if (SCI_MOD_ENABLED == phandle->mod_state){ + ret_err = SCI_ERR_MODULE_ENABLED; + } + else { + get_usecase_params( pcfg->usecase, &uc_parms); + + + if (get_cntr(MSTR, pcfg->probe_id, pcfg->usecase, pcfg->num_filters, + uc_parms.num_cntr_req, &mod, cntr_assigned)) + ret_err = SCI_ERR_SC_NOT_AVAILABLE; + else { + *pusecase_key = (struct sci_usecase_key_t *)cTools_memAlloc(sizeof(struct sci_usecase_key_t)); + if ( NULL == *pusecase_key ) + ret_err = SCI_ERR_MEM_ALLOC; + } + } + } + + if ( SCI_SUCCESS != ret_err ){ + if (NULL != phandle->psci_callback) + phandle->psci_callback(phandle, __FUNCTION__, ret_err); + return ret_err; + } + + /* Note - no more errors possible after this point */ + + /* Generate and initialize the usecase key */ + (*pusecase_key)->module_index = mod; + (*pusecase_key)->num_counters = uc_parms.num_cntr_req; + (*pusecase_key)->counter_index[0] = cntr_assigned[0]; + (*pusecase_key)->counter_index[1] = cntr_assigned[1]; + (*pusecase_key)->usecase = pcfg->usecase; + + /* put usecase key in the handle's link list */ + put_uckey(phandle, *pusecase_key); + + /* If the number of filters requested by the user is zero + * then setup the default values + */ + if (0 == pcfg->num_filters) { + filter.en = 1; + filter.mask_mstaddr = 0; /* Don't care - exclude from match */ + filter.mask_rd = 0; /* Enable all reads */ + filter.mask_wr = 0; /* Enable all writes */ + filter.mask_err = 0; /* Enable all errors */ + filter.mask_slvaddr = 0; + filter.mask_requserinfo = 0; + filter.mask_rspuserinfo = 0; + filter.match_mstaddr = 0; + filter.match_rd = 0; + filter.match_wr = 0; + filter.match_err = 0; + filter.match_slvaddr = 0; + filter.match_requserinfo = 0; + filter.match_rspuserinfo = 0; + + pcfg->filter.trans_qual = SCI_RD_OR_WR_DONTCARE; + + } + else { + /* Only one filter */ + + filter.match_mstaddr = 0; + filter.mask_mstaddr = 0; + + filter.mask_requserinfo = 0; + filter.mask_rspuserinfo = 0; + filter.match_requserinfo = 0; + filter.match_rspuserinfo = 0; + + filter.match_slvaddr = pcfg->filter.slave_addr_match; + if ( SCI_SLVID_ALL == pcfg->filter.slave_addr_match) + filter.mask_slvaddr = 0; + else + filter.mask_slvaddr = pcfg->filter.slave_addr_match; + + switch (pcfg->filter.trans_qual) { + case SCI_RD_ONLY: + filter.mask_rd = 1; + filter.mask_wr = 1; + filter.match_rd = 1; + filter.match_wr = 0; + break; + case SCI_WR_ONLY: + filter.mask_rd = 1; + filter.mask_wr = 1; + filter.match_rd = 0; + filter.match_wr = 1; + break; + case SCI_RD_OR_WR_NONE: + filter.mask_rd = 1; + filter.mask_wr = 1; + filter.match_rd = 0; + filter.match_wr = 0; + break; + case SCI_RD_OR_WR_DONTCARE: + filter.mask_rd = 0; + filter.mask_wr = 0; + filter.match_rd = 0; + filter.match_wr = 0; + break; + default: + return SCI_ERR_INVALID_PARM; + } + + switch (pcfg->filter.error_qual ) { + case SCI_ERR_ONLY: + filter.mask_err = 1; + filter.match_err = 1; + break; + case SCI_ERR_NONE: + filter.mask_err = 1; + filter.match_err = 0; + break; + case SCI_ERR_DONTCARE: + filter.mask_err = 0; + filter.match_err = 0; + break; + default: + return SCI_ERR_INVALID_PARM; + } + + /* All done so enable the filter last */ + filter.en = 1; + } + +#ifdef _STM_Logging + /* Setup the meta data */ + get_meta_data(phandle, *pusecase_key, + mstr_probe_name_table[pcfg->probe_id], + trans_type_table[pcfg->filter.trans_qual], + master_name_table[filter.match_mstaddr], + filter.mask_mstaddr ); +#endif + + /* Mark the counters used */ + for ( j= 0; j < uc_parms.num_cntr_req; j++ ){ + (mod_map[mod]->cnt_map)[cntr_assigned[j]].used = true; + } + + /* Set the use case */ + mod_map[mod]->usecase = pcfg->usecase; + mod_map[mod]->usecase_cnt++; + + /* Program the sc module for the use case */ + sc_regs = (struct sc_lat_regs *)mod_map[mod]->vbase_addr; + + if ( phandle->trigger_enable ) + sc_regs->trigen = 1; + else + sc_regs->trigen = 0; + + sc_regs->reqevt = uc_parms.reqevt; + sc_regs->rspevt = uc_parms.rspevt; + for ( j = 0; j < uc_parms.num_cntr_req; j++){ + if ( LAT0 == mod ) + sc_regs->evtmux_sel[cntr_assigned[j]] = (lat0_probe_map[pcfg->probe_id] * 2) + uc_parms.port_type; + else + sc_regs->evtmux_sel[cntr_assigned[j]] = (lat1_probe_map[pcfg->probe_id] * 2) + uc_parms.port_type; + } + + /* Program the filters + * Note that of two counters are needed for the use case, the filters of + * both counters are set identically + */ + + for ( j=0; j < uc_parms.num_cntr_req; j++ ) { + for ( k=0; k < num_filters; k++ ) { + struct lat_filter * sc_reg_filter = get_filter_addr(mod, cntr_assigned[j],k); + *sc_reg_filter = filter; + } + } + + /*Program the counter */ + for ( k=0; k < uc_parms.num_cntr_req; k++ ) { + int num_filters = lat_cnt_map[cntr_assigned[k]].num_filters; + if (1 == num_filters){ + struct lat_cnt_filter1 * sc_cnt_addr = (struct lat_cnt_filter1 *)get_cntr_addr( mod, cntr_assigned[k]); + sc_cnt_addr->op_sel = uc_parms.op_sel[k]; + sc_cnt_addr->op_evt_info_sel = uc_parms.evt_info_sel[k]; + sc_cnt_addr->globalen = 1; + } + } + + return SCI_SUCCESS; +} + +enum sci_err sci_remove_usecase (psci_handle const phandle, psci_usecase_key * usecase_key) +{ + + int i; + int mod; + enum sci_err ret_err = SCI_SUCCESS; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + if (NULL == *usecase_key) + ret_err = SCI_ERR_INVALID_PARM; + else + if (SCI_MOD_ENABLED == phandle->mod_state) + ret_err = SCI_ERR_MODULE_ENABLED; + + if ( SCI_SUCCESS != ret_err ){ + if (NULL != phandle->psci_callback) + phandle->psci_callback(phandle, __FUNCTION__, ret_err); + return ret_err; + } + + /* Can't set mod value until after parameter checks */ + mod = (*usecase_key)->module_index; + + /* Mark the counters not used */ + for ( i= 0; i < (*usecase_key)->num_counters; i++ ){ + (mod_map[mod]->cnt_map)[(*usecase_key)->counter_index[i]].used = false; + } + + /*Disable each counter used */ + for ( i = 0; i < (*usecase_key)->num_counters; i++ ) { + + switch (mod_map[mod]->mod_type){ + case SDRAM: + { + int k; + int num_filters = sdram_cnt_map[(*usecase_key)->counter_index[i]].num_filters; + if (2 == num_filters){ + struct sdram_cnt_filter2 * sc_cnt_addr = (struct sdram_cnt_filter2 *)get_cntr_addr( mod, (*usecase_key)->counter_index[i]); + sc_cnt_addr->globalen = 0; + + } + if (1 == num_filters){ + struct sdram_cnt_filter1 * sc_cnt_addr = (struct sdram_cnt_filter1 *)get_cntr_addr( mod, (*usecase_key)->counter_index[i]); + sc_cnt_addr->globalen = 0; + + } + if (0 == num_filters){ + struct sdram_cnt_filter0 * sc_cnt_addr = (struct sdram_cnt_filter0 *)get_cntr_addr( mod, (*usecase_key)->counter_index[i]); + sc_cnt_addr->globalen = 0; + } + + /* disable all filters for the counter(s) used */ + for (k=0; k < num_filters; k++){ + struct sdram_filter * filter = (struct sdram_filter *)get_filter_addr( mod, (*usecase_key)->counter_index[i], k); + filter->en = 0; + } + + break; + + } + case MSTR: + { + struct lat_cnt_filter1 * sc_cnt_addr = (struct lat_cnt_filter1 *)get_cntr_addr( mod, (*usecase_key)->counter_index[i]); + struct sdram_filter * filter = (struct sdram_filter *)get_filter_addr( mod, (*usecase_key)->counter_index[i], 0); + sc_cnt_addr->globalen = 0; + filter->en = 0; + + break; + } + } + + + } + + /* Unlink the usecase from the link list */ + if ( (*usecase_key) == phandle->pusecase_head) { + phandle->pusecase_head = (*usecase_key)->next; + } + else { + ((*usecase_key)->prev)->next = (*usecase_key)->next; + ((*usecase_key)->next)->prev = (*usecase_key)->prev; + } + + + + /* If this is the last use case using the module, free it for a new use case */ + if (0 == --mod_map[mod]->usecase_cnt) + mod_map[mod]->usecase = -1; + + /* free the usecase buf and set the clients copy to NULL */ + cTools_memFree(*usecase_key); + *usecase_key = NULL; + + return SCI_SUCCESS; +} + +enum sci_err sci_global_enable(psci_handle const phandle) +{ + int i; + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + /* If the module's usecase count is > 0 then enable the module*/ + for ( i=0; i < mod_cnt; i++ ){ + if ( 0 < mod_map[i]->usecase_cnt ){ + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr;; + sc_regs->soften = 1; + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr;; + sc_regs->soften = 1; + break; + } + } /* End of switch */ + + } + + } + + return SCI_SUCCESS; + +} +enum sci_err sci_global_disable(psci_handle const phandle) +{ + int i; + enum sci_err ret_err = SCI_SUCCESS; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + /* If the module's usecase count is < 0 then disable the module */ + for ( i=0; i < mod_cnt; i++ ){ + if ( 0 < mod_map[i]->usecase_cnt ){ + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr; + sc_regs->soften = 0; + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr; + sc_regs->soften = 0; + break; + } + } /* End of switch */ + } + + } + + /* Send all meta data */ +#ifdef _STM_Logging + ret_err = send_meta_data(phandle); +#endif + if ( SCI_SUCCESS != ret_err ){ + if (NULL != phandle->psci_callback) + phandle->psci_callback(phandle, __FUNCTION__, ret_err); + return ret_err; + } + + + return SCI_SUCCESS; +} + +enum sci_err sci_dump(psci_handle const phandle ) +{ + int i; + /* Dump the counters for each module that has use cases enabled */ + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + for ( i=0; i < mod_cnt; i++ ) { + if ( 0 != mod_map[i]->usecase_cnt){ + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr;; + sc_regs->dump_send = 1; + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr;; + sc_regs->dump_send = 1; + break; + } + } /* End of switch */ + } + } + return SCI_SUCCESS; +} + +#ifdef _SC_VER_1_16 +enum sci_err sci_dump_info(psci_handle const phandle, psci_usecase_key usecase_key, int * num_sci_cntrs) +{ + enum sci_err ret_err = SCI_SUCCESS; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + if (NULL == usecase_key) { + ret_err = SCI_ERR_INVALID_PARM; + if (NULL != phandle->psci_callback) + phandle->psci_callback(phandle, __FUNCTION__, ret_err); + return ret_err; + } + + *num_sci_cntrs = usecase_key->num_counters; + return ret_err; +} + +enum sci_err sci_dump_sdram_cntrs(int num_sci_cntrs, uint32_t * pbuf) +{ + reg32_t *pdump_cntrs; + int i; + + struct sc_sdram_regs *sc_regs = (struct sc_sdram_regs *)mod_map[0]->vbase_addr; + pdump_cntrs = &sc_regs->dump_cnt[0]; + + for (i=0; i< num_sci_cntrs; i++){ + *pbuf++ = pdump_cntrs[i]; + } + return SCI_SUCCESS; +} + +enum sci_err sci_dump_cntrs(psci_handle const phandle, psci_usecase_key usecase_key, int num_sci_cntrs, uint32_t * pbuf) +{ + /* Dump the counters to pbuf for the provided usecase_key */ + reg32_t * pdump_cntrs; + + enum sci_err ret_err = SCI_SUCCESS; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + if (NULL == usecase_key) { + ret_err = SCI_ERR_INVALID_PARM; + if (NULL != phandle->psci_callback) + phandle->psci_callback(phandle, __FUNCTION__, ret_err); + return ret_err; + } + + switch (mod_map[usecase_key->module_index]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs = (struct sc_sdram_regs *)mod_map[usecase_key->module_index]->vbase_addr; + pdump_cntrs = &sc_regs->dump_cnt[0]; + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs = (struct sc_lat_regs *)mod_map[usecase_key->module_index]->vbase_addr; + pdump_cntrs = &sc_regs->dump_cnt[0]; + break; + } + } /* End of switch */ + + /* return the counters requested */ + if (NULL != pbuf) { + int i; + + for (i=0; i< num_sci_cntrs; i++){ + *pbuf++ = pdump_cntrs[usecase_key->counter_index[i]]; + } + } + + return ret_err; +} + +enum sci_err sci_dump_disable(psci_handle const phandle) +{ + int i; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + /* Disable dumping for each module that has usecases assigned */ + for ( i=0; i < mod_cnt; i++ ) { + if ( 0 != mod_map[i]->usecase_cnt){ + + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr;; + sc_regs->dump_disable = 1; + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr;; + sc_regs->dump_disable = 1; + break; + } + } /* End of switch */ + } + } + + return SCI_SUCCESS; +} +enum sci_err sci_dump_enable(psci_handle const phandle ) +{ + int i; + + if ( NULL == phandle ) + return SCI_ERR_INVALID_HANDLE; + + /* Enable dumping for each module that has usecases assigned */ + for ( i=0; i < mod_cnt; i++ ) { + if ( 0 != mod_map[i]->usecase_cnt){ + + switch (mod_map[i]->mod_type){ + case SDRAM: + { + struct sc_sdram_regs * sc_regs = (struct sc_sdram_regs *)mod_map[i]->vbase_addr;; + sc_regs->dump_disable = 0; + break; + } + case MSTR: + { + struct sc_lat_regs * sc_regs = (struct sc_lat_regs *)mod_map[i]->vbase_addr;; + sc_regs->dump_disable = 0; + break; + } + } /* End of switch */ + } + } + return SCI_SUCCESS; +} +#endif +/* + * Internal utility functions + * + */ + +enum sci_err get_usecase_params( int usecase, struct usecase_parms * pusecase_parms) +{ + + /* Initialize use case paramters */ + switch (usecase){ + case SCI_SDRAM_THROUGHPUT: + case SCI_MSTR_THROUGHPUT: + pusecase_parms->num_cntr_req = 1; + pusecase_parms->reqevt = SC_EVENT_SEL_PKT; + pusecase_parms->rspevt = SC_EVENT_SEL_PKT; //TODO - use to be SC_EVENT_SEL_NONE, but Joe is setting to PKT - + // so need to check throughput/sample with a short bursts to + // confrim byte count. + pusecase_parms->port_type = SC_REQUEST_PROBE; + pusecase_parms->op_sel[0] = SC_OPSEL_EVT_INFO; + pusecase_parms->evt_info_sel[0] = SC_EVTINFOSEL_BYTELEN; + break; + case SCI_SDRAM_LINKOCCUPY_REQUEST: + case SCI_MSTR_LINKOCCUPY_REQUEST: + pusecase_parms->num_cntr_req = 1; + pusecase_parms->reqevt = SC_EVENT_SEL_IDLE; + pusecase_parms->rspevt = SC_EVENT_SEL_NONE; + pusecase_parms->port_type = SC_REQUEST_PROBE; + pusecase_parms->op_sel[0] = SC_OPSEL_FILTER_HIT; + pusecase_parms->evt_info_sel[0] = 0; + break; + case SCI_SDRAM_LINKOCCUPY_RESPONSE: + case SCI_MSTR_LINKOCCUPY_RESPONSE: + pusecase_parms->num_cntr_req = 1; + pusecase_parms->reqevt = SC_EVENT_SEL_NONE; + pusecase_parms->rspevt = SC_EVENT_SEL_IDLE; + pusecase_parms->port_type = SC_RESPONSE_PROBE; + pusecase_parms->op_sel[0] = SC_OPSEL_FILTER_HIT; + pusecase_parms->evt_info_sel[0] = 0; + break; + case SCI_SDRAM_AVGBURST_LENGTH: + case SCI_MSTR_AVGBURST_LENGTH: + pusecase_parms->num_cntr_req = 2; + pusecase_parms->reqevt = SC_EVENT_SEL_PKT; + pusecase_parms->rspevt = SC_EVENT_SEL_NONE; + pusecase_parms->port_type = SC_REQUEST_PROBE; + pusecase_parms->op_sel[0] = SC_OPSEL_EVT_INFO; + pusecase_parms->evt_info_sel[0] = SC_EVTINFOSEL_BYTELEN; + pusecase_parms->op_sel[1] = SC_OPSEL_FILTER_HIT; + pusecase_parms->evt_info_sel[1] = 0; + break; + case SCI_MSTR_AVGLATENCY: + pusecase_parms->num_cntr_req = 2; + pusecase_parms->reqevt = SC_EVENT_SEL_LATENCY; + pusecase_parms->rspevt = SC_EVENT_SEL_LATENCY; + pusecase_parms->port_type = SC_RESPONSE_PROBE; //SC_REQUEST_PROBE; + pusecase_parms->op_sel[0] = SC_OPSEL_EVT_INFO; + pusecase_parms->evt_info_sel[0] = SC_EVTINFOSEL_LATENCY; + pusecase_parms->op_sel[1] = SC_OPSEL_FILTER_HIT; + pusecase_parms->evt_info_sel[1] = 0; + default: + return SCI_ERR_INVALID_PARM; + }; + + return SCI_SUCCESS; + + +} + +enum sci_err get_cntr (enum sci_module_type mod_type, int probe_id, int usecase, + int num_filters, int num_cntr_req, + int * mod_index, int * cntr_assigned) +{ + int i,j; + int cntr_assigned_cnt = 0; + int probe_num = -1; + + /* Search for a SDRAM SC module and available counter elements */ + for ( i=0; i < mod_cnt; i++ ) { + if ( (NULL != mod_map[i]->vbase_addr) + && (mod_type == mod_map[i]->mod_type) + && (true == mod_map[i]->owner)) { + + /* Does the module support the probe */ + for (j=0; j < mod_map[i]->num_ports; j++){ + if (probe_id == mod_map[i]->port_map[j]) { + probe_num = j; + break; + } + } + if ( -1 == probe_num ) continue; + + /* If the requested use case is not compatible + * with the SC module's current use case, then + * check the next module. + */ +#if 0 + if ( (0 != mod_map[i]->usecase_cnt) + && (!usecase_compat_table[usecase][mod_map[i]->usecase])) + continue; +#else + if ( (0 != mod_map[i]->usecase_cnt) + && (SC_GET_USECASE_COMPAT_VALUE(mod_map[i]->usecase) != 0) + && (SC_GET_USECASE_COMPAT_VALUE(mod_map[i]->usecase) + != SC_GET_USECASE_COMPAT_VALUE(usecase))) + continue; +#endif + /* Are there counters available that meets our needs? + * Note - this search function does not try to find the best + * match, just the first counter that meets the criteria. + */ + for ( j=0; j< mod_map[i]->num_counters; j++ ) { + if ( ( false == (mod_map[i]->cnt_map)[j].used) + && ( num_filters <= (mod_map[i]->cnt_map)[j].num_filters) ){ + cntr_assigned[cntr_assigned_cnt++] = j; + } + if ( num_cntr_req == cntr_assigned_cnt ) + break; + } + + /* If we could not find the right number release these + * and try another module. + */ + if ( num_cntr_req != cntr_assigned_cnt ) + cntr_assigned_cnt = 0; + /* now fall through to check next module */ + else + break; + } + } + + if (0 == cntr_assigned_cnt) { + return SCI_ERR_SC_NOT_AVAILABLE; + } + + *mod_index = i; + + return SCI_SUCCESS; +} + + +void put_uckey(psci_handle const phandle, struct sci_usecase_key_t * puc_key) +{ + /* Add the usecase struct to the link list */ + + struct sci_usecase_key_t * next = phandle->pusecase_head; + if (NULL == next){ + /* First usecase in link list */ + phandle->pusecase_head = puc_key; + puc_key->next = NULL; + puc_key->prev = NULL; + } + else{ + /* Walk the list until we find the end */ + while ( NULL != next->next ){ + next = next->next; + } + puc_key->prev = next; + puc_key->next = NULL; + next->next = puc_key; + } + +} + +#ifdef _STM_Logging +enum sci_err get_meta_data(psci_handle const phandle, struct sci_usecase_key_t * puc_key, + const char * probe_name, + const char * trans_type, + const char * master_or_slave_name, + uint32_t mask ) +{ + + int i; + int32_t chr_cnt = 0; + int32_t mod_id = puc_key->module_index; + const char * cnt_name[2]; + char formula[32]; + int formula_size = sizeof(formula); + int formula_cnt; + const char * unit; + int ofmask; + uint32_t msg_rate = ( SDRAM == puc_key->module_index ) ? phandle->sdram_msg_rate + : phandle->mstr_msg_rate; + + //Malloc enough space for the attribute string + puc_key->pmeta_data_buf = (char *)cTools_memAlloc(SCI_META_BUFSIZE); + if ( NULL == puc_key->pmeta_data_buf ) + { + return SCI_ERR_MEM_ALLOC; + } + + chr_cnt += snprintf (puc_key->pmeta_data_buf, SCI_META_BUFSIZE, + "{type=SC,id=%d,name=%s,sw=%d,suppress=%d,probe=%s:%s:%s+0x%x,", + mod_id, + module_name_table[mod_id], + msg_rate, + phandle->data_options, + probe_name, + trans_type, + master_or_slave_name, + mask); + + /* This will get updated if the usecase uses a latency counter */ + ofmask = cnt_overflow_norm[puc_key->module_index]; + + switch (puc_key->usecase){ + case SCI_SDRAM_THROUGHPUT: + case SCI_MSTR_THROUGHPUT: +#ifdef _SC_VER_1_16 + case SCI_SDRAM_THROUGHPUT_MINALARM: + case SCI_SDRAM_THROUGHPUT_MAXALARM: + case SCI_MSTR_THROUGHPUT_MINALARM: + case SCI_MSTR_THROUGHPUT_MAXALARM: +#endif + cnt_name[0] = cntr_name_payload; + formula_cnt = snprintf(formula, formula_size, "100*(#%d/%d):2", + puc_key->counter_index[0], + msg_rate); + unit = usecase_units_bytesperwindow; + break; + case SCI_SDRAM_LINKOCCUPY_REQUEST: + case SCI_SDRAM_LINKOCCUPY_RESPONSE: + case SCI_MSTR_LINKOCCUPY_REQUEST: + case SCI_MSTR_LINKOCCUPY_RESPONSE: + cnt_name[0] = cntr_name_idle; + formula_cnt = snprintf(formula, formula_size, "100*(#%d/%d):3", + puc_key->counter_index[0], + msg_rate); + unit = usecase_units_percent; + break; + case SCI_SDRAM_AVGBURST_LENGTH: + case SCI_MSTR_AVGBURST_LENGTH: + cnt_name[0] = cntr_name_payload; + cnt_name[1] = cntr_name_packcnt; + formula_cnt = snprintf(formula, formula_size, "#%d/#%d):1", + puc_key->counter_index[0], + puc_key->counter_index[1]); + unit = usecase_units_bytesperpacket; + break; + case SCI_MSTR_AVGLATENCY: +#ifdef _SC_VER_1_16 + case SCI_MSTR_LATENCY_MAXALARM: +#endif + cnt_name[0] = cntr_name_latcyc; + cnt_name[1] = cntr_name_lattrans; + ofmask = cnt_overflow_lat[puc_key->module_index]; + formula_cnt = snprintf(formula, formula_size, "#%d/#%d):9", + puc_key->counter_index[0], + puc_key->counter_index[1]); + unit = usecase_units_cyclespertrans; + break; + }; + +#ifdef _DEBUG + if (0 == ofmask) + return SCI_ERR_STM; +#endif + + if ( formula_size < formula_cnt ) + return SCI_ERR_STM; + + /* Add counter names */ + for (i=0; i< puc_key->num_counters; i++){ + chr_cnt += snprintf ( puc_key->pmeta_data_buf+chr_cnt, SCI_META_BUFSIZE, + "#%d=%s,", puc_key->counter_index[i], cnt_name[i]); + } + + /* Add formula section */ + int usecase_index = SC_USECASE_MASK(puc_key->usecase); + chr_cnt += snprintf ( puc_key->pmeta_data_buf+chr_cnt, SCI_META_BUFSIZE, + "/$name=%s,formula=%s,unit=%s,ofmask=%d,$/}\n", +// usecase_name_table[puc_key->usecase], + usecase_name_table[usecase_index], + formula, + unit, + ofmask); + + puc_key->meta_data_byte_cnt = chr_cnt; + + if ( SCI_META_BUFSIZE < chr_cnt ) + { + return SCI_ERR_STM; + } + + return SCI_SUCCESS; +} + + +enum sci_err send_meta_data(psci_handle const phandle) +{ + eSTM_STATUS stm_retval = eSTM_SUCCESS; + enum sci_err sci_retval = SCI_SUCCESS; +#ifdef _DEBUG + if (NULL == phandle->pusecase_head) + return SCI_ERR_STM; + if (NULL == phandle->pstm_handle) + return SCI_SUCCESS; +#endif + + + struct sci_usecase_key_t * next = phandle->pusecase_head; + while (NULL != next){ + /* Export meta data */ +#if 1 + stm_retval = STMExport_putMeta(phandle->pstm_handle, + next->pmeta_data_buf, + next->meta_data_byte_cnt); +#else + /* Export with a putMsg for debugging meta data */ + stm_retval = STMXport_putMsg(phandle->pstm_handle, 0, + next->pmeta_data_buf, + next->meta_data_byte_cnt); +#endif + if ( eSTM_SUCCESS != stm_retval ) + { + sci_retval = SCI_ERR_STM; + } + next = next->next; + } + return sci_retval; +} +#endif + +void * get_cntr_addr( int mod, int cnt_index) +{ + return (void *)((uint32_t)(mod_map[mod]->vbase_addr) + + mod_map[mod]->cnt_map[cnt_index].cnt_offset); +} +void * get_filter_addr ( int mod, int cnt_index, int filter_index) +{ + switch (mod) { + case SDRAM0: + { + /* Not that sdram_cnt_filter2 and sdram_cnt_filter1 are identical + * except for the number of filter elements in the array so use the + * largest to determine the address for all. + */ + struct sdram_cnt_filter2 * cnt_addr; + cnt_addr = (struct sdram_cnt_filter2 *)get_cntr_addr( mod, cnt_index); + return (void *)&(cnt_addr->filter[filter_index]); + } + case LAT0: + case LAT1: + { + struct lat_cnt_filter1 * cnt_addr; + cnt_addr = (struct lat_cnt_filter1 *)get_cntr_addr( mod, cnt_index); + return (void *)&(cnt_addr->filter[filter_index]); + } + }; + + return NULL; +} + +#if defined(_SC_VER_1_16) +int sys_to_phys_addr(int sys_addr) +{ + int i; + + int phys_addr; + int phys_addr_mask; + int sys_addr_msb; + DMM_LISA_MAP reg; + for(i=3;i>=0;i--) + { + int sys_addr_mask; + mem_read(DMM_LISA_MAP_BASE+i*4, ®.val); + //check if we hit the good section + sys_addr_mask = (1 << 8) - (1 << reg.sys_size); + sys_addr_msb = (sys_addr >> 24) & 0x000000FF; + if(reg.sys_addr == (sys_addr_msb & sys_addr_mask)) + break; + } + if(i<0) + { + printf("Error: can't find a section that hit by sys address\n"); + return 0xFFFFFFFF; + } + + phys_addr_mask = (1 << reg.sys_size) -1; + phys_addr_mask <<= 24; + phys_addr_mask |= 0x00FFFFFF; + sys_addr &= phys_addr_mask; + + //if interliving is enable + if(reg.sdrc_intl != 0) + { + int tmp; + //compute lower address + phys_addr_mask = (1 << (reg.sdrc_intl + 6)) -1; + phys_addr = sys_addr & phys_addr_mask; + + tmp = (sys_addr >> reg.sdrc_intl) & ~phys_addr_mask; + phys_addr |= (tmp & (0xFFFFFFFF >> reg.sdrc_intl)); + } + else + { + phys_addr = sys_addr; + } + + phys_addr |= reg.sdrc_addr << 24; + + return phys_addr; +} +#endif + diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci.h tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,901 @@ +/* + * sci.h + * + * Statistic Collector Instrumentation Library + * - API Definitions + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/*! \file sci.h + CPT Library Function Prototypes +*/ + +/* The following defines the generic APIs. sci_dev.h contains + * device specific definitions. + */ + +#ifndef SCI_H +#define SCI_H + +#include +#include // The library uses C99 exact-width integer types +#include "sci_dev.h" + +#if !defined(__bool_true_false_are_defined) && !defined(_STM_Logging) +typedef enum +{ + false = 0, + true = 1 + +}bool; +#endif + +#ifdef _STM_Logging +#include "StmLibrary.h" +#endif + +/* Note - the version definitions must have the end of line immediately + * after the value (packaging script requirement) + */ +#define SCILIB_MAJOR_VERSION (0x0) + /*!< Major version number + - Incremented for API changes*/ +#define SCILIB_MINOR_VERSION (0x2) + /*!< Minor version number + - Incremented for bug fixes */ + +/*! \par sci_handle + sci handle object. This is an incomplete structure, thus making the actual + implementation private to the library. +*/ +typedef struct sci_handle_t sci_handle; + +/*! \par psci_handle + Pointer to a sci handle object +*/ +typedef sci_handle * psci_handle; + +/*! \par sci_err + SCILib error codes +*/ +enum sci_err { + SCI_SUCCESS, /*!< Function completed with no errors */ + SCI_ERR_INVALID_HANDLE = -1, /*!< Invalid sci handle */ + SCI_ERR_INVALID_PARM = -2, /*!< Invalid function parameter */ + SCI_ERR_MAPPING = -3, /*!< Memory mapping error */ + SCI_ERR_SC_NOT_AVAILABLE = -4, /*!< SC module not avaiable */ + SCI_ERR_MEM_ALLOC = -5, /*!< Memory allocation error */ + SCI_ERR_ACCESS = -6, /*!< SC module access error */ + SCI_ERR_REVISION = -7, /*!< SC module unexpected revision */ + SCI_ERR_MODULE_ENABLED = -8, /*!< Module must be disabled for operation */ + SCI_ERR_STM = -9 /*!< STM error */ +}; + +/*! \par sci_callback + \param[in] phandle SCILib handle. + \param[in] func Constant char pointer to the function name, normally + provided by the compiler using the __FUNCTION__ macro. + \param[in] ::sci_err_t error returned by calling routine + + Definition of the user implmented callback funtion. See ::sci_config. + +*/ +typedef void(*sci_callback)(psci_handle phandle, const char * func, enum sci_err); + +/*! \par sci_mode SCI Library operating mode. Allows user to select SC Module + counter export mode. + */ +#ifdef _SC_VER_1_16 +enum sci_mode { + SCI_MODE_STM, /*!< Export SC Module counters periodically + via STM (normal operating mode). */ + SCI_MODE_DUMP, /*!< Export SC Module counters on demand + via STM (see ::sci_dump()). */ + SCI_MODE_STM_COND, /*!< Export SC Module counters conditionally + via STM */ + SCI_MODE_DUMP_COND /*!< Export SC Module counters conditionally + on demand (see ::sci_dump()). + */ +}; +#else +enum sci_mode { + SCI_MODE_STM, /*!< Export SC Module counters periodically + via STM (normal operating mode). */ + SCI_MODE_DUMP /*!< Export SC Module counters on demand + via STM (see ::sci_dump() */ +}; +#endif + +/*! \par sci_config SCI Library configuration structure. If sci_open()is called + with a NULL sci_config pointer then the default value for + each parameter is utilized. + */ +struct sci_config { + sci_callback errhandler; /*!< Called by any SCI Library function + prior to returning an error. May be set to + NULL to disable this feature. Default is NULL. + */ + uint32_t sdram_msg_rate; /*!< 32-bit non-zero value used to set the + rate at which messages are generated (based + on SC Module clock rate). + Setting to 0 is not legal and will result + in sci_open() returning ::SCI_ERR_INVALID_PARM. + Default is the maximum value the module + supports. A value that is too large may cause + counter saturation. Reducing this value may + reduce or eliminate saturation errors, and + will increase the data resolution. + */ + uint32_t mstr_msg_rate; /*!< 32-bit non-zero value used to set the + rate at which messages are generated (based + on SC Module clock rate). + Setting to 0 is not legal and will result + in sci_open() returning ::SCI_ERR_INVALID_PARM. + Default is the maximum value the module + supports. A value that is too large may cause + counter saturation. Reducing this value may + reduce or eliminate saturation errors, and + will increase the data resolution. + */ + bool trigger_enable; /*!< Cross triggers enable/disable. Default + is disable. If Enabled EMU0 trigger enables, + EMU1 trigger disables the SC module. + */ + uint32_t data_options; /*!< This is a bit field that enables sw + filtering of certain data characteristics. + Bit 0 - If 1 suppress zero data, if 0 don't + suppress zero data. If a SC Module is + enabled during cycles where no accesses + are performed this option allows the zero + data provided in these cases to be suppressed + from the data provided on the host. + This option will have no effect on the actual + STM bandwidth (in other words all data is + transmitted), but it may reduce host file + sizes significantly and in some cases decrease + data processing times. + */ + enum sci_mode mode; /*!< See ::sci_mode */ + +#ifdef _STM_Logging + bool stm_log_enable; /*!< Enable/disable library generated STM + logging messages. The default is disabled */ + STMHandle * pstm_handle; /*!< A pointer to a STM Handle for logging + and providing meta data (required by host + tools). The default is NULL.*/ + int stm_ch; /*!< A STM channel to use for SCI Library + logging messages. + */ +#endif +}; +/*! \par sci_open + + Open the SCI Library API. + + \param[out] pphandle A pointer to a NULL ::psci_handle. If sci_open + exits with a return value of ::SCI_SUCCESS, + the ::psci_handle pointer is set to a valid + sci handle object pointer. + \param[in] pconfig A pointer to a ::sci_config structure. + If pconfig is NULL all parameters are set to + their default values. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + \li ::SCI_ERR_INVALID_PARM + \li ::SCI_ERR_MEM_ALLOC + \li ::SCI_ERR_SC_NOT_AVAILABLE + \li ::SCI_ERR_REVISION + \li ::SCI_ERR_MAPPING + + \par Details: + \details + + This function must be called and return ::SCI_SUCCESS prior to calling any + other SCI Library function that requires a ::psci_handle. + If this function is called with a non-NULL ppHandle pointer this function + will exit and return ::SCI_ERR_INVALID_HANDLE. + + Any errors found with pconfig parameters will cause the function to exit + and return ::SCI_ERR_INVALID_PARM. + + If the device's SC module is not compatible with this version of the + library, this function will exit and return ::SCI_ERR_REVISION. + + The library will attempt to acquire ownsership of every SC module in the + system. Under normal circumstances only those SC modules used by the kernel + will not be avaiable, although the debugger can also own modules. If no + modules are avaiable then this function will exit and + return ::SCI_ERR_SC_NOT_AVAILABLE. + + Storage for sci_handle is allocated through a call to the client provided + external function cTools_memAlloc(). If a memory allocation error occurs + this function will exit and returns ::SCI_ERR_MEM_ALLOC. + cTools_memMap(), also a client provided function, is called to map the + physical SC Module base address to a virtual address space. If a mapping + error occurs this function exits returns ::SCI_ERR_MAPPING. + + If there are no errors detected the function exits with ::SC_SUCCESS. + + If pconfig is a NULL pointer, the default configuration parameters are: + \li errhandler is NULL. + \li pstm_handle is NULL. + \li SC STM messsage rate is set to the max value. + +*/ +enum sci_err sci_open (psci_handle * const pphandle, + struct sci_config * const pconfig); +/*! \par sci_close + + Close the SCI Library API. + + \param[out] pphandle A pointer to a ::psci_handle. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + + \par Details: + \details + + This function must be called and return ::SCI_SUCCESS to release resources + acquired with sci_open(). Any usecases that have not been removed, see + sci_remove_usecase(), will also be removed. + This function will also set the phandle pointed to by pphandle to NULL. + If pphandle points to a NULL phandle this function + will exit and return ::SCI_ERR_INVALID_HANDLE. + +*/ +enum sci_err sci_close (psci_handle * const pphandle); + +/*! \par sci_get_version + + Get version information ofthe SCILib and SC module. + + \param[out] phandle A pointer to a handle provided by sci_open. + \param[in] plib_major_ver A pointer to the location used to store the + libraries major version number. + \param[in] plib_minor_ver A pointer to the location used to store the + libraries minor version number. + \param[in] plib_func_id A pointer to the location used to store the + libraries functional id value. + \param[in] pmod_func_id A pointer to the location used to store the + SC module's functional id value. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_ACCESS + \li ::SCI_ERR_REVISION + + \par Details: + \details + + This function assumes that all the SC modules in a device are the same + revision and func id, so it only looks at the first module sci_open + aquired ownership for. This function will aquire the module's func id and + it's type identifier. If either do not match the values expected + for this device, this function will exit with ::SCI_ERR_REVISION. + If no SC modules are accessible (owned by an other application or debugger) + this function exits with ::SCI_ERR_ACCESS. + +*/ +enum sci_err sci_get_version (psci_handle const phandle, + uint32_t * const plib_major_ver, + uint32_t * const plib_minor_ver, + uint32_t * const plib_func_id, + uint32_t * const pmod_func_id ); + + +/*! \par sci_sdram_usecase Selects for sdram usecases */ + +/* Note that the usecase enums are encoded. The LS 16 bits are the normal + * usecase enumeration, and the MS 16 bits is a compatibility code. If the + * compatibility code is 0 the usecase is not compatible with any others. + * Bits 8:15 indicate the module type the usecase can be applied to, where: + * 0x00 is the SDRAM module + * 0x01 is the LAT moule + */ + +enum sci_sdram_usecase { + SCI_SDRAM_THROUGHPUT = 0x00010000, /*!< Throughput in bytes per + sample window usecase select */ + SCI_SDRAM_LINKOCCUPY_REQUEST = 0x00000001, /*!< Request Port Link occupancy + percentage usecase select */ + SCI_SDRAM_LINKOCCUPY_RESPONSE = 0x00000002, /*!< Response Port Link occupancy + percentage usecase select */ + SCI_SDRAM_AVGBURST_LENGTH = 0x00010003 /*!< Average burst length in + bytes usecase select */ +/* Since SDRAM does not support latency usecase must skip enum 0x00000004 */ +#ifdef _SC_VER_1_16 + , + SCI_SDRAM_THROUGHPUT_MINALARM = 0x00000005, /*!< Throughput minimum alarm + usecase */ + SCI_SDRAM_THROUGHPUT_MAXALARM = 0x00000006 /*!< Throughput maximum alarm + usecase */ +/* Since SDRAM does not support latency usecase must skip enum 0x00000007 */ +#endif + }; + +/*! \par sci_mstr_usecase Selects for master usecases */ + +enum sci_mstr_usecase { + SCI_MSTR_THROUGHPUT = 0x00010100, /*!< Throughput in bytes per + sample window usecase select */ + SCI_MSTR_LINKOCCUPY_REQUEST = 0x00000101, /*!< Request Port Link occupancy + percentage usecase select */ + SCI_MSTR_LINKOCCUPY_RESPONSE = 0x00000102, /*!< Response Port Link occupancy + percentage usecase select */ + SCI_MSTR_AVGBURST_LENGTH = 0x000010103, /*!< Average burst length in + bytes usecase select */ + SCI_MSTR_AVGLATENCY = 0x00000104 /*!< Average latency in + cycles usecase select */ +#ifdef _SC_VER_1_16 + , + SCI_MSTR_THROUGHPUT_MINALARM = 0x00000105, /*!< Throughput minimum alarm + usecase select*/ + SCI_MSTR_THROUGHPUT_MAXALARM = 0x00000106, /*!< Throughput maximum alarm + usecase select*/ + SCI_MSTR_LATENCY_MAXALARM = 0x00000107 /*< Average latency maximum + alarm usecase select */ +#endif +}; + +/*! \par sci_trans_qual Transaction qualification selects for both sdram and + master usecases. +*/ +enum sci_trans_qual { + SCI_RD_ONLY, /*!< Read transactions only */ + SCI_WR_ONLY, /*!< Write transactions only */ + SCI_RD_OR_WR_NONE, /*!< No read or write transactions - only errors*/ + SCI_RD_OR_WR_DONTCARE /*!< Either read or write transactions*/ +}; + +/*! \par sci_error_qual Error qualification selects for sdram and master + usecases. +*/ +enum sci_error_qual { + SCI_ERR_ONLY, /*!< Error transactions only */ + SCI_ERR_NONE, /*!< No error transactions */ + SCI_ERR_DONTCARE}; /*!< Error transactions don't care */ + +/*! \par sci_filter_sdram Filter configuration structure for sdram usecases */ +struct sci_filter_sdram +{ + enum sci_master_addr mstr_addr_match; /*!< Master address match */ + uint32_t mstr_addr_mask; /*!< Master address mask */ + enum sci_trans_qual trans_qual; /*!< Tranaction qualifier */ + enum sci_error_qual error_qual; /*!< Error qualifier */ +//#if _SC_VER_1_16 +// bool addr_filter_enable; /*!< Probe address filter enable */ +// uint32_t addr_filter_max; /*!< Probe address maximum */ +// uint32_t addr_filter_min; /*!< Probe address minimum */ +//#endif +}; + +/*! \par sci_filter_mstr Filter configuration structure for master usecases */ +struct sci_filter_mstr { + enum sci_slave_addr slave_addr_match; /*!< Slave address match */ + uint32_t slave_addr_mask; /*!< Slave address mask */ + enum sci_trans_qual trans_qual; /*!< Tranaction qualifier */ + enum sci_error_qual error_qual; /*!< Error qualifier */ +}; + +/*! \par sci_alarm Alarm configuration structure */ +#ifdef _SC_VER_1_16 +struct sci_alarm { + uint32_t alarm_min; /*!< Minimum alarm threshold */ + uint32_t alarm_max; /*!< Maximum alarm threshold */ + bool alarm_msg_enable; /*!< Enable STM messages on alarm */ + }; +#endif + +/*! \par sci_config_sdram Configuration structure for sdram usecases */ +struct sci_config_sdram { + enum sci_sdram_usecase usecase; /*!< sdram usecase selection */ + enum probeid_sdram probe_id; /*!< sdram probe selection */ + int num_filters; /*!< Number of filters required + for the usecase (0,1 or 2). */ + struct sci_filter_sdram filter[2]; /*!< sdram filters configuration*/ +#ifdef _SC_VER_1_16 + bool addr_filter_enable; /*!< Probe address filter enable */ + uint32_t addr_filter_min; /*!< Probe address minimum */ + uint32_t addr_filter_max; /*!< Probe address maximum */ + struct sci_alarm alarm; /*!< Alarm configuration */ +#endif +}; + +/*! \par sci_config_mstr Configuration structure for master usecases */ +struct sci_config_mstr { + enum sci_mstr_usecase usecase; /*!< Master usecase selection */ + enum probeid_mstr probe_id; /*!< Master probe selection */ + int num_filters; /*!< Number of filters required + for the usecase (0 or 1). */ + struct sci_filter_mstr filter; /*!< Master filter configuration */ +#if _SCI_VER_1_16 + struct sci_alarm alarm; /*!< Alarm configuration */ +#endif +}; + +/*! \par sci_usecase_key Usecase key opaque structure */ +typedef struct sci_usecase_key_t sci_usecase_key; +/*! \par sci_usecase_key Usecase key structure pointer */ +typedef sci_usecase_key * psci_usecase_key; + +/*! \par sci_reg_usecase_sdram + + Register a sdram usecase. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \param[in] pcfg A pointer to the sci_config_sdram structure + that defines this usecase. + + \param[out] usecase_key A pointer to a usecase_key pointer. The + usecase_key pointer must be initialized + to NULL. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + \li ::SCI_ERR_INVALID_PARM + \li ::SCI_ERR_MODULE_ENABLED + \li ::SCI_ERR_SC_NOT_AVAILABLE + \li ::SCI_ERR_MEM_ALLOC + + \par Details: + \details + + This function registers use cases for the sdram Statistic Collectors. + If ::SCI_SUCCESS is returned the function successfully registered and + programmed the usecase. This function may only be called if the module + has not been enabled (see sci_global_enable())or has been disabled + (see sci_global_disable()). + + If the number of filters is set to zero a default filter is used + (all filter masks set to 0 which enables all cycles, or in other words + disables all filtering). + + If phandle is NULL the function exots with ::SCI_ERR_INVALID_HANDLE. + if pcfg is NULL or the usecase key pointer is not NULL this function will + exit with ::SCI_ERR_INVALID_PARM. + If this function is called while the modules are enabled this function + exits with ::SCI_ERR_MODULE_ENABLED. + If a statistic counter that meets the requirements of the usecase is not + avaiable then this function exits with ::SCI_ERR_SC_NOT_AVAILABLE. + If memory allocation for the usecase key fails the function exits with + ::SCI_ERR_MEM_ALLOC. + +*/ +enum sci_err sci_reg_usecase_sdram(psci_handle const phandle, + struct sci_config_sdram * const pcfg, + psci_usecase_key * usecase_key ); + +/*! \par sci_reg_usecase_mstr + + Register a master usecase. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \param[in] pcfg A pointer to the sci_config_sdram structure + that defines this usecase. + + \param[out] usecase_key A pointer to a usecase_key pointer. The + usecase_key pointer must be initialized + to NULL. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + \li ::SCI_ERR_INVALID_PARM + \li ::SCI_ERR_MODULE_ENABLED + \li ::SCI_ERR_SC_NOT_AVAILABLE + \li ::SCI_ERR_MEM_ALLOC + + \par Details: + \details + + This function registers use cases for the master Statistic Collectors. + If ::SCI_SUCCESS is returned the function successfully registered and + programmed the usecase. This function may only be called if the module + has not been enabled (see sci_global_enable())or has been disabled + (see sci_global_disable()). + + If the number of filters is set to zero a default filter is used + (all filter masks set to 0 which enables all cycles, or in other words + disables all filtering). + + If phandle is NULL the function exots with ::SCI_ERR_INVALID_HANDLE. + if pcfg is NULL or the usecase key pointer is not NULL this function will + exit with ::SCI_ERR_INVALID_PARM. + If this function is called while the modules are enabled this function + exits with ::SCI_ERR_MODULE_ENABLED. + If a statistic counter that meets the requirements of the usecase is not + avaiable then this function exits with ::SCI_ERR_SC_NOT_AVAILABLE. + If memory allocation for the usecase key fails the function exits with + ::SCI_ERR_MEM_ALLOC. + +*/ +enum sci_err sci_reg_usecase_mstr(psci_handle const phandle, + struct sci_config_mstr * const pcfg, + psci_usecase_key * usecase_key ); + +/*! \par sci_remove_usecase + + Remove a registered sdram or master usecase. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \param[in] usecase_key A usecase_key pointer. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + \li ::SCI_ERR_INVALID_PARM + \li ::SCI_ERR_MODULE_ENABLED + + \par Details: + \details + + This function removes a registered use case for the sdram or master + Statistic Collectors. + If ::SCI_SUCCESS is returned the function successfully removed the + registered usecase. + This function may only be called if the module has not been enabled + (see sci_global_enable())or has been disabled (see sci_global_disable()). + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + If this function is called while the modules are enabled this function + exits with ::SCI_ERR_MODULE_ENABLED. + If this function is called with a NULL usecase_key it exits with + ::SCI_ERR_INVALID_PARM. +*/ + +enum sci_err sci_remove_usecase (psci_handle const phandle, + psci_usecase_key * usecase_key); + +/*! \par sci_global_enable + + Enabled all registered sdram and master usecase. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + + \par Details: + \details + + This function enables all registered use case and starts STM message + generation (per sci_mode parameter set with sci_open()). + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + +*/ + +enum sci_err sci_global_enable(psci_handle const phandle); + +/*! \par sci_global_disable + + Disable all registered sdram and master usecase. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + + \par Details: + \details + + This function disables all registered use case and terminates STM message + generation (per sci_mode parameter set with sci_open). + + This function also causes meta data (data required for host post processing) + to be broadcast through STMLib if pstm_handle is not null (see ::sci_config). + If pstm_handle is null, then meta data will not be made avaiable for post + processing and only the raw counter values will be displayed. + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + +*/ +enum sci_err sci_global_disable(psci_handle const phandle); + +/*! \par sci_dump + + Manually dump the counters for each module that has use cases enabled. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + + \par Details: + \details + + This function maually dumps (verses allowing the statistic counters + to be dumped to STM periodically) the counters out STM. If the + Library is opended in a dump mode then this function must be called + to export the statistic counters out STM. If opened in STM mode this + function has no effect. + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + +*/ + +enum sci_err sci_dump(psci_handle const phandle ); + +#ifdef _SC_VER_1_16 +/*! \par sci_dump_info + + For the provided usecase_key retrive the number of statistic counters used. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \param[in] usecase_key usecase key. + + \param[out] pnum_sci_cntrs Pointer to where the number of counters utilized + by the usecase is stored. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + \li ::SCI_ERR_INVALID_PARM + + \par Details: + \details + + This function retrives the number of counters used by a specific usecase. + This information is needed by the client to provide a large enough + uint32_t array (pbuf) to the sci_dump_cntrs function (see ::sci_dump). + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + If usecase_key is NULL this function exits with ::SCI_ERR_INVALID_PARM. + +*/ +enum sci_err sci_dump_info(psci_handle const phandle, + psci_usecase_key usecase_key, + int * pnum_sci_cntrs); + + +/*! \par sci_dump_cntrs + + Manually dump the counters for the provided use case to a buffer. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \param[in] usecase_key usecase key. + + \param[in] num_sci_cntrs Number of counters to store in pbuf. + ( from ::sci_get_dumpinfo). + + \param[out] pbuf Pointer to the where this function stores the + statistic counters if pbuf is not NULL. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + \li ::SCI_ERR_INVALID_PARM + + \par Details: + \details + + This function retrives the counters used by a specific usecase. + This information is provided to the client to provide a large enough + uint32_t array for the sci_dump function (see ::sci_dump). + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + If usecase_key is NULL this function exits with ::SCI_ERR_INVALID_PARM. + +*/ +enum sci_err sci_dump_cntrs(psci_handle const phandle, + psci_usecase_key usecase_key, + int num_sci_cntrs, uint32_t * pbuf); + +enum sci_err sci_dump_sdram_cntrs(int num_sci_cntrs, uint32_t * pbuf); + + +/*! \par sci_dump_disabled + + For each module that has usecases enabled, disable STM message dumping. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + + \par Details: + \details + + This function disables STM message dumping for each statistic collector + module that has a usecase registered for it. + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + +*/ +enum sci_err sci_dump_disable(psci_handle const phandle); + +/*! \par sci_dump_enabled + + For each module that has usecases enabled, enable STM message dumping. + + \param[in] phandle A pointer to a handle provided by sci_open. + + \return enum ::sci_err See details for conditions that cause the + following errors: + \li ::SCI_SUCCESS + \li ::SCI_ERR_INVALID_HANDLE + + \par Details: + \details + + This function enables STM message dumping for each statistic collector + module that has a usecase registered for it. + + If phandle is NULL the function exits with ::SCI_ERR_INVALID_HANDLE. + +*/ +enum sci_err sci_dump_enable(psci_handle const phandle); +#endif +/*! \mainpage + The Statistic Collector Instrumentation (SCI) Library provides a use case + based programming API for the sdram and master Statistic Collector modules. + A Statistic Collector provide bus statistics for the selected probe that + can be fitered. Filtering parameters are dependent on the statistic collector + type. Depending on the operating mode messages that contain the counter values + can be export via STM peridocally or on demand (dump mode). + + \par Devices Supported + Devices currently supported by the library are: + \li OMAP4430 + \li OMAP4460 + \li OMAP5430 + + \par CPT Library Revision History + + + + + +
Revision Date Notes
0.0 9/14/2011 Alpha, OMAP4430 validation only
0.1 10/06/2011 Alpha, OMAP4430 and OMAP5430 validation. + Modified dump API from version 0.0. + Fixed Latency usecase bug.
+ + \par Conventions + The following public naming conventions are used by the API + \li sci_ - Prefix for public CPT Library functions, structures and enumerations + + \par Build Notes + SCILib supports the following pre-defined symbols that if defined + enable the functionality at compile time. + + \li _STM_Logging - If defined the SCILib will depend on the STMLib. + + \n Note - The minimum revision STMLib that supports SCILib meta data + transport is version 3.1. + + The library must be configure for a specific device by providing at compile + time one of the following pre-defined symbols: + \li _OMAP4430 + \li _OMAP4460 + \li _OMAP5430 + \li SCI_VER_1_16 (note only valid for OAP4460 and OMAP5430 builds) + + \par Directory Structure + + SCILib is a component of cTools so it resides within the cTools directory structure. + + @code + + |--cTools + | + |-- SCILib + | | + | |-- doc + | | | + | | |--sci_omap4430_html + | | |--sci_omap4460_html + | | |--sci_omap5430_html + | | | + | | |-index.html (Doxygen API documentation) + | | + | |-- include (Public API include file) + | |-- src (Private .c and .h files ) + | |-- projects (Target specific library builds) + | | + | |--omap4430_A9 + | |--omap4460_A9 + | |--omap5430_A15 + |-- Examples (Target specific stand-alone example projects) + | + |--common (files common across examples) + |--OMAP4430 + |--OMAP5430 + + + @endcode + + \par Helper Functions + + Helper functions allow the library to be ported easily to different + operating environments without modifications to the library directly. + Within the library these functions are declared extern so the library + will build but can not be linked without implementations for the following + helper functions: + + \li void * cTools_memAlloc(size_t sizeInBytes); \n\n + If allocation successful returns pointer to allocated memory, else if not + successful return NULL. + + \li void * cTools_memMap(unsigned int phyAddr, unsigned int mapSizeInBytes); \n\n + Map a physical address to a virtual address space. Return the virtual pointer + if successful, else return NULL. Return phyAddr if virtual mapping not required. + + \li void cTools_memFree(void * ptr); \n\n + Free the memory at the ptr (returned from cTools_memAlloc()) call. + + \li void cTools_memUnMap(void * vAddr, unsigned int mapSizeInBytes); \n\n + Unmap virtual address space starting at vAddr (returned from cTools_memMap()) + of mapSizeInBytes length. If virtual address mapping not required simply return. + + \par CPT Export Notes + The Statistic Collector STM messages are enabled by CCS when the STM module is + connected by default. If you have modified the defaults you may need to enable + the export of Statistic Collector STM messages through the CSS Breakpoint view by + creating a Trace job with the following Trace Properties: + \li Trace Type: System + \li STM Trace Type: Trace Export Configuration + \li Enable HW Message Sources: + \li Message Source N: Statstic Collection + + If you are working remotely from CCS and using the ETB to capture STM data + then you must provide your own application code to enable the CPT module's STM messages. + +*/ +#endif /*SCI_H*/ diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_common.h tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_common.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_common.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_common.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1172 @@ +/* + * sci_common.h + * + * Statistic Collector Instrumentation Library + * - Statistic Collector module specific definitions + * - Device specific configurations + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef SCI_COMMON_H +#define SCI_COMMON_H + +#include +#include + +/* Statistic Collector register typedef */ +typedef volatile uint32_t reg32_t; + +/* + * SC module sdram (OCP) and lat (NTTP) counter element structure definitions. + * Note that these definitions are simply used for addressing purposes and + * will not be used for defining specific bits per register. +*/ + + + +/* + * sdram structure definitions +*/ +struct sdram_filter { +#ifdef _SC_VER_1_12 + reg32_t en; + reg32_t mask_mstaddr; + reg32_t mask_rd; + reg32_t mask_wr; + reg32_t mask_err; + reg32_t mask_reserved; + reg32_t mask_userinfo; + reg32_t match_mstaddr; + reg32_t match_rd; + reg32_t match_wr; + reg32_t match_err; + reg32_t match_reserved; + reg32_t match_userinfo; +#endif +#ifdef _SC_VER_1_16 + reg32_t en; + reg32_t mask_rd; + reg32_t mask_wr; + reg32_t mask_mstaddr; + reg32_t reserved0; + reg32_t mask_err; + reg32_t mask_userinfo; + reg32_t reserved1; + reg32_t reserved2; + reg32_t match_rd; + reg32_t match_wr; + reg32_t match_mstaddr; + reg32_t reserved3; + reg32_t match_err; + reg32_t match_userinfo; + reg32_t reserved4; + reg32_t reserved5; +#endif +}; + +#ifdef _SC_VER_1_16 +#define DMM_LISA_MAP_BASE 0x4e000040 +typedef union DMM_LISA_MAP +{ + unsigned int val; + struct { + unsigned int sdrc_addr :8; + unsigned int sdrc_map :2; + unsigned int :6; + unsigned int sdrc_addrspc:2; + unsigned int sdrc_intl :2; + unsigned int sys_size :3; + unsigned int :1; + unsigned int sys_addr :8; + }; +}DMM_LISA_MAP; +#endif + +// Counter with zero filter elements +struct sdram_cnt_filter0 { + reg32_t globalen; +#ifdef _SC_VER_1_16 + reg32_t addrmin; + reg32_t addrmax; + reg32_t addren; + reg32_t reserved0[77]; +#endif + reg32_t op_threshold_minval; + reg32_t op_threshold_maxval; + reg32_t op_evt_info_sel; + reg32_t op_sel; + reg32_t reserved; +}; + +// Counter with one filter elements +struct sdram_cnt_filter1 { + reg32_t globalen; +#ifdef _SC_VER_1_16 + reg32_t addrmin; + reg32_t addrmax; + reg32_t addren; +#endif + struct sdram_filter filter[1]; +#ifdef _SC_VER_1_16 + reg32_t reserved0[60]; +#endif + reg32_t op_threshold_minval; + reg32_t op_threshold_maxval; + reg32_t op_evt_info_sel; + reg32_t op_sel; + reg32_t reserved; +}; + +// Counter with two filter elements +struct sdram_cnt_filter2 { + reg32_t globalen; +#ifdef _SC_VER_1_16 + reg32_t addrmin; + reg32_t addrmax; + reg32_t addren; +#endif + struct sdram_filter filter[2]; +#ifdef _SC_VER_1_16 + reg32_t reserved0[43]; +#endif + reg32_t op_threshold_minval; + reg32_t op_threshold_maxval; + reg32_t op_evt_info_sel; + reg32_t op_sel; + reg32_t reserved1; +}; + +/* + * NTTP mapping structure definitions +*/ + +struct lat_filter { +#ifdef _SC_VER_1_12 + reg32_t en; + reg32_t mask_mstaddr; + reg32_t mask_requserinfo; + reg32_t mask_rspuserinfo; + reg32_t mask_rd; + reg32_t mask_wr; + reg32_t mask_err; + reg32_t mask_slvaddr; + reg32_t match_mstaddr; + reg32_t match_requserinfo; + reg32_t match_rspuserinfo; + reg32_t match_rd; + reg32_t match_wr; + reg32_t match_err; + reg32_t match_slvaddr; +#endif +#ifdef _SC_VER_1_16 + reg32_t en; + reg32_t mask_rd; + reg32_t mask_wr; + reg32_t mask_mstaddr; + reg32_t mask_slvaddr; + reg32_t mask_err; + reg32_t mask_requserinfo; + reg32_t mask_rspuserinfo; + reg32_t reserved0; + reg32_t match_rd; + reg32_t match_wr; + reg32_t match_mstaddr; + reg32_t match_slvaddr; + reg32_t match_err; + reg32_t match_requserinfo; + reg32_t match_rspuserinfo; + reg32_t reserved1; +#endif +}; + +/* Counter with one filter elements */ +struct lat_cnt_filter1 { + reg32_t globalen; +#ifdef _SC_VER_1_16 + reg32_t reserved0; + reg32_t reserved1; + reg32_t reserved2; +#endif + struct lat_filter filter[1]; +#ifdef _SC_VER_1_16 + reg32_t reserved3[60]; +#endif + reg32_t op_threshold_minval; + reg32_t op_threshold_maxval; + reg32_t op_evt_info_sel; + reg32_t op_sel; + reg32_t reserved4; +}; + +/* + * Register definitions + * + */ +#define SC_REQUEST_PROBE 0x0 +#define SC_RESPONSE_PROBE 0x1 + + +#define SC_EVENT_SEL_NONE 0x0 /* No event selected */ +#define SC_EVENT_SEL_ANY 0x1 /* Any clock cycles */ +#define SC_EVENT_SEL_TRANSFER 0x2 /* Header, necker or data has been accepted by the receiver */ +#define SC_EVENT_SEL_WAIT 0x3 /* Transfer initiated but the transmitter has no data to send */ +#define SC_EVENT_SEL_BUSY 0x4 /* Receiver applies flow control */ +#define SC_EVENT_SEL_PKT 0x5 /* Transfer of a new packet header */ +#define SC_EVENT_SEL_DATA 0x6 /* Transfer of a payload word + * Request link: Store data + * Respose link: Load data + */ +#define SC_EVENT_SEL_IDLE 0x7 /* No communication over the link */ +#define SC_EVENT_SEL_LATENCY 0x8 /* Debug bit detection */ + +/* If op_sel set to MIN_MAX_HIT or EVT_INFO then evt_info_sel applies */ +#define SC_EVTINFOSEL_BYTELEN 0x0 /* Length of transfer in bytes */ +#define SC_EVTINFOSEL_PRESSURE 0x1 /* Pressure */ +#define SC_EVTINFOSEL_LATENCY 0x2 /* Amount of wait time */ + +/* op_sel determines how the counter functions */ +#define SC_OPSEL_FILTER_HIT 0x0 /* Counter increments on a filter hit */ +#define SC_OPSEL_MINMAX_HIT 0x1 /* Counter increments when the filter hits + * and the selected event info is in range + * (Min threshold <= Evt_Info <= Max threshold) + */ +#define SC_OPSEL_EVT_INFO 0x2 /* Selected Evt_Info added to the counter value + * when the filter hits + */ +#define SC_OPSEL_AND_FILTER 0x3 /* Counter increments by one when all unit + * filters hit. + */ +#define SC_OPSEL_OR_FILTER 0x4 /* Counter increments by one when at least + * one unit filters hits. + */ +#define SC_OPSEL_SUM_REQ_EVT 0x5 /* Counter sums the events from any request + * port. + */ +#define SC_OPSEL_SUM_RSP_EVT 0x6 /* Counter sums the events from any response + * port. + */ +#define SC_OPSEL_SUM_ALL_EVT 0x7 /* Counter sums the events from any request + * and response ports. + */ +#define SC_OPSEL_EX_EVT 0x8 /* Counter increments by one when the selected + * ExtEvt input signal is sampled high + */ + + +/* + * Generic mapping structure definitions +*/ + +enum sci_module_type {SDRAM, MSTR}; + +struct cnt_elements { + bool used; + int num_filters; + uint32_t cnt_offset; +}; + +//TODO seprate into two structures, constants and modifiable +struct mod_element_map { + enum sci_module_type mod_type; + uint32_t base_addr; + uint32_t * vbase_addr; + bool owner; + int usecase; /* First use case - used for compatibility testing */ + int usecase_cnt; /* Number of use case jobs attached */ + int mod_size; /* In bytes */ + int num_counters; + struct cnt_elements * cnt_map; + int num_ports; + int * port_map; +}; + +#ifdef _STM_Logging +/* The following are common strings and tables shared between all device types */ + +/* Trasaction type names */ +const char trans_type_rd[] = "Rd"; +const char trans_type_wr[] = "Wr"; +const char trans_type_none[] = "RdWrNone"; +const char trans_type_dontcare[] = "RdWrDontCare"; + +/* Use sci_trans_qual to select */ +const char * trans_type_table[] = { trans_type_rd, + trans_type_wr, + trans_type_none, + trans_type_dontcare}; + + + +/* Usecase enums for sdram and mstr sc module types are identical + 0 SCI_SDRAM_THROUGHPUT, SCI_MSTR_THROUGHPUT + 1 SCI_SDRAM_LINKOCCUPY_REQUEST, SCI_MSTR_LINKOCCUPY_REQUEST + 2 SCI_SDRAM_LINKOCCUPY_RESPONSE, SCI_MSTR_LINKOCCUPY_RESPONSE + 3 SCI_SDRAM_AVGBURST_LENGTH, SCI_MSTR_AVGBURST_LENGTH + 4 SCI_SDRAM_AVGLATENCY_NOT_SUPPORTED SCI_MSTR_AVGLATENCY +#if SCI_VER_1_16 + 5 SCI_SDRAM_THROUGHPUT_MINALARM, SCI_MSTR_THROUGHPUT_MINALARM + 6 SCI_SDRAM_THROUGHPUT_MAXALARM, SCI_MSTR_THROUGHPUT_MAXALARM + 7 SCI_SDRAM_LATENCY_MAXALARM_NOT_SUPPORTED SCI_MSTR_LATENCY_MAXALARM +#endif +*/ +const char usecase_name_tp[] = "ThroughPut per Sampling Period"; +const char usecase_name_reslo[] ="Request Port Link Occupancy"; +const char usecase_name_rsplo[] ="Response Port Link Occupancy"; +const char uusecase_name_abl[] = "Average Burst Length"; +const char uusecase_name_ald[] = "Average Latency Distribution"; +const char uusecase_name_tpmax[] = "ThroughPut per Sample Period - Max Alarm"; +const char uusecase_name_tpmin[] = "ThroughPut per Sample Period - Min Alarm"; +const char uusecase_name_aldmax[] = "Average Latency - Max Alarm"; + +/* Use usecaseid to index */ +const char * usecase_name_table[] = { + usecase_name_tp, + usecase_name_reslo, + usecase_name_rsplo, + uusecase_name_abl, + uusecase_name_ald, + uusecase_name_tpmax, + uusecase_name_tpmin, + uusecase_name_aldmax +}; + +/* Counter names */ +const char cntr_name_payload[]= "Payload Length"; +const char cntr_name_idle[] = "Idle"; +const char cntr_name_packcnt[] = "Packet Count"; +const char cntr_name_latcyc[] = "Latency Cycle Count"; +const char cntr_name_lattrans[] = "Latency Transaction Count"; + +const int usecase_formula_table[] = {2,3,3,1,9,2,2,9}; + +const char usecase_units_bytesperpacket[] = "Bytes/Packet"; +const char usecase_units_bytesperwindow[] = "Bytes/Sample Window"; +const char usecase_units_percent[] ="%"; +const char usecase_units_cyclespertrans[] = "Cycles/Transaction"; + +#define SCI_META_BUFSIZE 256 + +#endif //End of _STM_Logging + +/* TP LOREQ LORESP ABL AL TA+ TA- LA + * TP - Throughput true false false true false false false false + * LOREQ - Link Occupancy Request false true false false false false false false + * LORSP - Link Occupancy Respose false false true false false false false false + * ABL- Average burst length true false false true false false false false + * AL - Average latency false false false false true false false false + * TA+ - Throughput Alarm Max false false false false false true false false + * TA- - Throughput Alarm Min false false false false false false true false + * LA - Latency alarm false false false false false false false true + */ +#if 0 +bool usecase_compat_table[8][8] = { true, false, false, true, false, false, false, false, + false, true, false, false, false, false, false, false, + false, false, true, false, false, false, false, false, + true, false, false, true, false, false, false, false, + false, false, false, false, true, false, true, false, + false, false, false, false, false, true, false, false, + false, false, false, false, false, false, true, false, + false, false, false, false, false, false, false, true}; +#endif + + +#define SC_GET_USECASE_COMPAT_VALUE(n) ((n) >> 16) +#define SC_USECASE_MASK(n) ((n) & 0x000000FF) + +#define SC_MOD_TYPE (0x003A0001) /* Identifies the module as a SC Module */ + +#define GET_SCMOD_FUNC(n) ((n) >> 24) + +/* + * The following are device specific internel definitions + */ + +/*****************************************************************************/ +/* OMAP4430 and OMAP4460 specific definitions */ +/*****************************************************************************/ +#if defined(_OMAP4430) || defined(_OMAP4460) + +#define SC_SDRAM_BASE 0x45000400 /* sdram sc module base address */ +#define SC_LAT0_BASE 0x45000600 +#define SC_LAT1_BASE 0x45000800 + +#define SC_LIB_FUNC (0x0) /* SC Module ID this library + is compatible with */ +const uint32_t mod_func_ver[] = { 0x0, 0x0, 0x0 }; + +#define SC_SDRAM_NUM_CNTRS 5 /* sdram number of counter elements */ +#define SC_SDRAM_NUM_PROBES 2 + +// LAT0 and LAT1 have identical register mappings + +#define SC_LAT_NUM_CNTRS 4 +#define SC_LAT0_NUM_PROBES 6 +#define SC_LAT1_NUM_PROBES 5 + +/* This struct discribes the sdram SC Module address space*/ +struct sc_sdram_regs { + reg32_t stdhosthdr_core; + reg32_t stdhosthdr_version; + reg32_t en; + reg32_t soften; + reg32_t trigen; + reg32_t reqevt; + reg32_t rspevt; + reg32_t evtmux_sel[SC_SDRAM_NUM_CNTRS]; + reg32_t dump_identifier; + reg32_t dump_collecttime; + reg32_t dump_slvaddr; + reg32_t dump_mstaddr; + reg32_t dump_slvofs; + reg32_t dump_manual; + reg32_t dump_send; +#ifdef _SC_VER_1_16 + reg32_t dump_disable; + reg32_t dump_alarm_trig; + reg32_t dump_alarm_minval; + reg32_t dump_alarm_maxval; + reg32_t dump_alarm_mode[SC_SDRAM_NUM_CNTRS]; + reg32_t dump_cnt[SC_SDRAM_NUM_CNTRS]; +#endif + // Note that the fitler mapping is device dependent - so use mod_element_map to access + struct sdram_cnt_filter2 cnt0; + struct sdram_cnt_filter1 cnt1; + struct sdram_cnt_filter2 cnt2; + struct sdram_cnt_filter1 cnt3; + struct sdram_cnt_filter0 cnt4; +}; + + +struct cnt_elements sdram_cnt_map[] = { + false, 2, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt0), + false, 1, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt1), + false, 2, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt2), + false, 1, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt3), + false, 0, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt4) +}; + +/* + * The request port number is the index*2, + * the respose port number is the index*2 +1 + */ +int sdram_probe_map[] = { SCI_EMIF1, + SCI_EMIF2 +}; + +struct mod_element_map mod_sdram_map = { SDRAM, + SC_SDRAM_BASE, + NULL, + false, + -1, + 0, + sizeof(struct sc_sdram_regs), + SC_SDRAM_NUM_CNTRS, + sdram_cnt_map, + SC_SDRAM_NUM_CNTRS, + sdram_probe_map +}; + + +struct sc_lat_regs { + reg32_t stdhosthdr_core; + reg32_t stdhosthdr_version; + reg32_t en; + reg32_t soften; + reg32_t trigen; + reg32_t reqevt; + reg32_t rspevt; + reg32_t evtmux_sel[SC_LAT_NUM_CNTRS]; + reg32_t dump_identifier; + reg32_t dump_collecttime; + reg32_t dump_slvaddr; + reg32_t dump_mstaddr; + reg32_t dump_slvofs; + reg32_t dump_manual; + reg32_t dump_send; +#ifdef _SC_VER_1_16 + reg32_t dump_disable; + reg32_t dump_alarm_trig; + reg32_t dump_alarm_minval; + reg32_t dump_alarm_maxval; + reg32_t dump_alarm_mode[SC_LAT_NUM_CNTRS]; + reg32_t dump_cnt[SC_LAT_NUM_CNTRS]; +#endif + // Note that the fitler mapping is device dependent - so use mod_element_map to access + struct lat_cnt_filter1 cnt[4]; +}; + + +struct cnt_elements lat_cnt_map[] = { + false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[0]), + false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[1]), + false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[2]), + false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[3]), +}; + +/* + * The request port number is the index*2, + * the respose port number is the index*2 +1 + */ +int lat0_probe_map[] = { SCI_MODENA, + SCI_TESLA, + SCI_SDMA_RD, + SCI_SDMA_WR, + SCI_DSS, + SCI_ISS, +}; + +int lat1_probe_map[] = { SCI_IVAHD, + SCI_MODENA, + SCI_SDMA_WR, + SCI_SGX, + SCI_DUCATI +}; + +struct mod_element_map mod_lat0_map = { MSTR, + SC_LAT0_BASE, + NULL, + false, + -1, + 0, + sizeof(struct sc_lat_regs), + SC_LAT_NUM_CNTRS, + lat_cnt_map, + SC_LAT0_NUM_PROBES, + lat0_probe_map +}; + +struct mod_element_map mod_lat1_map = { MSTR, + SC_LAT1_BASE, + NULL, + false, + -1, + 0, + sizeof(struct sc_lat_regs), + SC_LAT_NUM_CNTRS, + lat_cnt_map, + SC_LAT1_NUM_PROBES, + lat1_probe_map +}; + +enum module_id {SDRAM0, LAT0, LAT1} module_id; +struct mod_element_map * mod_map[] = { &mod_sdram_map, &mod_lat0_map, &mod_lat1_map }; +//TODO confirm counter widths are correct +const int cnt_overflow_norm[] = {65535-32, 4096-128, 4096-128}; +const int cnt_overflow_lat[] = {0, 1023-32, 1023-32}; + +const int mod_cnt = sizeof mod_map/sizeof mod_map[0]; + +#ifdef _STM_Logging +/* + * The following are required for meta data generation + */ + +/* Module names */ +const char module_name_sdram[] = "SDRAM"; +const char module_name_lat0[] = "LAT0"; +const char module_name_lat1[] = "LAT1"; + +/* Use module number to index */ +const char * module_name_table[] = {module_name_sdram, + module_name_lat0, + module_name_lat1}; +/* SDRAM probe names */ +const char probe_name_emif0[] = "EMIF1"; +const char probe_name_emif1[] = "EMIF2"; + +/*Use sdram probe id to index */ +const char * sdram_probe_name_table[] = { probe_name_emif0, + probe_name_emif1}; +/* MSTR probe names */ +const char probe_name_mstr_mod[] = "MODENA"; +const char probe_name_mstr_tes[] = "TESLA"; +const char probe_name_mstr_sdmard[] = "SDMA_RD"; +const char probe_name_mstr_sdmawr[] = "SDMA_WR"; +const char probe_name_mstr_dss[] = "DSS"; +const char probe_name_mstr_iss[] = "ISS"; +const char probe_name_mstr_ivahd[] = "IVAHD"; +const char probe_name_mstr_sgx[] = "SGX"; +const char probe_name_mstr_duc[] = "DUCATI"; + +/* Use mastr probe id to index */ +const char * mstr_probe_name_table[] = {probe_name_mstr_mod, + probe_name_mstr_tes, + probe_name_mstr_sdmard, + probe_name_mstr_sdmawr, + probe_name_mstr_dss, + probe_name_mstr_iss, + probe_name_mstr_ivahd, + probe_name_mstr_sgx, + probe_name_mstr_duc}; + + +/* Master addr names */ +const char master_name_mpuss[] = "MPUSS"; +const char master_name_dap[] = "DAP"; +const char master_name_ieee1500[] = "IEEE1500"; +const char master_name_tesla[] = "Tesla"; +const char master_name_ivahd[] = "IVAHD"; +const char master_name_iss[] = "ISS"; +const char master_name_ducati[] = "Ducati"; +const char master_name_face[] = "Face Detect (SMP)"; +const char master_name_sdramrd[] = "sDMA_RD"; +const char master_name_sdramwr[] = "sDMA_WR"; +const char master_name_sgx[] = "SGX"; +const char master_name_dss[] = "DSS"; +const char master_name_sad2d[] = "SAD2D (SMP)"; +const char master_name_hsi[] = "HSI"; +const char master_name_mmc1[] = "MMC1"; +const char master_name_mmc2[] = "MMC2"; +const char master_name_mmc6[] = "MMC6 (MDI)"; +const char master_name_unipro[] = "UNIPRO1"; +const char master_name_usbhost[] = "USB Host HS"; +const char master_name_usbotghs[] = "USB OTG HS"; +const char master_name_usbhostfs[] = "USB HOST FS (SMP)"; + +/* Use enum sci_master_addr >> 2 to index */ +const char * master_name_table[] = { + master_name_mpuss, /* 0x00 */ + NULL, + NULL, + NULL, + master_name_dap, /* 0x04 */ + master_name_ieee1500, /* 0x05 */ + NULL, + NULL, + master_name_tesla, /* 0x08 */ + NULL, + NULL, + NULL, + master_name_ivahd, /* 0x0C */ + NULL, + NULL, + NULL, + master_name_iss, /* 0x10 */ + master_name_ducati, /* 0x11 */ + master_name_face, /* 0x12 */ + NULL, + master_name_sdramrd, /* 0x14 */ + master_name_sdramwr, /* 0x15 */ + NULL, + NULL, + master_name_sgx, /* 0x18 */ + NULL, + NULL, + NULL, + master_name_dss, /* 0x1C */ + NULL, + NULL, + NULL, + master_name_sad2d, /* 0x20 */ + NULL, + NULL, + NULL, + master_name_hsi, /* 0x24 */ + NULL, + NULL, + NULL, + master_name_mmc1, /* 0x28 */ + master_name_mmc2, /* 0x29 */ + master_name_mmc6, /* 0x2A */ + NULL, + NULL, + NULL, + master_name_unipro, /* 0x2C */ + NULL, + NULL, + NULL, + master_name_usbhost, /* 0x30 */ + master_name_usbotghs, /* 0x31 */ + master_name_usbhostfs /* 0x32 */ +}; + +/* Slave addr names */ +const char slave_name_hostclk1[] = "Host CLK1"; +const char slave_name_dmm1[] = "DMM1 - NIU"; +const char slave_name_dmm2[] = "DMM2 - NIU (SMP)"; +const char slave_name_abe[] = "ABE - NIU"; +const char slave_name_l4cfg[] = "L4CFG - NIU"; +/* hole */ +const char slave_name_hostclk2[] = "Host CLK2"; +const char slave_name_gpmc[] = "GPMC - NIU"; +const char slave_name_ocmram[] = "OCMRAM - NIU"; +const char slave_name_dss[] = "DSS - NIU"; +const char slave_name_iss[] = "ISS - NIU"; +const char slave_name_ducati[] = "Ducati - NIU"; +const char slave_name_sgx[] = "SGX - NIU"; +const char slave_name_ivahd[] = "IVAHD - NIU"; +const char slave_name_sl2[] = "SL2 - NIU"; +const char slave_name_l4per0[] = "L4PER0 - NIU"; +const char slave_name_l4per1[] = "L4PER1 - NIU"; +const char slave_name_l4per2[] = "L4PER2 - NIU"; +const char slave_name_l4per3[] = "L4PER3 - NIU"; +const char slave_name_aes1[] = "AES1 - NIU"; +const char slave_name_aes2[] = "AES2 - NIU"; +const char slave_name_sha1[] = "SHA1 - NIU"; +const char slave_name_mod[] = "Modem (MID)"; +/*hole*/ +const char slave_name_hostclk3[] = "Host CLK3"; +const char slave_name_dbgss[] = "DebugSS - NIU"; + +const char * slave_name_table[] = { + slave_name_hostclk1, + slave_name_dmm1, + slave_name_dmm2, + slave_name_abe, + slave_name_l4cfg, + NULL, + slave_name_hostclk2, + slave_name_gpmc, + slave_name_ocmram, + slave_name_dss, + slave_name_iss, + slave_name_ducati, + slave_name_sgx, + slave_name_ivahd, + slave_name_sl2, + slave_name_l4per0, + slave_name_l4per1, + slave_name_l4per2, + slave_name_l4per3, + slave_name_aes1, + slave_name_aes2, + slave_name_sha1, + slave_name_mod, + NULL, + slave_name_hostclk3, + slave_name_dbgss +}; + + +#endif //End of _STM_Logging + +#endif /* End of _OMAP4430 */ + +#if defined(_OMAP5430) || defined(_OMAP4470) +/*****************************************************************************/ +/* OMAP5430 specific definitions */ +/*****************************************************************************/ +#define SC_SDRAM_BASE 0x45001000 /* sdram sc module base address */ +#define SC_LAT0_BASE 0x45002000 +#define SC_LAT1_BASE 0x45003000 + +const uint32_t mod_func_ver[] = { 0x1, 0x1, 0x1 }; +#define SC_LIB_FUNC (0x1) /* SC Module ID this library + is compatible with */ + +#define SC_SDRAM_NUM_CNTRS 8 /* sdram number of counter elements */ +#define SC_SDRAM_NUM_PROBES 5 + +// LAT0 and LAT1 have identical register mappings + +#define SC_LAT_NUM_CNTRS 4 +#define SC_LAT0_NUM_PROBES 7 +#define SC_LAT1_NUM_PROBES 5 + +/* This struct discribes the sdram SC Module address space*/ +struct sc_sdram_regs { + reg32_t stdhosthdr_core; + reg32_t stdhosthdr_version; + reg32_t en; + reg32_t soften; +#ifdef _SC_VER_1_16 + reg32_t ignore_suspend; +#endif + reg32_t trigen; + reg32_t reqevt; + reg32_t rspevt; + reg32_t evtmux_sel[SC_SDRAM_NUM_CNTRS]; + reg32_t dump_identifier; + reg32_t dump_collecttime; + reg32_t dump_slvaddr; + reg32_t dump_mstaddr; + reg32_t dump_slvofs; + reg32_t dump_manual; /* dump_mode for version 1.16 */ + reg32_t dump_send; +#ifdef _SC_VER_1_16 + reg32_t dump_disable; + reg32_t dump_alarm_trig; + reg32_t dump_alarm_minval; + reg32_t dump_alarm_maxval; + reg32_t dump_alarm_mode[SC_SDRAM_NUM_CNTRS]; + reg32_t dump_cnt[SC_SDRAM_NUM_CNTRS]; +#endif + // Note that the fitler mapping is device dependent - so use mod_element_map to access + struct sdram_cnt_filter2 cnt0; + struct sdram_cnt_filter1 cnt1; + struct sdram_cnt_filter2 cnt2; + struct sdram_cnt_filter1 cnt3; + struct sdram_cnt_filter1 cnt4; + struct sdram_cnt_filter1 cnt5; + struct sdram_cnt_filter0 cnt6; + struct sdram_cnt_filter0 cnt7; +}; + + +struct cnt_elements sdram_cnt_map[] = { + {false, 2, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt0)}, + {false, 1, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt1)}, + {false, 2, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt2)}, + {false, 1, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt3)}, + {false, 1, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt4)}, + {false, 1, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt5)}, + {false, 0, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt6)}, + {false, 0, (uint32_t)(&((struct sc_sdram_regs *)0)->cnt7)} }; + +/* + * The request port number is the index*2, + * the respose port number is the index*2 +1 + */ +int sdram_probe_map[] = { SCI_EMIF1, + SCI_EMIF2, + SCI_MA_MPU_P1, + SCI_MA_MPU_P2, + SCI_EMIF_LL +}; + +struct mod_element_map mod_sdram_map = { SDRAM, + SC_SDRAM_BASE, + NULL, + false, + -1, + 0, + sizeof(struct sc_sdram_regs), + SC_SDRAM_NUM_CNTRS, + sdram_cnt_map, + SC_SDRAM_NUM_CNTRS, + sdram_probe_map +}; + + +struct sc_lat_regs { + reg32_t stdhosthdr_core; + reg32_t stdhosthdr_version; + reg32_t en; + reg32_t soften; +#ifdef _SC_VER_1_16 + reg32_t ignore_suspend; +#endif + reg32_t trigen; + reg32_t reqevt; + reg32_t rspevt; + reg32_t evtmux_sel[SC_LAT_NUM_CNTRS]; + reg32_t reserved0[4]; + reg32_t dump_identifier; + reg32_t dump_collecttime; + reg32_t dump_slvaddr; + reg32_t dump_mstaddr; + reg32_t dump_slvofs; + reg32_t dump_manual; + reg32_t dump_send; +#ifdef _SC_VER_1_16 + reg32_t dump_disable; + reg32_t dump_alarm_trig; + reg32_t dump_alarm_minval; + reg32_t dump_alarm_maxval; + reg32_t dump_alarm_mode[SC_LAT_NUM_CNTRS]; + reg32_t reserved1[4]; + reg32_t dump_cnt[SC_LAT_NUM_CNTRS]; + reg32_t reserved2[4]; +#endif + // Note that the fitler mapping is device dependent - so use mod_element_map to access + struct lat_cnt_filter1 cnt[4]; +}; + + +struct cnt_elements lat_cnt_map[] = { + {false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[0])}, + {false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[1])}, + {false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[2])}, + {false, 1, (uint32_t)(&((struct sc_lat_regs *)0)->cnt[3])} }; + +/* + * The request port number is the index*2, + * the respose port number is the index*2 +1 + */ +int lat0_probe_map[] = { SCI_MPU, + SCI_DSP, + SCI_SDMA_RD, + SCI_SDMA_WR, + SCI_DSS, + SCI_ISS, + SCI_GPU_P1 +}; + +int lat1_probe_map[] = { SCI_IVA, + SCI_MPU, + SCI_SDMA_WR, + SCI_GPU_P2, + SCI_IPU +}; + +struct mod_element_map mod_lat0_map = { MSTR, + SC_LAT0_BASE, + NULL, + false, + -1, + 0, + sizeof(struct sc_lat_regs), + SC_LAT_NUM_CNTRS, + lat_cnt_map, + SC_LAT0_NUM_PROBES, + lat0_probe_map +}; + +struct mod_element_map mod_lat1_map = { MSTR, + SC_LAT1_BASE, + NULL, + false, + -1, + 0, + sizeof(struct sc_lat_regs), + SC_LAT_NUM_CNTRS, + lat_cnt_map, + SC_LAT1_NUM_PROBES, + lat1_probe_map +}; + +enum module_id {SDRAM0, LAT0, LAT1} module_id; +struct mod_element_map * mod_map[] = { &mod_sdram_map, &mod_lat0_map, &mod_lat1_map }; +//TODO confirm counter widths are correct +const int cnt_overflow_norm[] = {65535-32, 4096-128, 4096-128}; +const int cnt_overflow_lat[] = {0, 1023-32, 1023-32}; + +const int mod_cnt = sizeof mod_map/sizeof mod_map[0]; + +#ifdef _STM_Logging +/* + * The following are required for meta data generation + */ + +/* Module names */ +const char module_name_sdram[] = "SDRAM"; +const char module_name_lat0[] = "LAT0"; +const char module_name_lat1[] = "LAT1"; + +/* Use module number to index */ +const char * module_name_table[] = {module_name_sdram, + module_name_lat0, + module_name_lat1}; +/* EMIF probe names */ +const char probe_name_sdram0[] = "EMIF1_SYS"; +const char probe_name_sdram1[] = "EMIF2_SYS"; +const char probe_name_sdram2[] = "MA_MPU_P1"; +const char probe_name_sdram3[] = "MA_MPU_P2"; +const char probe_name_sdram4[] = "EMIF1_LL"; + +/*Use sdram probe id to index */ +const char * sdram_probe_name_table[] = { probe_name_sdram0, + probe_name_sdram1, + probe_name_sdram2, + probe_name_sdram3, + probe_name_sdram4}; + + +/* MSTR probe names */ +const char probe_name_mstr_mpu[] = "MPU"; +const char probe_name_mstr_dsp[] = "DSP"; +const char probe_name_mstr_sdmard[] = "SDMA_RD"; +const char probe_name_mstr_sdmawr[] = "SDMA_WR"; +const char probe_name_mstr_dss[] = "DSS"; +const char probe_name_mstr_iss[] = "ISS"; +const char probe_name_mstr_gpu1[] = "GPU_P1"; +const char probe_name_mstr_iva[] = "IVA"; +const char probe_name_mstr_gpu2[] = "GPU_P2"; +const char probe_name_mstr_ipu[] = "IPU"; + +/* Use mastr probe id to index */ +const char * mstr_probe_name_table[] = {probe_name_mstr_mpu, + probe_name_mstr_dsp, + probe_name_mstr_sdmard, + probe_name_mstr_sdmawr, + probe_name_mstr_dss, + probe_name_mstr_iss, + probe_name_mstr_gpu1, + probe_name_mstr_iva, + probe_name_mstr_gpu2, + probe_name_mstr_ipu}; + + +/* Master addr names */ +const char master_name_mpu[] = "MPU"; +const char master_name_dap[] = "DAP"; +const char master_name_dsp[] = "DSP"; +const char master_name_iva[] = "IVA"; +const char master_name_iss[] = "ISS"; +const char master_name_ipu[] = "IPU"; +const char master_name_fdif[] = "FDIF"; +const char master_name_cal[] = "CAL"; +const char master_name_sdramrd[] = "SDRAM_rd"; +const char master_name_sdramwr[] = "SDRAM_wr"; +const char master_name_gpu_p1[] = "GPU_P1"; +const char master_name_gpu_p2[] = "GPU_P2"; +const char master_name_dss[] = "DSS"; +const char master_name_c2c[] = "C2C"; +const char master_name_lli[] = "LLI"; +const char master_name_hsi[] = "HSI"; +const char master_name_unipro1[] = "UNIPRO1"; +const char master_name_unipro2[] = "UNIPRO2"; +const char master_name_mmc1[] = "MMC1"; +const char master_name_mmc2[] = "MMC2"; +const char master_name_sata[] = "SATA"; +const char master_name_usbhosths[] = "USB Host HS"; +const char master_name_usbotghs[] = "USB OTG HS"; + +/* Use enum sci_master_addr >> 2 to index */ +const char * master_name_table[] = { + master_name_mpu, /* 0x00 */ + NULL, + NULL, + NULL, + master_name_dap, /* 0x04 */ + NULL, + NULL, + NULL, + master_name_dsp, /* 0x08 */ + NULL, + NULL, + NULL, + master_name_iva, /* 0x0C */ + NULL, + NULL, + NULL, + master_name_iss, /* 0x10 */ + master_name_ipu, /* 0x11 */ + master_name_fdif, /* 0x12 */ + master_name_cal, /* 0x13 */ + master_name_sdramrd, /* 0x14 */ + master_name_sdramwr, /* 0x15 */ + NULL, + NULL, + master_name_gpu_p1, /* 0x18 */ + master_name_gpu_p2, /* 0x19 */ + NULL, + NULL, + master_name_dss, /* 0x1C */ + NULL, + NULL, + NULL, + master_name_c2c, /* 0x20 */ + master_name_lli, + NULL, + NULL, + master_name_hsi, /* 0x24 */ + master_name_unipro1, + master_name_unipro2, + NULL, + master_name_mmc1, /* 0x28 */ + master_name_mmc2, /* 0x29 */ + master_name_sata, /* 0x2A */ + NULL, + NULL, + NULL, + NULL, + NULL, + master_name_usbhosths, /* 0x30 */ + NULL, + NULL, + master_name_usbotghs /* 0x33 */ +}; + +/* Slave addr names */ +const char slave_name_hostclk1[] = "HOST_CLK1"; +const char slave_name_dmm1[] = "DMM_P1"; +const char slave_name_dmm2[] = "DMM_P2"; +const char slave_name_abe[] = "ABE"; +const char slave_name_l4cfg[] = "L4CFG"; +/* hole */ +const char slave_name_hostclk2[] = "HOST_CLK2"; +const char slave_name_gpmc[] = "GPMC"; +const char slave_name_ocmram[] = "OCM_RAM"; +const char slave_name_dss[] = "DSS"; +const char slave_name_iss[] = "ISS"; +const char slave_name_ipu[] = "IPU"; +const char slave_name_gpu[] = "GPU"; +const char slave_name_iva[] = "IVA"; +const char slave_name_sl2[] = "SL2"; +const char slave_name_l4per0[] = "L4_PER_P0"; +const char slave_name_l4per1[] = "L4_PER_P1"; +const char slave_name_l4per2[] = "L4_PER_P2"; +const char slave_name_l4per3[] = "L4_PER_P3"; +/*hole */ +/*hole */ +/*hole */ +const char slave_name_c2c[] = "C2C"; +const char slave_name_lli[] = "LLI"; +const char slave_name_hostclk3[] = "HOST_CLK3"; +const char slave_name_l3_instr[] = "L3_ONSTR"; +const char slave_name_cal[] = "CAL"; +/*hole */ +const char slave_name_dbgss[] = "DebugSS_CT_TBR"; + +const char * slave_name_table[] = { + slave_name_hostclk1, + slave_name_dmm1, + slave_name_dmm2, + slave_name_abe, + slave_name_l4cfg, + NULL, + slave_name_hostclk2, + slave_name_gpmc, + slave_name_ocmram, + slave_name_dss, + slave_name_iss, + slave_name_ipu, + slave_name_gpu, + slave_name_iva, + slave_name_sl2, + slave_name_l4per0, + slave_name_l4per1, + slave_name_l4per2, + slave_name_l4per3, + NULL, + NULL, + NULL, + slave_name_c2c, + slave_name_lli, + slave_name_hostclk3, + slave_name_l3_instr, + slave_name_cal, + NULL, + slave_name_dbgss + +}; + + +#endif //End of _STM_Logging + +#endif //End of _OMAP5430 + + +#endif //End of SCI_COMMON_H diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_dev.h tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_dev.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_dev.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_dev.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,222 @@ +/* + * sci.h + * + * Statistic Collector Instrumentation Library + * - Device speciifc definitions required by the API + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef SCI_DEV_H +#define SCI_DEV_H + +/* + * The following are extenral device specific definitions + */ +#if defined(_OMAP4430) || defined(_OMAP4460) + +/*! \par probeid_sdram Probe selection for sdram statistic collectors. */ +enum probeid_sdram { + SCI_EMIF1, + SCI_EMIF2 +}; + +/*! \par probeid_mstr Probe selection for master statistic collectors. */ +enum probeid_mstr { + SCI_MODENA, + SCI_TESLA, + SCI_SDMA_RD, + SCI_SDMA_WR, + SCI_DSS, + SCI_ISS, + SCI_IVAHD, + SCI_SGX, + SCI_DUCATI +}; + +/*! \par sci_master_addr Master address enumerations. */ +enum sci_master_addr { + SCI_MSTID_MPUSS = 0x0, + SCI_MSTID_DAP = 0x10, + SCI_MSTID_IEEE1500 = 0x14, + SCI_MSTID_TESLA = 0x20, + SCI_MSTID_IVAHD = 0x30, + SCI_MSTID_ISS = 0x40, + SCI_MSTID_DUCATI = 0x44, + SCI_MSTID_FACE_DETECT_SMP = 0x48, + SCI_MSTID_SDMA_RD = 0x50, + SCI_MSTID_SDMA_WR = 0x54, + SCI_MSTID_CRYPTO_DMA_RD = 0x58, + SCI_MSTID_CRYPTO_DMA_WR = 0x5C, + SCI_MSTID_SGX = 0x60, + SCI_MSTID_DSS = 0x70, + SCI_MSTID_SAD2D = 0x80, + SCI_MSTID_HSI = 0x90, + SCI_MSTID_MMC1 = 0xA0, + SCI_MSTID_MMC2 = 0xA4, + SCI_MSTID_MMC6_MID = 0xA8, + SCI_MSTID_UNIPRO1 = 0xB0, + SCI_MSTID_USB_HOST_HS_SMP = 0xC0, + SCI_MSTID_USB_OTG_HS = 0xC4, + SCI_MSTID_USB_HOST_FS_SMP = 0xC8, + SCI_MASTID_ALL +}; + +/*! \par sci_slave_addr Slave address enumerations. */ +enum sci_slave_addr { + SCI_SLVID_HOST_CLK1 = 0x0, + SCI_SLVID_DMM1_NIU = 0x1, + SCI_SLVID_DMM2_NIU_SMP = 0x2, + SCI_SLVID_ABE_NIU = 0x3, + SCI_SLVID_L4CFG_NIU = 0x4, + SCI_SLVID_HOST_CLK2 = 0x6, + SCI_SLVID_GPMC_NIU = 0x7, + SCI_SLVID_OCMRAM_NIU = 0x8, + SCI_SLVID_DSS_NIU = 0x9, + SCI_SLVID_ISS_NIU = 0xA, + SCI_SLVID_DUCATI_NIU = 0xB, + SCI_SLVID_SGX_NIU = 0xC, + SCI_SLVID_IVAHD_NIU = 0xD, + SCI_SLVID_SL2_NIU = 0xE, + SCI_SLVID_L4PER0_NIU = 0xF, + SCI_SLVID_L4PER1_NIU = 0x10, + SCI_SLVID_L4PER2_NIU = 0x11, + SCI_SLVID_L4PER3_NIU = 0x12, + SCI_SLVID_AES1_NIU = 0x13, + SCI_SLVID_AES2_NIU = 0x14, + SCI_SLVID_SHA1_NIU = 0x15, + SCI_SLVID_MODEM_MID = 0x16, + SCI_SLVID_HOST_CLK3 = 0x18, + SCI_SLVID_DEBUGSS_NIU = 0x19, + SCI_SLVID_ALL +}; + + + +#endif + +#if defined(_OMAP5430) || defined(_OMAP4470) + +/*! \par probeid_sdram Probe selection for sdram statistic collectors. */ +enum probeid_sdram { + SCI_EMIF1, + SCI_EMIF2, + SCI_MA_MPU_P1, + SCI_MA_MPU_P2, + SCI_EMIF_LL +}; + +/*! \par probeid_mstr Probe selection for master statistic collectors. */ +enum probeid_mstr { + SCI_MPU, + SCI_DSP, + SCI_SDMA_RD, + SCI_SDMA_WR, + SCI_DSS, + SCI_ISS, + SCI_GPU_P1, + SCI_IVA, + SCI_GPU_P2, + SCI_IPU +}; + +/*! \par sci_master_addr Master address enumerations. */ +enum sci_master_addr { + SCI_MSTID_MPUSS = 0x0, + SCI_MSTID_DAP = 0x10, + SCI_MSTID_DSP = 0x20, + SCI_MSTID_IVA = 0x30, + SCI_MSTID_ISS = 0x40, + SCI_MSTID_IPU = 0x44, + SCI_MSTID_FDIF = 0x48, + SCI_MSTID_SDMA_RD = 0x50, + SCI_MSTID_SDMA_WR = 0x54, + SCI_MSTID_GPU_P1 = 0x60, + SCI_MSTID_GPU_P2 = 0x64, + SCI_MSTID_BB2D_P1 = 0x68, + SCI_MSTID_BB2D_P2 = 0x6C, + SCI_MSTID_DSS = 0x70, + SCI_MSTID_C2C = 0x80, +#if defined(_OMAP5430) + SCI_MSTID_LLI = 0x84, +#endif + SCI_MSTID_HSI = 0x90, +#if defined(_OMAP5430) + SCI_MSTID_UNIPRO1 = 0x94, + SCI_MSTID_UNIPRO2 = 0x98, +#endif + SCI_MSTID_MMC1 = 0xA0, + SCI_MSTID_MMC2 = 0xA4, +#if defined(_OMAP5430) + SCI_MSTID_SATA = 0xA8, +#endif + SCI_MSTID_USB_HOST_HS = 0xC0, + SCI_MSTID_USB_OTG_HS = 0xC4, + SCI_MSTID_USB_OTG_FS = 0xC8, +#if defined(_OMAP5430) + SCI_MSTID_USB3 = 0xCC, +#endif + SCI_MASTID_ALL +}; + +/*! \par sci_slave_addr Slave address enumerations. */ +enum sci_slave_addr { + SCI_SLVID_HOST_CLK1 = 0x0, + SCI_SLVID_DMM_P1_TARG = 0x1, + SCI_SLVID_DMM_P2_TARG = 0x2, + SCI_SLVID_ABE_TARG = 0x3, + SCI_SLVID_L4_CFG_TARG = 0x4, + SCI_SLVID_HOST_CLK2 = 0x6, + SCI_SLVID_GPMC_TARG= 0x7, + SCI_SLVID_OCM_RAM_TARG = 0x8, + SCI_SLVID_DSS_TARG = 0x9, + SCI_SLVID_ISS_TARG = 0xA, + SCI_SLVID_IPU_TARG = 0xB, + SCI_SLVID_GPU_TARG = 0xC, + SCI_SLVID_IVA_TARG = 0xD, + SCI_SLVID_SL2_TARG = 0xE, + SCI_SLVID_L4_PER_P0_TARG = 0xF, + SCI_SLVID_L4_PER_P1_TARG = 0x10, + SCI_SLVID_L4_PER_P2_TARG = 0x11, + SCI_SLVID_L4_PER_P3_TARG = 0x12, + SCI_SLVID_C2C_TARG = 0x16, + SCI_SLVID_LLI_TARG = 0x17, + SCI_SLVID_HOST_CLK3 = 0x18, + SCI_SLVID_L3_INSTR_TARG = 0x19, + SCI_SLVID_CAL_TARG = 0x1A, + SCI_SLVID_DEBUGSS_CT_TBR_TARG = 0x1C, + SCI_SLVID_ALL +}; + +#endif +#endif // #ifndef SCI_DEV_H diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_swcapture.c tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_swcapture.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_swcapture.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_swcapture.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1069 @@ +/* + * + * @Component OMAPCONF + * @Filename sci_swcapture.c + * @Description statistiscal collectors + * @Author Frederic Turgis (f-turgis@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sci.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct name_value { + char *name; + char *name_ccs; + unsigned int value; +}; + +struct name_value match_master[] = { +{ "alldmm", "All DMM", SCI_MASTID_ALL }, +{ "mpuss", "MPUSS", SCI_MSTID_MPUSS }, +{ "dap", "DAP", SCI_MSTID_DAP }, +{ "dsp", "DSP", SCI_MSTID_DSP }, +{ "iva", "IVA", SCI_MSTID_IVA }, +{ "iss", "ISS", SCI_MSTID_ISS }, +{ "ipu", "IPU", SCI_MSTID_IPU }, +{ "fdid", "FDID", SCI_MSTID_FDIF }, +{ "sdma_rd", "SDMA_RD", SCI_MSTID_SDMA_RD }, +{ "sdma_wr", "SDMA_WR", SCI_MSTID_SDMA_WR }, +{ "gpu_p1", "GPU_P1", SCI_MSTID_GPU_P1 }, +{ "gpu_p2", "GPU_P2", SCI_MSTID_GPU_P2 }, +{ "bb2d_p1", "BB2D_P1", SCI_MSTID_BB2D_P1 }, +{ "bb2d_p2", "BB2D_P2", SCI_MSTID_BB2D_P2 }, +{ "dss", "DSS", SCI_MSTID_DSS }, +{ "c2c", "C2C", SCI_MSTID_C2C }, +{ "lli", "LLI", SCI_MSTID_LLI }, +{ "hsi", "HSI", SCI_MSTID_HSI }, +{ "unipro1", "UNIPRO1", SCI_MSTID_UNIPRO1 }, +{ "unipro2", "UNIPRO2", SCI_MSTID_UNIPRO2 }, +{ "mmc1", "MMC1", SCI_MSTID_MMC1 }, +{ "mmc2", "MMC2", SCI_MSTID_MMC2 }, +{ "sata", "SATA", SCI_MSTID_SATA }, +{ "usb_host_hs", "USB_HOST_HS", SCI_MSTID_USB_HOST_HS }, +{ "usb_otg_hs", "USB_OTG_HS", SCI_MSTID_USB_OTG_HS }, +{ "usb_otg_fs", "USB_OTG_FS", SCI_MSTID_USB_OTG_FS }, +{ "usb3", "USB3", SCI_MSTID_USB3 }, +{ NULL, NULL, 0 } +}; + +struct name_value match_qualifier[] = { +{ "r", "Rd", SCI_RD_ONLY }, +{ "r+w", "Rd/Wr", SCI_RD_OR_WR_DONTCARE }, +{ "w", "Wr", SCI_WR_ONLY }, +{ NULL, NULL, 0 } +}; + +struct name_value match_probe[] = { +{ "emif1", "EMIF 0", SCI_EMIF1 }, +{ "emif2", "EMIF 1", SCI_EMIF2 }, +{ NULL, NULL, 0 } +}; + +struct sci_config_sdram my_config_emif1 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF1, 1, { { SCI_MASTID_ALL, 0xff, SCI_WR_ONLY, SCI_ERR_DONTCARE } } }; +struct sci_config_sdram my_config_emif2 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF2, 1, { { SCI_MASTID_ALL, 0xff, SCI_WR_ONLY, SCI_ERR_DONTCARE } } }; +struct sci_config_sdram my_config_emif3 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF1, 1, { { SCI_MASTID_ALL, 0xff, SCI_RD_ONLY, SCI_ERR_DONTCARE } } }; +struct sci_config_sdram my_config_emif4 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF2, 1, { { SCI_MASTID_ALL, 0xff, SCI_RD_ONLY, SCI_ERR_DONTCARE } } }; +struct sci_config_sdram my_config_emif5 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF1, 1, { { SCI_MASTID_ALL, 0xff, SCI_WR_ONLY, SCI_ERR_DONTCARE } } }; +struct sci_config_sdram my_config_emif6 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF2, 1, { { SCI_MASTID_ALL, 0xff, SCI_WR_ONLY, SCI_ERR_DONTCARE } } }; +struct sci_config_sdram my_config_emif7 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF1, 0, { { SCI_MASTID_ALL, 0xff, SCI_RD_OR_WR_DONTCARE, SCI_ERR_DONTCARE } } }; +struct sci_config_sdram my_config_emif8 = { SCI_SDRAM_THROUGHPUT, SCI_EMIF2, 0, { { SCI_MASTID_ALL, 0xff, SCI_RD_OR_WR_DONTCARE, SCI_ERR_DONTCARE } } }; + +struct sci_config_sdram * pmy_cfg[] = { + &my_config_emif1, + &my_config_emif2, + &my_config_emif3, + &my_config_emif4, + &my_config_emif5, + &my_config_emif6, + &my_config_emif7, + &my_config_emif8, + }; + +#define GET_32K *(addr_32k) +#define MAX_ITERATIONS 1000000UL + +static char msg[8][100], msg_overflow[8][100]; // messages for CCS like output (-a 1 option) +static volatile unsigned int *addr_32k = NULL; // 32K timestamping +static uint32_t counters[(8+1)*MAX_ITERATIONS]; // timestamp+counters storing in "-a 1" mode +static unsigned int num_use_cases = 4; +static unsigned int option_overflow_counter_index[2], option_overflow_threshold[2]; +static unsigned int option_overflow_iterations; +static unsigned int tests; // number of tests really executed in case of Ctrl-C +static unsigned int nosleep_32k_reg; // -n option +static unsigned int option_nosleep_32k = 0; // -n option +static unsigned int option_accumulation_type; // -a option +static unsigned int valid_usecase_cnt = 0; +static psci_handle psci_hdl = NULL; +static psci_usecase_key my_usecase_key[8] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; + + +void sci_errhandler(psci_handle phandle, const char * func, enum sci_err err); +void nosleep_32k_enable(void); +void nosleep_32k_disable(void); + +// Generic handling of sample array +#define SAMPLE_SIZE (1 + num_use_cases) // sample contains 1 timestamp + x counters +#define TIMESTAMP_INDEX (0) // timestamp is first index in 1 sample +#define COUNTER_INDEX (1) // counters are put just after timestamp + +void dump_buffer(void) +{ + uint32_t *counters_current = counters; + unsigned int timestamp0, time; + unsigned int i,j, tests_overflow; + unsigned int *prev_counter, *current_counter; + tests_overflow = 1; + unsigned int overflow_on = 0; + + fprintf(stderr, "%u iterations finished, dumping to file\n", tests); + + // for each test, we will compute delta between prev and current and print at current timestamp + for (i = 0; i < tests - 1; i++) + { + unsigned int timestamp = *(counters_current + TIMESTAMP_INDEX + SAMPLE_SIZE); + if (i == 0) { + timestamp0 = *(counters_current + TIMESTAMP_INDEX); + printf("Ref timestamp: %u\n", timestamp0); + } + // Use relative timestamp + time = timestamp - timestamp0; + + // Detect reset. Sample i triggers reset so sample i+1 delta to i is ignored + if ( ( (option_overflow_iterations > 0) && (tests_overflow > option_overflow_iterations) ) + || ( (option_overflow_iterations == 0) + && ( (*(counters_current + COUNTER_INDEX + option_overflow_counter_index[0]) >= option_overflow_threshold[0]) + || (*(counters_current + COUNTER_INDEX + option_overflow_counter_index[1]) >= option_overflow_threshold[1]) + ) + ) + ) + overflow_on = 1; + + for (j = 0; j < num_use_cases; j++) { + // current counter is in fact next sample, i.e. j + sample_size. prev is j + current_counter = counters_current + SAMPLE_SIZE + COUNTER_INDEX + j; + prev_counter = counters_current + COUNTER_INDEX + j; + + // Overflow at 2^32. We can't fix that + if (*current_counter == 0xFFFFFFFF) { + fprintf(stderr, "ERROR: counter %d %s overflowed at time %u, don't trust results\n", j, msg[j], time); + printf("ERROR: counter %d %s overflowed at time %u, don't trust results\n", j, msg[j], time); + } + + // Dump result. In case of overflow, just print for reference, post-processing will ignore + if (overflow_on == 1) { + printf("Warning: overflow\n"); + printf("0,0,0,S,,SDRAM,,%u,%s,T,V,%u,,,,0,\n", *current_counter - *prev_counter, msg_overflow[j], time); + } + else { + // HW bug, you read a counter that is < previous value. We fix this by forcing same value than previous sample + if (*current_counter < *prev_counter) { + fprintf(stderr, "WARNING: HW bug, counter %d %s N-1=%u N=%u at time %u. omapconf fixes it\n", j, msg[j], *prev_counter, *current_counter, time); + printf("WARNING: HW bug, counter %d %s N-1=%u N=%u at time %u. omapconf fixes it\n", j, msg[j], *prev_counter, *current_counter, time); + // omapconf fix, any value is OK as this is only about deltas + *current_counter = *prev_counter; + } + + printf("0,0,0,S,,SDRAM,,%u,%s,T,V,%u,,,,0,\n", *current_counter - *prev_counter, msg[j], time); + } + } + counters_current += SAMPLE_SIZE; + + if (overflow_on == 1) { + tests_overflow = 0; + overflow_on = 0; + } + tests_overflow++; + } +} + +void sci_killhandler(void) +{ + unsigned int i; + + if (option_accumulation_type == 1) + dump_buffer(); + + mem_unmap_32k(addr_32k); + + if (option_nosleep_32k) + nosleep_32k_disable(); + + for (i = 0; i < valid_usecase_cnt; i++) { + sci_remove_usecase( psci_hdl, &my_usecase_key[i]); + } + + sci_global_disable(psci_hdl); + sci_close(&psci_hdl); + powerdm_emu_disable(); +} + + +int statcoll_main(int argc, char **argv) +{ + struct sci_config my_sci_config; + enum sci_err my_sci_err; + int c, option_index = 0; + static int longopt_flag; + unsigned int option_delay_us; + unsigned int option_overflow_delay_us; + unsigned int option_iterations; + unsigned int option_disable = 0; + unsigned int option_min_addr; + unsigned int option_max_addr; + unsigned int describe_loop; + + // Default values of options + option_delay_us = 1000000; // 1 second + option_overflow_delay_us = 1000000; // 1 second + option_overflow_iterations = option_overflow_delay_us / option_delay_us; + option_accumulation_type = 2; // dump on terminal + option_iterations = 0; // infinite iterations + option_overflow_counter_index[0] = 0; // check counter 0 for overflow + option_overflow_counter_index[1] = 0; + option_overflow_threshold[0] = 0; // reset at each capture + option_overflow_threshold[1] = 0; + + static struct option long_options[] = + { + /* These options set a flag. */ + {"m0", required_argument, &longopt_flag, 'm'}, + {"m1", required_argument, &longopt_flag, 'm'}, + {"m2", required_argument, &longopt_flag, 'm'}, + {"m3", required_argument, &longopt_flag, 'm'}, + {"m4", required_argument, &longopt_flag, 'm'}, + {"m5", required_argument, &longopt_flag, 'm'}, + {"m6", required_argument, &longopt_flag, 'm'}, + {"m7", required_argument, &longopt_flag, 'm'}, + {"tr0", required_argument, &longopt_flag, 'q'}, + {"tr1", required_argument, &longopt_flag, 'q'}, + {"tr2", required_argument, &longopt_flag, 'q'}, + {"tr3", required_argument, &longopt_flag, 'q'}, + {"tr4", required_argument, &longopt_flag, 'q'}, + {"tr5", required_argument, &longopt_flag, 'q'}, + {"tr", required_argument, &longopt_flag, 'q'}, + {"p0", required_argument, &longopt_flag, 'p'}, + {"p1", required_argument, &longopt_flag, 'p'}, + {"p2", required_argument, &longopt_flag, 'p'}, + {"p3", required_argument, &longopt_flag, 'p'}, + {"p4", required_argument, &longopt_flag, 'p'}, + {"p5", required_argument, &longopt_flag, 'p'}, + {"p6", required_argument, &longopt_flag, 'p'}, + {"p7", required_argument, &longopt_flag, 'p'}, + {"allcounters", no_argument, &longopt_flag, '8'}, + {"overflow_delay", required_argument, &longopt_flag, '1'}, + {0, 0, 0, 0} + }; + + while ((c = getopt_long (argc, argv, "hnm:d:a:i:o:t:r:p:q:D", long_options, &option_index)) != -1) { + // small trick to merge long options with short options of same doaain (-m and --m0 --m1 ...) + unsigned int long_opt = 0; + + if (c == 0) + { + long_opt = 1; + c = long_options[option_index].val; + } + + switch (c) + { + case 'h': + { + unsigned int loop = 0; + + printf("\n\tomapconf trace bw [-h] [<-m | --m> <0xyy | ma_mpu | alldmm | dss | iva | ...>] [<-p | --p ] [<--tr | --tr> ] [-d x] [--overflow_delay x] [-a 1 or 2] [-i x] [-o x -t y] [-r 0xaaaaaaaa-0xbbbbbbbb] [-n]\n"); + printf("\n\t-m, -p, -q sets all 8 counters while -m0, --p0, --q0 to --m7, --tr7, --p5 set 1 counter only\n"); + printf("\n\t-m <0xyy | ma_mpu | alldmm | dss | iva | ...> (MA_MPU_1_2 deprecated)\n"); + printf("\t\tMaster initiator monitored. WARNING: All DMM traffic includes DSS, IVA, GPU, ... but not MA_MPU, which requires parallel monitoring \n"); + printf("\t\tma_mpu (MA_MPU_1_2 deprecated) - Non DMM MPU memory traffic, see Examples\n"); + + while (match_master[loop].name != NULL) + { + printf("\t\t%s 0x%x\n", match_master[loop].name, match_master[loop].value); + loop++; + } + + printf("\n\t-d xxx or 0.xx\n"); + printf("\t\tDelay in ms between 2 captures, can be float\n"); + printf("\n\t--overflow_delay xxx or 0.xx\n"); + printf("\t\tDelay in ms after which HW IP is reset to avoid overflow. Disables -o -t options. Can be float.\n"); + printf("\n\t-p or --p \n"); + printf("\t\tProbed channel. 1 counter can monitor only EMIF1 or EMIF2\n"); + printf("\n\t--tr or --tr \n"); + printf("\t\tTransaction qualifier. Rd or Wr or Rd+Wr monitoring. HW implementation prevents changing this on last 2 counters\n"); + printf("\n\t-a 1 or 2\n"); + printf("\t\taccumulation type. 2: dump at every capture. 1: dump only at end\n"); + printf("\n\t-i x\n"); + printf("\t\tnumber of iterations (for -a 1). You can Ctrl-C during test, current captures will be displayed\n"); + printf("\n\t-o x -t y \n"); + printf("\t\tindex for overflow handling + threshold to reset HW. Disables auto-reset of HW IP based on time (--overflow_delay). You MUST use them for -a 1\n"); + printf("\t\tUse this option twice to set 2 different thresholds on 2 different counters\n"); + printf("\n\t-r 0xaa-0xbb\n"); + printf("\t\taddress filtering, like 0x9b000000-0x9f000000\n"); + printf("\n\t-n\n"); + printf("\t\tno sleep of 32kHz (work-around for 32kHz reading HW bug). MANDATORY for OMAP5 until fix is found\n"); + printf("\n\t-D\n"); + printf("\t\tdisable statcol (deprecated)\n"); + printf("\n\tExamples:\n"); + printf("\tDefault: --p7 emif2 (this forces use of 8 counters and counter 7 is using emif2 as default probed channel)\n"); + printf("\t\tCounter: 0 Master: alldmm Transaction: w Probe: emif1\n"); + printf("\t\tCounter: 1 Master: alldmm Transaction: w Probe: emif2\n"); + printf("\t\tCounter: 2 Master: alldmm Transaction: r Probe: emif1\n"); + printf("\t\tCounter: 3 Master: alldmm Transaction: r Probe: emif2\n"); + printf("\t\tCounter: 4 Master: alldmm Transaction: w Probe: emif1\n"); + printf("\t\tCounter: 5 Master: alldmm Transaction: w Probe: emif2\n"); + printf("\t\tCounter: 6 Master: alldmm Transaction: r+w Probe: emif1\n"); + printf("\t\tCounter: 7 Master: alldmm Transaction: r+w Probe: emif2\n"); + printf("\n\t-m 0x70 -d 1000 -a 2 (often used as -m 0x70 only)\n"); + printf("\t\taccumulation 2 is reading of registers and tracing them immediately\n"); + printf("\t\tFormat is time: time_start time_end delta_time -> Wr_DMM_EMIF1 Wr_DMM_EMIF2 Rd_DMM_EMIF1 Rd_DMM_EMIF2 (MB/s)\n"); + printf("\n\t-m dss -d 0.3 -a 1 -i 40000 -o 2 -t 3000000000\n"); + printf("\t\taccumulation 1 is reading of registers and storing in RAM. Result is dumped at the end with CCS format to reuse\n"); + printf("\t\texisting post-processing. So you must set iterations. Overflow is taken into account. Suits small delays\n"); + printf("\n\t-m MA_MPU -d 1000 -a 2 --overflow_delay 500\n"); + printf("\t\tMA_MPU is MPU memory adaptor, a direct path to EMIF. MA_MPU will display:\n"); + printf("\t\tWr_MA_MPU_EMIF1 Wr_MA_MPU_EMIF2 Rd_MA_MPU_EMIF Rd_MA_MPU_EMIF2 (MB/s)\n"); + printf("\n\t--tr r+w -p emif1 --m0 ma_mpu --m1 ma_mpu --tr1 w --p1 emif2 --m2 gpu_p1 --m3 dss --m4 alldmm --m5 alldmm --p5 emif2\n"); + printf("\t\tCounter: 0 Master: ma_mpu Transaction: r+w Probe: emif1\n"); + printf("\t\tCounter: 1 Master: ma_mpu Transaction: w Probe: emif2\n"); + printf("\t\tCounter: 2 Master: gpu_p1 Transaction: r+w Probe: emif1\n"); + printf("\t\tCounter: 3 Master: dss Transaction: r+w Probe: emif1\n"); + printf("\t\tCounter: 4 Master: alldmm Transaction: r+w Probe: emif1\n"); + printf("\t\tCounter: 5 Master: alldmm Transaction: r+w Probe: emif2\n"); + printf("\n\t2 masters + all traffic on EMIF1 and EMIF2: --tr r+w --m0 dss --m1 dss --m2 iva --m3 iva --m6 ma_mpu --m7 ma_mpu\n"); + printf("\tNote that you can monitor more masters if you have identified earlier that traffic is well balanced over EMIF1 and EMIF2, i.e. traffic for this master = 2 * EMIF1 = 2 * EMIF2\n"); + printf("\n\tDefault settings:\n"); + printf("\t\t-m 0xcd -d 1000 -a 2 -i 0 --overflow_delay 1000\n"); + printf("\t\tall initiators, 1000ms delay, accumulation 2, infinite iterations, auto-reset IP after 1 s, i.e. always stop/restart HW IP after 1 capture\n"); + printf("\n\tPost-processing (for -a 1):\n"); + printf("\t\tgit clone git://gitorious.tif.ti.com/omap-video-perf/runperf.git, instrumentation/bandwidth/BWstats_ccsv5.py\n"); + printf("\t\tpython-matplotlib is needed\n"); + printf("\n\tWiki:\n"); + printf("\t\t\n\n"); + + //sci_global_disable(psci_hdl); + //sci_close(&psci_hdl); + + return 0; + } + + case 'm': + { + unsigned int index; + + if (long_opt == 1) { + index = long_options[option_index].name[1] - '0'; + + // go up to 6 couhters + if ((index + 1) > num_use_cases) + num_use_cases = index + 1; + } + + if (!strstr(optarg, "ma_mpu")) { + unsigned int loop = 0; + + if (strstr(optarg, "0x")) { + unsigned int a; + sscanf(optarg, "%x", &a); + while (match_master[loop].name != NULL) + { + if (match_master[loop].value == a) + break; + loop++; + } + } + else { + while (match_master[loop].name != NULL) + { + if (!strcmp(match_master[loop].name, optarg)) + break; + loop++; + } + } + + if (match_master[loop].name != NULL) { + if (long_opt == 1) { + pmy_cfg[index]->filter[0].mstr_addr_match = match_master[loop].value; + if (pmy_cfg[index]->probe_id == SCI_MA_MPU_P1) + pmy_cfg[index]->probe_id = SCI_EMIF1; + if (pmy_cfg[index]->probe_id == SCI_MA_MPU_P2) + pmy_cfg[index]->probe_id = SCI_EMIF2; + } + else { + unsigned int i; + + for (i = 0; i < sizeof(pmy_cfg)/sizeof(struct sci_config_sdram *); i++) { + pmy_cfg[i]->filter[0].mstr_addr_match = match_master[loop].value; + if (pmy_cfg[i]->probe_id == SCI_MA_MPU_P1) + pmy_cfg[i]->probe_id = SCI_EMIF1; + if (pmy_cfg[i]->probe_id == SCI_MA_MPU_P2) + pmy_cfg[i]->probe_id = SCI_EMIF2; + } + } + } + // parsing error + else { + printf("ERROR: %s option of -m is not recognized\n", optarg); + goto END; + } + } + else if ( (!strcmp(optarg, "ma_mpu_1_2")) && (long_opt == 0) ) { + my_config_emif1.probe_id = SCI_MA_MPU_P1; + my_config_emif1.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif2.probe_id = SCI_MA_MPU_P2; + my_config_emif2.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif3.probe_id = SCI_MA_MPU_P1; + my_config_emif3.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif4.probe_id = SCI_MA_MPU_P2; + my_config_emif5.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif5.probe_id = SCI_MA_MPU_P1; + my_config_emif6.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif6.probe_id = SCI_MA_MPU_P2; + my_config_emif6.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif7.probe_id = SCI_MA_MPU_P1; + my_config_emif7.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif8.probe_id = SCI_MA_MPU_P2; + my_config_emif8.filter[0].mstr_addr_match = SCI_MASTID_ALL; + } + else if (!strcmp(optarg, "ma_mpu")) { + if (long_opt == 1) { + pmy_cfg[index]->filter[0].mstr_addr_match = SCI_MASTID_ALL; + if (pmy_cfg[index]->probe_id == SCI_EMIF1) + pmy_cfg[index]->probe_id = SCI_MA_MPU_P1; + if (pmy_cfg[index]->probe_id == SCI_EMIF2) + pmy_cfg[index]->probe_id = SCI_MA_MPU_P2; + } + else { + unsigned int i; + + for (i = 0; i < sizeof(pmy_cfg)/sizeof(struct sci_config_sdram *); i++) { + pmy_cfg[i]->filter[0].mstr_addr_match = SCI_MASTID_ALL; + if (pmy_cfg[i]->probe_id == SCI_EMIF1) + pmy_cfg[i]->probe_id = SCI_MA_MPU_P1; + if (pmy_cfg[i]->probe_id == SCI_EMIF2) + pmy_cfg[i]->probe_id = SCI_MA_MPU_P2; + } + } + } + else { + printf("ERROR: %s option of -m is not recognized\n", optarg); + goto END; + } + } + break; + case 'q': + { + unsigned int loop = 0; + unsigned int index; + + if (!strcmp(long_options[option_index].name, "tr")) + long_opt = 0; + + if (long_opt == 1) { + index = long_options[option_index].name[2] - '0'; + + // go up to 6 couhters + if ((index + 1) > num_use_cases) + num_use_cases = index + 1; + } + + while (match_qualifier[loop].name != NULL) + { + if (!strcmp(match_qualifier[loop].name, optarg)) + break; + loop++; + } + + if (match_qualifier[loop].name != NULL) { + if (long_opt == 1) { + pmy_cfg[index]->filter[0].trans_qual = match_qualifier[loop].value; + } + else { + unsigned int i; + + for (i = 0; i < sizeof(pmy_cfg)/sizeof(struct sci_config_sdram *); i++) { + pmy_cfg[i]->filter[0].trans_qual = match_qualifier[loop].value; + } + } + } + else { + printf("ERROR: %s option of -q/--qx not recognized\n", optarg); + goto END; + } + } + break; + case 'p': + { + unsigned int loop = 0; + unsigned int index; + + if (long_opt == 1) { + index = long_options[option_index].name[1] - '0'; + + // go up to 6 couhters + if ((index + 1) > num_use_cases) + num_use_cases = index + 1; + } + + while (match_probe[loop].name != NULL) + { + if (!strcmp(match_probe[loop].name, optarg)) + break; + loop++; + } + + if (match_probe[loop].name != NULL) { + if (long_opt == 1) { + if (pmy_cfg[index]->probe_id == SCI_MA_MPU_P1) { + if (match_probe[loop].value == SCI_EMIF2) + pmy_cfg[index]->probe_id = SCI_MA_MPU_P2; + } + else if (pmy_cfg[index]->probe_id == SCI_MA_MPU_P2) { + if (match_probe[loop].value == SCI_EMIF1) + pmy_cfg[index]->probe_id = SCI_MA_MPU_P1; + } + else { + pmy_cfg[index]->probe_id = match_probe[loop].value; + } + } + else { + unsigned int i; + + for (i = 0; i < sizeof(pmy_cfg)/sizeof(struct sci_config_sdram *); i++) { + if ( (pmy_cfg[i]->probe_id == SCI_MA_MPU_P1) && (match_probe[loop].value == SCI_EMIF2) ) + pmy_cfg[i]->probe_id = SCI_MA_MPU_P2; + else if ( (pmy_cfg[i]->probe_id == SCI_MA_MPU_P2) && (match_probe[loop].value == SCI_EMIF1) ) + pmy_cfg[i]->probe_id = SCI_MA_MPU_P1; + else + pmy_cfg[i]->probe_id = match_probe[loop].value; + } + } + } + else { + printf("ERROR: %s option of -p/--px not recognized\n", optarg); + goto END; + } + } + break; + case 'd': + { + float a; + if ( (sscanf(optarg, "%f", &a) > 0) && (a > 0)) + option_delay_us = a * 1000; + else { + printf("ERROR: %s option of -d not recognized or wrong\n", optarg); + goto END; + } + if (option_overflow_iterations > 0) + option_overflow_iterations = option_overflow_delay_us / option_delay_us; + } + break; + case 'a': + sscanf(optarg, "%u", &option_accumulation_type); + if ((option_accumulation_type != 1) && (option_accumulation_type != 2)) { + printf("ERROR: %s option of -a not recognized or wrong\n", optarg); + goto END; + } + break; + case 'i': + if (sscanf(optarg, "%u", &option_iterations) == 0) { + printf("ERROR: %s option of -i not recognized\n", optarg); + goto END; + } + break; + case 'o': + { + static unsigned int o_count = 0; + unsigned int result; + + if ((sscanf(optarg, "%u", &result) == 0) || (result > 7)) { + printf("ERROR: %s option of -o not recognized or too high\n", optarg); + goto END; + } + + option_overflow_counter_index[1] = result; + if (o_count++ == 0) + option_overflow_counter_index[0] = result; + option_overflow_delay_us = 0; + option_overflow_iterations = 0; + } + break; + case 't': + { + static unsigned int t_count = 0; + unsigned int result; + + if (sscanf(optarg, "%u", &result) == 0) { + printf("ERROR: %s option of -t not recognized\n", optarg); + goto END; + } + + option_overflow_threshold[1] = result; + if (t_count++ == 0) + option_overflow_threshold[0] = result; + option_overflow_delay_us = 0; + option_overflow_iterations = 0; + } + break; + case 'n': + option_nosleep_32k = 1; + break; + case '8': + num_use_cases = sizeof(pmy_cfg)/sizeof(struct sci_config_sdram *); + break; + case '1': + { + float a; + if ( (sscanf(optarg, "%f", &a) > 0) && (a > 0)) { + option_overflow_delay_us = a * 1000; + option_overflow_iterations = option_overflow_delay_us / option_delay_us; + } + else { + printf("ERROR: %s option of --overflow_delay not recognized or wrong\n", optarg); + goto END; + } + } + break; + case 'r': + sscanf(optarg, "0x%x-0x%x", &option_min_addr, &option_max_addr); + + my_config_emif1.addr_filter_min = option_min_addr; + my_config_emif2.addr_filter_min = option_min_addr; + my_config_emif3.addr_filter_min = option_min_addr; + my_config_emif4.addr_filter_min = option_min_addr; + my_config_emif5.addr_filter_min = option_min_addr; + my_config_emif6.addr_filter_min = option_min_addr; + + my_config_emif1.addr_filter_max = option_max_addr; + my_config_emif2.addr_filter_max = option_max_addr; + my_config_emif3.addr_filter_max = option_max_addr; + my_config_emif4.addr_filter_max = option_max_addr; + my_config_emif5.addr_filter_max = option_max_addr; + my_config_emif6.addr_filter_max = option_max_addr; + + my_config_emif1.addr_filter_enable = true; + my_config_emif2.addr_filter_enable = true; + my_config_emif3.addr_filter_enable = true; + my_config_emif4.addr_filter_enable = true; + my_config_emif5.addr_filter_enable = true; + my_config_emif6.addr_filter_enable = true; + break; + case 'D': + option_disable = 1; + default: + printf("ERROR: Unknown option\n"); + goto END; + } + } + + // Error checking, are there still elements ? + if (optind < argc) + { + printf ("ERROR: non-option ARGV-elements: "); + while (optind < argc) + printf ("%s ", argv[optind++]); + putchar ('\n'); + goto END; + } + + // Even if above chhanges config of counter 7 and 8, we restore default as they can't filter + my_config_emif7.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif7.filter[0].trans_qual = SCI_RD_OR_WR_DONTCARE; + my_config_emif8.filter[0].mstr_addr_match = SCI_MASTID_ALL; + my_config_emif8.filter[0].trans_qual = SCI_RD_OR_WR_DONTCARE; + + // Describe configuration of counters in human readable format + for (describe_loop = 0; describe_loop < num_use_cases; describe_loop++) { + unsigned int a, b, c; + char *a_name, *b_name, *c_name; + unsigned int loop = 0, loop_transaction = 0; + + a = pmy_cfg[describe_loop]->filter[0].mstr_addr_match; + b = pmy_cfg[describe_loop]->filter[0].trans_qual; + c = pmy_cfg[describe_loop]->probe_id; + + while (match_probe[loop].name != NULL) + { + if (match_probe[loop].value == c) + break; + loop++; + } + if (match_probe[loop].name != NULL) { + c_name = match_probe[loop].name; + strcpy(msg[describe_loop], match_probe[loop].name_ccs); + strcpy(msg_overflow[describe_loop], match_probe[loop].name_ccs); + } + else { + c_name = "ERROR"; + strcpy(msg[describe_loop], "ERROR"); + strcpy(msg_overflow[describe_loop], "ERROR"); + } + + loop_transaction = 0; + while (match_qualifier[loop_transaction].name != NULL) + { + if (match_qualifier[loop_transaction].value == b) + break; + loop_transaction++; + } + if (match_qualifier[loop_transaction].name != NULL) { + char temp[20]; + + b_name = match_qualifier[loop_transaction].name; + sprintf(temp, ":%s:", match_qualifier[loop_transaction].name_ccs); + strcat(msg[describe_loop], temp); + sprintf(temp, ":%s:", match_qualifier[loop_transaction].name); + strcat(msg_overflow[describe_loop], temp); + } + else { + b_name = "ERROR"; + strcat(msg[describe_loop], ":ERROR:"); + strcat(msg_overflow[describe_loop], ":ERROR:"); + } + + loop = 0; + while (match_master[loop].name != NULL) + { + if (match_master[loop].value == a) + break; + loop++; + } + if (match_master[loop].name != NULL) { + a_name = match_master[loop].name; + strcat(msg[describe_loop], match_master[loop].name_ccs); + strcat(msg_overflow[describe_loop], match_master[loop].name_ccs); + } + else { + a_name = "ERROR"; + strcat(msg[describe_loop], "ERROR"); + strcat(msg_overflow[describe_loop], "ERROR"); + } + + if ( (pmy_cfg[describe_loop]->filter[0].mstr_addr_match == SCI_MASTID_ALL) && (pmy_cfg[describe_loop]->probe_id == SCI_MA_MPU_P1)) { + printf("Counter: %d Master: ma_mpu Transaction: %s Probe: emif1\n", describe_loop, b_name); + sprintf(msg[describe_loop], "EMIF 0:%s:MA_MPU", match_qualifier[loop_transaction].name_ccs); + sprintf(msg_overflow[describe_loop], "EMIF 0:%s:MA_MPU", match_qualifier[loop_transaction].name); + continue; + } + if ( (pmy_cfg[describe_loop]->filter[0].mstr_addr_match == SCI_MASTID_ALL) && (pmy_cfg[describe_loop]->probe_id == SCI_MA_MPU_P2)) { + printf("Counter: %d Master: ma_mpu Transaction: %s Probe: emif2\n", describe_loop, b_name); + sprintf(msg[describe_loop], "EMIF 1:%s:MA_MPU", match_qualifier[loop_transaction].name_ccs); + sprintf(msg_overflow[describe_loop], "EMIF 1:%s:MA_MPU", match_qualifier[loop_transaction].name); + continue; + } + + printf("Counter: %d Master: %s Transaction: %s Probe: %s\n", describe_loop, a_name, b_name, c_name); + } + + printf("delay in us: %u\n", option_delay_us); + if (option_overflow_iterations > 0) + printf("overflow delay in us: %u (iterations=%u)\n", option_overflow_delay_us, option_overflow_iterations); + else + printf("overflow delay in us: DISABLED (-o -t used)\n"); + printf("accumulation type: %u\n", option_accumulation_type); + printf("iterations (0=infinite): %u\n", option_iterations); + if (option_overflow_iterations == 0) { + printf("Overflow counter index: %u %u\n", option_overflow_counter_index[0], option_overflow_counter_index[1]); + printf("Overflow threshold: %u %u\n", option_overflow_threshold[0], option_overflow_threshold[1]); + } + else { + printf("Overflow counter index: DISABLED (overflow delay used)\n"); + printf("Overflow threshold: DISABLED (overflow delay used)\n"); + } + + if (option_iterations > MAX_ITERATIONS) { + option_iterations = MAX_ITERATIONS; + printf("WARNING: MAX_ITERATIONS(%d) exceeded\n", option_iterations); + } + + powerdm_emu_enable(); + + ///////////////////////////////////////////////////// + //Make sure DebugSS is powered up and enabled // + ///////////////////////////////////////////////////// + my_sci_config.errhandler = sci_errhandler; + my_sci_config.data_options = 0; //Disable options + my_sci_config.trigger_enable = false; + my_sci_config.sdram_msg_rate = 1; + my_sci_config.mstr_msg_rate = 1; + my_sci_config.mode = SCI_MODE_DUMP; + + addr_32k = mem_map_32k(); + + my_sci_err = sci_open(&psci_hdl, &my_sci_config); + + if (SCI_SUCCESS != my_sci_err) exit(-1); + + { + uint32_t plib_major_ver; + uint32_t plib_minor_ver; + uint32_t plib_func_id; + uint32_t pmod_func_id; + + sci_get_version(psci_hdl, &plib_major_ver, &plib_minor_ver, + &plib_func_id, &pmod_func_id ); + + if ( plib_func_id != pmod_func_id ) + { + printf ("Error - func missmatch with device %d %d\n", plib_func_id, pmod_func_id); + sci_close(&psci_hdl); + powerdm_emu_disable(); + exit(-1); + } + } + + // Test + { + unsigned int i, j; + + for (i = 0; i < num_use_cases; i++) { + my_sci_err = sci_reg_usecase_sdram(psci_hdl, pmy_cfg[i], &my_usecase_key[i] ); + + if ( SCI_SUCCESS != my_sci_err) break; + + valid_usecase_cnt++; + } + + /* If you kill the process, statcoll is left running. this is an option to disable it. We should intercept and handle signal */ + if (option_disable == 1) { + sci_global_disable(psci_hdl); + sci_close(&psci_hdl); + return 0; + } + + /* And this is an ugly hack to disable it so that it will reset counters at enable */ + sci_global_disable(psci_hdl); + + if (option_nosleep_32k) + nosleep_32k_enable(); + + if (valid_usecase_cnt == num_use_cases) + { + uint32_t *counters_current = counters; + unsigned int tests_overflow = 1; + + if (option_accumulation_type == 1) { + for (tests = 0; tests < (option_iterations * 9); tests++) + counters[tests] = 0; + + my_sci_err = sci_global_enable(psci_hdl); + + for (tests = 0; tests < option_iterations; tests++) { + usleep(option_delay_us); + *(counters_current + TIMESTAMP_INDEX) = GET_32K; + sci_dump_sdram_cntrs(num_use_cases, counters_current + COUNTER_INDEX); + + if ( ( (option_overflow_iterations > 0) && (tests_overflow > option_overflow_iterations) ) + || ( (option_overflow_iterations == 0) + && ( (*(counters_current + COUNTER_INDEX + option_overflow_counter_index[0]) >= option_overflow_threshold[0]) + || (*(counters_current + COUNTER_INDEX + option_overflow_counter_index[1]) >= option_overflow_threshold[1]) + ) + ) + ) { + sci_global_disable(psci_hdl); + sci_global_enable(psci_hdl); + counters_current += SAMPLE_SIZE; + *(counters_current + TIMESTAMP_INDEX) = GET_32K; + sci_dump_sdram_cntrs(num_use_cases, counters_current + COUNTER_INDEX); + tests++; + tests_overflow = 1; + //printf("overflow %u\n", *counters_current - counters[0]); + } + counters_current += SAMPLE_SIZE; + tests_overflow++; + } + } + else { + uint32_t *counters_prev; + uint32_t *counters_overflow; + unsigned int overflow_on; + uint32_t delta_time; + unsigned int tests_overflow = 1; + + for (i = 0; i < sizeof(counters)/4; i++) + counters[i] = 0; + counters_prev = counters; + counters_current = counters + SAMPLE_SIZE; + counters_overflow = counters + 2 * SAMPLE_SIZE; + + sci_global_enable(psci_hdl); + *(counters_prev + TIMESTAMP_INDEX) = GET_32K; + sci_dump_sdram_cntrs(num_use_cases, counters_prev + COUNTER_INDEX); + + for (;;) { + tests_overflow++; + + usleep(option_delay_us); + *(counters_current + TIMESTAMP_INDEX) = GET_32K; + sci_dump_sdram_cntrs(num_use_cases, counters_current + COUNTER_INDEX); + + + if ( ( (option_overflow_iterations > 0) && (tests_overflow > option_overflow_iterations) ) + || ( (option_overflow_iterations == 0) + && ( (*(counters_current + COUNTER_INDEX + option_overflow_counter_index[0]) >= option_overflow_threshold[0]) + || (*(counters_current + COUNTER_INDEX + option_overflow_counter_index[1]) >= option_overflow_threshold[1]) + ) + ) + ) { + sci_global_disable(psci_hdl); + sci_global_enable(psci_hdl); + *(counters_overflow + TIMESTAMP_INDEX) = GET_32K; + sci_dump_sdram_cntrs(num_use_cases, counters_overflow + COUNTER_INDEX); + overflow_on = 1; + tests_overflow = 1; + } + + /* trace current - prev */ + delta_time = *(counters_current + TIMESTAMP_INDEX) - *(counters_prev + TIMESTAMP_INDEX); + printf("time: %u %u %u -> ", *(counters_current + TIMESTAMP_INDEX), *(counters_prev + TIMESTAMP_INDEX), delta_time); + for (j = 0; j < num_use_cases; j++) { + printf("%.2f ", ((float)(*(counters_current + COUNTER_INDEX + j) - *(counters_prev + COUNTER_INDEX + j))/1000000)*32768.0/delta_time); + } + printf("\n"); + + for (j = 0; j < num_use_cases; j++) { + if (*(counters_current + COUNTER_INDEX + j) == 0xFFFFFFFF) { + fprintf(stderr, "ERROR: counter %d %s overflowed at time %u, don't trust results\n", j, msg[j], *(counters_current + TIMESTAMP_INDEX)); + printf("ERROR: counter %d %s overflowed at time %u, don't trust results\n", j, msg[j], *(counters_current + TIMESTAMP_INDEX)); + } + } + + /* pointers increment */ + if (overflow_on == 1) { + overflow_on = 0; + counters_current = counters_overflow; + } + + // offset all pointers by 1 sample + counters_prev = counters_current; + + if ((unsigned int)(counters_current - counters) == (2 * SAMPLE_SIZE)) + counters_current = counters; + else + counters_current += SAMPLE_SIZE; + + counters_overflow = counters_current; + if ((unsigned int)(counters_overflow - counters) == (2 * SAMPLE_SIZE)) + counters_overflow = counters; + else + counters_overflow += SAMPLE_SIZE; + } + } + } + else { + printf(" SCI Lib Error %d\n", my_sci_err); + } + } + + sci_killhandler(); +END: + exit(0); +} + +void sci_errhandler(psci_handle phandle, const char * func, enum sci_err err) +{ + enum sci_err my_sci_err = SCI_SUCCESS; + + printf("SCILib failure %d in function: %s \n", err, func ); + + if (NULL != phandle) + my_sci_err = sci_close(&phandle); + + if ( my_sci_err ) + exit(-2); + else + exit (-3); +} + + +void nosleep_32k_enable(void) +{ + unsigned int reg; + unsigned int reg_clk; + + if (cpu_is_omap54xx()) { + if (cpu_revision_get() == REV_ES1_0) + reg_clk = OMAP5430ES1_CM_WKUPAON_CLKSTCTRL; + else + reg_clk = OMAP5430_CM_WKUPAON_CLKSTCTRL; + } else if (cpu_is_omap44xx()) { + reg_clk = OMAP4430_CM_WKUP_CLKSTCTRL; + } + mem_read(reg_clk, ®); + nosleep_32k_reg = reg & 0x3; + reg = reg & (~0x3); + mem_write(reg_clk, reg); +} + +void nosleep_32k_disable(void) +{ + unsigned int reg; + unsigned int reg_clk; + + if (cpu_is_omap54xx()) { + if (cpu_revision_get() == REV_ES1_0) + reg_clk = OMAP5430ES1_CM_WKUPAON_CLKSTCTRL; + else + reg_clk = OMAP5430_CM_WKUPAON_CLKSTCTRL; + } else if (cpu_is_omap44xx()) { + reg_clk = OMAP4430_CM_WKUP_CLKSTCTRL; + } + + mem_read(reg_clk, ®); + reg = reg | nosleep_32k_reg; + mem_write(reg_clk, reg); +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_swcapture.h tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_swcapture.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/statcoll/sci_swcapture.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/statcoll/sci_swcapture.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,53 @@ +/* + * + * @Component OMAPCONF + * @Filename sci_swcapture.h + * @Description statistiscal collectors + * @Author Frederic Turgis (f-turgis@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __SCI_SWCAPTURE_H__ +#define __SCI_SWCAPTURE_H__ + + +int statcoll_main(int argc, char **argv); +void sci_killhandler(void); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/timestamp_32k.c tiomapconf-1.61.1/arch/arm/mach-omap/common/timestamp_32k.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/timestamp_32k.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/timestamp_32k.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,131 @@ +/* + * + * @Component OMAPCONF + * @Filename timestamp_32k.c + * @Description 32kHz based timestamps helper functions + * @Author Frederic Turgis (f-turgis@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +static volatile unsigned int *addr_32k = NULL; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mem_map_32k + * @BRIEF map given physical address + * @RETURNS 32K virtual address + * @DESCRIPTION map given physical address + *//*------------------------------------------------------------------------ */ +volatile unsigned int *mem_map_32k(void) +{ + unsigned int reg_32k; + + if (cpu_is_omap54xx()) + reg_32k = OMAP5430_CR; + else if (cpu_is_omap44xx()) + reg_32k = T32KSYNCNT_CR; + + return mem_map_address(reg_32k); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION mem_unmap_32k + * @BRIEF unmap given physical address + * @param[in] addr: 32K virtual address to be unmapped + * @DESCRIPTION unmap given physical address + *//*------------------------------------------------------------------------ */ +void mem_unmap_32k(volatile unsigned int *addr) +{ + mem_unmap_address((unsigned int *) addr); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION timestamp_32k_main + * @BRIEF print delta time between 32K clock to clock_gettime(), + * 32K clock to gettimeofday(). + * @RETURNS 1 + * @param[in] argc: number of argument (should be 0 or 1 max) + * @param[in] argv: arguments (argv[0] = number of loops, default 10) + * @DESCRIPTION print delta time between 32K clock to clock_gettime(), + * 32K clock to gettimeofday(). + *//*------------------------------------------------------------------------ */ +int timestamp_32k_main(int argc, char **argv) +{ + struct timespec clock_get; + struct timeval gtod; + unsigned int counter_32k; + unsigned int loop = 0; + long long int value_32k; + + addr_32k = mem_map_32k(); + + if (argc > 1) + loop = atoi(argv[1]); + if (loop == 0) + loop = 10; + + for (; loop > 0; loop--) { + clock_gettime(CLOCK_MONOTONIC, &clock_get); + gettimeofday(>od, NULL); + counter_32k = *addr_32k; + value_32k = (long long int)((double)counter_32k / 32768 * 1000000); + printf("32K to clock_gettime: %lld 32K to gettimeofday: %lld 32K: %u/%lld.%06lld clock_gettime: %u.%06u gtod: %u.%06u\n", \ + (long long int)(clock_get.tv_sec) * 1000000 + clock_get.tv_nsec / 1000 - value_32k, \ + (long long int)(gtod.tv_sec) * 1000000 + gtod.tv_usec - value_32k, + counter_32k, value_32k / 1000000, (long long int)(value_32k - value_32k / 1000000 * 1000000), \ + (unsigned int) clock_get.tv_sec, (unsigned int)(clock_get.tv_nsec / 1000), (unsigned int)gtod.tv_sec, (unsigned int)gtod.tv_usec); + } + + mem_unmap_32k(addr_32k); + + return 1; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/timestamp_32k.h tiomapconf-1.61.1/arch/arm/mach-omap/common/timestamp_32k.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/timestamp_32k.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/timestamp_32k.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,54 @@ +/* + * + * @Component OMAPCONF + * @Filename timestamp_32k.h + * @Description 32kHz based timestamps helper functions + * @Author Frederic Turgis (f-turgis@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __TIMESTAMP_32K_H__ +#define __TIMESTAMP_32K_H__ + + +volatile unsigned int *mem_map_32k(void); +void mem_unmap_32k(volatile unsigned int *addr); +int timestamp_32k_main(int argc, char **argv); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/voltdomain.c tiomapconf-1.61.1/arch/arm/mach-omap/common/voltdomain.c --- tiomapconf-1.52.0/arch/arm/mach-omap/common/voltdomain.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/voltdomain.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,374 @@ +/* + * + * @Component OMAPCONF + * @Filename voltdomain.c + * @Description Generic Voltage Domain Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include + + +/* #define VOLTDM_DEBUG */ +#ifdef VOLTDM_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_init + * @BRIEF initialize internal data + * @DESCRIPTION initialize internal data (architecture dependent) + *//*------------------------------------------------------------------------ */ +void voltdm_init(void) +{ + #ifdef VOLTDM_DEBUG + int i, count; + const genlist *voltdm_list; + voltdm_info voltdm; + #endif + + if (cpu_is_omap44xx()) { + voltdm44xx_init(); + } else if (cpu_is_omap54xx()) { + voltdm54xx_init(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } + + #ifdef VOLTDM_DEBUG + voltdm_list = voltdm_list_get(); + count = genlist_getcount((genlist *) voltdm_list); + printf("Voltage Domain List:\n"); + for (i = 0; i < count; i++) { + genlist_get((genlist *) voltdm_list, i, + (voltdm_info *) &voltdm); + printf(" %s:\n", voltdm.name); + printf(" ID:%d\n", voltdm.id); + if (voltdm.voltst == NULL) + printf(" Status Register: does not exist\n"); + else + printf(" Status Register: %s\n", + reg_name_get(voltdm.voltst)); + printf("\n\n"); + } + printf("Voltage Domain count: %d\n\n", count); + #endif +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_deinit + * @BRIEF free dynamically allocated internal data. + * @DESCRIPTION free dynamically allocated internal data. + * MUST BE CALLED AT END OF EXECUTION. + *//*------------------------------------------------------------------------ */ +void voltdm_deinit(void) +{ + if (cpu_is_omap44xx()) { + voltdm44xx_deinit(); + } else if (cpu_is_omap54xx()) { + voltdm54xx_deinit(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_list_get + * @BRIEF return the list of voltage domain(s) + * @RETURNS list of voltage domain(s) in case of success + * NULL if not available + * @DESCRIPTION return the number of voltage domain(s) + *//*------------------------------------------------------------------------ */ +const genlist *voltdm_list_get(void) +{ + if (cpu_is_omap44xx()) { + return voltdm44xx_list_get(); + } else if (cpu_is_omap54xx()) { + return voltdm54xx_list_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return NULL; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_s2id + * @BRIEF convert voltage domain provided as a string + * (as defined in voltdm.h) into a plaftorm-specific + * voltage domain ID (integer). + * @RETURNS plaftorm-specific voltage domain ID (> 0) if success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in] voltdm: voltage domain name (as defined in voltdm.h) + * @DESCRIPTION convert voltage domain provided as a string + * (as defined in voltdm.h) into a plaftorm-specific + * voltage domain ID (integer). + *//*------------------------------------------------------------------------ */ +int voltdm_s2id(const char *voltdm) +{ + CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG); + + if (cpu_is_omap44xx()) { + if (strcmp(voltdm, VDD_WKUP) == 0) + return (int) OMAP4_LDO_WKUP; + else if (strcmp(voltdm, VDD_MPU) == 0) + return (int) OMAP4_VDD_MPU; + else if (strcmp(voltdm, VDD_IVA) == 0) + return (int) OMAP4_VDD_IVA; + else if (strcmp(voltdm, VDD_CORE) == 0) + return (int) OMAP4_VDD_CORE; + else + return OMAPCONF_ERR_ARG; + } else if (cpu_is_omap54xx()) { + if (strcmp(voltdm, VDD_WKUP) == 0) + return (int) VDD54XX_WKUP; + else if (strcmp(voltdm, VDD_MPU) == 0) + return (int) VDD54XX_MPU; + else if (strcmp(voltdm, VDD_MM) == 0) + return (int) VDD54XX_MM; + else if (strcmp(voltdm, VDD_CORE) == 0) + return (int) VDD54XX_CORE; + else + return OMAPCONF_ERR_ARG; + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_count_get + * @BRIEF return the number of voltage domain(s) + * @RETURNS number of voltage domain(s) (> 0) in case of success + * OMAPCONF_ERR_CPU + * @DESCRIPTION return the number of voltage domain(s) + *//*------------------------------------------------------------------------ */ +int voltdm_count_get(void) +{ + if (cpu_is_omap44xx()) { + return voltdm44xx_count_get(); + } else if (cpu_is_omap54xx()) { + return voltdm54xx_count_get(); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_voltage_get + * @BRIEF return the current voltage supplied to a voltage domain. + * @RETURNS supplied voltage in micro-volt (> 0) in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_NOT_AVAILABLE + * OMAPCONF_ERR_INTERNAL + * @param[in] voltdm: voltage domain name (as defined in voltdm.h) + * @DESCRIPTION return the current voltage supplied to a voltage domain. + *//*------------------------------------------------------------------------ */ +int voltdm_voltage_get(const char *voltdm) +{ + int id, ret; + double volt; + + CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG); + + voltdm_init(); + + id = voltdm_s2id(voltdm); + if (id < 0) + return (double) OMAPCONF_ERR_ARG; + + if (cpu_is_omap44xx()) { + ret = voltdm44xx_get_voltage((voltdm44xx_id) id, &volt); + if (ret < 0) + return (double) ret; + else + return v2uv(volt); + } else if (cpu_is_omap54xx()) { + return v2uv(voltdm54xx_voltage_get((voltdm54xx_id) id)); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return (double) OMAPCONF_ERR_CPU; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_voltage_set + * @BRIEF set the voltage supplied to a voltage domain. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_NOT_AVAILABLE + * OMAPCONF_ERR_UNEXPECTED + * OMAPCONF_ERR_INTERNAL + * @param[in] voltdm: voltage domain name (as defined in voltdm.h) + * @param[in] uv: new voltage to be set (in micro-volt) + * @DESCRIPTION return the current voltage supplied to a voltage domain. + *//*------------------------------------------------------------------------ */ +int voltdm_voltage_set(const char *voltdm, int uv) +{ + int id; + + CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG); + + voltdm_init(); + + id = voltdm_s2id(voltdm); + if (id < 0) + return (double) OMAPCONF_ERR_ARG; + + if (cpu_is_omap44xx()) { + return sr44xx_voltage_set( + (unsigned int) id, (unsigned long) uv); + } else if (cpu_is_omap54xx()) { + return voltdm54xx_voltage_set( + (voltdm54xx_id) id, (unsigned long) uv); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_nominal_voltage_get + * @BRIEF return the nominal voltage supplied to a voltage domain. + * @RETURNS nominal voltage in micro-volt (> 0) in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in] voltdm: voltage domain name (as defined in voltdm.h) + * @DESCRIPTION return the nominal voltage supplied to a voltage domain. + * In case SmartReflex AVS Class3 is enabled, + * it may differ from the current supplied voltage. + *//*------------------------------------------------------------------------ */ +int voltdm_nominal_voltage_get(const char *voltdm) +{ + int id; + int uvolt; + + CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG); + + voltdm_init(); + + id = voltdm_s2id(voltdm); + if (id < 0) { + uvolt = OMAPCONF_ERR_ARG; + } else if (cpu_is_omap44xx()) { + uvolt = v2uv(voltdm44xx_nominal_voltage_get( + (voltdm44xx_id) id)); + } else if (cpu_is_omap54xx()) { + uvolt = v2uv(voltdm54xx_nominal_voltage_get( + (voltdm54xx_id) id)); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + uvolt = OMAPCONF_ERR_CPU; + } + + dprintf("%s(%s) = %duV\n", __func__, voltdm, uvolt); + return uvolt; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION voltdm_por_nominal_voltage_get + * @BRIEF return the nominal voltage to be supplied to a + * voltage domain, as defined in Data Manual. + * @RETURNS nominal voltage in micro-volt (> 0) in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in] voltdm: voltage domain name (as defined in voltdm.h) + * @param[in] opp: OPP provided as a string (as defined in opp.h) + * @DESCRIPTION return the nominal voltage to be supplied to a + * voltage domain, as defined in Data Manual. + * Not read from the platform, but from internal tables. + *//*------------------------------------------------------------------------ */ +int voltdm_por_nominal_voltage_get(const char *voltdm, const char *opp) +{ + int vdd_id, opp_id; + + CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG); + + voltdm_init(); + + vdd_id = voltdm_s2id(voltdm); + if (vdd_id < 0) + return OMAPCONF_ERR_ARG; + + opp_id = opp_s2id(opp); + if (opp_id < 0) + return opp_id; + + if (cpu_is_omap44xx()) { + return v2uv(voltdm44xx_por_nominal_voltage_get( + (voltdm44xx_id) vdd_id, (opp44xx_id) opp_id)); + } else if (cpu_is_omap54xx()) { + return v2uv(voltdm54xx_por_nominal_voltage_get( + (voltdm54xx_id) vdd_id, (opp54xx_id) opp_id)); + } else { + fprintf(stderr, + "omapconf: %s(): cpu not supported!!!\n", __func__); + return OMAPCONF_ERR_CPU; + } +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/common/voltdomain.h tiomapconf-1.61.1/arch/arm/mach-omap/common/voltdomain.h --- tiomapconf-1.52.0/arch/arm/mach-omap/common/voltdomain.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/common/voltdomain.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,87 @@ +/* + * + * @Component OMAPCONF + * @Filename voltdomain.h + * @Description Generic Voltage Domain Definitions & APIs + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __VOLTDOMAIN_H__ +#define __VOLTDOMAIN_H__ + + +#include +#include + + +#define VOLTDM_MAX_NAME_LENGTH 16 + +#define VDD_WKUP ((const char *) "VDD_WKUP") /* Common */ +#define VDD_MPU ((const char *) "VDD_MPU") /* Common */ +#define VDD_IVA ((const char *) "VDD_IVA") /* OMAP4 */ +#define VDD_MM ((const char *) "VDD_MM") /* OMAP5 */ +#define VDD_CORE ((const char *) "VDD_CORE") /* Common */ + + +typedef struct { + const char *name; + int id; + reg *voltst; +} voltdm_info; + + +void voltdm_init(void); +void voltdm_deinit(void); + +const genlist *voltdm_list_get(void); +int voltdm_count_get(void); + +int voltdm_s2id(const char *voltdm); + +int voltdm_count_get(void); +const genlist *voltdm_list_get(void); + +int voltdm_voltage_get(const char *voltdm); +int voltdm_voltage_set(const char *voltdm, int uv); + +int voltdm_nominal_voltage_get(const char *voltdm); +int voltdm_por_nominal_voltage_get(const char *voltdm, const char *opp); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/audit44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/audit44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/audit44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/audit44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1969 @@ +/* + * + * @Component OMAPCONF + * @Filename audit44xx.c + * @Description OMAP4 Power Audit Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define AUDIT44XX_DEBUG */ +#ifdef AUDIT44XX_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + +static const char pass[5] = "Pass"; +static const char fail[5] = "FAIL"; +static const char ignore[12] = "Ignored (1)"; +static const char warning[8] = "Warning"; + + +/* #define MODULE_AUTOIDLE_MODE_AUDIT44XX_DEBUG */ +#ifdef MODULE_AUTOIDLE_MODE_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#endif +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_autoidle_mode_audit44xx + * @BRIEF module autoidle mode audit. + * @RETURNS pointer to global pass string in case of successfull + * audit + * pointer to global fail string in case of failing audit + * pointer to global ignore string in case of unavailable + * or internal error + * @param[in] mod_id: module ID + * @param[in,out] mode: module autoidle mode (returned) + * @param[in,out] mode_por: expected module autoidle mode (returned) + * @param[in,out] err_nbr: error number (returned) + * @param[in,out] wng_nbr: warning number (returned) + * @DESCRIPTION module autoidle mode audit. + *//*------------------------------------------------------------------------ */ +char *module_autoidle_mode_audit44xx(mod44xx_id mod_id, + mod_autoidle_mode *mode, mod_autoidle_mode *mode_por, + unsigned int *err_nbr, unsigned int *wng_nbr) +{ + int ret; + char mod_name[MOD44XX_MAX_NAME_LENGTH]; + + CHECK_CPU(44xx, (char *) ignore); + CHECK_NULL_ARG(mode, (char *) ignore); + CHECK_NULL_ARG(mode_por, (char *) ignore); + CHECK_NULL_ARG(err_nbr, (char *) ignore); + CHECK_NULL_ARG(wng_nbr, (char *) ignore); + + *err_nbr = 0; + *wng_nbr = 0; + *mode = MOD_AUTOIDLE_MODE_MAX; + *mode_por = MOD_AUTOGATING; + + /* Get module autoidle mode */ + ret = mod44xx_get_autoidle_mode(mod_id, mode); + if (ret == 1) { + if (*mode != *mode_por) { + dprintf("%s(): %s AUTOIDLE mode disabled.\n", __func__, + mod44xx_get_name(mod_id, mod_name)); + (*err_nbr)++; + return (char *) fail; + } else { + dprintf("%s(): %s AUTOIDLE mode enabled.\n", __func__, + mod44xx_get_name(mod_id, mod_name)); + return (char *) pass; + } + } else if (ret == 0) { + dprintf( + "%s(): %s disabled. Module registers cannot be audited.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + return (char *) ignore; + } else if (ret == OMAPCONF_ERR_NOT_AVAILABLE) { + dprintf("%s(): %s has no AUTOIDLE bit\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + return (char *) ignore; + } else { + fprintf(stderr, + "omapconf: internal error while checking module %s AUTOIDLE bit! (%d)\n", + mod44xx_get_name(mod_id, mod_name), ret); + return (char *) ignore; + } +} +#ifdef MODULE_AUTOIDLE_MODE_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) +#endif + + +/* #define MODULE_IDLE_MODE_AUDIT44XX_DEBUG */ +#ifdef MODULE_IDLE_MODE_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#endif +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_idle_mode_audit44xx + * @BRIEF module idle mode audit. + * @RETURNS pointer to global pass string in case of successfull + * audit + * pointer to global fail string in case of failing audit + * pointer to global warning string in case of sub-optimal + * configuration + * pointer to global ignore string in case of unavailable + * or internal error + * @param[in] mod_id: module ID + * @param[in,out] mode: module idle mode (returned) + * @param[in,out] mode_por: expected module idle mode (returned) + * @param[in,out] err_nbr: error number (returned) + * @param[in,out] wng_nbr: warning number (returned) + * @DESCRIPTION module idle mode audit. + *//*------------------------------------------------------------------------ */ +char *module_idle_mode_audit44xx(mod44xx_id mod_id, + mod_idle_mode *mode, mod_idle_mode *mode_por, + unsigned int *err_nbr, unsigned int *wng_nbr) +{ + int ret; + char mod_name[MOD44XX_MAX_NAME_LENGTH]; + char *status; + + CHECK_CPU(44xx, (char *) ignore); + CHECK_NULL_ARG(mode, (char *) ignore); + CHECK_NULL_ARG(mode_por, (char *) ignore); + CHECK_NULL_ARG(err_nbr, (char *) ignore); + CHECK_NULL_ARG(wng_nbr, (char *) ignore); + + *err_nbr = 0; + *wng_nbr = 0; + *mode = MOD_IDLE_MODE_MAX; + *mode_por = MOD_SMART_IDLE; + + /* Get module IDLE mode */ + ret = mod44xx_get_idle_mode(mod_id, mode); + switch (ret) { + case 1: + break; + + case 0: + dprintf( + "%s(): %s disabled. Module registers cannot be audited.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + status = (char *) ignore; + goto module_idle_mode_audit44xx_end; + + case OMAPCONF_ERR_NOT_AVAILABLE: + dprintf("%s(): %s has no IDLE bit\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + status = (char *) ignore; + goto module_idle_mode_audit44xx_end; + + default: + fprintf(stderr, + "omapconf: internal error while checking module %s IDLE mode! (%d)\n", + mod44xx_get_name(mod_id, mod_name), ret); + status = (char *) ignore; + goto module_idle_mode_audit44xx_end; + } + + switch (*mode) { + case MOD_SMART_IDLE_WAKEUP: + dprintf( + "%s(): %s IDLE mode correctly configured to SMART-IDLE WAKEUP.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + status = (char *) pass; + goto module_idle_mode_audit44xx_end; + + case MOD_SMART_IDLE: + if (mod44xx_has_smart_idle_wakeup_mode(mod_id)) { + dprintf( + "%s(): %s IDLE mode set to SMART-IDLE instead of SMART-IDLE WAKEUP!\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + status = (char *) fail; + (*err_nbr)++; + } else { + dprintf( + "%s(): %s IDLE mode correctly configured to SMART-IDLE.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + status = (char *) pass; + } + goto module_idle_mode_audit44xx_end; + + case MOD_FORCE_IDLE: + dprintf( + "%s(): %s IDLE mode = FORCE-IDLE instead of SMART-IDLE.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + if (mod_id == OMAP4_SYNCTIMER) { + /* This module has no Smart-Idle mode */ + status = (char *) pass; + } else { + status = (char *) warning; + (*wng_nbr)++; + } + goto module_idle_mode_audit44xx_end; + + default: + if ((mod_id == OMAP4_UART1) || + (mod_id == OMAP4_UART2) || + (mod_id == OMAP4_UART3) || + (mod_id == OMAP4_UART4)) { + /* + * UART IP idle management is buggy (cf errata). + * When active, must be used in no-idle mode. + */ + status = (char *) pass; + } else { + dprintf( + "%s(): %s IDLE mode not set to SMART-IDLE but %s!\n", + __func__, mod44xx_get_name(mod_id, mod_name), + mod_idle_mode_name_get(*mode)); + status = (char *) fail; + (*err_nbr)++; + } + goto module_idle_mode_audit44xx_end; + } + +module_idle_mode_audit44xx_end: + return status; +} +#ifdef MODULE_IDLE_MODE_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) +#endif + + +/* #define MODULE_STANDBY_MODE_AUDIT44XX_DEBUG */ +#ifdef MODULE_STANDBY_MODE_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#endif +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_standby_mode_audit44xx + * @BRIEF module standby mode audit. + * @RETURNS pointer to global pass string in case of successfull + * audit + * pointer to global fail string in case of failing audit + * pointer to global warning string in case of sub-optimal + * configuration + * pointer to global ignore string in case of unavailable + * or internal error + * @param[in] mod_id: module ID + * @param[in,out] mode: module standby mode (returned) + * @param[in,out] mode_por: expected module standby mode (returned) + * @param[in,out] err_nbr: error number (returned) + * @param[in,out] wng_nbr: warning number (returned) + * @DESCRIPTION module standby mode audit. + *//*------------------------------------------------------------------------ */ +char *module_standby_mode_audit44xx(mod44xx_id mod_id, + mod_standby_mode *mode, mod_standby_mode *mode_por, + unsigned int *err_nbr, unsigned int *wng_nbr) +{ + int ret; + char mod_name[MOD44XX_MAX_NAME_LENGTH]; + + CHECK_CPU(44xx, (char *) ignore); + CHECK_NULL_ARG(mode, (char *) ignore); + CHECK_NULL_ARG(mode_por, (char *) ignore); + CHECK_NULL_ARG(err_nbr, (char *) ignore); + CHECK_NULL_ARG(wng_nbr, (char *) ignore); + + *err_nbr = 0; + *wng_nbr = 0; + *mode = MOD_STANDBY_MODE_MAX; + *mode_por = MOD_SMART_STANDBY; + + /* Get module STANDBY mode */ + ret = mod44xx_get_standby_mode(mod_id, mode); + switch (ret) { + case 1: + switch (*mode) { + case MOD_SMART_STANDBY: + dprintf( + "%s(): %s STANDBY mode correctly configured to MOD_SMART_STANDBY.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + return (char *) pass; + case MOD_FORCE_STANDBY: + (*wng_nbr)++; + dprintf( + "%s(): %s STANDBY mode = FORCE-IDLE instead of SMART-STANDBY.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + return (char *) warning; + case MOD_STANDBY_MODE_RESERVED: + if (mod_id == OMAP4_FSUSBHOST) { + dprintf( + "%s(): FSUSBHOST STANDBY mode correctly set to SMART-STANDBY WITH WAKEUP\n", + __func__); + return (char *) pass; + } else { + (*err_nbr)++; + #ifdef MODULE_STANDBY_MODE_AUDIT44XX_DEBUG + dprintf( + "%s(): %s STANDBY mode not set to SMART-STANDBY but %s!\n", + __func__, + mod44xx_get_name(mod_id, mod_name), + mod_standby_mode_name_get(*mode)); + #endif + return (char *) fail; + } + default: + (*err_nbr)++; + #ifdef MODULE_STANDBY_MODE_AUDIT44XX_DEBUG + dprintf( + "%s(): %s STANDBY mode not set to SMART-STANDBY but %s!\n", + __func__, mod44xx_get_name(mod_id, mod_name), + mod_standby_mode_name_get(*mode)); + #endif + return (char *) fail; + } + case 0: + dprintf( + "%s(): %s disabled. Module registers cannot be audited.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + return (char *) ignore; + case OMAPCONF_ERR_NOT_AVAILABLE: + dprintf("%s(): %s has no STANDBY mode\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + return (char *) ignore; + default: + fprintf(stderr, + "omapconf: internal error while checking module %s STANDBY mode! (%d)\n", + mod44xx_get_name(mod_id, mod_name), ret); + return (char *) ignore; + } +} +#ifdef MODULE_STANDBY_MODE_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) +#endif + + +/* #define MODULE_CLOCKACTIVITY_BIT_AUDIT44XX_DEBUG */ +#ifdef MODULE_CLOCKACTIVITY_BIT_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#endif +/* ------------------------------------------------------------------------*//** + * @FUNCTION module_clockactivity_bit_audit44xx + * @BRIEF module clock activity mode audit. + * @RETURNS pointer to global pass string in case of successfull + * audit + * pointer to global fail string in case of failing audit + * pointer to global warning string in case of sub-optimal + * configuration + * pointer to global ignore string in case of unavailable + * or internal error + * @param[in] mod_id: module ID + * @param[in,out] mode: module clock activity mode (returned) + * @param[in,out] mode_por: expected module clock activity mode (returned) + * @param[in,out] err_nbr: error number (returned) + * @param[in,out] wng_nbr: warning number (returned) + * @DESCRIPTION module clock activity mode audit. + *//*------------------------------------------------------------------------ */ +char *module_clockactivity_bit_audit44xx(mod44xx_id mod_id, + mod_clock_activity_mode *mode, + mod_clock_activity_mode *mode_por, + unsigned int *err_nbr, unsigned int *wng_nbr) +{ + int ret; + char mod_name[MOD44XX_MAX_NAME_LENGTH]; + + CHECK_CPU(44xx, (char *) ignore); + CHECK_NULL_ARG(mode, (char *) ignore); + CHECK_NULL_ARG(mode_por, (char *) ignore); + CHECK_NULL_ARG(err_nbr, (char *) ignore); + CHECK_NULL_ARG(wng_nbr, (char *) ignore); + + *err_nbr = 0; + *wng_nbr = 0; + *mode = MOD_CLOCK_ACTIVITY_MODE_MAX; + *mode_por = MOD_FCLK_AUTO_ICLK_AUTO; + + /* Get module CLOCKACTIVITY mode */ + ret = mod44xx_get_clock_activity_mode(mod_id, mode); + switch (ret) { + case 1: + switch (*mode) { + case MOD_FCLK_AUTO_ICLK_AUTO: + /* + * Functional clock can be switched-off; + * L4 clock can be switched-off + */ + dprintf( + "%s(): CLOCKACTIVITY bit correctly configured\n", + __func__); + return (char *) pass; + case MOD_FCLK_AUTO_ICLK_ON: + /* + * Functional clock can be switched-off; + * L4 clock is maintained during wake-up period + */ + case MOD_FCLK_ON_ICLK_AUTO: + /* + * Functional clock is maintained during wake-up period; + * L4 clock can be switched-off + */ + (*wng_nbr)++; + #ifdef MODULE_CLOCKACTIVITY_BIT_AUDIT44XX_DEBUG + dprintf("%s(): Warning: %s CLOCKACTIVITY = %s\n", + __func__, + mod44xx_get_name(mod_id, mod_name), + mod_clock_activity_mode_name_get(*mode)); + #endif + return (char *) warning; + case MOD_FCLK_ON_ICLK_ON: + /* + * Functional clock is maintained during wake-up period; + * L4 clock is maintained during wake-up period + */ + default: + (*err_nbr)++; + #ifdef MODULE_CLOCKACTIVITY_BIT_AUDIT44XX_DEBUG + dprintf("%s(): Warning: %s CLOCKACTIVITY = %s\n", + __func__, + mod44xx_get_name(mod_id, mod_name), + mod_clock_activity_mode_name_get(*mode)); + #endif + return (char *) fail; + } + case 0: + dprintf( + "%s(): %s disabled. Module registers cannot be audited.\n", + __func__, mod44xx_get_name(mod_id, mod_name)); + return (char *) ignore; + case OMAPCONF_ERR_NOT_AVAILABLE: + dprintf("%s(): %s has no CLOCKACTIVITY mode\n", __func__, + mod44xx_get_name(mod_id, mod_name)); + return (char *) ignore; + default: + fprintf(stderr, + "omapconf: internal error while checking %s CLOCKACTIVITY mode! (%d)\n", + mod44xx_get_name(mod_id, mod_name), ret); + return (char *) ignore; + } +} +#ifdef MODULE_CLOCKACTIVITY_BIT_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) +#endif + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION audit44xx_dpll + * @BRIEF audit DPLL Configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in] stream: output file (NULL: no output (silent)) + * @param[in] dpll_id: DPLL ID + * (use DPLL44XX_ID_MAX to audit all DPLLs) + * @param[in] opp_id: OPP ID + * (use OPP44XX_ID_MAX to audit all OPPs) + * @param[in] curr_opp: audit current OPP only (=1) or all OPPs (=0) + * @param[in,out] err_nbr: audit error number + * @param[in,out] wng_nbr: audit warning number + * @DESCRIPTION audit DPLL Configuration + *//*------------------------------------------------------------------------ */ +int audit44xx_dpll(FILE *stream, dpll44xx_id dpll_id, opp44xx_id opp_id, + unsigned short curr_opp, unsigned int *err_nbr, unsigned int *wng_nbr) +{ + int ret = 0; + char s[256]; + char logfilename[256]; + FILE *fp; + unsigned int row; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + char prev_gov[CPUFREQ_GOV_MAX_NAME_LENGTH] = ""; + char prev_gov2[CPUFREQ_GOV_MAX_NAME_LENGTH] = ""; + opp44xx_id opp; + double freq_mpu; + unsigned int _err_nbr = 0, _wng_nbr = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_ARG_LESS_THAN(dpll_id, DPLL44XX_ID_MAX + 1, OMAPCONF_ERR_ARG); + CHECK_ARG_LESS_THAN(opp_id, OPP44XX_ID_MAX + 1, OMAPCONF_ERR_ARG); + CHECK_ARG_LESS_THAN(curr_opp, 2, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + + *err_nbr = 0; + *wng_nbr = 0; + + /* Create audit report log file */ + strcpy(logfilename, "dpll_audit_report.txt"); + fp = workdir_fopen(logfilename, "w+"); + if (fp == NULL) { + fprintf(stderr, "Could not create %s file!\n\n", logfilename); + return 0; + } + + fprintf(fp, + "OMAPCONF DPLL Configuration Audit Detailed Log:\n\n"); + omapconf_revision_show(fp); + chips_info_show(fp, 1); + release_info_show(fp); + + if (curr_opp == 1) { + ret = dpll44xx_audit(dpll_id, opp_id, fp, err_nbr, wng_nbr); + if (ret != 0) + goto audit44xx_dpll_end; + ret = dpll44xx_audit(dpll_id, opp_id, stream, err_nbr, wng_nbr); + if (ret != 0) + goto audit44xx_dpll_end; + + if (*err_nbr == 0) + sprintf(s, "SUCCESS! DPLL Configuration audit " + "completed with 0 error (%u warning(s))" + ".\n\n", *wng_nbr); + else + sprintf(s, "FAILED! DPLL Configuration audit " + "completed with %u error(s) and %u " + "warning(s).\n\n", *err_nbr, *wng_nbr); + + if (stream != NULL) { + fprintf(stream, "Audit details saved in %s file.\n\n\n", + logfilename); + fputs(s, stream); + } + fputs(s, fp); + ret = 0; + goto audit44xx_dpll_end; + } + + /* Save current governor (will be altered by cpufreq_set() call) */ + if (cpufreq_scaling_governor_get(prev_gov) == NULL) { + ret = OMAPCONF_ERR_NOT_AVAILABLE; + goto audit44xx_dpll_end; + } + + /* Retrieve number of available MPU OPPs */ + if (cpufreq_opp_nbr_get() == 0) { + ret = OMAPCONF_ERR_NOT_AVAILABLE; + goto audit44xx_dpll_end; + } + + row = 0; + autoadjust_table_init(table); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "DPLL Configuration AUDIT Summary"); + autoadjust_table_strncpy(table, row, 1, "Audit STATUS"); + row++; + + for (opp = OMAP4_OPP50; (unsigned int) opp <= cpufreq_opp_nbr_get(); + opp++) { + _err_nbr = 0; + _wng_nbr = 0; + + /* Set MPU OPP */ + ret = mod44xx_get_por_clk_speed(OMAP4_MPU, opp, &freq_mpu); + if (ret != 0) { + err_internal_msg_show(); + goto audit44xx_dpll_end; + } + + ret = cpufreq_set((unsigned int) (freq_mpu * 1000)); + if (ret != 0) { + err_internal_msg_show(); + goto audit44xx_dpll_end; + } + + fprintf(fp, "DPLLs Configuration Audit at MPU %s:\n\n", + opp44xx_name_get(opp, OMAP4_VDD_MPU)); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "At MPU %s", + opp44xx_name_get(opp, OMAP4_VDD_MPU)); + + /* Run audit at this OPP */ + ret = dpll44xx_audit(dpll_id, OPP44XX_ID_MAX, fp, + &_err_nbr, &_wng_nbr); + if (ret != 0) { + err_internal_msg_show(); + goto audit44xx_dpll_end; + } + + if (_err_nbr == 0) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", _wng_nbr); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error, %u warning(s))", + _err_nbr, _wng_nbr); + (*err_nbr) += _err_nbr; + (*wng_nbr) += _wng_nbr; + row++; + fprintf(fp, "\n\n\n"); + } + + /* Report final audit status */ + autoadjust_table_fprint(fp, table, row, 2); + sprintf(s, "NB: DPLL IVA may not have been audited accross all " + "IVA OPPs (no kernel interface to control IVA OPP " + "available).\n\n"); + fputs(s, fp); + if (stream != NULL) { + autoadjust_table_fprint(stream, table, row, 2); + fputs(s, stream); + } + if (*err_nbr == 0) + sprintf(s, "\nSUCCESS! DPLLs Configuration " + "audit completed with 0 error (%u warning(s))" + ".\n\n\n", *wng_nbr); + else + sprintf(s, "\nFAILED! DPLLs Configuration " + "audit completed with %u error(s) and %u " + "warning(s).\n\n\n", *err_nbr, *wng_nbr); + fputs(s, fp); + if (stream != NULL) { + fprintf(stream, "DPLLs Configuration audit details saved " + "in %s file.\n", logfilename); + fputs(s, stream); + } + + +audit44xx_dpll_end: + /* Restore CPUFreq governor */ + if (strlen(prev_gov) != 0) + cpufreq_scaling_governor_set(prev_gov, prev_gov2); + /* Close opened file */ + if (fp != NULL) + fclose(fp); + return ret; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION audit44xx_dpll_main + * @BRIEF analyze command-line arguments & call DPLL audit with + * selected options. + * @RETURNS 0 on success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_INTERNAL + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in] argc: shell input argument number + * @param[in] argv: shell input argument(s) + * @DESCRIPTION analyze command-line arguments & call DPLL audit with + * selected options. + *//*------------------------------------------------------------------------ */ +int audit44xx_dpll_main(int argc, char *argv[]) +{ + int ret = 0; + dpll44xx_id dpll_id; + opp44xx_id opp_id; + unsigned int err_nbr = 0, wng_nbr = 0; + unsigned short pos_opp_id, pos_dpll_id, curr_opp; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_NULL_ARG(argv, OMAPCONF_ERR_ARG); + + /* Retrieve user options */ + dprintf("%s(): argc=%u\n", __func__, argc); + #ifdef AUDIT44XX_DEBUG + for (curr_opp = 0; curr_opp < argc; curr_opp++) { + dprintf("%s(): argv[%u]=%s\n", __func__, + curr_opp, argv[curr_opp]); + } + #endif + + if (argc == 0) { + /* Audit all DPLLs at current OPP by default */ + dpll_id = DPLL44XX_ID_MAX; + opp_id = OPP44XX_ID_MAX; + curr_opp = 1; + goto audit44xx_dpll_audit; + } else if (argc == 2) { + if (strcmp(argv[0], "-d") == 0) { + opp_id = OPP44XX_ID_MAX; + curr_opp = 1; + dpll_id = dpll44xx_s2id(argv[1]); + if (dpll_id == DPLL44XX_ID_MAX) { + if (strcmp(argv[1], "all") == 0) + dpll_id = DPLL44XX_ID_MAX; + else + goto audit44xx_dpll_err_arg; + } + goto audit44xx_dpll_audit; + } else if (strcmp(argv[0], "-o") == 0) { + dpll_id = DPLL44XX_ID_MAX; + curr_opp = 1; + opp_id = opp44xx_s2id(argv[1]); + if (opp_id == OPP44XX_ID_MAX) { + if (strcmp(argv[1], "all") == 0) { + opp_id = OPP44XX_ID_MAX; + curr_opp = 0; + } else { + goto audit44xx_dpll_err_arg; + } + } + goto audit44xx_dpll_audit; + } else { + goto audit44xx_dpll_err_arg; + } + } else if (argc == 4) { + curr_opp = 1; + if (strcmp(argv[0], "-d") == 0) + pos_dpll_id = 1; + else if (strcmp(argv[2], "-d") == 0) + pos_dpll_id = 3; + else + goto audit44xx_dpll_err_arg; + dpll_id = dpll44xx_s2id(argv[pos_dpll_id]); + if (dpll_id == DPLL44XX_ID_MAX) { + if (strcmp(argv[pos_dpll_id], "all") == 0) + dpll_id = DPLL44XX_ID_MAX; + else + goto audit44xx_dpll_err_arg; + } + + if (strcmp(argv[0], "-o") == 0) + pos_opp_id = 1; + else if (strcmp(argv[2], "-o") == 0) + pos_opp_id = 3; + else + goto audit44xx_dpll_err_arg; + opp_id = opp44xx_s2id(argv[pos_opp_id]); + if (opp_id == OPP44XX_ID_MAX) { + if (strcmp(argv[pos_opp_id], "all") == 0) { + opp_id = OPP44XX_ID_MAX; + curr_opp = 0; + } else { + goto audit44xx_dpll_err_arg; + } + } + goto audit44xx_dpll_audit; + } else { + goto audit44xx_dpll_err_arg; + } + +audit44xx_dpll_audit: + dprintf("%s(): dpll_id=%s, opp_id=%s curr_opp=%u\n", __func__, + dpll44xx_name_get(dpll_id), + opp44xx_name_get(opp_id, OMAP4_VDD_MPU), curr_opp); + + ret = audit44xx_dpll(stdout, dpll_id, opp_id, curr_opp, + &err_nbr, &wng_nbr); + + goto audit44xx_dpll_end; + +audit44xx_dpll_err_arg: + help(HELP_AUDIT); + ret = OMAPCONF_ERR_ARG; + +audit44xx_dpll_end: + return ret; +} + + +/* #define SYSCONFIG_AUDIT44XX_DEBUG */ +#ifdef SYSCONFIG_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#endif +/* ------------------------------------------------------------------------*//** + * @FUNCTION sysconfig_audit44xx + * @BRIEF OMAP4 SYSCONFIG registers audit. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in,out] stream: output file - NULL: no output (silent) + * @param[in,out] err_nbr: pointer to return audit error number + * @param[in,out] wng_nbr: pointer to return audit warning number + * @DESCRIPTION OMAP4 SYSCONFIG registers audit. + *//*------------------------------------------------------------------------ */ +int sysconfig_audit44xx(FILE *stream, unsigned int *err_nbr, + unsigned int *wng_nbr) +{ + mod44xx_id i; + mod_autoidle_mode autoidle_mode, autoidle_mode_por; + mod_idle_mode idle_mode, idle_mode_por; + mod_interface_type type; + mod_standby_mode standby_mode, standby_mode_por; + mod_clock_activity_mode clock_activity_mode, + clock_activity_mode_por; + char *status; + unsigned int err_nbr_tmp = 0, wng_nbr_tmp = 0; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row; + char mod_name[MOD44XX_MAX_NAME_LENGTH]; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + + *err_nbr = 0; + *wng_nbr = 0; + + autoadjust_table_init(table); + + row = 0; + strncpy(table[row][0], "MODULES SYSCONFIG AUDIT", TABLE_MAX_ELT_LEN); + strncpy(table[row][1], "AUTOIDLE", TABLE_MAX_ELT_LEN); + strncpy(table[row][2], "IDLE", TABLE_MAX_ELT_LEN); + strncpy(table[row][3], "STANDBY", TABLE_MAX_ELT_LEN); + strncpy(table[row][4], "CLOCKACTIVITY", TABLE_MAX_ELT_LEN); + row++; + + for (i = 0; i < OMAP4_MODULE_ID_MAX; i++) { + dprintf("\n%s(): Module #%d name = %s\n", __func__, + i, mod44xx_get_name(i, mod_name)); + + switch (i) { + case OMAP4_CRYPTODMA: + case OMAP4_AES1: + case OMAP4_AES2: + case OMAP4_SHA2MD5_1: + case OMAP4_RNG: + case OMAP4_DES3DES: + case OMAP4_PKAEIP29: + case OMAP4_USIM: + case OMAP4_WDT1: + case OMAP4_TIMER12: + case OMAP4_CUST_EFUSE: + /* + * Secure Modules, not accessible on HS, + * not referenced on GP + */ + dprintf("\tSecure Modules (not accessible (HS) / not " + "referenced (GP)\n"); + continue; + + case OMAP4_ICONT1: + case OMAP4_ICONT2: + case OMAP4_VDMA: + case OMAP4_IME3: + case OMAP4_IPE3: + case OMAP4_ILF3: + case OMAP4_MC3: + case OMAP4_CALC3: + case OMAP4_ECD3: + case OMAP4_ICONT1_SB: + case OMAP4_ICONT2_SB: + case OMAP4_ILF3_SB: + case OMAP4_IME3_SB: + case OMAP4_CALC3_SB: + case OMAP4_IPE3_SB: + case OMAP4_MC3_SB: + case OMAP4_ECD3_SB: + case OMAP4_SIMCOP: + case OMAP4_SIMCOP_DMA: + case OMAP4_SIMCOP_DCT: + case OMAP4_SIMCOP_VLCDJ: + case OMAP4_SIMCOP_ROT: + case OMAP4_MPU_M3: + /* + * These are HW accelerators IP. During AV record, + * modules are changing state quicker than omapconf + * code, causing from time to time incorrect access to + * a disabled module (i.e. bus error). + * Workaround: skip these internal HW IPs. + */ + dprintf("\tHW accelerators IP, skipped.\n"); + continue; + + case OMAP4_DISPC: + /* With clock autogating enabled, DISPC I-CLK is getting + * gated at such high pace (bursts) that there is a + * probability of bus error */ + dprintf("\tDISPC, skipped.\n"); + continue; + + case OMAP4_BB2D: + if (!cpu_is_omap4470()) + continue; + else + goto sysconfig_audit44xx_default; + + case OMAP4_FSUSBHOST: + if (cpu_is_omap4470()) + continue; + else + goto sysconfig_audit44xx_default; + +sysconfig_audit44xx_default: + default: + /* Get module interface type */ + mod44xx_get_interface_type(i, &type); + if (type == MOD_INTERFACE_NONE) { + dprintf("\tNo SYSCONFIG register to audit.\n"); + continue; + } + + /* Check if module is accessible */ + if (mod44xx_is_accessible(i) != 1) { + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "%s", mod44xx_get_name(i, mod_name)); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "NA"); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "NA"); + snprintf(table[row][3], TABLE_MAX_ELT_LEN, + "NA"); + snprintf(table[row][4], TABLE_MAX_ELT_LEN, + "NA"); + row++; + dprintf("\tModule is not accessible.\n"); + continue; + } + + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "%s", mod44xx_get_name(i, mod_name)); + /* Audit module's autoidle bit */ + status = module_autoidle_mode_audit44xx(i, + &autoidle_mode, &autoidle_mode_por, + &err_nbr_tmp, &wng_nbr_tmp); + if (status == pass) { + strncpy(table[row][1], status, + TABLE_MAX_ELT_LEN); + + } else if ((i == OMAP4_ICR_MDM) || + (i == OMAP4_ICR_MPU)) { + /* by default no C2C driver */ + status = (char *) warning; + (*wng_nbr)++; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "Warning (%s)", + mod_autoidle_mode_name_get( + autoidle_mode)); + } else if (status == fail) { + (*err_nbr)++; + strncpy(table[row][1], status, + TABLE_MAX_ELT_LEN); + } /* else do nothing in case of status == ignore */ + dprintf("\tAutoidle audit: mode=%s, status=%s\n", + mod_autoidle_mode_name_get(autoidle_mode), + status); + dprintf("\t\tTotal error number=%u, total warning " + "number=%u\n", *err_nbr, *wng_nbr); + + /* Audit module's IDLE mode */ + status = module_idle_mode_audit44xx(i, + &idle_mode, &idle_mode_por, + &err_nbr_tmp, &wng_nbr_tmp); + if (status == pass) { + strncpy(table[row][2], status, + TABLE_MAX_ELT_LEN); + } else if (status == warning) { + (*wng_nbr)++; + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "Warning (Force-Idle)"); + } else if ((i == OMAP4_TIMER1) || + (i == OMAP4_DSI1) || + (i == OMAP4_DSI2) || + (i == OMAP4_HDMI)) { + /* still configured to no-idle ... */ + status = (char *) warning; + (*wng_nbr)++; + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "Warning (%s)", + mod_idle_mode_name_get(idle_mode)); + } else if (status == fail) { + (*err_nbr)++; + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "FAIL (%s)", + mod_idle_mode_name_get(idle_mode)); + } /* else do nothing in case of status == ignore */ + dprintf("\tIdle mode audit: mode=%s, status=%s\n", + mod_idle_mode_name_get(idle_mode), status); + dprintf("\t\tTotal error number=%u, total warning " + "number=%u\n", *err_nbr, *wng_nbr); + + /* Audit module's STANDBY mode */ + status = module_standby_mode_audit44xx(i, + &standby_mode, &standby_mode_por, + &err_nbr_tmp, &wng_nbr_tmp); + if (status == pass) { + strncpy(table[row][3], status, + TABLE_MAX_ELT_LEN); + } else if (status == fail) { + (*err_nbr)++; + snprintf(table[row][3], TABLE_MAX_ELT_LEN, + "FAIL (%s)", mod_standby_mode_name_get( + standby_mode)); + } else if (status == warning) { + (*wng_nbr)++; + snprintf(table[row][3], TABLE_MAX_ELT_LEN, + "Warning (Force-standby)"); + } /* else do nothing in case of status == ignore */ + dprintf("\tStandby mode audit: mode=%s, status=%s\n", + mod_standby_mode_name_get(standby_mode), + status); + dprintf("\t\tTotal error number=%u, total warning " + "number=%u\n", *err_nbr, *wng_nbr); + + /* Audit module's CLOCKACTIVITY bit configuration */ + status = module_clockactivity_bit_audit44xx(i, + &clock_activity_mode, &clock_activity_mode_por, + &err_nbr_tmp, &wng_nbr_tmp); + if (status == pass) { + strncpy(table[row][4], status, + TABLE_MAX_ELT_LEN); + } else if (status == fail) { + (*err_nbr)++; + snprintf(table[row][4], TABLE_MAX_ELT_LEN, + "FAIL (%s)", + mod_clock_activity_mode_name_get( + clock_activity_mode)); + } else if (status == warning) { + (*wng_nbr)++; + snprintf(table[row][4], TABLE_MAX_ELT_LEN, + "Warning (%s)", + mod_clock_activity_mode_name_get( + clock_activity_mode)); + } /* else do nothing in case of status == ignore */ + dprintf("\tCLOCKACTIVITY mode audit: mode=%s, " + "status=%s\n", mod_clock_activity_mode_name_get( + clock_activity_mode), + status); + dprintf("\t\tTotal error number=%u, total warning " + "number=%u\n", *err_nbr, *wng_nbr); + row++; + } + } + + if (stream != NULL) { + autoadjust_table_fprint(stream, table, row, 5); + fprintf(stream, "NB:\n"); + fprintf(stream, " - Show 'NA' when module is disabled.\n"); + fprintf(stream, " - Show empty cell(s) when module does not " + "feature this mode.\n"); + fprintf(stream, " - AUTOIDLE MODE:\n"); + fprintf(stream, " - Report Pass if enabled, FAIL otherwise." + "\n"); + fprintf(stream, " - IDLE MODE:\n"); + fprintf(stream, " - Report Pass if set to \"Smart-Idle\" or " + "\"Smart-Idle Wakeup\" (when available).\n"); + fprintf(stream, " - Modules featuring \"Smart-Idle Wakeup" + "\" mode must be programmed in this mode. Audit will " + "report FAIL even with \"Smart-Idle\" mode.\n"); + fprintf(stream, " - Report Warning (with setting) in case of" + " \"Force-Idle\" mode.\n"); + fprintf(stream, " - Report FAIL (with incorrect setting) " + "otherwise.\n"); + fprintf(stream, " - STANDBY MODE:\n"); + fprintf(stream, " - Report Pass if set to \"Smart-Standby\" " + "or \"Smart-Standby Wakeup\" (when available).\n"); + fprintf(stream, " - Modules featuring \"Smart-Standby " + "Wakeup\" mode must be programmed in this mode. Audit " + "will report FAIL even with \"Smart-Standby\" mode.\n"); + fprintf(stream, " - Report Warning (with setting) in case of" + " \"Force-Standby\" mode.\n"); + fprintf(stream, " - Report FAIL (with incorrect setting) " + "otherwise.\n"); + fprintf(stream, " - CLOCKACTIVITY MODE:\n"); + fprintf(stream, " - Report Pass if both I-CLK and F-CLK are " + "set to AUTO mode.\n"); + fprintf(stream, " - Report Warning if one of I-CLK or F-CLK " + "is set to ON mode.\n"); + fprintf(stream, " - Report FAIL (with incorrect setting) " + "otherwise.\n\n"); + + if (*err_nbr == 0) { + fprintf(stream, "SUCCESS! Modules SYSCONFIG registers " + "audit completed with 0 error " + "(%d warning(s))\n\n", + *wng_nbr); + } else { + fprintf(stream, "FAILED! Modules SYSCONFIG registers " + "audit completed with %d error and " + "%d warning.\n\n", + *err_nbr, *wng_nbr); + } + } + + return 0; +} +#ifdef SYSCONFIG_AUDIT44XX_DEBUG +#undef dprintf +#define dprintf(format, ...) +#endif + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION clkspeed_audit44xx + * @BRIEF OMAP4 Clock Speed audit. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in,out] stream: output file - NULL: no output (silent) + * @param[in,out] err_nbr: pointer to return audit error number + * @param[in,out] wng_nbr: pointer to return audit warning number + * @DESCRIPTION OMAP4 Clock Speed audit. + *//*------------------------------------------------------------------------ */ +int clkspeed_audit44xx(FILE *stream, unsigned int *err_nbr, + unsigned int *wng_nbr) +{ + mod44xx_id module_id; + voltdm44xx_id volt_dom_id; + clock44xx_id src_clk_id; + int ret; + opp44xx_id current_opp; + mod_module_mode mmode; + double speed_curr = 0.0, speed_por = 0.0, speed_opp50_por = 0.0; + const char pass[10] = "pass"; + const char fail[10] = "FAIL"; + const char warning1[10] = "warn. (1)"; + const char warning2[10] = "warn. (2)"; + const char warning3[10] = "warn. (3)"; + const char ignore4[10] = "ign. (4)"; + char *status; + char s_curr[12], s_por[12], s_src[CLOCK44XX_MAX_NAME_LENGTH]; + char mod_name[MOD44XX_MAX_NAME_LENGTH]; + char src_clk_name[CLOCK44XX_MAX_NAME_LENGTH]; + char s_opp[OPP44XX_MAX_NAME_LENGTH] = "ERR"; + char prev_gov[16], prev_gov2[16]; + + if (!cpu_is_omap44xx()) + return OMAPCONF_ERR_CPU; + if ((err_nbr == NULL) || (wng_nbr == NULL)) + return OMAPCONF_ERR_ARG; + + *err_nbr = 0; + *wng_nbr = 0; + + /* Switch to userspace governor temporarily, + * so that OPP cannot change during audit and does not false it. + */ + cpufreq_scaling_governor_set("userspace", prev_gov); + + if (stream != NULL) { + fprintf(stream, + "|-----------------------------------------------------" + "--------------------------------------------------" + "|\n"); + fprintf(stream, "| %-20s | %-21s | %-12s | %-27s | %-9s |\n", + " CLOCK SPEED AUDIT", "", "", " Clock Rate (MHz)", + ""); + fprintf(stream, + "| %-20s | %-21s | %-12s | %-12s | %-12s | %-9s |\n", + "Module", "Source Clock", "OPP", "Current", "Expected", + "STATUS"); + fprintf(stream, + "|-----------------------------------------------------" + "--------------------------------------------------" + "|\n"); + } + for (module_id = 0; module_id < OMAP4_MODULE_ID_MAX; module_id++) { + dprintf("%s():Auditing module %s\n", __func__, + mod44xx_get_name(module_id, mod_name)); + /* Filter module ID */ + switch (module_id) { + case OMAP4_RFBI: + dprintf("%s(): RFBI FCLK not generated by PRCM.\n", + __func__); + /* RFBI functional clock not generated by PRCM */ + break; + + case OMAP4_MCSPI1_HL: + case OMAP4_MCSPI2_HL: + case OMAP4_MCSPI3_HL: + case OMAP4_MCSPI4_HL: + case OMAP4_MMC1_HL: + case OMAP4_MMC2_HL: + case OMAP4_MMC3_HL: + case OMAP4_MMC4_HL: + case OMAP4_MMC5_HL: + /* Duplicates of OMAP4_xyz, skip it */ + dprintf("%s(): duplicate of OMAP4_xyz, skip it.\n", + __func__); + break; + + case OMAP4_MMU_DSP: + case OMAP4_DSP_WUGEN: + case OMAP4_ICONT1: + case OMAP4_ICONT2: + case OMAP4_VDMA: + case OMAP4_IME3: + case OMAP4_IPE3: + case OMAP4_ILF3: + case OMAP4_MC3: + case OMAP4_CALC3: + case OMAP4_ECD3: + case OMAP4_ICONT1_SB: + case OMAP4_ICONT2_SB: + case OMAP4_ILF3_SB: + case OMAP4_IME3_SB: + case OMAP4_CALC3_SB: + case OMAP4_IPE3_SB: + case OMAP4_MC3_SB: + case OMAP4_ECD3_SB: + case OMAP4_SL2: + case OMAP4_P1500: + case OMAP4_MMU_MPU_M3: + /* + * Part of IVA_HD subsystem + * all clocked by same OMAP4_IVAHD_ROOT_CLK clock + */ + dprintf("%s(): part of IVA_HD SS, skip it.\n", + __func__); + break; + + case OMAP4_CCP2: + case OMAP4_CSI2_A: + case OMAP4_CSI2_B: + case OMAP4_TCTRL: + case OMAP4_BTE: + case OMAP4_CBUFF: + case OMAP4_ISP5: + case OMAP4_RSZ: + case OMAP4_SIMCOP: + case OMAP4_SIMCOP_DMA: + case OMAP4_SIMCOP_DCT: + case OMAP4_SIMCOP_VLCDJ: + case OMAP4_SIMCOP_ROT: + /* + * Part of CAM subsystem + * all clocked by same OMAP4_ISS_CLK clock + */ + dprintf("%s(): part of CAM SS, skip it.\n", + __func__); + break; + + case OMAP4_CRYPTODMA: + case OMAP4_AES1: + case OMAP4_AES2: + case OMAP4_SHA2MD5_1: + case OMAP4_RNG: + case OMAP4_DES3DES: + case OMAP4_PKAEIP29: + case OMAP4_USIM: + case OMAP4_WDT1: + case OMAP4_TIMER12: + case OMAP4_CUST_EFUSE: + /* + * Secure Modules, not accessible on HS, + * not referenced on GP + */ + dprintf("%s(): secure module, skip it.\n", + __func__); + break; + + case OMAP4_UNIPRO1: + /* Only present in OMAP4430ES1.0, skip it otherwise */ + if ((cpu_is_omap4430() && + (cpu_revision_get() != REV_ES1_0)) + || cpu_is_omap4460() || cpu_is_omap4470()) + break; + + case OMAP4_DDRPHY: + case OMAP4_DLL: + /* Internal. + * No need to show it, tend to confuse people. + * Showing EMIF speed is sufficient. + */ + dprintf("%s(): internal, skip it.\n", + __func__); + break; + + case OMAP4_FSUSBHOST: + if (cpu_is_omap4470()) + break; + else + goto clkspeed_audit44xx_default; + + case OMAP4_BB2D: + if (!cpu_is_omap4470()) + break; + else + goto clkspeed_audit44xx_default; + +clkspeed_audit44xx_default: + default: + /* init variables */ + status = (char *) ignore4; + speed_curr = -1.0; + snprintf(s_curr, 12, "%s", "NOT FOUND"); + snprintf(s_src, 21, "%s", "NOT FOUND"); + strcpy(s_opp, "NOT FOUND"); + speed_por = -2.0; + speed_opp50_por = -2.0; + snprintf(s_por, 12, "%s", "NA"); + + volt_dom_id = mod44xx_get_voltdm(module_id); + ret = mod44xx_get_clk_speed(module_id, + &src_clk_id, + ¤t_opp, + &speed_curr); + + if (src_clk_id != OMAP4_CLOCK_ID_MAX) { + snprintf(s_src, CLOCK44XX_MAX_NAME_LENGTH, "%s", + clk44xx_get_name(src_clk_id, + src_clk_name)); + } else { + dprintf("%s(): src_clk not found!\n", __func__); + status = (char *) warning1; + (*wng_nbr)++; + goto clkspeed_audit44xx_show; + } + if (speed_curr >= 0) { + mhz2string(speed_curr, s_curr); + } else { + dprintf("%s(): speed not found!\n", __func__); + status = (char *) warning1; + (*wng_nbr)++; + goto clkspeed_audit44xx_show; + } + if (current_opp != OPP44XX_ID_MAX) { + voltdm44xx_opp2string(s_opp, + current_opp, volt_dom_id); + } else { + dprintf("%s(): opp not found!\n", __func__); + status = (char *) warning2; + (*wng_nbr)++; + goto clkspeed_audit44xx_show; + } + if (ret != 0) { + dprintf("%s(): src_clk/speed/opp not found!\n", + __func__); + status = (char *) warning1; + (*wng_nbr)++; + goto clkspeed_audit44xx_show; + } + /* Keep only 3 decimals for comparison */ + speed_curr = (int)(speed_curr * 1000.0) / + 1000.0; + dprintf("%s(): speed=%.3lfMHz\n", __func__, speed_curr); + + /* + * Get Plan Of Record (POR) module's functional + * source clock speed + */ + ret = mod44xx_get_por_clk_speed(module_id, + current_opp, &speed_por); + mod44xx_get_mode(module_id, &mmode); + if ((ret == 0) && (speed_por != -1.0)) { + mhz2string(speed_por, s_por); + /* + * Keep only 3 decimals for comparison + */ + speed_por = (int)(speed_por * 1000.0) / + 1000.0; + dprintf("%s(): PoR speed=%.3lfMHz\n", + __func__, speed_por); + + if (speed_curr == speed_por) { + status = (char *) pass; + dprintf("%s(): pass!\n", + __func__); + } else if (((module_id == OMAP4_AESS) || + (module_id == OMAP4_DMIC) || + (module_id == OMAP4_L4_ABE)) && + (current_opp == OMAP4_OPP100)) { + /* + * From ICS pastry, + * ABE is not always following + * IVAHD OPP. i.e. it's possible + * that VDD_IVA=OPP100 but ABE + * stays at OPP50 clock rates. + */ + mod44xx_get_por_clk_speed( + module_id, OMAP4_OPP50, + &speed_opp50_por); + if (speed_curr == + speed_opp50_por) { + status = (char *) pass; + mhz2string( + speed_opp50_por, + s_por); + dprintf("%s(): pass!\n", + __func__); + } else { + dprintf("%s(): FAILED!" + "\n", __func__); + status = (char *) fail; + (*err_nbr)++; + } + } else if (mmode == MOD_DISABLED_MODE) { + /* + * may not be a true failure + * when module is disabled + * (not configured). Does not + * impact power. + */ + dprintf("%s(): disabled " + "module.\n", + __func__); + status = (char *) warning3; + (*wng_nbr)++; + } else { + dprintf("%s(): FAILED!\n", + __func__); + status = (char *) fail; + (*err_nbr)++; + } + } else { + dprintf("%s(): warning POR speed " + "not found!\n", __func__); + status = (char *) warning1; + (*wng_nbr)++; + } + +clkspeed_audit44xx_show: + if (stream != NULL) + fprintf(stream, + "| %-20s | %-21s | %-12s | %-12s " + "| %-12s | %-9s |\n", + mod44xx_get_name(module_id, mod_name), + s_src, s_opp, s_curr, s_por, status); + } + } + if (stream != NULL) { + fprintf(stream, + "|-----------------------------------------------------" + "--------------------------------------------------" + "|\n\n"); + + fprintf(stream, "NB:\n"); + fprintf(stream, " (1) Internal error (data not found).\n"); + fprintf(stream, " (2) OPP not found, could not audit module " + "rate.\n"); + fprintf(stream, " (3) Clock rate does no match target rate, " + "but module is disabled (no power impact).\n"); + fprintf(stream, " (4) No target clock rate available " + "(module not used on TI reference platform).\n\n"); + + if (*err_nbr == 0) + fprintf(stream, "SUCCESS! Clock Speed audit " + "completed with 0 error (%d warning(s))\n\n", + *wng_nbr); + else + fprintf(stream, "FAILED! Clock Speed audit " + "completed with %d error and %d warning.\n\n", + *err_nbr, *wng_nbr); + } + + /* Restore CPUFreq governor */ + cpufreq_scaling_governor_set(prev_gov, prev_gov2); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION audit44xx_sr_avs + * @BRIEF audit Smart-Reflex AVS Configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * @param[in] stream: output file (NULL: no output (silent)) + * @param[in] sr_id: SR module ID + * (use OMAP4_SR_ID_MAX to audit all modules) + * @param[in] curr_opp: audit current OPP only (=1) or all OPPs (=0) + * @param[in,out] err_nbr: audit error number + * @param[in,out] wng_nbr: audit warning number + * @DESCRIPTION audit Smart-Reflex AVS Configuration (SR + VP modules) + *//*------------------------------------------------------------------------ */ +int audit44xx_sr_avs(FILE *stream, omap4_sr_module_id sr_id, + unsigned short curr_opp, unsigned int *err_nbr, unsigned int *wng_nbr) +{ + unsigned int vp_err_nbr = 0, vp_wng_nbr = 0; + unsigned int sr_err_nbr = 0, sr_wng_nbr = 0; + opp44xx_id opp; + double freq_mpu; + int ret; + unsigned int row; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + char prev_gov[CPUFREQ_GOV_MAX_NAME_LENGTH]; + char prev_gov2[CPUFREQ_GOV_MAX_NAME_LENGTH]; + char opp_name[OPP44XX_MAX_NAME_LENGTH]; + char *workdir; + char s[256]; + FILE *fp; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + + + if (cpu_is_omap4470()) { + (*wng_nbr) += 1; + if (stream != NULL) + fprintf(stream, "SR AVS Golden settings not yet " + "available, audit cannot be run.\n\n"); + return 0; + } + + /* Create audit report log file */ + workdir = workdir_get(); + if (workdir != NULL) { + strcpy(s, workdir); + strcat(s, "sr_avs_audit_report.txt"); + } else { + return 0; + } + fp = fopen(s, "w+"); + if (fp == NULL) { + fprintf(stderr, "Could not create %s file!\n\n", s); + return 0; + } + fprintf(fp, + "OMAPCONF SR AVS Configuration Audit Detailed Log:\n\n"); + omapconf_revision_show(fp); + chips_info_show(fp, 1); + release_info_show(fp); + + if (curr_opp == 1) { + ret = sr44xx_audit(fp, sr_id, &sr_err_nbr, &sr_wng_nbr); + if (ret != 0) { + fclose(fp); + return ret; + } + (*err_nbr) += sr_err_nbr; + (*wng_nbr) += sr_wng_nbr; + + ret = vp44xx_config_audit(fp, (vp44xx_mod_id) sr_id, + &vp_err_nbr, &vp_wng_nbr); + if (ret != 0) { + fclose(fp); + return ret; + } + (*err_nbr) += vp_err_nbr; + (*wng_nbr) += vp_wng_nbr; + + rewind(fp); + while ((fgets(s, 256, fp) != NULL) && (s[0] != '|')); + fputs(s, stream); + if (stream != NULL) { + while (fgets(s, 256, fp) != NULL) + fputs(s, stream); + fprintf(stream, + "Audit details saved in %s file.\n", + "sr_avs_audit_report.txt"); + if (*err_nbr == 0) + fprintf(stream, + "\nSUCCESS! SR AVS Configuration audit " + "completed with 0 error (%u warning(s))" + ".\n\n", *wng_nbr); + else + fprintf(stream, + "\nFAILED! SR AVS Configuration audit " + "completed with %u error(s) and %u " + "warning(s).\n\n", *err_nbr, *wng_nbr); + } + + if (*err_nbr == 0) + fprintf(fp, + "\nSUCCESS! SR AVS Configuration audit " + "completed with 0 error (%u warning(s))" + ".\n\n", *wng_nbr); + else + fprintf(fp, + "\nFAILED! SR AVS Configuration audit " + "completed with %u error(s) and %u warning(s)" + ".\n\n", *err_nbr, *wng_nbr); + fclose(fp); + ret = 0; + goto audit44xx_sr_avs_end; + } + + + row = 0; + autoadjust_table_init(table); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "SR AVS Configuration AUDIT Summary"); + autoadjust_table_strncpy(table, row, 1, "SR Audit STATUS"); + autoadjust_table_strncpy(table, row, 2, "VP Audit STATUS"); + row++; + + /* Save current governor (will be altered by cpufreq_set() call */ + cpufreq_scaling_governor_get(prev_gov); + + for (opp = OMAP4_OPP50; (unsigned int) opp <= cpufreq_opp_nbr_get(); + opp++) { + sr_err_nbr = 0; + sr_wng_nbr = 0; + vp_err_nbr = 0; + vp_wng_nbr = 0; + + /* Set MPU OPP */ + ret = mod44xx_get_por_clk_speed(OMAP4_MPU, opp, &freq_mpu); + if (ret != 0) { + fclose(fp); + goto audit44xx_sr_avs_end; + } + ret = cpufreq_set((unsigned int) (freq_mpu * 1000)); + if (ret != 0) { + fclose(fp); + goto audit44xx_sr_avs_end; + } + voltdm44xx_opp2string(opp_name, opp, OMAP4_VDD_MPU); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "At MPU %s", + opp_name); + fprintf(fp, "SR AVS Configuration Audit at MPU %s:\n\n", + opp_name); + + /* Run audit at this OPP */ + ret = sr44xx_audit(fp, sr_id, &sr_err_nbr, + &sr_wng_nbr); + if (ret != 0) { + fclose(fp); + goto audit44xx_sr_avs_end; + } + if (sr_err_nbr == 0) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", sr_wng_nbr); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error, %u warning(s))", + sr_err_nbr, sr_wng_nbr); + (*err_nbr) += sr_err_nbr; + (*wng_nbr) += sr_wng_nbr; + + ret = vp44xx_config_audit(fp, (vp44xx_mod_id) sr_id, + &vp_err_nbr, &vp_wng_nbr); + if (ret != 0) { + fclose(fp); + goto audit44xx_sr_avs_end; + } + if (vp_err_nbr == 0) + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", vp_wng_nbr); + else + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "FAIL (%u error, %u warning(s))", + vp_err_nbr, vp_wng_nbr); + row++; + (*err_nbr) += vp_err_nbr; + (*wng_nbr) += vp_wng_nbr; + fprintf(fp, "\n\n\n"); + } + + /* Report final audit status */ + autoadjust_table_fprint(fp, table, row, 3); + fprintf(fp, "NB: SR IVA may not have been audited accross all " + "IVA OPPs (no kernel interface to control IVA OPP " + "available).\n\n"); + if (stream != NULL) { + autoadjust_table_fprint(stream, table, row, 3); + fprintf(stream, "NB: SR IVA may not have been audited accross " + "all IVA OPPs (no kernel interface to control IVA OPP " + "available).\n\n"); + } + if (*err_nbr == 0) + fprintf(fp, "\nSUCCESS! Full SR AVS Configuration " + "audit completed with 0 error (%u warning(s))" + ".\n\n", *wng_nbr); + else + fprintf(fp, "\nFAILED! Full SR AVS Configuration " + "audit completed with %u error(s) and %u " + "warning(s).\n\n", *err_nbr, *wng_nbr); + fclose(fp); + + if (stream != NULL) { + fprintf(stream, "Audit details saved in %s file.\n", s); + if (*err_nbr == 0) + fprintf(stream, "\nSUCCESS! Full SR AVS Configuration " + "audit completed with 0 error (%u warning(s))" + ".\n\n", *wng_nbr); + else + fprintf(stream, "\nFAILED! Full SR AVS Configuration " + "audit completed with %u error(s) and %u " + "warning(s).\n\n", *err_nbr, *wng_nbr); + } + + +audit44xx_sr_avs_end: + /* Restore CPUFreq governor */ + cpufreq_scaling_governor_set(prev_gov, prev_gov2); + return ret; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION full_audit44xx + * @BRIEF full OMAP4 power configuration audit + * (dplls, sysconfig, clkspeed, statdep, avs, pads). + * @RETURNS 0 in case of success + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @DESCRIPTION full OMAP4 power configuration audit + * (dplls, sysconfig, clkspeed, statdep, avs, pads). + *//*------------------------------------------------------------------------ */ +int full_audit44xx(void) +{ + unsigned int dplls_err_nbr = 0, dplls_wng_nbr = 0; + unsigned int syscfg_err_nbr = 0, syscfg_wng_nbr = 0; + unsigned int clkspeed_err_nbr = 0, clkspeed_wng_nbr = 0; + unsigned int statdep_err_nbr = 0, statdep_wng_nbr = 0; + unsigned int avs_err_nbr = 0, avs_wng_nbr = 0; + int pad_violation_count; + unsigned int err_nbr = 0, wng_nbr = 0; + unsigned int row = 0; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + char *workdir; + char s[256]; + FILE *fp; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + /* Create audit report log file */ + workdir = workdir_get(); + if (workdir != NULL) { + strcpy(s, workdir); + strcat(s, "full_audit_report.txt"); + } else { + return 0; + } + fp = fopen(s, "w+"); + if (fp == NULL) { + fprintf(stderr, "Could not create %s file!\n\n", s); + return 0; + } + fprintf(fp, + "OMAPCONF Full Power Configuration Audit Detailed Log:\n\n"); + omapconf_revision_show(fp); + chips_info_show(fp, 1); + release_info_show(fp); + + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "Full Power Configuration AUDIT Summary"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "STATUS"); + row++; + + audit44xx_dpll(fp, DPLL44XX_ID_MAX, OPP44XX_ID_MAX, + 0, &dplls_err_nbr, &dplls_wng_nbr); + fputs("\n\n\n", fp); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "DPLLs Configuration Audit"); + if (dplls_err_nbr == 0) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", dplls_wng_nbr); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error(s), %u warning(s))", + dplls_err_nbr, dplls_wng_nbr); + row++; + err_nbr += dplls_err_nbr; + wng_nbr += dplls_wng_nbr; + + sysconfig_audit44xx(fp, + &syscfg_err_nbr, &syscfg_wng_nbr); + fputs("\n\n\n", fp); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "SYSCONFIG IP Registers Audit"); + if (syscfg_err_nbr == 0) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", syscfg_wng_nbr); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error(s), %u warning(s))", + syscfg_err_nbr, syscfg_wng_nbr); + row++; + err_nbr += syscfg_err_nbr; + wng_nbr += syscfg_wng_nbr; + + clkspeed_audit44xx(fp, + &clkspeed_err_nbr, &clkspeed_wng_nbr); + fputs("\n\n\n", fp); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "Clock Speed Audit"); + if (clkspeed_err_nbr == 0) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", clkspeed_wng_nbr); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error(s), %u warning(s))", + clkspeed_err_nbr, clkspeed_wng_nbr); + row++; + err_nbr += clkspeed_err_nbr; + wng_nbr += clkspeed_wng_nbr; + + statdep44xx_audit(fp, + &statdep_err_nbr, &statdep_wng_nbr); + fputs("\n\n\n", fp); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "Static Dependencies Audit"); + if (statdep_err_nbr == 0) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", statdep_wng_nbr); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error(s), %u warning(s))", + statdep_err_nbr, statdep_wng_nbr); + row++; + err_nbr += statdep_err_nbr; + wng_nbr += statdep_wng_nbr; + + audit44xx_sr_avs(fp, OMAP4_SR_ID_MAX, 0, + &avs_err_nbr, &avs_wng_nbr); + fputs("\n\n\n", fp); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "SR AVS Audit"); + if (avs_err_nbr == 0) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, %u warning(s))", avs_wng_nbr); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error(s), %u warning(s))", + avs_err_nbr, avs_wng_nbr); + row++; + err_nbr += avs_err_nbr; + wng_nbr += avs_wng_nbr; + + pad_violation_count = pads44xx_audit(fp); + fputs("\n\n\n", fp); + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "IO PAD Audit"); + if (pad_violation_count < 0) { + wng_nbr++; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "ABORTED (0 error, 1 warning(s))"); + } else if (pad_violation_count == 0) { + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "PASS (0 error, 0 warning(s))"); + } else { + err_nbr++; + snprintf(table[row][1], TABLE_MAX_ELT_LEN, + "FAIL (%u error(s), 0 warning(s))", + pad_violation_count); + } + row++; + + autoadjust_table_fprint(stdout, table, row, 2); + autoadjust_table_fprint(fp, table, row, 2); + printf("Audit details saved in %s file.\n\n\n", s); + if (err_nbr == 0) { + sprintf(s, "SUCCESS! Full Power Configuration Audit " + "completed with 0 error (%u warning(s))\n\n", wng_nbr); + } else { + sprintf(s, "FAILED! Full Power Configuration Audit " + "completed with %u error(s) and %u warning(s).\n\n", + err_nbr, wng_nbr); + } + fputs(s, stdout); + fputs(s, fp); + + fclose(fp); + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION audit44xx_main + * @BRIEF OMAP4 audit menu + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in] argc: shell input argument number + * @param[in] argv: shell input argument(s) + * @DESCRIPTION OMAP4 audit menu + *//*------------------------------------------------------------------------ */ +int audit44xx_main(int argc, char *argv[]) +{ + unsigned int err_nbr = 0, wng_nbr = 0; + int ret; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (argc == 1) { + help(HELP_AUDIT); + ret = 0; + } else if (strcmp(argv[1], "dpll") == 0) { + ret = audit44xx_dpll_main(argc - 2, argv + 2); + } else if (strcmp(argv[1], "perf") == 0) { + ret = audit_performances_main(argc - 2, argv + 2); + } else if (argc == 2) { + if (strcmp(argv[1], "full") == 0) { + ret = full_audit44xx(); + } else if (strcmp(argv[1], "sysconfig") == 0) { + ret = sysconfig_audit44xx(stdout, + &err_nbr, &wng_nbr); + } else if (strcmp(argv[1], "clkspeed") == 0) { + ret = clkspeed_audit44xx(stdout, + &err_nbr, &wng_nbr); + } else if (strcmp(argv[1], "statdep") == 0) { + ret = statdep44xx_audit(stdout, + &err_nbr, &wng_nbr); + } else if (strcmp(argv[1], "avs") == 0) { + ret = audit44xx_sr_avs(stdout, OMAP4_SR_ID_MAX, 1, + &err_nbr, &wng_nbr); + } else if (strcmp(argv[1], "pads") == 0) { + ret = pads44xx_audit(stdout); + } else { + ret = uc_audit44xx_main(argc, argv); + } + } else if ((argc == 3) && + (strcmp(argv[1], "avs") == 0)) { + if (strcmp(argv[2], "mpu") == 0) { + ret = audit44xx_sr_avs(stdout, OMAP4_SR_MPU, 1, + &err_nbr, &wng_nbr); + } else if (strcmp(argv[2], "iva") == 0) { + ret = audit44xx_sr_avs(stdout, OMAP4_SR_IVA, 1, + &err_nbr, &wng_nbr); + } else if (strcmp(argv[2], "core") == 0) { + ret = audit44xx_sr_avs(stdout, OMAP4_SR_CORE, 1, + &err_nbr, &wng_nbr); + } else if (strcmp(argv[2], "full") == 0) { + ret = audit44xx_sr_avs(stdout, OMAP4_SR_ID_MAX, 0, + &err_nbr, &wng_nbr); + } else { + help(HELP_AUDIT); + ret = 0; + } + } else if ((argc == 3) && + (strcmp(argv[2], "full_log") == 0)) { + ret = uc_audit44xx_main(argc, argv); + } else { + help(HELP_AUDIT); + ret = 0; + } + + return ret; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/audit44xx.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/audit44xx.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/audit44xx.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/audit44xx.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,67 @@ +/* + * + * @Component OMAPCONF + * @Filename audit44xx.h + * @Description OMAP4 Power Audit Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __AUDIT44XX_H__ +#define __AUDIT44XX_H__ + + +#include +#include +#include +#include + + +int audit44xx_main(int argc, char *argv[]); +int clkspeed_audit44xx(FILE *stream, unsigned int *err_nbr, + unsigned int *wng_nbr); +int sysconfig_audit44xx(FILE *stream, unsigned int *err_nbr, + unsigned int *wng_nbr); +int audit44xx_sr_avs(FILE *stream, omap4_sr_module_id sr_id, + unsigned short curr_opp, unsigned int *err_nbr, unsigned int *wng_nbr); +int audit44xx_dpll_main(int argc, char *argv[]); +int audit44xx_dpll(FILE *stream, dpll44xx_id dpll_id, opp44xx_id opp_id, + unsigned short curr_opp, unsigned int *err_nbr, unsigned int *wng_nbr); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/counters44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/counters44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/counters44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/counters44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1091 @@ +/* + * + * @Component OMAPCONF + * @Filename counters44xx.c + * @Description Collect data from PL310 L2 Cache Counters + * @Author Steve Korson (s-korson@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define OMAP4CONF_COUNTERS_DEBUG */ +#ifdef OMAP4CONF_COUNTERS_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +#define PERF_TRACE_SAMPLING_RATE_MS 100 /* ms */ + + +typedef struct { + unsigned int count; + double total; /* in microseconds */ + double min; /* in microseconds */ + double max; /* in microseconds */ + double avg; /* in microseconds */ +} time_stats; + + +static char file_prefix[64] = "omap_performance_"; +static char trace_perf_file[64] = "trace.dat"; +static char trace_perf_stats_file[64] = "stats.txt"; + +int sampling_rate = PERF_TRACE_SAMPLING_RATE_MS; + +/* +// skorson +// Assigning a default like this is not preferable, but doing so +// makes it backward compatible for the trace perf option +// Leave signed, set -1 to represent disabled or unused. +// The state can contain any positive value to indicate enabled and the value. +*/ +static int trace_state[TRACE_CFG_TABLE_MAX] = { + 1, /* TRACE_CFG_TIMER_32K_SYNC - Default to enable timestamp */ + -1, /* TRACE_CFG_L2CC_CNT0_FILTER, */ + -1, /* TRACE_CFG_L2CC_CNT1_FILTER, */ + -1, /* TRACE_CFG_EMIF0_CNT0_FILTER, */ + -1, /* TRACE_CFG_EMIF1_CNT0_FILTER, */ + EMIF44XX_PERF_CNT_FILTER_DATA_TRANSFER_CYCLES, /*TRACE_CFG_EMIF0_CNT1_FILTER, */ + EMIF44XX_PERF_CNT_FILTER_DATA_TRANSFER_CYCLES, /*TRACE_CFG_EMIF1_CNT1_FILTER, */ + -1, /* TRACE_CFG_EMIF0_MCLK_CYCLES, */ + -1, /* TRACE_CFG_EMIF1_MCLK_CYCLES, */ + -1, /* TRACE_CFG_ENABLED_OPTIONS_MAX, */ +/* Options that don't require data storage (i.e. options for env. or */ +/* other control of a traced option.) beyond this point. */ + -1, /* TRACE_CFG_EMIF0_CNT0_ID, */ + -1, /* TRACE_CFG_EMIF1_CNT0_ID, */ + -1, /* TRACE_CFG_EMIF0_CNT1_ID, */ + -1, /* TRACE_CFG_EMIF1_CNT1_ID, */ + -1, /* TRACE_CFG_EMIF0_CNT0_ADDRSPACE, */ + -1, /* TRACE_CFG_EMIF1_CNT0_ADDRSPACE, */ + -1, /* TRACE_CFG_EMIF0_CNT1_ADDRSPACE, */ + -1, /* TRACE_CFG_EMIF1_CNT1_ADDRSPACE, */ + -1, /* TRACE_CFG_SAMPLE_INTERVAL // State option unused */ + -1, /* TRACE_CFG_NORMALIZE // State option unused */ + -1, /* TRACE_CFG_FILE_PREFIX // State option unused */ + -1 /* TRACE_CFG_LONG_HEADER // State option used in if clause before printing */ + }; + + +static unsigned int capture_time = 10; +char defaults_file[64] = ".omapconf_defaults"; + + + +#ifdef OMAP4CONF_COUNTERS_DEBUG +#undef dprintf +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#endif +/** + * Function: counters44xx_perf + * Role: trace OMAP performance (CPU Load, OPP & memory bandwidth usage). + * Parameters: + * capture_time: capture (trace) duration + * Return: + * 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_NOT_AVAILABLE + * OMAPCONF_ERR_UNEXPECTED + */ +int counters44xx_count(unsigned int capture_time) +{ + + unsigned int i; + unsigned int sample_cnt; + int ret; + unsigned int addr, data, l2_disabled_prior = 0; + unsigned int *trace_buf[TRACE_CFG_ENABLED_OPTIONS_MAX]; + unsigned short emif; + unsigned int sample; + FILE *fp = NULL; + char s[16]; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row = 0; + char name[64]; + char tmp_name[64]; + char option[64]; + unsigned int temp, avg, min, max; + + + /* Configure EMIF counters */ + ret = 0; + if (trace_state[TRACE_CFG_EMIF0_CNT0_FILTER] >= 0) + ret = emif44xx_perf_cnt_configure(EMIF44XX_0, 0, + trace_state[TRACE_CFG_EMIF0_CNT0_FILTER], + trace_state[TRACE_CFG_EMIF0_CNT0_ID], + trace_state[TRACE_CFG_EMIF0_CNT0_ADDRSPACE]); + if (trace_state[TRACE_CFG_EMIF1_CNT0_FILTER] >= 0) + ret |= emif44xx_perf_cnt_configure(EMIF44XX_1, 0, + trace_state[TRACE_CFG_EMIF1_CNT0_FILTER], + trace_state[TRACE_CFG_EMIF1_CNT0_ID], + trace_state[TRACE_CFG_EMIF1_CNT0_ADDRSPACE]); + if (trace_state[TRACE_CFG_EMIF0_CNT1_FILTER] >= 0) + ret |= emif44xx_perf_cnt_configure(EMIF44XX_0, 1, + trace_state[TRACE_CFG_EMIF0_CNT1_FILTER], + trace_state[TRACE_CFG_EMIF0_CNT1_ID], + trace_state[TRACE_CFG_EMIF0_CNT1_ADDRSPACE]); + if (trace_state[TRACE_CFG_EMIF1_CNT1_FILTER] >= 0) + ret |= emif44xx_perf_cnt_configure(EMIF44XX_1, 1, + trace_state[TRACE_CFG_EMIF1_CNT1_FILTER], + trace_state[TRACE_CFG_EMIF1_CNT1_ID], + trace_state[TRACE_CFG_EMIF1_CNT1_ADDRSPACE]); + + if (ret != 0) { + fprintf(stderr, "%s(): error while configuring EMIF perf. " + "counters!\n", __func__); + ret = OMAPCONF_ERR_NOT_AVAILABLE; + goto counters44xx_count_err; + } + + /* Configure L2CC counters */ + /* Do this regardless whether enabled or disabled (at this point.) */ + if (trace_state[TRACE_CFG_L2CC_CNT0_FILTER] >= 0) + ret = l2cc44xx_perf_cnt_configure(0, trace_state[TRACE_CFG_L2CC_CNT0_FILTER], 1); /* for last entry, should use boolean 'true' */ + if (trace_state[TRACE_CFG_L2CC_CNT1_FILTER] >= 0) + ret = l2cc44xx_perf_cnt_configure(1, trace_state[TRACE_CFG_L2CC_CNT1_FILTER], 1); /* for last entry, should use boolean 'true' */ + +/* +// if (ret != 0) { +// fprintf(stderr, "%s(): error while configuring L2CC perf. " +// "counters!\n", __func__); +// ret = OMAPCONF_ERR_NOT_AVAILABLE; +// goto counters44xx_count_err; +// } +*/ + + /* Allocate buffer to store sampled data, unless continuous capture is enabled */ + if (capture_time > 0) { + if (sampling_rate > 0) { + sample_cnt = 1 + ((capture_time * 1000) / sampling_rate); + } else { + /* If smaple rate of 0, trace as fast as possible for the capture time. */ + sample_cnt = 1 + ((capture_time * 1000)); + } + } else { + /* Hack. If capture_time == 0, capture continuous. Need room for at least 2 samples. */ + sample_cnt = 2; + + if (trace_state[TRACE_CFG_LONG_HEADER] == 1) { + printf("#\n"); + printf("# ----------------- OMAP4430 Performance Trace+ ----------" + "--------------------------------------------------------------" + "-----\n"); + printf("#\n"); + /* printf("# NB:\n"); */ + printf("# * This is an intrusive trace (counters polling).\n"); + printf("# Idle C-States usage was altered.\n"); + printf("# Limted additional CPU & EMIFs loads generated.\n"); + printf("#\n"); + /* printf("# * If CPU1 Load = -5.0, it means CPU1 is OFFLINE.\n"); */ + /* printf("#\n"); */ + /* printf("# * CPU LOADS CANNOT be directly converted to Mhz.\n"); */ + /* printf("# OPP may have changed during the audit.\n"); */ + /* printf("#\n"); */ + printf("# ----------------------- Trace FORMAT -------------------" + "--------------------------------------------------------------" + "-----\n"); + printf("#\n"); + printf("# Trace Length: %us\n", capture_time); + printf("#\n"); + printf("# Trace Sampling Rate: %ums\n", + sampling_rate); + printf("#\n"); + + printf("# Number of samples: %u\n", sample_cnt - 1); + printf("#\n"); + printf("# %10.10s ", "Timestamp(s)"); + }; + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + if (trace_state[i] >= 0) {/* Traces state is enabled if non-zero state value. */ + ret = value2name(i, name, trace_config_options_table); + printf("\t%10.10s", name); + switch (i) { + case TRACE_CFG_EMIF0_CNT0_FILTER: + case TRACE_CFG_EMIF1_CNT0_FILTER: + case TRACE_CFG_EMIF0_CNT1_FILTER: + case TRACE_CFG_EMIF1_CNT1_FILTER: + ret = value2name(trace_state[i], name, emif_event_counters); + ret = snprintf(tmp_name, 64, "%s%s", ".", name); + ret = snprintf(name, 64, "%s", tmp_name); + break; + case TRACE_CFG_L2CC_CNT0_FILTER: + case TRACE_CFG_L2CC_CNT1_FILTER: + ret = value2name(trace_state[i], name, l2cc_event_counters_table); + ret = snprintf(tmp_name, 64, "%s%s", ".", name); + ret = snprintf(name, 64, "%s", tmp_name); + break; + default: + strcpy(name, " "); + break; + } /* end switch */ + printf("%s ", name); + } + } + printf("\n"); + + if (trace_state[TRACE_CFG_LONG_HEADER] == 1) { + printf("#\n"); + printf("# ----------------------- Trace START --------------------" + "--------------------------------------------------------------" + "-----\n"); + } + } + + dprintf("%s(): capture_time=%us, sample_cnt=%u\n", __func__, + capture_time, sample_cnt); + + + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + if (trace_state[i] >= 0) {/* Traces state is enabled if non-zero state value. */ + /* Add three sample entries to hold min, avg, max */ + trace_buf[i] = malloc((sample_cnt+3) * sizeof(unsigned int)); + if (trace_buf[i] == NULL) { + ret = value2name(i, name, trace_config_options_table); + fprintf(stderr, "%s(): could not allocate %s!\n", + __func__, name); + ret = OMAPCONF_ERR_NOT_AVAILABLE; + goto counters44xx_count_err; + } + } + } /* end for i < TRACE_CFG_ENABLED_OPTIONS_MAX */ + + /* Enable L2CC counters */ + ret = l2cc44xx_perf_cnt_enable(); + + + /* Sample performance indicators periodically */ + printf("\n"); + + printf("Sampling OMAP Counters for %us, please wait...\n", + capture_time); + + + for (sample = 0; sample < sample_cnt; sample++) { + +/* + // This could be a big for loop and 'switch' statemenet... + // Get CPU runtime execution stats + // Get EMIF cnt0, cnt1 & total mclk cycle counts as enabled + // skorson + // Being lazy and doing these two one after the other. I suppose code could be written + // to convert a for 0 to 1 loop but with only two, this is OK. +*/ + + + emif = 0; + if (trace_state[TRACE_CFG_EMIF0_CNT0_FILTER] >= 0) { + trace_buf[TRACE_CFG_EMIF0_CNT0_FILTER][sample] = emif44xx_perf_cnt_get_count( + emif, EMIF44XX_PERF_CNT_0); + dprintf("%s(): EMIF0 counter 0 value=%u\n", __func__, + trace_buf[TRACE_CFG_EMIF0_CNT0_FILTER][sample]); + } + if (trace_state[TRACE_CFG_EMIF0_CNT1_FILTER] >= 0) { + trace_buf[TRACE_CFG_EMIF0_CNT1_FILTER][sample] = emif44xx_perf_cnt_get_count( + emif, EMIF44XX_PERF_CNT_1); + dprintf("%s(): EMIF0 counter 1 value=%u\n", __func__, + trace_buf[TRACE_CFG_EMIF0_CNT1_FILTER][sample]); + } + + if (trace_state[TRACE_CFG_EMIF0_MCLK_CYCLES] >= 0) { + trace_buf[TRACE_CFG_EMIF0_MCLK_CYCLES][sample] = emif44xx_perf_cnt_get_time(emif); + } + + emif = 1; + if (trace_state[TRACE_CFG_EMIF1_CNT0_FILTER] >= 0) { + trace_buf[TRACE_CFG_EMIF1_CNT0_FILTER][sample] = emif44xx_perf_cnt_get_count( + emif, EMIF44XX_PERF_CNT_0); + dprintf("%s(): EMIF1 counter 0 value=%u\n", __func__, + trace_buf[TRACE_CFG_EMIF1_CNT0_FILTER][sample]); + } + if (trace_state[TRACE_CFG_EMIF1_CNT1_FILTER] >= 0) { + trace_buf[TRACE_CFG_EMIF1_CNT1_FILTER][sample] = emif44xx_perf_cnt_get_count( + emif, EMIF44XX_PERF_CNT_1); + dprintf("%s(): EMIF1 counter 1 value=%u\n", __func__, + trace_buf[TRACE_CFG_EMIF1_CNT1_FILTER][sample]); + } + + if (trace_state[TRACE_CFG_EMIF1_MCLK_CYCLES] >= 0) { + trace_buf[TRACE_CFG_EMIF1_MCLK_CYCLES][sample] = emif44xx_perf_cnt_get_time(emif); + dprintf("%s(): EMIF1 MCLK cycles=%u\n", __func__, + trace_buf[TRACE_CFG_EMIF1_MCLK_CYCLES][sample]); + } + + +/* +// FIXME: There is a bug where the L2 Counters are being disabled. Until this is known, enable the following +// block to determine if the counter has been disabled during a run. Print appropriate ERROR to screen... +*/ + if ((trace_state[TRACE_CFG_L2CC_CNT0_FILTER] >= 0) || (trace_state[TRACE_CFG_L2CC_CNT1_FILTER] >= 0)) { + + + /* check if counter is still enabled.... */ + ret = name2addr("EVENT_COUNTER_CONTROL", &addr, + (reg_table *) omap4_mpuss_pl310_reg_table); + ret = mem_read(addr, &data); + dprintf("EVENT COUNTER VALUE: 0x%x 0x%x\n", addr, data); + if (ret != 0) { + fprintf(stderr, "%s(): error reading L2CC (PL310) EVENT_COUNTER_CONTROL reg!\n", + __func__); + return OMAPCONF_ERR_REG_ACCESS; + } + if (data == 0 && l2_disabled_prior == 0) { + l2_disabled_prior = 1; + fprintf(stderr, "%s(): WARNING:L2CC (PL310) EVENT_COUNTER_CONTROL was DISABLED during a run!!!\n", + __func__); + fprintf(stderr, "%s(): WARNING: Counter values will be invalid (zero) after this point.\n", + __func__); + } + } + +/* END FIXME */ + + + + if (trace_state[TRACE_CFG_L2CC_CNT0_FILTER] >= 0) { + trace_buf[TRACE_CFG_L2CC_CNT0_FILTER][sample] = + (unsigned int) l2cc44xx_get_perf_cnt(0); + dprintf("%s(): l2_event_cnt[0] sample %d = 0x%x %d\n", __func__, sample, + trace_buf[TRACE_CFG_L2CC_CNT0_FILTER][sample], trace_buf[TRACE_CFG_L2CC_CNT0_FILTER][sample]); + } + if (trace_state[TRACE_CFG_L2CC_CNT1_FILTER] >= 0) { + trace_buf[TRACE_CFG_L2CC_CNT1_FILTER][sample] = + (unsigned int) l2cc44xx_get_perf_cnt(1); + dprintf("%s(): l2_event_cnt[1] sample %d = 0x%x %d\n", __func__, sample, + trace_buf[TRACE_CFG_L2CC_CNT1_FILTER][sample], trace_buf[TRACE_CFG_L2CC_CNT1_FILTER][sample]); + } + + if (trace_state[TRACE_CFG_TIMER_32K_SYNC] >= 0) { + addr = T32KSYNCNT_CR; + ret = mem_read(addr, &data); + trace_buf[TRACE_CFG_TIMER_32K_SYNC][sample] = data; + dprintf("%s(): 32K CLK cycles=%u\n", __func__, + trace_buf[TRACE_CFG_TIMER_32K_SYNC][sample]); + } + dprintf("\n"); + /* Sleep for some [minimum] time before sampling again */ + + + + if ((capture_time == 0) && (sample > 0)) { + /* Save timestamp */ + printf("[unix time stamp here]"); + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + if (trace_state[i] >= 0) { + sprintf(s, "%u", count32_delta(trace_buf[i][0], + trace_buf[i][1])); + printf("\t%10.10s", s); + } /* if state >= 0 */ + } /* for i to TRACE_CFG_ENABLED_OPTIONS_MAX */ + printf("\n"); + + /* Now move sample[1] to sample[0] */ + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + if (trace_state[i] >= 0) { + trace_buf[i][0] = trace_buf[i][1]; + } /* if state >= 0 */ + } /* for i to TRACE_CFG_ENABLED_OPTIONS_MAX */ + sample = 0; + } + + /* SLeep onyl if a sampling rate is set. */ + /* Sampling rate of 0 is as fast as possible... */ + if (sampling_rate > 0) + usleep(sampling_rate * 1000); + } + + /* Disable L2CC counters */ + /* Do regardless of whether enabled for tracing or not. */ + ret = l2cc44xx_perf_cnt_disable(); + + printf("Sampling done, processing and saving data...\n"); + + /* Open trace output file */ + fp = workdir_fopen(trace_perf_file, "w"); + if (fp == NULL) { + fprintf(stderr, "%s(): could not create %s!\n", + __func__, trace_perf_file); + ret = OMAPCONF_ERR_NOT_AVAILABLE; + goto counters44xx_count_err; + } + + dprintf("INFO: TRACE_CFG_LONG_HEADER %d\n", trace_state[TRACE_CFG_LONG_HEADER]); + + if (trace_state[TRACE_CFG_LONG_HEADER] == 1) { + fprintf(fp, "#\n"); + fprintf(fp, "# ----------------- OMAP4430 Performance Trace+ ----------" + "--------------------------------------------------------------" + "-----\n"); + fprintf(fp, "#\n"); + /* fprintf(fp, "# NB:\n"); */ + fprintf(fp, "# * This is an intrusive trace (counters polling).\n"); + fprintf(fp, "# Idle C-States usage was altered.\n"); + fprintf(fp, "# Limted additional CPU & EMIFs loads generated.\n"); + fprintf(fp, "#\n"); + /* fprintf(fp, "# * If CPU1 Load = -5.0, it means CPU1 is OFFLINE.\n"); */ + /* fprintf(fp, "#\n"); */ + /* fprintf(fp, "# * CPU LOADS CANNOT be directly converted to Mhz.\n"); */ + /* fprintf(fp, "# OPP may have changed during the audit.\n"); */ + /* fprintf(fp, "#\n"); */ + fprintf(fp, "# ----------------------- Trace FORMAT -------------------" + "--------------------------------------------------------------" + "-----\n"); + fprintf(fp, "#\n"); + fprintf(fp, "# Trace Length: %us\n", capture_time); + fprintf(fp, "#\n"); + fprintf(fp, "# Trace Sampling Rate: %ums\n", + sampling_rate); + fprintf(fp, "#\n"); + + fprintf(fp, "# Number of samples: %u\n", sample_cnt - 1); + fprintf(fp, "#\n"); + fprintf(fp, "# %10.10s ", "Timestamp(s)"); + }; + + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + if (trace_state[i] >= 0) {/* Traces state is enabled if non-zero state value. */ + ret = value2name(i, name, trace_config_options_table); + fprintf(fp, "\t%10.10s", name); + switch (i) { + case TRACE_CFG_EMIF0_CNT0_FILTER: + case TRACE_CFG_EMIF1_CNT0_FILTER: + case TRACE_CFG_EMIF0_CNT1_FILTER: + case TRACE_CFG_EMIF1_CNT1_FILTER: + ret = value2name(trace_state[i], name, emif_event_counters); + ret = snprintf(tmp_name, 64, "%s%s", ".", name); + ret = snprintf(name, 64, "%s", tmp_name); + break; + case TRACE_CFG_L2CC_CNT0_FILTER: + case TRACE_CFG_L2CC_CNT1_FILTER: + ret = value2name(trace_state[i], name, l2cc_event_counters_table); + ret = snprintf(tmp_name, 64, "%s%s", ".", name); + ret = snprintf(name, 64, "%s", tmp_name); + break; + default: + strcpy(name, " "); + break; + } /* end switch */ + fprintf(fp, "%s ", name); + } + } + fprintf(fp, "\n"); + if (trace_state[TRACE_CFG_LONG_HEADER] == 1) { + fprintf(fp, "#\n"); + fprintf(fp, "# ----------------------- Trace START --------------------" + "--------------------------------------------------------------" + "-----\n"); + } + dprintf ("I'm here 0\n"); + + /* Note: dropping first sample (or using it to normalize data to 0) */ + for (sample = 1; sample < sample_cnt; sample++) { + if (sampling_rate > 0) { + /* Save timestamp */ + sprintf(s, "%.3lf", (double) + (sample * sampling_rate) / 1000.0); + fprintf(fp, "%10.10s", s); + } else { + sprintf(s, "%.3lf", (double) + (sample)); + fprintf(fp, "%10.10s", s); + } + + dprintf ("I'm here 1.%d\n", sample); + + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + if (trace_state[i] >= 0) { + +/* +// For now, treating this timer as a counter - its easier to perform calculations +// (std. dev, mean, error etc.) +// if ( i == TRACE_CFG_TIMER_32K_SYNC ) { +// // These don't need offset adjusted like counters +// sprintf(s, "%u", count32_delta(trace_buf[i][0], +// trace_buf[i][sample]) ); +// fprintf(fp, "\t%10.10s", s); +// continue; +// } +*/ + + dprintf("INFO: Current Sample %d Value %d Previous %d\n", + sample, trace_buf[i][sample], trace_buf[i][sample - 1]); + + sprintf(s, "%u", + count32_delta(trace_buf[i][sample - 1], + trace_buf[i][sample])); + fprintf(fp, "\t%10.10s", s); + } /* if state >= 0 */ + } /* for i to TRACE_CFG_ENABLED_OPTIONS_MAX */ + + dprintf ("I'm here 2\n"); + fprintf(fp, "\n"); + } /* for sample < sample_cnt */ + + if (trace_state[TRACE_CFG_LONG_HEADER]) { + fprintf(fp, "# ------------------------ Trace END ---------------------" + "--------------------------------------------------------------" + "-----\n"); + }; + fclose(fp); + printf("Performance trace saved into \"%s\" file.\n", + trace_perf_file); + + + + /* Calculate Averages/Statistics*/ + fp = workdir_fopen(trace_perf_stats_file, "w"); + if (fp == NULL) { + fprintf(stderr, "%s(): could not create %s!\n", + __func__, trace_perf_stats_file); + ret = OMAPCONF_ERR_NOT_AVAILABLE; + goto counters44xx_count_err; + } + dprintf ("I'm here 2\n"); + autoadjust_table_init(table); + row = 0; + strncpy(table[row][0], "Performance Statistics", TABLE_MAX_ELT_LEN); + strncpy(table[row][1], "Option", TABLE_MAX_ELT_LEN); + strncpy(table[row][2], "Min", TABLE_MAX_ELT_LEN); + strncpy(table[row][3], "Max", TABLE_MAX_ELT_LEN); + strncpy(table[row][4], "Average", TABLE_MAX_ELT_LEN); + row++; + + /* Note: sample_cnt+0 = min, +1=avg, +2 = max */ + min = sample_cnt; + avg = sample_cnt+1; + max = sample_cnt+2; + + + dprintf ("I'm here 3\n"); + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + /* Whats the 'if' below for? Will always be true... */ + if (trace_state[i] >= 0) { + trace_buf[i][min] = ~0; + trace_buf[i][max] = 0; + trace_buf[i][avg] = 0; + dprintf ("I'm here 3.%d\n", i); + ret = value2name(i, name, trace_config_options_table); + dprintf ("Name: %s MIN: %d MAX: %d AVG: %d\n", name, trace_buf[i][min], trace_buf[i][max], trace_buf[i][avg]); + for (sample = 1; sample < sample_cnt; sample++) { + dprintf ("I'm here 3.%d.%d\n", i, sample); + temp = count32_delta(trace_buf[i][sample - 1], + trace_buf[i][sample]); + dprintf ("I'm here 3.%d.%d !FREQ %d\n", i, sample, temp); + if (temp > trace_buf[i][max]) + trace_buf[i][max] = temp; + if (temp < trace_buf[i][min]) + trace_buf[i][min] = temp; + trace_buf[i][avg] = (unsigned int) avg_recalc((double) trace_buf[i][avg], + (double) temp, sample - 1); + ret = value2name(i, name, trace_config_options_table); + dprintf ("Name: %s MIN: %d MAX: %d AVG: %d\n", name, trace_buf[i][min], trace_buf[i][max], trace_buf[i][avg]); + } /* for sample < sample_cnt */ + dprintf ("I'm here 4.%d\n", i); + /* Save statistics */ + ret = value2name(i, name, trace_config_options_table); + dprintf ("Name: %s MIN: %d MAX: %d AVG: %d\n", name, trace_buf[i][min], trace_buf[i][max], trace_buf[i][avg]); + strncpy(table[row][0], name, TABLE_MAX_ELT_LEN); + + + strcpy (option, ""); + switch (i) { + case TRACE_CFG_EMIF0_CNT0_FILTER: + case TRACE_CFG_EMIF1_CNT0_FILTER: + case TRACE_CFG_EMIF0_CNT1_FILTER: + case TRACE_CFG_EMIF1_CNT1_FILTER: + ret = value2name(trace_state[i], option, emif_event_counters); + break; + case TRACE_CFG_L2CC_CNT0_FILTER: + case TRACE_CFG_L2CC_CNT1_FILTER: + ret = value2name(trace_state[i], option, l2cc_event_counters_table); + break; + default: + break; + } /* end switch */ + strncpy(table[row][1], option, TABLE_MAX_ELT_LEN); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.2d", trace_buf[i][min]); + snprintf(table[row][3], TABLE_MAX_ELT_LEN, "%.2d", trace_buf[i][max]); + snprintf(table[row][4], TABLE_MAX_ELT_LEN, "%.2d", trace_buf[i][avg]); + row++; + } /* if (trace_state[i] >= 0 */ + + } /* for i to TRACE_CFG_ENABLED_OPTIONS_MAX */ + dprintf ("I'm here 5\n"); + + + autoadjust_table_fprint(fp, table, row, 4); + fclose(fp); + printf("Performance statistics saved into \"%s\" file.\n\n", + trace_perf_stats_file); + dprintf ("I'm here 6\n"); + autoadjust_table_print(table, row, 4); + dprintf ("I'm here 7\n"); + return ret; + +counters44xx_count_err: + /* Free allocated buffers */ + for (i = 0; i < TRACE_CFG_ENABLED_OPTIONS_MAX; i++) { + if (trace_state[i] >= 0) {/* Traces state is enabled if non-neg state value. */ + if (trace_buf[i] != NULL) { + free(trace_buf[i]); + } + } + } /* end for i < TRACE_CFG_ENABLED_OPTIONS_MAX */ + + return ret; +} + + +/** + * Function: counters44xx_get_defaults + * Role: Process defaults from a file. + * Parameters: + * *fp: pointer to a a file opened for reading. + * Return: + * 0 in case of success + * >1 if error processing the defaults + * Modifies: + * Modifies the various global perf trace values. + */ +int counters44xx_get_defaults(char *defaults_file) +{ + char param[64]; + char tmp_name[64]; + int i, j; + int ret; + int invalid_char = 0; + unsigned int param_index; + unsigned int value_index; + + unsigned int table_size; + name_desc_val_table *default_tablep; + + dprintf("Hello!!! Calling Defaults routine.\n"); + + /* Build name/val/desc array to hold defaults */ + + + table_size = (sizeof(trace_config_options_table)); + default_tablep = malloc(table_size); + if (default_tablep == NULL) { + fprintf(stderr, "%s(): ERROR: Unable to allocate memory for defaults table.Exiting.\n", __func__); + return OMAPCONF_ERR_UNEXPECTED; + } + /* Must clear here. Other routines may depend on content being zeroed if not used. */ + memset(default_tablep, '\0', table_size); + + + dprintf("Hello!!! Filling table with parameters.\n"); + + /* Fill the table with the parameters for which we are looking */ + i = 0; + while (strcmp(trace_config_options_table[i].name, "END") != 0) { + + ret = snprintf((default_tablep[i]).name, OMAPCONF_REG_NAME_MAX_LENGTH, "%s", trace_config_options_table[i].name); + i++; + }; + /* Add required END entry */ + ret = snprintf((default_tablep[i]).name, OMAPCONF_REG_NAME_MAX_LENGTH, "%s", "END"); + j = i+1; /* j now contains max entries in the default_tablep array */ + + + /* Call the get defaults routine */ + dprintf("Calling Defaults routine.\n"); + /* The middle paramter is an optional prefix string */ + ret = omapconf_getdefaults(defaults_file, "", default_tablep); + dprintf("Returned.\n"); + + /* Process the returned values */ + i = 0; + while (strcmp(default_tablep[i].name, "END") != 0) { + dprintf("Checking on item %d %s %s.\n", i, default_tablep[i].name, default_tablep[i].desc); + /* If not an empty paramter... */ + if (strncmp(default_tablep[i].desc, "", 1) != 0) { + ret = name2value(default_tablep[i].name, ¶m_index, trace_config_options_table); + switch (param_index) { + /* Following are simple enabled/disabled items */ + case TRACE_CFG_TIMER_32K_SYNC: + case TRACE_CFG_EMIF0_MCLK_CYCLES: + case TRACE_CFG_EMIF1_MCLK_CYCLES: + case TRACE_CFG_LONG_HEADER: + if (strcmp(lowercase(default_tablep[i].desc), "enabled") == 0) + trace_state[param_index] = 1; + else + trace_state[param_index] = -1; + break; + case TRACE_CFG_EMIF0_CNT0_FILTER: + case TRACE_CFG_EMIF1_CNT0_FILTER: + case TRACE_CFG_EMIF0_CNT1_FILTER: + case TRACE_CFG_EMIF1_CNT1_FILTER: + ret = name2value(default_tablep[i].desc, &value_index, emif_event_counters); + if (value_index == EMIF44XX_PERF_CNT_FILTER_DISABLED) { + trace_state[param_index] = -1; + } else { + trace_state[param_index] = value_index; + } + break; + case TRACE_CFG_EMIF0_CNT0_ID: + case TRACE_CFG_EMIF0_CNT1_ID: + case TRACE_CFG_EMIF1_CNT0_ID: + case TRACE_CFG_EMIF1_CNT1_ID: + if (!(strcmp(lowercase(default_tablep[i].desc), "disabled") == 0)) { + ret = sscanf(default_tablep[i].desc, "%u", &trace_state[param_index]); + if (ret != 1) { + fprintf(stderr, "%s(): Error - Integer ID did not match for %s: %s!!\n", + __func__, param, default_tablep[i].desc); + trace_state[param_index] = -1; + break; + }; + }; + if (trace_state[param_index] > 255) { + fprintf(stderr, "%s(): Error - Param %s Integer ID > 255: %s!!\n", + __func__, param, default_tablep[i].desc); + trace_state[param_index] = -1; + } + break; + case TRACE_CFG_EMIF0_CNT0_ADDRSPACE: + case TRACE_CFG_EMIF0_CNT1_ADDRSPACE: + case TRACE_CFG_EMIF1_CNT0_ADDRSPACE: + case TRACE_CFG_EMIF1_CNT1_ADDRSPACE: + ret = name2value(default_tablep[i].desc, &value_index, emif_event_memaddrspace); + if (ret < 0) { + fprintf(stderr, "%s(): Error - Unexpected Address Space for %s: %s!!\n", + __func__, param, default_tablep[i].desc); + trace_state[param_index] = -1; + break; + }; + trace_state[param_index] = value_index; + break; + + + case TRACE_CFG_L2CC_CNT0_FILTER: + case TRACE_CFG_L2CC_CNT1_FILTER: + dprintf("Made it to TRACE_CFG_L2CC_CNTn_FILTER.\n"); + ret = name2value(default_tablep[i].desc, &value_index, l2cc_event_counters_table); + if (ret < 0) { + fprintf(stderr, "%s(): Error - Unexpected L2CC Event Counter for %s: %s!!\n", + __func__, param, default_tablep[i].desc); + trace_state[param_index] = -1; + break; + }; + dprintf ("Im Here L2CC: Value Index: 0x%X\n", trace_state[param_index]); + /* Note, for L2CC, disabled tracing is value 0x0 */ + if (!(value_index == L2CC44XX_EVT_CNT_DISABLED)) + trace_state[param_index] = value_index; + break; + + case TRACE_CFG_SAMPLE_INTERVAL: + ret = sscanf(default_tablep[i].desc, "%d", &sampling_rate); + if (ret != 1) { + help(HELP_TRACE); + return OMAPCONF_ERR_ARG; + } +/* +// if (sampling_rate == 0) { +// printf("0 sec sample time not allowed, ...\n\n"); +// sampling_rate = PERF_TRACE_SAMPLING_RATE_MS; +// return OMAPCONF_ERR_ARG; +// } +*/ + break; + case TRACE_CFG_FILE_PREFIX: + /* skorson - + If argument includes optional file prefix + NB: You must specify a time if specifying a prefix + */ + /* skorson - I'm sure there is a better way to do this... */ + for (j = 0; j < 64; j++) { + if (default_tablep[i].desc[j] == '\0') { + file_prefix[j] = default_tablep[i].desc[j]; + break; + } /* End of string - add to file_prefix?*/ + if (j >= 20) { + invalid_char++; + break; + } /* Prefix is too long */ + if (default_tablep[i].desc[j] >= '0' && default_tablep[i].desc[j] <= '9') { + file_prefix[j] = default_tablep[i].desc[j]; + continue; + } /* valid number */ + if (default_tablep[i].desc[j] >= 'A' && default_tablep[i].desc[j] <= 'Z') { + file_prefix[j] = default_tablep[i].desc[j]; + continue; + } /* valid uprcase */ + if (default_tablep[i].desc[j] >= 'a' && default_tablep[i].desc[j] <= 'z') { + file_prefix[j] = default_tablep[i].desc[j]; + continue; + } /* valid lwrcase */ + if (default_tablep[i].desc[j] == '_' || default_tablep[i].desc[j] == '[' + || default_tablep[i].desc[j] == ']' || default_tablep[i].desc[j] == '.' + || default_tablep[i].desc[j] == '-') { + file_prefix[j] = default_tablep[i].desc[j]; + continue; + } /* valid \_ \- \[ \] \. */ + invalid_char++; break; + } /* end for */ + + if (invalid_char) { + printf("invalid prefix. Use <= 20 letters, digits, _-.[ or ] ...\n\n"); + return OMAPCONF_ERR_ARG; + } /* end if */ + + /* skorson - + Here we have a file_prefix as the prefix. Now prepend to file names. + built a small string prepend utility to simplify. + This probably already exists somewhere... */ + + ret = snprintf(tmp_name, 64, "%s%s", file_prefix, trace_perf_file); + ret = snprintf(trace_perf_file, 64, "%s", tmp_name); + ret = snprintf(tmp_name, 64, "%s%s", file_prefix, trace_perf_stats_file); + ret = snprintf(trace_perf_stats_file, 64, "%s", tmp_name); + + break; + + case TRACE_CFG_NORMALIZE: + printf("WARNING: Normalization not yet supported. Post-process this for now.\n"); + if (strcmp(lowercase(default_tablep[i].desc), "enabled") == 0) { + trace_state[param_index] = 1; + trace_state[TRACE_CFG_TIMER_32K_SYNC] = 1; + } else + trace_state[param_index] = -1; + break; + + default: + fprintf(stderr, "%s(): Error - No matching Parameter: entry %d %s!!\n", + __func__, i, param); + /* return OMAPCONF_ERR_ARG; */ + continue; + } /* end switch */ + } /* end if found a value in defaults file */ + i++; + } /* End while */ + + return 0; +} + + +/** + * Function: omap4conf_print_defaults + * Role: + * Parameters: + * None + * Return: + * 0 in case of success + */ +int counters44xx_print_defaults() +{ + int i; + int ret; + char name[64]; + char example_default[128]; + char desc[128]; + + printf("\n\n"); + printf("# Counter Tracing Defaults Template\n"); + printf("# This can be used directly as an .omapconf_defaults file.\n"); + printf("\n"); + for (i = 0; i < TRACE_CFG_TABLE_MAX; i++) { + ret = value2name(i, name, trace_config_options_table); + ret = value2desc(i, desc, trace_config_options_table); + ret = value2desc(i, example_default, trace_config_defaults_table); + if (ret >= 0) { + printf("%s\t%s\t# %s\n", name, example_default, desc); + } + } + return 0; +} + +#ifdef OMAP4CONF_COUNTERS_DEBUG +#undef dprintf +#define dprintf(format, ...) +#endif + +/** + * Function: counters44xx_main + * Role: + * Parameters: + * argc: shell input argument number + * argv: shell input argument(s) + * Return: + * 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_NOT_AVAILABLE + * OMAPCONF_ERR_UNEXPECTED + */ +int counters44xx_main(int argc, char *argv[]) +{ + int ret; + int i; + int help_skip = 0; + int invalid_char = 0; + char tmp_name[64]; + + if (!cpu_is_omap44xx()) + return OMAPCONF_ERR_CPU; + + /* Check if a defaults file is provided */ + if ((argc < 1) || (argc > 3)) { + help44xx(HELP_COUNTERS, ""); + return OMAPCONF_ERR_ARG; + } + + dprintf("%s(): ARGC: %d\n", __func__, argc); + for (i = 0; i < argc; i++) { + dprintf("%s(): ARGV[%d]: %s\n", __func__, i, argv[i]); + if (strcmp(argv[i], "help") == 0) + help_skip++; + } + +/* +// skorson - Gotta be a better way to do this... +// I see other parts of the code use 'goto'... +*/ + if (help_skip == 0) { + if ((argc >= 2) && + (strcmp(argv[1], "defaults") == 0)) { + counters44xx_print_defaults(); + return 0; + } + + + /* Currently all variables are global to this file. */ + ret = counters44xx_get_defaults(defaults_file); + if (ret) { + fprintf(stderr, "%s(): ERROR: Error reading %s default file. Using programmed defaults.\n", + __func__, defaults_file); + } + + /* Retrieve capture_time */ + if (argc >= 2) { + ret = sscanf(argv[1], "%d", &capture_time); + if (ret != 1) { + help44xx(HELP_COUNTERS, ""); + return OMAPCONF_ERR_ARG; + } + if (capture_time == 0) { + printf("Continuous Trace Selected ...\n\n"); + } + } /* end if argc >= 2 */ + + if (argc >= 3) { + /* skorson - + If argument includes optional file prefix + NB: You must specify a time if specifying a prefix + */ + /* skorson - checking for safe characters. I'm sure there is a better way to do this... */ + for (i = 0; i < 64; i++) { + if (argv[2][i] == '\0') { + file_prefix[i] = argv[2][i]; break; } /* End of string - add to file_prefix?*/ + if (i >= 20) { + invalid_char++; + break; + } /* Prefix is too long */ + if (argv[2][i] >= '0' && argv[2][i] <= '9') { + file_prefix[i] = argv[2][i]; + continue; + } /* valid number */ + if (argv[2][i] >= 'A' && argv[2][i] <= 'Z') { + file_prefix[i] = argv[2][i]; + continue; + } /* valid uprcase */ + if (argv[2][i] >= 'a' && argv[2][i] <= 'z') { + file_prefix[i] = argv[2][i]; + continue; + } /* valid lwrcase */ + if (argv[2][i] == '_' || argv[2][i] == '[' + || argv[2][i] == ']' || argv[2][i] == '.' + || argv[2][i] == '-') { + file_prefix[i] = argv[2][i]; + continue; + } /* valid \_ \- \[ \] \. */ + invalid_char++; + break; + } /* end for */ + + if (invalid_char) { + printf("invalid prefix. Use <= 20 letters, digits, _-.[ or ] ...\n\n"); + return OMAPCONF_ERR_ARG; + } /* end if */ + + /* skorson - + Here we have a file_prefix as the prefix. Now prepend to file names. + built a small string prepend utility to simplify. + This probably already exists somewhere... */ +/* printf("DEBUG: Prefix == %s\n", file_prefix); */ + + ret = snprintf(tmp_name, 64, "%s%s", file_prefix, trace_perf_file); + ret = snprintf(trace_perf_file, 64, "%s", tmp_name); + + ret = snprintf(tmp_name, 64, "%s%s", file_prefix, trace_perf_stats_file); + ret = snprintf(trace_perf_stats_file, 64, "%s", tmp_name); + + + } /* End if argc = 3 */ + } /* End if help_skip == 0 */ + + /* Retrieve trace type and call associated function */ + if (!help_skip) { + ret = counters44xx_count(capture_time); + } else if ((strcmp(argv[1], "help") == 0) && (argc >= 3)) { + help44xx(HELP_COUNTERS, argv[2]); + } else { + help44xx(HELP_COUNTERS, "all"); + ret = OMAPCONF_ERR_ARG; + } + + return ret; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/counters44xx.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/counters44xx.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/counters44xx.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/counters44xx.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,160 @@ +/* + * + * @Component OMAPCONF + * @Filename counters44xx.h + * @Description Collect OMAP4 PRCM PMI Traces in ETB + * @Author Steve Korson (s-korson@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __COUNTERS44XX_H__ +#define __COUNTERS44XX_H__ + +#include + + +typedef enum { + /* + * The options thta can be traced (i.e. enabled/disabled or appear in a + * file). Must be first. + */ + TRACE_CFG_TIMER_32K_SYNC, + TRACE_CFG_L2CC_CNT0_FILTER, + TRACE_CFG_L2CC_CNT1_FILTER, + TRACE_CFG_EMIF0_CNT0_FILTER, + TRACE_CFG_EMIF1_CNT0_FILTER, + TRACE_CFG_EMIF0_CNT1_FILTER, + TRACE_CFG_EMIF1_CNT1_FILTER, + TRACE_CFG_EMIF0_MCLK_CYCLES, + TRACE_CFG_EMIF1_MCLK_CYCLES, + /* Index Marker */ + TRACE_CFG_ENABLED_OPTIONS_MAX, + /* + * Options that don't require data storage (i.e. options for env. or + * other control of a traced option.) beyond this point. + */ + TRACE_CFG_EMIF0_CNT0_ID, + TRACE_CFG_EMIF1_CNT0_ID, + TRACE_CFG_EMIF0_CNT1_ID, + TRACE_CFG_EMIF1_CNT1_ID, + TRACE_CFG_EMIF0_CNT0_ADDRSPACE, + TRACE_CFG_EMIF1_CNT0_ADDRSPACE, + TRACE_CFG_EMIF0_CNT1_ADDRSPACE, + TRACE_CFG_EMIF1_CNT1_ADDRSPACE, + TRACE_CFG_SAMPLE_INTERVAL, + TRACE_CFG_NORMALIZE, /* + * When enabled, normalize results based on the + * TRACE_CFG_TIMER_32K_SYNC count. + * Setting enabled auto-enables + * TRACE_CFG_TIMER_32K_SYNC counting. + * Not configured (does not do anything) + * at this time. + */ + TRACE_CFG_FILE_PREFIX, + TRACE_CFG_LONG_HEADER, + /* Index marker */ + TRACE_CFG_TABLE_MAX + } trace_cfg_options_type; + + +static const name_desc_val_table trace_config_options_table[] = { + {"TIMER_32K_SYNC", "(ENABLED | DISABLED) free-running 32K timer timestamp.", TRACE_CFG_TIMER_32K_SYNC}, + {"L2CC_CNT0_FILTER", "Value of L2CC Event 0 event to trace (or DISABLED).", TRACE_CFG_L2CC_CNT0_FILTER}, + {"L2CC_CNT1_FILTER", "Value of L2CC Event 1 event to trace (or DISABLED).", TRACE_CFG_L2CC_CNT1_FILTER}, + {"EMIF0_CNT0_FILTER", "Value of EMIF0 CNT0 event to trace (or DISABLED).", TRACE_CFG_EMIF0_CNT0_FILTER}, + {"EMIF1_CNT0_FILTER", "Value of EMIF1 CNT0 event to trace (or DISABLED).", TRACE_CFG_EMIF1_CNT0_FILTER}, + {"EMIF0_CNT1_FILTER", "Value of EMIF0 CNT1 event to trace (or DISABLED).", TRACE_CFG_EMIF0_CNT1_FILTER}, + {"EMIF1_CNT1_FILTER", "Value of EMIF1 CNT1 event to trace (or DISABLED).", TRACE_CFG_EMIF1_CNT1_FILTER}, + {"EMIF0_CNT0_ID", "0 to 255 ID value (or DISABLED).", TRACE_CFG_EMIF0_CNT0_ID}, + {"EMIF1_CNT0_ID", "0 to 255 ID value (or DISABLED).", TRACE_CFG_EMIF1_CNT0_ID}, + {"EMIF0_CNT1_ID", "0 to 255 ID value (or DISABLED).", TRACE_CFG_EMIF0_CNT1_ID}, + {"EMIF1_CNT1_ID", "0 to 255 ID value (or DISABLED).", TRACE_CFG_EMIF1_CNT1_ID}, + {"EMIF0_CNT0_ADDRSP", "Addr-Space Filter (or DISABLED).", TRACE_CFG_EMIF0_CNT0_ADDRSPACE}, + {"EMIF1_CNT0_ADDRSP", "Addr-Space Filter (or DISABLED).", TRACE_CFG_EMIF1_CNT0_ADDRSPACE}, + {"EMIF0_CNT1_ADDRSP", "Addr-Space Filter (or DISABLED).", TRACE_CFG_EMIF0_CNT1_ADDRSPACE}, + {"EMIF1_CNT1_ADDRSP", "Addr-Space Filter (or DISABLED).", TRACE_CFG_EMIF1_CNT1_ADDRSPACE}, + {"EMIF0_MCLK_CYCLES", "EMIF0 MCLK cycles since EMIF0 reset (ENABLED | DISABLED).", TRACE_CFG_EMIF0_MCLK_CYCLES}, + {"EMIF1_MCLK_CYCLES", "EMIF1 MCLK cycles since EMIF1 reset (ENABLED | DISABLED).", TRACE_CFG_EMIF1_MCLK_CYCLES}, + {"SAMPLE_INTERVAL", "Integer sample interval, in ms.", TRACE_CFG_SAMPLE_INTERVAL}, + {"FILE_PREFIX", "20 character file prefix [a-zA-Z0-9\\[\\]\\._-].", TRACE_CFG_FILE_PREFIX}, + {"LONG_HEADER", "(ENABLED | DISABLED) a long header in the dat file.", TRACE_CFG_LONG_HEADER}, + /* END OF TABLE IS REQUIRED! */ + {"END", "END of Table.", 0} }; + +static const name_desc_val_table trace_config_defaults_table[] = { + {"TIMER_32K_SYNC", "ENABLED", TRACE_CFG_TIMER_32K_SYNC}, + {"L2CC_CNT0_FILTER", "CO", TRACE_CFG_L2CC_CNT0_FILTER}, + {"L2CC_CNT1_FILTER", "DRHIT", TRACE_CFG_L2CC_CNT1_FILTER}, + {"EMIF0_CNT0_FILTER", "TOTAL_READ", TRACE_CFG_EMIF0_CNT0_FILTER}, + {"EMIF1_CNT0_FILTER", "DISABLED", TRACE_CFG_EMIF1_CNT0_FILTER}, + {"EMIF0_CNT1_FILTER", "TOTAL_READ", TRACE_CFG_EMIF0_CNT1_FILTER}, + {"EMIF1_CNT1_FILTER", "DISABLED", TRACE_CFG_EMIF1_CNT1_FILTER}, + {"EMIF0_CNT0_ID", "DISABLED", TRACE_CFG_EMIF0_CNT0_ID}, + {"EMIF1_CNT0_ID", "DISABLED", TRACE_CFG_EMIF1_CNT0_ID}, + {"EMIF0_CNT1_ID", "DISABLED", TRACE_CFG_EMIF0_CNT1_ID}, + {"EMIF1_CNT1_ID", "DISABLED", TRACE_CFG_EMIF1_CNT1_ID}, + {"EMIF0_CNT0_ADDRSP", "DISABLED", TRACE_CFG_EMIF0_CNT0_ADDRSPACE}, + {"EMIF1_CNT0_ADDRSP", "DISABLED", TRACE_CFG_EMIF1_CNT0_ADDRSPACE}, + {"EMIF0_CNT1_ADDRSP", "DISABLED", TRACE_CFG_EMIF0_CNT1_ADDRSPACE}, + {"EMIF1_CNT1_ADDRSP", "DISABLED", TRACE_CFG_EMIF1_CNT1_ADDRSPACE}, + {"EMIF0_MCLK_CYCLES", "ENABLED", TRACE_CFG_EMIF0_MCLK_CYCLES}, + {"EMIF1_MCLK_CYCLES", "ENABLED", TRACE_CFG_EMIF1_MCLK_CYCLES}, + {"SAMPLE_INTERVAL", "10", TRACE_CFG_SAMPLE_INTERVAL}, + {"FILE_PREFIX", "results_01_", TRACE_CFG_FILE_PREFIX}, + {"LONG_HEADER", "DISABLED", TRACE_CFG_LONG_HEADER}, + /* END OF TABLE IS REQUIRED! */ + {"END", "END of Table." , 0} }; + + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION counters44xx_main + * @BRIEF main entry point + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_NOT_AVAILABLE + * OMAPCONF_ERR_UNEXPECTED + * @param[in] argc: shell input argument number + * @param[in] argv: shell input argument(s) + * @DESCRIPTION Counters functions main entry point + *//*------------------------------------------------------------------------ */ +int counters44xx_main(int argc, char *argv[]); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/cpuinfo44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/cpuinfo44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/cpuinfo44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/cpuinfo44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,145 @@ +/* + * + * @Component OMAPCONF + * @Filename cpuinfo44xx.c + * @Description OMAP4 CPU Info Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include + + +/* #define CPUID44XX_DEBUG */ +#ifdef CPUID44XX_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION cpu44xx_silicon_max_speed_get + * @BRIEF return silicon max speed (depending on cpu type and + * silicon type) + * @RETURNS Silicon max speed (in MHz) + * 0 in case of error + * @DESCRIPTION return silicon max speed (depending on cpu type and + * silicon type) + *//*------------------------------------------------------------------------ */ +unsigned int cpu44xx_silicon_max_speed_get(void) +{ + unsigned int max_speed; + + switch (cpu_get()) { + case OMAP_4430: + switch (cpu_silicon_type_get()) { + case LOW_PERF_SI: + max_speed = 800; + break; + case STANDARD_PERF_SI: + max_speed = 1000; + break; + case HIGH_PERF_SI: + max_speed = 1200; + break; + default: + max_speed = 0; + break; + } + break; + + case OMAP_4460: + switch (cpu_silicon_type_get()) { + case STANDARD_PERF_SI: + max_speed = 1200; + break; + case HIGH_PERF_SI: + max_speed = 1500; + break; + default: + max_speed = 0; + break; + } + break; + + case OMAP_4470: + switch (cpu_silicon_type_get()) { + case STANDARD_PERF_SI: + max_speed = 1300; + break; + case HIGH_PERF_SI: + max_speed = 1500; + break; + default: + max_speed = 0; + break; + } + break; + + default: + fprintf(stderr, "%s(): unknown chip!\n", __func__); + max_speed = 0; + } + + dprintf("%s(): max speed = %dMHz\n", __func__, max_speed); + return max_speed; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION cpu44xx_cores_count_get + * @BRIEF return the number of CPU cores available + * @RETURNS >0 number of CPU cores available + * 0 in case of error (unknown architecture) + * @param[in] none + * @DESCRIPTION return the number of CPU cores available + *//*------------------------------------------------------------------------ */ +unsigned int cpu44xx_cores_count_get(void) +{ + if (cpu_is_omap44xx()) { + return 2; + } else { + fprintf(stderr, "%s(): unknown architecture!\n", __func__); + return 0; + } +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/cpuinfo44xx.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/cpuinfo44xx.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/cpuinfo44xx.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/cpuinfo44xx.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,53 @@ +/* + * + * @Component OMAPCONF + * @Filename cpuinfo44xx.h + * @Description OMAP4 CPU Info Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __CPUID44XX_H__ +#define __CPUID44XX_H__ + + +unsigned int cpu44xx_silicon_max_speed_get(void); +unsigned int cpu44xx_cores_count_get(void); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/ctt44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/ctt44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/ctt44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/ctt44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,495 @@ +/* + * + * @Component OMAPCONF + * @Filename ctt44xx.c + * @Description Display PRCM registers in a format that can be + * imported into the clock tree tool (CTT) + * @Author Jon Hunter (jon-hunter@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define CTT44XX_DEBUG */ +#ifdef CTT44XX_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +#define PRCM_CTT_REG_TABLE_SIZE 238 + + +static char ctt_filename[] = "CTT-OMAP44XX-REG_DUMP.rd1"; +static reg_table prcm_ctt_reg_table[PRCM_CTT_REG_TABLE_SIZE]; + + +static int ctt44xx_regtable_init(void); + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION ctt44xx_dump + * @BRIEF dump PRCM registers + * @RETURNS 0 + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @DESCRIPTION dump PRCM registers + *//*------------------------------------------------------------------------ */ +int ctt44xx_dump(void) +{ + unsigned int i = 0; + unsigned int ret, val = 0; + int err = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_ARG); + + printf("The Clock Tree Tool can import register settings from a *.rd1 " + "file.\n"); + printf("The format of the *.rd1 file is:\n\n"); + printf("DeviceName OMAPxxxx_ESx.x\n"); + printf(" \n"); + printf(" \n"); + printf("...\n\n"); + printf("Copy the below output between the begin and end separators " + "into a\n"); + printf("file with the extension *.rd1 and this file can be read by the" + "\n"); + printf("Clock Tree Tool\n\n"); + printf("|--------------------------- ctt dump begin ------------------" + "----|\n"); + + if (cpu_is_omap4430()) + printf("DeviceName OMAP4430_ES2.x\n"); + else if (cpu_is_omap4460()) + printf("DeviceName OMAP4460_ES1.x\n"); + else if (cpu_is_omap4470()) + printf("DeviceName OMAP4470_ES1.0\n"); + else + return OMAPCONF_ERR_CPU; + + ctt44xx_regtable_init(); + + while (prcm_ctt_reg_table[i].addr != 0) { + /* display register addr & content (hex) */ + ret = mem_read(prcm_ctt_reg_table[i].addr, &val); + if (ret == 0) + printf("0x%08X 0x%08X\n", prcm_ctt_reg_table[i].addr, + val); + else { + fprintf(stderr, + "omapconf: read error! (addr=0x%08X, err=%d)\n", + prcm_ctt_reg_table[i].addr, ret); + err = OMAPCONF_ERR_REG_ACCESS; + } + i++; + } + + printf("|---------------------------- ctt dump end --------------------" + "---|\n"); + + return err; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION ctt44xx_rd1_export + * @BRIEF export PRCM registers in CTT RD1 format + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_NOT_AVAILABLE + * @param[in] filename: output file name + * @DESCRIPTION export PRCM registers in CTT RD1 format + *//*------------------------------------------------------------------------ */ +int ctt44xx_rd1_export(char *filename) +{ + unsigned int i = 0; + unsigned int ret, val = 0; + int err = 0; + FILE *fd = NULL; + + CHECK_CPU(44xx, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(filename, OMAPCONF_ERR_ARG); + + fd = fopen(filename, "w"); + if (fd == NULL) { + printf("error: could not create %s file!\n", filename); + return OMAPCONF_ERR_NOT_AVAILABLE; + } + + if (cpu_is_omap4430()) { + fprintf(fd, "DeviceName OMAP4430_ES2.x\n"); + } else if (cpu_is_omap4460()) { + fprintf(fd, "DeviceName OMAP4460_ES1.x\n"); + } else if (cpu_is_omap4470()) { + fprintf(fd, "DeviceName OMAP4470_ES1.0\n"); + } else { + err = OMAPCONF_ERR_CPU; + goto ctt44xx_rd1_export_end; + } + + ctt44xx_regtable_init(); + + while (prcm_ctt_reg_table[i].addr != 0) { + /* display register addr & content (hex) */ + ret = mem_read(prcm_ctt_reg_table[i].addr, &val); + if (ret == 0) + fprintf(fd, "0x%08X 0x%08X\n", + prcm_ctt_reg_table[i].addr, val); + else { + fprintf(stderr, + "omapconf: read error! (addr=0x%08X, err=%d)\n", + prcm_ctt_reg_table[i].addr, ret); + err = OMAPCONF_ERR_REG_ACCESS; + } + i++; + } + + printf("Output written to file '%s'.\n", filename); + err = 0; + +ctt44xx_rd1_export_end: + if (fd != NULL) + fclose(fd); + return err; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION ctt44xx_main + * @BRIEF main entry point for ctt + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in] argc: shell input argument number + * @param[in] argv: shell input argument(s) + * @DESCRIPTION main entry point for ctt + *//*------------------------------------------------------------------------ */ +int ctt44xx_main(int argc, char *argv[]) +{ + int ret; + + CHECK_CPU(44xx, OMAPCONF_ERR_ARG); + + if (argc == 2) { + if (strcmp(argv[1], "dump") == 0) + ret = ctt44xx_dump(); + else if (strcmp(argv[1], "rd1") == 0) + ret = ctt44xx_rd1_export(ctt_filename); + else { + help(HELP_EXPORT); + ret = OMAPCONF_ERR_ARG; + } + } else { + help(HELP_EXPORT); + ret = OMAPCONF_ERR_ARG; + } + + return ret; +} + + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION ctt44xx_regtable_init + * @BRIEF initialize regtable + * @RETURNS 0 + * OMAPCONF_ERR_CPU + * @DESCRIPTION initialize regtable + *//*------------------------------------------------------------------------ */ +static int ctt44xx_regtable_init(void) +{ + int i = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_ARG); + + /* Init PRCM registers table */ + prcm_ctt_reg_table[i++].addr = 0x4a004100; + prcm_ctt_reg_table[i++].addr = 0x4a004108; + prcm_ctt_reg_table[i++].addr = 0x4a004110; + prcm_ctt_reg_table[i++].addr = 0x4a004120; + prcm_ctt_reg_table[i++].addr = 0x4a004124; + prcm_ctt_reg_table[i++].addr = 0x4a004128; + prcm_ctt_reg_table[i++].addr = 0x4a00412c; + prcm_ctt_reg_table[i++].addr = 0x4a004130; + prcm_ctt_reg_table[i++].addr = 0x4a004134; + prcm_ctt_reg_table[i++].addr = 0x4a004138; + prcm_ctt_reg_table[i++].addr = 0x4a00413c; + prcm_ctt_reg_table[i++].addr = 0x4a004140; + prcm_ctt_reg_table[i++].addr = 0x4a004144; + prcm_ctt_reg_table[i++].addr = 0x4a004148; + prcm_ctt_reg_table[i++].addr = 0x4a00414c; + prcm_ctt_reg_table[i++].addr = 0x4a004150; + prcm_ctt_reg_table[i++].addr = 0x4a004160; + prcm_ctt_reg_table[i++].addr = 0x4a004164; + prcm_ctt_reg_table[i++].addr = 0x4a004168; + prcm_ctt_reg_table[i++].addr = 0x4a00416c; + prcm_ctt_reg_table[i++].addr = 0x4a004170; + prcm_ctt_reg_table[i++].addr = 0x4a004188; + prcm_ctt_reg_table[i++].addr = 0x4a00418c; + prcm_ctt_reg_table[i++].addr = 0x4a00419c; + prcm_ctt_reg_table[i++].addr = 0x4a0041a0; + prcm_ctt_reg_table[i++].addr = 0x4a0041a4; + prcm_ctt_reg_table[i++].addr = 0x4a0041a8; + prcm_ctt_reg_table[i++].addr = 0x4a0041ac; + prcm_ctt_reg_table[i++].addr = 0x4a0041b8; + prcm_ctt_reg_table[i++].addr = 0x4a0041bc; + prcm_ctt_reg_table[i++].addr = 0x4a0041c8; + prcm_ctt_reg_table[i++].addr = 0x4a0041cc; + prcm_ctt_reg_table[i++].addr = 0x4a0041dc; + prcm_ctt_reg_table[i++].addr = 0x4a0041e0; + prcm_ctt_reg_table[i++].addr = 0x4a0041e4; + prcm_ctt_reg_table[i++].addr = 0x4a0041e8; + prcm_ctt_reg_table[i++].addr = 0x4a0041ec; + prcm_ctt_reg_table[i++].addr = 0x4a0041f0; + prcm_ctt_reg_table[i++].addr = 0x4a0041f4; + prcm_ctt_reg_table[i++].addr = 0x4a004208; + prcm_ctt_reg_table[i++].addr = 0x4a00420c; + prcm_ctt_reg_table[i++].addr = 0x4a004260; + prcm_ctt_reg_table[i++].addr = 0x4a004264; + prcm_ctt_reg_table[i++].addr = 0x4a004270; + prcm_ctt_reg_table[i++].addr = 0x4a004280; + prcm_ctt_reg_table[i++].addr = 0x4a004400; + prcm_ctt_reg_table[i++].addr = 0x4a004404; + prcm_ctt_reg_table[i++].addr = 0x4a004408; + prcm_ctt_reg_table[i++].addr = 0x4a004420; + prcm_ctt_reg_table[i++].addr = 0x4a004500; + prcm_ctt_reg_table[i++].addr = 0x4a004520; + prcm_ctt_reg_table[i++].addr = 0x4a004528; + prcm_ctt_reg_table[i++].addr = 0x4a004530; + prcm_ctt_reg_table[i++].addr = 0x4a004538; + prcm_ctt_reg_table[i++].addr = 0x4a004540; + prcm_ctt_reg_table[i++].addr = 0x4a004548; + prcm_ctt_reg_table[i++].addr = 0x4a004550; + prcm_ctt_reg_table[i++].addr = 0x4a004558; + prcm_ctt_reg_table[i++].addr = 0x4a004560; + prcm_ctt_reg_table[i++].addr = 0x4a004568; + prcm_ctt_reg_table[i++].addr = 0x4a004570; + prcm_ctt_reg_table[i++].addr = 0x4a004578; + prcm_ctt_reg_table[i++].addr = 0x4a004580; + prcm_ctt_reg_table[i++].addr = 0x4a004588; + prcm_ctt_reg_table[i++].addr = 0x4a008100; + prcm_ctt_reg_table[i++].addr = 0x4a008104; + prcm_ctt_reg_table[i++].addr = 0x4a008108; + prcm_ctt_reg_table[i++].addr = 0x4a008110; + prcm_ctt_reg_table[i++].addr = 0x4a008114; + prcm_ctt_reg_table[i++].addr = 0x4a008118; + prcm_ctt_reg_table[i++].addr = 0x4a00811c; + prcm_ctt_reg_table[i++].addr = 0x4a008124; + prcm_ctt_reg_table[i++].addr = 0x4a008128; + prcm_ctt_reg_table[i++].addr = 0x4a00812c; + prcm_ctt_reg_table[i++].addr = 0x4a008130; + prcm_ctt_reg_table[i++].addr = 0x4a008138; + prcm_ctt_reg_table[i++].addr = 0x4a008140; + prcm_ctt_reg_table[i++].addr = 0x4a008144; + prcm_ctt_reg_table[i++].addr = 0x4a008148; + prcm_ctt_reg_table[i++].addr = 0x4a00814c; + prcm_ctt_reg_table[i++].addr = 0x4a008150; + prcm_ctt_reg_table[i++].addr = 0x4a008154; + prcm_ctt_reg_table[i++].addr = 0x4a008158; + prcm_ctt_reg_table[i++].addr = 0x4a00815c; + prcm_ctt_reg_table[i++].addr = 0x4a008160; + prcm_ctt_reg_table[i++].addr = 0x4a008164; + prcm_ctt_reg_table[i++].addr = 0x4a008180; + prcm_ctt_reg_table[i++].addr = 0x4a008184; + prcm_ctt_reg_table[i++].addr = 0x4a008188; + prcm_ctt_reg_table[i++].addr = 0x4a00818c; + prcm_ctt_reg_table[i++].addr = 0x4a008190; + prcm_ctt_reg_table[i++].addr = 0x4a0081b4; + prcm_ctt_reg_table[i++].addr = 0x4a008600; + prcm_ctt_reg_table[i++].addr = 0x4a008628; + prcm_ctt_reg_table[i++].addr = 0x4a008630; + prcm_ctt_reg_table[i++].addr = 0x4a008638; + prcm_ctt_reg_table[i++].addr = 0x4a008640; + prcm_ctt_reg_table[i++].addr = 0x4a008700; + prcm_ctt_reg_table[i++].addr = 0x4a008708; + prcm_ctt_reg_table[i++].addr = 0x4a008720; + prcm_ctt_reg_table[i++].addr = 0x4a008800; + prcm_ctt_reg_table[i++].addr = 0x4a008808; + prcm_ctt_reg_table[i++].addr = 0x4a008820; + prcm_ctt_reg_table[i++].addr = 0x4a008828; + prcm_ctt_reg_table[i++].addr = 0x4a008830; + prcm_ctt_reg_table[i++].addr = 0x4a008900; + prcm_ctt_reg_table[i++].addr = 0x4a008904; + prcm_ctt_reg_table[i++].addr = 0x4a008908; + prcm_ctt_reg_table[i++].addr = 0x4a008920; + prcm_ctt_reg_table[i++].addr = 0x4a008a00; + prcm_ctt_reg_table[i++].addr = 0x4a008a04; + prcm_ctt_reg_table[i++].addr = 0x4a008a08; + prcm_ctt_reg_table[i++].addr = 0x4a008a20; + prcm_ctt_reg_table[i++].addr = 0x4a008b00; + prcm_ctt_reg_table[i++].addr = 0x4a008b20; + prcm_ctt_reg_table[i++].addr = 0x4a008b28; + prcm_ctt_reg_table[i++].addr = 0x4a008b30; + prcm_ctt_reg_table[i++].addr = 0x4a008b38; + prcm_ctt_reg_table[i++].addr = 0x4a008b40; + prcm_ctt_reg_table[i++].addr = 0x4a008c00; + prcm_ctt_reg_table[i++].addr = 0x4a008c04; + prcm_ctt_reg_table[i++].addr = 0x4a008c08; + prcm_ctt_reg_table[i++].addr = 0x4a008c20; + prcm_ctt_reg_table[i++].addr = 0x4a008c30; + prcm_ctt_reg_table[i++].addr = 0x4a008d00; + prcm_ctt_reg_table[i++].addr = 0x4a008d08; + prcm_ctt_reg_table[i++].addr = 0x4a008d20; + prcm_ctt_reg_table[i++].addr = 0x4a008d28; + prcm_ctt_reg_table[i++].addr = 0x4a008d30; + prcm_ctt_reg_table[i++].addr = 0x4a008d38; + prcm_ctt_reg_table[i++].addr = 0x4a008e00; + prcm_ctt_reg_table[i++].addr = 0x4a008e20; + prcm_ctt_reg_table[i++].addr = 0x4a008e28; + prcm_ctt_reg_table[i++].addr = 0x4a008e40; + prcm_ctt_reg_table[i++].addr = 0x4a008f00; + prcm_ctt_reg_table[i++].addr = 0x4a008f04; + prcm_ctt_reg_table[i++].addr = 0x4a008f08; + prcm_ctt_reg_table[i++].addr = 0x4a008f20; + prcm_ctt_reg_table[i++].addr = 0x4a008f28; + prcm_ctt_reg_table[i++].addr = 0x4a009000; + prcm_ctt_reg_table[i++].addr = 0x4a009004; + prcm_ctt_reg_table[i++].addr = 0x4a009008; + prcm_ctt_reg_table[i++].addr = 0x4a009020; + prcm_ctt_reg_table[i++].addr = 0x4a009028; + prcm_ctt_reg_table[i++].addr = 0x4a009100; + prcm_ctt_reg_table[i++].addr = 0x4a009104; + prcm_ctt_reg_table[i++].addr = 0x4a009108; + prcm_ctt_reg_table[i++].addr = 0x4a009120; + prcm_ctt_reg_table[i++].addr = 0x4a009200; + prcm_ctt_reg_table[i++].addr = 0x4a009204; + prcm_ctt_reg_table[i++].addr = 0x4a009208; + prcm_ctt_reg_table[i++].addr = 0x4a009220; + prcm_ctt_reg_table[i++].addr = 0x4a009300; + prcm_ctt_reg_table[i++].addr = 0x4a009304; + prcm_ctt_reg_table[i++].addr = 0x4a009308; + prcm_ctt_reg_table[i++].addr = 0x4a009328; + prcm_ctt_reg_table[i++].addr = 0x4a009330; + prcm_ctt_reg_table[i++].addr = 0x4a009338; + prcm_ctt_reg_table[i++].addr = 0x4a009358; + prcm_ctt_reg_table[i++].addr = 0x4a009360; + prcm_ctt_reg_table[i++].addr = 0x4a009368; + prcm_ctt_reg_table[i++].addr = 0x4a0093d0; + prcm_ctt_reg_table[i++].addr = 0x4a0093e0; + prcm_ctt_reg_table[i++].addr = 0x4a009400; + prcm_ctt_reg_table[i++].addr = 0x4a009408; + prcm_ctt_reg_table[i++].addr = 0x4a009428; + prcm_ctt_reg_table[i++].addr = 0x4a009430; + prcm_ctt_reg_table[i++].addr = 0x4a009438; + prcm_ctt_reg_table[i++].addr = 0x4a009440; + prcm_ctt_reg_table[i++].addr = 0x4a009448; + prcm_ctt_reg_table[i++].addr = 0x4a009450; + prcm_ctt_reg_table[i++].addr = 0x4a009458; + prcm_ctt_reg_table[i++].addr = 0x4a009460; + prcm_ctt_reg_table[i++].addr = 0x4a009468; + prcm_ctt_reg_table[i++].addr = 0x4a009470; + prcm_ctt_reg_table[i++].addr = 0x4a009478; + prcm_ctt_reg_table[i++].addr = 0x4a009480; + prcm_ctt_reg_table[i++].addr = 0x4a009488; + prcm_ctt_reg_table[i++].addr = 0x4a0094a0; + prcm_ctt_reg_table[i++].addr = 0x4a0094a8; + prcm_ctt_reg_table[i++].addr = 0x4a0094b0; + prcm_ctt_reg_table[i++].addr = 0x4a0094b8; + prcm_ctt_reg_table[i++].addr = 0x4a0094c0; + prcm_ctt_reg_table[i++].addr = 0x4a0094e0; + prcm_ctt_reg_table[i++].addr = 0x4a0094f0; + prcm_ctt_reg_table[i++].addr = 0x4a0094f8; + prcm_ctt_reg_table[i++].addr = 0x4a009500; + prcm_ctt_reg_table[i++].addr = 0x4a009508; + prcm_ctt_reg_table[i++].addr = 0x4a009520; + prcm_ctt_reg_table[i++].addr = 0x4a009528; + prcm_ctt_reg_table[i++].addr = 0x4a009538; + prcm_ctt_reg_table[i++].addr = 0x4a009540; + prcm_ctt_reg_table[i++].addr = 0x4a009548; + prcm_ctt_reg_table[i++].addr = 0x4a009550; + prcm_ctt_reg_table[i++].addr = 0x4a009558; + prcm_ctt_reg_table[i++].addr = 0x4a009560; + prcm_ctt_reg_table[i++].addr = 0x4a306100; + prcm_ctt_reg_table[i++].addr = 0x4a306108; + prcm_ctt_reg_table[i++].addr = 0x4a30610c; + prcm_ctt_reg_table[i++].addr = 0x4a306110; + prcm_ctt_reg_table[i++].addr = 0x4a307800; + prcm_ctt_reg_table[i++].addr = 0x4a307820; + prcm_ctt_reg_table[i++].addr = 0x4a307830; + prcm_ctt_reg_table[i++].addr = 0x4a307838; + prcm_ctt_reg_table[i++].addr = 0x4a307840; + prcm_ctt_reg_table[i++].addr = 0x4a307850; + prcm_ctt_reg_table[i++].addr = 0x4a307860; + prcm_ctt_reg_table[i++].addr = 0x4a307878; + prcm_ctt_reg_table[i++].addr = 0x4a307888; + prcm_ctt_reg_table[i++].addr = 0x4a307a00; + prcm_ctt_reg_table[i++].addr = 0x4a307a08; + prcm_ctt_reg_table[i++].addr = 0x4a307a20; + prcm_ctt_reg_table[i++].addr = 0x4a30a000; + prcm_ctt_reg_table[i++].addr = 0x4a30a100; + prcm_ctt_reg_table[i++].addr = 0x4a30a104; + prcm_ctt_reg_table[i++].addr = 0x4a30a110; + prcm_ctt_reg_table[i++].addr = 0x4a30a11c; + prcm_ctt_reg_table[i++].addr = 0x4a30a204; + prcm_ctt_reg_table[i++].addr = 0x4a30a208; + prcm_ctt_reg_table[i++].addr = 0x4a30a210; + prcm_ctt_reg_table[i++].addr = 0x4a30a214; + prcm_ctt_reg_table[i++].addr = 0x4a30a218; + prcm_ctt_reg_table[i++].addr = 0x4a30a21c; + prcm_ctt_reg_table[i++].addr = 0x4a30a220; + prcm_ctt_reg_table[i++].addr = 0x4a30a224; + prcm_ctt_reg_table[i++].addr = 0x4a30a234; + prcm_ctt_reg_table[i++].addr = 0x4a30a310; + prcm_ctt_reg_table[i++].addr = 0x4a30a314; + prcm_ctt_reg_table[i++].addr = 0x4a30a318; + prcm_ctt_reg_table[i++].addr = 0x4a30a31c; + prcm_ctt_reg_table[i++].addr = 0x4a30a320; + prcm_ctt_reg_table[i++].addr = 0x4a30a324; + prcm_ctt_reg_table[i++].addr = 0x4a30a400; + prcm_ctt_reg_table[i++].addr = 0x4a30a41c; + prcm_ctt_reg_table[i++].addr = 0x4a30a420; + prcm_ctt_reg_table[i++].addr = 0x4a30a510; + prcm_ctt_reg_table[i++].addr = 0x4a30a514; + prcm_ctt_reg_table[i++].addr = 0x4a30a51c; + prcm_ctt_reg_table[i].addr = 0; + + dprintf("prcm_ctt_reg_table last index=%d, size=%d\n", i, i + 1); + + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/ctt44xx.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/ctt44xx.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/ctt44xx.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/ctt44xx.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,57 @@ +/* + * + * @Component OMAPCONF + * @Filename ctt44xx.h + * @Description Display PRCM registers in a format that can be + * imported into the clock tree tool (CTT) + * @Author Jon Hunter (jon-hunter@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __CTT44XX_H__ +#define __CTT44XX_H__ + + +int ctt44xx_dump(void); +int ctt44xx_rd1_export(char *filename); + +/* DEPRECATED, DO NOT USE ANYMORE */ +int ctt44xx_main(int argc, char *argv[]); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/display44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/display44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/display44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/display44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1493 @@ +/* + * + * @Component OMAPCONF + * @Filename display44xx.c + * @Description OMAP4 Display Configuration + * @Author Erwan Petillon (e-petillon@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* #define DISPLAY44XX_DEBUG */ +#ifdef DISPLAY44XX_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + +#define DSS_REG_TABLE_SIZE 5 +#define DSI1_REG_TABLE_SIZE 64 +#define DSI1_PHY_REG_TABLE_SIZE 7 +#define DSI1_PLL_REG_TABLE_SIZE 10 +#define DSI2_REG_TABLE_SIZE 64 +#define DSI2_PHY_REG_TABLE_SIZE 7 +#define DSI2_PLL_REG_TABLE_SIZE 10 +#define RFBI_REG_TABLE_SIZE 25 +#define VENC_REG_TABLE_SIZE 44 +#define DISPC_REG_TABLE_SIZE 351 + + +typedef enum { + HDMI_PHY_48MHz_FCLK, + DSS_ALWON_SYS_CLK, + DSS_FCLK, + DSS_L3_ICLK, + OPTFCLK_TV_FCLK, + OPTFCLK_SYS_CLK, + OPTFCLK_48MHZ_CLK, + OPTFCLK_DSSCLK, + DISPLAY44XX_CLOCK_ID_MAX +} display44xx_clock_id; + + +reg_table dss_reg_table[DSS_REG_TABLE_SIZE]; +reg_table dispc_reg_table[DISPC_REG_TABLE_SIZE]; +reg_table dsi1_reg_table[DSI1_REG_TABLE_SIZE]; +reg_table dsi1_phy_reg_table[DSI1_PHY_REG_TABLE_SIZE]; +reg_table dsi1_pll_reg_table[DSI1_PLL_REG_TABLE_SIZE]; +reg_table dsi2_reg_table[DSI2_REG_TABLE_SIZE]; +reg_table dsi2_phy_reg_table[DSI2_PHY_REG_TABLE_SIZE]; +reg_table dsi2_pll_reg_table[DSI2_PLL_REG_TABLE_SIZE]; +reg_table rfbi_reg_table[RFBI_REG_TABLE_SIZE]; +reg_table venc_reg_table[VENC_REG_TABLE_SIZE]; + +static unsigned int init_done = 0; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION display44xx_init_regtable + * @BRIEF initialize regtable + * @RETURNS 0 + * OMAPCONF_ERR_CPU + * @DESCRIPTION initialize regtable + *//*------------------------------------------------------------------------ */ +int display44xx_init_regtable(void) +{ + int i = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + /* Init DSS registers table */ + strcpy(dss_reg_table[i].name , "DSS_REVISION"); + dss_reg_table[i++].addr = DSS_REVISION; + strcpy(dss_reg_table[i].name , "DSS_SYSSTATUS"); + dss_reg_table[i++].addr = DSS_SYSSTATUS; + strcpy(dss_reg_table[i].name , "DSS_CTRL"); + dss_reg_table[i++].addr = DSS_CTRL; + strcpy(dss_reg_table[i].name , "DSS_STATUS"); + dss_reg_table[i++].addr = DSS_STATUS; + strcpy(dss_reg_table[i].name, "END"); + dss_reg_table[i].addr = 0; + + /* Init DSI1 PHY registers table */ + i = 0; + strcpy(dsi1_phy_reg_table[i].name , "DSI1_PHY_REGISTER0"); + dsi1_phy_reg_table[i++].addr = DSI1_PHY_REGISTER0; + strcpy(dsi1_phy_reg_table[i].name , "DSI1_PHY_REGISTER1"); + dsi1_phy_reg_table[i++].addr = DSI1_PHY_REGISTER1; + strcpy(dsi1_phy_reg_table[i].name , "DSI1_PHY_REGISTER2"); + dsi1_phy_reg_table[i++].addr = DSI1_PHY_REGISTER2; + strcpy(dsi1_phy_reg_table[i].name , "DSI1_PHY_REGISTER3"); + dsi1_phy_reg_table[i++].addr = DSI1_PHY_REGISTER3; + strcpy(dsi1_phy_reg_table[i].name , "DSI1_PHY_REGISTER4"); + dsi1_phy_reg_table[i++].addr = DSI1_PHY_REGISTER4; + strcpy(dsi1_phy_reg_table[i].name , "DSI1_PHY_REGISTER5"); + dsi1_phy_reg_table[i++].addr = DSI1_PHY_REGISTER5; + strcpy(dsi1_phy_reg_table[i].name, "END"); + dsi1_phy_reg_table[i].addr = 0; + + /* Init DSI1 PHY registers table */ + i = 0; + strcpy(dsi1_reg_table[i].name , "DSI1_REVISION"); + dsi1_reg_table[i++].addr = DSI1_REVISION; + strcpy(dsi1_reg_table[i].name , "DSI1_SYSCONFIG"); + dsi1_reg_table[i++].addr = DSI1_SYSCONFIG; + strcpy(dsi1_reg_table[i].name , "DSI1_SYSSTATUS"); + dsi1_reg_table[i++].addr = DSI1_SYSSTATUS; + strcpy(dsi1_reg_table[i].name , "DSI1_IRQSTATUS"); + dsi1_reg_table[i++].addr = DSI1_IRQSTATUS; + strcpy(dsi1_reg_table[i].name , "DSI1_IRQENABLE"); + dsi1_reg_table[i++].addr = DSI1_IRQENABLE; + strcpy(dsi1_reg_table[i].name , "DSI1_CTRL"); + dsi1_reg_table[i++].addr = DSI1_CTRL; + strcpy(dsi1_reg_table[i].name , "DSI1_GNQ"); + dsi1_reg_table[i++].addr = DSI1_GNQ; + strcpy(dsi1_reg_table[i].name , "DSI1_COMPLEXIO_CFG1"); + dsi1_reg_table[i++].addr = DSI1_COMPLEXIO_CFG1; + strcpy(dsi1_reg_table[i].name , "DSI1_COMPLEXIO_IRQSTATUS"); + dsi1_reg_table[i++].addr = DSI1_COMPLEXIO_IRQSTATUS; + strcpy(dsi1_reg_table[i].name , "DSI1_COMPLEXIO_IRQENABLE"); + dsi1_reg_table[i++].addr = DSI1_COMPLEXIO_IRQENABLE; + strcpy(dsi1_reg_table[i].name , "DSI1_CLK_CTRL"); + dsi1_reg_table[i++].addr = DSI1_CLK_CTRL; + strcpy(dsi1_reg_table[i].name , "DSI1_TIMING1"); + dsi1_reg_table[i++].addr = DSI1_TIMING1; + strcpy(dsi1_reg_table[i].name , "DSI1_TIMING2"); + dsi1_reg_table[i++].addr = DSI1_TIMING2; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING1"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING1; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING2"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING2; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING3"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING3; + strcpy(dsi1_reg_table[i].name , "DSI1_CLK_TIMING"); + dsi1_reg_table[i++].addr = DSI1_CLK_TIMING; + strcpy(dsi1_reg_table[i].name , "DSI1_TX_FIFO_VC_SIZE"); + dsi1_reg_table[i++].addr = DSI1_TX_FIFO_VC_SIZE; + strcpy(dsi1_reg_table[i].name , "DSI1_RX_FIFO_VC_SIZE"); + dsi1_reg_table[i++].addr = DSI1_RX_FIFO_VC_SIZE; + strcpy(dsi1_reg_table[i].name , "DSI1_COMPLEXIO_CFG2"); + dsi1_reg_table[i++].addr = DSI1_COMPLEXIO_CFG2; + strcpy(dsi1_reg_table[i].name , "DSI1_RX_FIFO_VC_FULLNESS"); + dsi1_reg_table[i++].addr = DSI1_RX_FIFO_VC_FULLNESS; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING4"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING4; + strcpy(dsi1_reg_table[i].name , "DSI1_TX_FIFO_VC_EMPTINESS"); + dsi1_reg_table[i++].addr = DSI1_TX_FIFO_VC_EMPTINESS; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING5"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING5; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING6"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING6; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING7"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING7; + strcpy(dsi1_reg_table[i].name , "DSI1_STOPCLK_TIMING"); + dsi1_reg_table[i++].addr = DSI1_STOPCLK_TIMING; + strcpy(dsi1_reg_table[i].name , "DSI1_CTRL2"); + dsi1_reg_table[i++].addr = DSI1_CTRL2; + strcpy(dsi1_reg_table[i].name , "DSI1_VM_TIMING8"); + dsi1_reg_table[i++].addr = DSI1_VM_TIMING8; + strcpy(dsi1_reg_table[i].name , "DSI1_TE_HSYNC_WIDTH_0"); + dsi1_reg_table[i++].addr = DSI1_TE_HSYNC_WIDTH_0; + strcpy(dsi1_reg_table[i].name , "DSI1_TE_VSYNC_WIDTH_0"); + dsi1_reg_table[i++].addr = DSI1_TE_VSYNC_WIDTH_0; + strcpy(dsi1_reg_table[i].name , "DSI1_TE_HSYNC_NUMBER_0"); + dsi1_reg_table[i++].addr = DSI1_TE_HSYNC_NUMBER_0; + strcpy(dsi1_reg_table[i].name , "DSI1_TE_HSYNC_WIDTH_1"); + dsi1_reg_table[i++].addr = DSI1_TE_HSYNC_WIDTH_1; + strcpy(dsi1_reg_table[i].name , "DSI1_TE_VSYNC_WIDTH_1"); + dsi1_reg_table[i++].addr = DSI1_TE_VSYNC_WIDTH_1; + strcpy(dsi1_reg_table[i].name , "DSI1_TE_HSYNC_NUMBER_1"); + dsi1_reg_table[i++].addr = DSI1_TE_HSYNC_NUMBER_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_CTRL_1"); + dsi1_reg_table[i++].addr = DSI1_VC_CTRL_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_TE_1"); + dsi1_reg_table[i++].addr = DSI1_VC_TE_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_HEADER_1"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_HEADER_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_PAYLOAD_1"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_PAYLOAD_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_SHORT_PACKET_HEADER_1"); + dsi1_reg_table[i++].addr = DSI1_VC_SHORT_PACKET_HEADER_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQSTATUS_1"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQSTATUS_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQENABLE_1"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQENABLE_1; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_CTRL_2"); + dsi1_reg_table[i++].addr = DSI1_VC_CTRL_2; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_TE_2"); + dsi1_reg_table[i++].addr = DSI1_VC_TE_2; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_HEADER_2"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_HEADER_2; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_PAYLOAD_2"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_PAYLOAD_2; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_SHORT_PACKET_HEADER_2"); + dsi1_reg_table[i++].addr = DSI1_VC_SHORT_PACKET_HEADER_2; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQSTATUS_2"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQSTATUS_2; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQENABLE_2"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQENABLE_2; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_CTRL_3"); + dsi1_reg_table[i++].addr = DSI1_VC_CTRL_3; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_TE_3"); + dsi1_reg_table[i++].addr = DSI1_VC_TE_3; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_HEADER_3"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_HEADER_3; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_PAYLOAD_3"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_PAYLOAD_3; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_SHORT_PACKET_HEADER_3"); + dsi1_reg_table[i++].addr = DSI1_VC_SHORT_PACKET_HEADER_3; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQSTATUS_3"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQSTATUS_3; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQENABLE_3"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQENABLE_3; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_CTRL_4"); + dsi1_reg_table[i++].addr = DSI1_VC_CTRL_4; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_TE_4"); + dsi1_reg_table[i++].addr = DSI1_VC_TE_4; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_HEADER_4"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_HEADER_4; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_LONG_PACKET_PAYLOAD_4"); + dsi1_reg_table[i++].addr = DSI1_VC_LONG_PACKET_PAYLOAD_4; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_SHORT_PACKET_HEADER_4"); + dsi1_reg_table[i++].addr = DSI1_VC_SHORT_PACKET_HEADER_4; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQSTATUS_4"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQSTATUS_4; + strcpy(dsi1_reg_table[i].name , "DSI1_VC_IRQENABLE_4"); + dsi1_reg_table[i++].addr = DSI1_VC_IRQENABLE_4; + strcpy(dsi1_reg_table[i].name, "END"); + dsi1_reg_table[i].addr = 0; + + + /* Init DSI1 PLL registers table */ + i = 0; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_CONTROL"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_CONTROL; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_STATUS"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_STATUS; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_GO"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_GO; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_CONFIGURATION1"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_CONFIGURATION1; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_CONFIGURATION2"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_CONFIGURATION2; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_CONFIGURATION3"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_CONFIGURATION3; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_SSC_CONFIGURATION1"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_SSC_CONFIGURATION1; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_SSC_CONFIGURATION2"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_SSC_CONFIGURATION2; + strcpy(dsi1_pll_reg_table[i].name , "DSI1_PLL_CONFIG"); + dsi1_pll_reg_table[i++].addr = DSI1_PLL_CONFIG; + strcpy(dsi1_pll_reg_table[i].name, "END"); + dsi1_pll_reg_table[i].addr = 0; + + /* Init DSI2 PE registers table */ + i = 0; + strcpy(dsi2_reg_table[i].name , "DSI2_REVISION"); + dsi2_reg_table[i++].addr = DSI2_REVISION; + strcpy(dsi2_reg_table[i].name , "DSI2_SYSCONFIG"); + dsi2_reg_table[i++].addr = DSI2_SYSCONFIG; + strcpy(dsi2_reg_table[i].name , "DSI2_SYSSTATUS"); + dsi2_reg_table[i++].addr = DSI2_SYSSTATUS; + strcpy(dsi2_reg_table[i].name , "DSI2_IRQSTATUS"); + dsi2_reg_table[i++].addr = DSI2_IRQSTATUS; + strcpy(dsi2_reg_table[i].name , "DSI2_IRQENABLE"); + dsi2_reg_table[i++].addr = DSI2_IRQENABLE; + strcpy(dsi2_reg_table[i].name , "DSI2_CTRL"); + dsi2_reg_table[i++].addr = DSI2_CTRL; + strcpy(dsi2_reg_table[i].name , "DSI2_GNQ"); + dsi2_reg_table[i++].addr = DSI2_GNQ; + strcpy(dsi2_reg_table[i].name , "DSI2_COMPLEXIO_CFG1"); + dsi2_reg_table[i++].addr = DSI2_COMPLEXIO_CFG1; + strcpy(dsi2_reg_table[i].name , "DSI2_COMPLEXIO_IRQSTATUS"); + dsi2_reg_table[i++].addr = DSI2_COMPLEXIO_IRQSTATUS; + strcpy(dsi2_reg_table[i].name , "DSI2_COMPLEXIO_IRQENABLE"); + dsi2_reg_table[i++].addr = DSI2_COMPLEXIO_IRQENABLE; + strcpy(dsi2_reg_table[i].name , "DSI2_CLK_CTRL"); + dsi2_reg_table[i++].addr = DSI2_CLK_CTRL; + strcpy(dsi2_reg_table[i].name , "DSI2_TIMING1"); + dsi2_reg_table[i++].addr = DSI2_TIMING1; + strcpy(dsi2_reg_table[i].name , "DSI2_TIMING2"); + dsi2_reg_table[i++].addr = DSI2_TIMING2; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING1"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING1; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING2"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING2; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING3"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING3; + strcpy(dsi2_reg_table[i].name , "DSI2_CLK_TIMING"); + dsi2_reg_table[i++].addr = DSI2_CLK_TIMING; + strcpy(dsi2_reg_table[i].name , "DSI2_TX_FIFO_VC_SIZE"); + dsi2_reg_table[i++].addr = DSI2_TX_FIFO_VC_SIZE; + strcpy(dsi2_reg_table[i].name , "DSI2_RX_FIFO_VC_SIZE"); + dsi2_reg_table[i++].addr = DSI2_RX_FIFO_VC_SIZE; + strcpy(dsi2_reg_table[i].name , "DSI2_COMPLEXIO_CFG2"); + dsi2_reg_table[i++].addr = DSI2_COMPLEXIO_CFG2; + strcpy(dsi2_reg_table[i].name , "DSI2_RX_FIFO_VC_FULLNESS"); + dsi2_reg_table[i++].addr = DSI2_RX_FIFO_VC_FULLNESS; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING4"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING4; + strcpy(dsi2_reg_table[i].name , "DSI2_TX_FIFO_VC_EMPTINESS"); + dsi2_reg_table[i++].addr = DSI2_TX_FIFO_VC_EMPTINESS; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING5"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING5; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING6"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING6; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING7"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING7; + strcpy(dsi2_reg_table[i].name , "DSI2_STOPCLK_TIMING"); + dsi2_reg_table[i++].addr = DSI2_STOPCLK_TIMING; + strcpy(dsi2_reg_table[i].name , "DSI2_CTRL2"); + dsi2_reg_table[i++].addr = DSI2_CTRL2; + strcpy(dsi2_reg_table[i].name , "DSI2_VM_TIMING8"); + dsi2_reg_table[i++].addr = DSI2_VM_TIMING8; + strcpy(dsi2_reg_table[i].name , "DSI2_TE_HSYNC_WIDTH_0"); + dsi2_reg_table[i++].addr = DSI2_TE_HSYNC_WIDTH_0; + strcpy(dsi2_reg_table[i].name , "DSI2_TE_VSYNC_WIDTH_0"); + dsi2_reg_table[i++].addr = DSI2_TE_VSYNC_WIDTH_0; + strcpy(dsi2_reg_table[i].name , "DSI2_TE_HSYNC_NUMBER_0"); + dsi2_reg_table[i++].addr = DSI2_TE_HSYNC_NUMBER_0; + strcpy(dsi2_reg_table[i].name , "DSI2_TE_HSYNC_WIDTH_1"); + dsi2_reg_table[i++].addr = DSI2_TE_HSYNC_WIDTH_1; + strcpy(dsi2_reg_table[i].name , "DSI2_TE_VSYNC_WIDTH_1"); + dsi2_reg_table[i++].addr = DSI2_TE_VSYNC_WIDTH_1; + strcpy(dsi2_reg_table[i].name , "DSI2_TE_HSYNC_NUMBER_1"); + dsi2_reg_table[i++].addr = DSI2_TE_HSYNC_NUMBER_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_CTRL_1"); + dsi2_reg_table[i++].addr = DSI2_VC_CTRL_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_TE_1"); + dsi2_reg_table[i++].addr = DSI2_VC_TE_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_HEADER_1"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_HEADER_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_PAYLOAD_1"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_PAYLOAD_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_SHORT_PACKET_HEADER_1"); + dsi2_reg_table[i++].addr = DSI2_VC_SHORT_PACKET_HEADER_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQSTATUS_1"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQSTATUS_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQENABLE_1"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQENABLE_1; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_CTRL_2"); + dsi2_reg_table[i++].addr = DSI2_VC_CTRL_2; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_TE_2"); + dsi2_reg_table[i++].addr = DSI2_VC_TE_2; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_HEADER_2"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_HEADER_2; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_PAYLOAD_2"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_PAYLOAD_2; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_SHORT_PACKET_HEADER_2"); + dsi2_reg_table[i++].addr = DSI2_VC_SHORT_PACKET_HEADER_2; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQSTATUS_2"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQSTATUS_2; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQENABLE_2"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQENABLE_2; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_CTRL_3"); + dsi2_reg_table[i++].addr = DSI2_VC_CTRL_3; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_TE_3"); + dsi2_reg_table[i++].addr = DSI2_VC_TE_3; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_HEADER_3"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_HEADER_3; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_PAYLOAD_3"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_PAYLOAD_3; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_SHORT_PACKET_HEADER_3"); + dsi2_reg_table[i++].addr = DSI2_VC_SHORT_PACKET_HEADER_3; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQSTATUS_3"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQSTATUS_3; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQENABLE_3"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQENABLE_3; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_CTRL_4"); + dsi2_reg_table[i++].addr = DSI2_VC_CTRL_4; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_TE_4"); + dsi2_reg_table[i++].addr = DSI2_VC_TE_4; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_HEADER_4"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_HEADER_4; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_LONG_PACKET_PAYLOAD_4"); + dsi2_reg_table[i++].addr = DSI2_VC_LONG_PACKET_PAYLOAD_4; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_SHORT_PACKET_HEADER_4"); + dsi2_reg_table[i++].addr = DSI2_VC_SHORT_PACKET_HEADER_4; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQSTATUS_4"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQSTATUS_4; + strcpy(dsi2_reg_table[i].name , "DSI2_VC_IRQENABLE_4"); + dsi2_reg_table[i++].addr = DSI2_VC_IRQENABLE_4; + strcpy(dsi2_reg_table[i].name, "END"); + dsi2_reg_table[i].addr = 0; + + /* Init DSI2 PHY registers table */ + i = 0; + strcpy(dsi2_phy_reg_table[i].name , "DSI2_PHY_REGISTER0"); + dsi2_phy_reg_table[i++].addr = DSI2_PHY_REGISTER0; + strcpy(dsi2_phy_reg_table[i].name , "DSI2_PHY_REGISTER1"); + dsi2_phy_reg_table[i++].addr = DSI2_PHY_REGISTER1; + strcpy(dsi2_phy_reg_table[i].name , "DSI2_PHY_REGISTER2"); + dsi2_phy_reg_table[i++].addr = DSI2_PHY_REGISTER2; + strcpy(dsi2_phy_reg_table[i].name , "DSI2_PHY_REGISTER3"); + dsi2_phy_reg_table[i++].addr = DSI2_PHY_REGISTER3; + strcpy(dsi2_phy_reg_table[i].name , "DSI2_PHY_REGISTER4"); + dsi2_phy_reg_table[i++].addr = DSI2_PHY_REGISTER4; + strcpy(dsi2_phy_reg_table[i].name , "DSI2_PHY_REGISTER5"); + dsi2_phy_reg_table[i++].addr = DSI2_PHY_REGISTER5; + strcpy(dsi2_phy_reg_table[i].name, "END"); + dsi2_phy_reg_table[i].addr = 0; + + /* Init DSI2 PLL registers table */ + i = 0; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_CONTROL"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_CONTROL; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_STATUS"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_STATUS; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_GO"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_GO; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_CONFIGURATION1"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_CONFIGURATION1; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_CONFIGURATION2"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_CONFIGURATION2; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_CONFIGURATION3"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_CONFIGURATION3; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_SSC_CONFIGURATION1"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_SSC_CONFIGURATION1; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_SSC_CONFIGURATION2"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_SSC_CONFIGURATION2; + strcpy(dsi2_pll_reg_table[i].name , "DSI2_PLL_CONFIG"); + dsi2_pll_reg_table[i++].addr = DSI2_PLL_CONFIG; + strcpy(dsi2_pll_reg_table[i].name, "END"); + dsi2_pll_reg_table[i].addr = 0; + + /* Init RFBI registers table */ + i = 0; + strcpy(rfbi_reg_table[i].name , "RFBI_REVISION"); + rfbi_reg_table[i++].addr = RFBI_REVISION; + strcpy(rfbi_reg_table[i].name , "RFBI_SYSCONFIG"); + rfbi_reg_table[i++].addr = RFBI_SYSCONFIG; + strcpy(rfbi_reg_table[i].name , "RFBI_SYSSTATUS"); + rfbi_reg_table[i++].addr = RFBI_SYSSTATUS; + strcpy(rfbi_reg_table[i].name , "RFBI_CONTROL"); + rfbi_reg_table[i++].addr = RFBI_CONTROL; + strcpy(rfbi_reg_table[i].name , "RFBI_PIXEL_CNT"); + rfbi_reg_table[i++].addr = RFBI_PIXEL_CNT; + strcpy(rfbi_reg_table[i].name , "RFBI_LINE_NUMBER"); + rfbi_reg_table[i++].addr = RFBI_LINE_NUMBER; + strcpy(rfbi_reg_table[i].name , "RFBI_CMD"); + rfbi_reg_table[i++].addr = RFBI_CMD; + strcpy(rfbi_reg_table[i].name , "RFBI_PARAM"); + rfbi_reg_table[i++].addr = RFBI_PARAM; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA"); + rfbi_reg_table[i++].addr = RFBI_DATA; + strcpy(rfbi_reg_table[i].name , "RFBI_READ"); + rfbi_reg_table[i++].addr = RFBI_READ; + strcpy(rfbi_reg_table[i].name , "RFBI_STATUS"); + rfbi_reg_table[i++].addr = RFBI_STATUS; + strcpy(rfbi_reg_table[i].name , "RFBI_CONFIG"); + rfbi_reg_table[i++].addr = RFBI_CONFIG; + strcpy(rfbi_reg_table[i].name , "RFBI_ONOFF_TIME"); + rfbi_reg_table[i++].addr = RFBI_ONOFF_TIME; + strcpy(rfbi_reg_table[i].name , "RFBI_CYCLE_TIME"); + rfbi_reg_table[i++].addr = RFBI_CYCLE_TIME; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE0"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE0; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE1"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE1; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE2"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE2; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE3"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE3; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE4"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE4; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE5"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE5; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE6"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE6; + strcpy(rfbi_reg_table[i].name , "RFBI_DATA_CYCLE7"); + rfbi_reg_table[i++].addr = RFBI_DATA_CYCLE7; + strcpy(rfbi_reg_table[i].name , "RFBI_VSYNC_WIDTH"); + rfbi_reg_table[i++].addr = RFBI_VSYNC_WIDTH; + strcpy(rfbi_reg_table[i].name , "RFBI_HSYNC_WIDTH"); + rfbi_reg_table[i++].addr = RFBI_HSYNC_WIDTH; + strcpy(rfbi_reg_table[i].name, "END"); + rfbi_reg_table[i].addr = 0; + + /* Init VENC registers table */ + i = 0; + strcpy(venc_reg_table[i].name , "VENC_REV_ID"); + venc_reg_table[i++].addr = VENC_REV_ID; + strcpy(venc_reg_table[i].name , "VENC_STATUS"); + venc_reg_table[i++].addr = VENC_STATUS; + strcpy(venc_reg_table[i].name , "VENC_F_CONTROL"); + venc_reg_table[i++].addr = VENC_F_CONTROL; + strcpy(venc_reg_table[i].name , "VENC_VIDOUT_CTRL"); + venc_reg_table[i++].addr = VENC_VIDOUT_CTRL; + strcpy(venc_reg_table[i].name , "VENC_SYNC_CTRL"); + venc_reg_table[i++].addr = VENC_SYNC_CTRL; + strcpy(venc_reg_table[i].name , "VENC_LLEN"); + venc_reg_table[i++].addr = VENC_LLEN; + strcpy(venc_reg_table[i].name , "VENC_FLENS"); + venc_reg_table[i++].addr = VENC_FLENS; + strcpy(venc_reg_table[i].name , "VENC_HFLTR_CTRL"); + venc_reg_table[i++].addr = VENC_HFLTR_CTRL; + strcpy(venc_reg_table[i].name , "VENC_CC_CARR_WSS_CARR"); + venc_reg_table[i++].addr = VENC_CC_CARR_WSS_CARR; + strcpy(venc_reg_table[i].name , "VENC_C_PHASE"); + venc_reg_table[i++].addr = VENC_C_PHASE; + strcpy(venc_reg_table[i].name , "VENC_GAIN_U"); + venc_reg_table[i++].addr = VENC_GAIN_U; + strcpy(venc_reg_table[i].name , "VENC_GAIN_V"); + venc_reg_table[i++].addr = VENC_GAIN_V; + strcpy(venc_reg_table[i].name , "VENC_GAIN_Y"); + venc_reg_table[i++].addr = VENC_GAIN_Y; + strcpy(venc_reg_table[i].name , "VENC_BLACK_LEVEL"); + venc_reg_table[i++].addr = VENC_BLACK_LEVEL; + strcpy(venc_reg_table[i].name , "VENC_BLANK_LEVEL"); + venc_reg_table[i++].addr = VENC_BLANK_LEVEL; + strcpy(venc_reg_table[i].name , "VENC_X_COLOR"); + venc_reg_table[i++].addr = VENC_X_COLOR; + strcpy(venc_reg_table[i].name , "VENC_M_CONTROL"); + venc_reg_table[i++].addr = VENC_M_CONTROL; + strcpy(venc_reg_table[i].name , "VENC_BSTAMP_WSS_DATA"); + venc_reg_table[i++].addr = VENC_BSTAMP_WSS_DATA; + strcpy(venc_reg_table[i].name , "VENC_S_CARR"); + venc_reg_table[i++].addr = VENC_S_CARR; + strcpy(venc_reg_table[i].name , "VENC_LINE21"); + venc_reg_table[i++].addr = VENC_LINE21; + strcpy(venc_reg_table[i].name , "VENC_LN_SEL"); + venc_reg_table[i++].addr = VENC_LN_SEL; + strcpy(venc_reg_table[i].name , "VENC_L21_WC_CTL"); + venc_reg_table[i++].addr = VENC_L21_WC_CTL; + strcpy(venc_reg_table[i].name , "VENC_HTRIGGER_VTRIGGER"); + venc_reg_table[i++].addr = VENC_HTRIGGER_VTRIGGER; + strcpy(venc_reg_table[i].name , "VENC_SAVID_EAVID"); + venc_reg_table[i++].addr = VENC_SAVID_EAVID; + strcpy(venc_reg_table[i].name , "VENC_FLEN_FAL"); + venc_reg_table[i++].addr = VENC_FLEN_FAL; + strcpy(venc_reg_table[i].name , "VENC_LAL_PHASE_RESET"); + venc_reg_table[i++].addr = VENC_LAL_PHASE_RESET; + strcpy(venc_reg_table[i].name , "VENC_HS_INT_START_STOP_X"); + venc_reg_table[i++].addr = VENC_HS_INT_START_STOP_X; + strcpy(venc_reg_table[i].name , "VENC_HS_EXT_START_STOP_X"); + venc_reg_table[i++].addr = VENC_HS_EXT_START_STOP_X; + strcpy(venc_reg_table[i].name , "VENC_VS_INT_START_X"); + venc_reg_table[i++].addr = VENC_VS_INT_START_X; + strcpy(venc_reg_table[i].name , "VENC_VS_INT_STOP_X_VS_INT_START_Y"); + venc_reg_table[i++].addr = VENC_VS_INT_STOP_X_VS_INT_START_Y; + strcpy(venc_reg_table[i].name , "VENC_VS_INT_STOP_Y_VS_EXT_START_X"); + venc_reg_table[i++].addr = VENC_VS_INT_STOP_Y_VS_EXT_START_X; + strcpy(venc_reg_table[i].name , "VENC_VS_EXT_STOP_X_VS_EXT_START_Y"); + venc_reg_table[i++].addr = VENC_VS_EXT_STOP_X_VS_EXT_START_Y; + strcpy(venc_reg_table[i].name , "VENC_VS_EXT_STOP_Y"); + venc_reg_table[i++].addr = VENC_VS_EXT_STOP_Y; + strcpy(venc_reg_table[i].name , "VENC_AVID_START_STOP_X"); + venc_reg_table[i++].addr = VENC_AVID_START_STOP_X; + strcpy(venc_reg_table[i].name , "VENC_AVID_START_STOP_Y"); + venc_reg_table[i++].addr = VENC_AVID_START_STOP_Y; + strcpy(venc_reg_table[i].name , "VENC_FID_INT_START_X_FID_INT_START_Y"); + venc_reg_table[i++].addr = VENC_FID_INT_START_X_FID_INT_START_Y; + strcpy(venc_reg_table[i].name , + "VENC_FID_INT_OFFSET_Y_FID_EXT_START_X"); + venc_reg_table[i++].addr = VENC_FID_INT_OFFSET_Y_FID_EXT_START_X; + strcpy(venc_reg_table[i].name , + "VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y"); + venc_reg_table[i++].addr = VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y; + strcpy(venc_reg_table[i].name , "VENC_TVDETGP_INT_START_STOP_X"); + venc_reg_table[i++].addr = VENC_TVDETGP_INT_START_STOP_X; + strcpy(venc_reg_table[i].name , "VENC_TVDETGP_INT_START_STOP_Y"); + venc_reg_table[i++].addr = VENC_TVDETGP_INT_START_STOP_Y; + strcpy(venc_reg_table[i].name , "VENC_GEN_CTRL"); + venc_reg_table[i++].addr = VENC_GEN_CTRL; + strcpy(venc_reg_table[i].name , "VENC_OUTPUT_CONTROL"); + venc_reg_table[i++].addr = VENC_OUTPUT_CONTROL; + strcpy(venc_reg_table[i].name , "VENC_OUTPUT_TEST"); + venc_reg_table[i++].addr = VENC_OUTPUT_TEST; + strcpy(venc_reg_table[i].name, "END"); + venc_reg_table[i].addr = 0; + + /* Init DISPC registers table */ + i = 0; + strcpy(dispc_reg_table[i].name , "DISPC_REVISION"); + dispc_reg_table[i++].addr = DISPC_REVISION; + strcpy(dispc_reg_table[i].name , "DISPC_SYSCONFIG"); + dispc_reg_table[i++].addr = DISPC_SYSCONFIG; + strcpy(dispc_reg_table[i].name , "DISPC_SYSSTATUS"); + dispc_reg_table[i++].addr = DISPC_SYSSTATUS; + strcpy(dispc_reg_table[i].name , "DISPC_IRQSTATUS"); + dispc_reg_table[i++].addr = DISPC_IRQSTATUS; + strcpy(dispc_reg_table[i].name , "DISPC_IRQENABLE"); + dispc_reg_table[i++].addr = DISPC_IRQENABLE; + strcpy(dispc_reg_table[i].name , "DISPC_CONTROL1"); + dispc_reg_table[i++].addr = DISPC_CONTROL1; + strcpy(dispc_reg_table[i].name , "DISPC_CONFIG1"); + dispc_reg_table[i++].addr = DISPC_CONFIG1; + strcpy(dispc_reg_table[i].name , "DISPC_DEFAULT_COLOR0"); + dispc_reg_table[i++].addr = DISPC_DEFAULT_COLOR0; + strcpy(dispc_reg_table[i].name , "DISPC_DEFAULT_COLOR1"); + dispc_reg_table[i++].addr = DISPC_DEFAULT_COLOR1; + strcpy(dispc_reg_table[i].name , "DISPC_TRANS_COLOR0"); + dispc_reg_table[i++].addr = DISPC_TRANS_COLOR0; + strcpy(dispc_reg_table[i].name , "DISPC_TRANS_COLOR1"); + dispc_reg_table[i++].addr = DISPC_TRANS_COLOR1; + strcpy(dispc_reg_table[i].name , "DISPC_LINE_STATUS"); + dispc_reg_table[i++].addr = DISPC_LINE_STATUS; + strcpy(dispc_reg_table[i].name , "DISPC_LINE_NUMBER"); + dispc_reg_table[i++].addr = DISPC_LINE_NUMBER; + strcpy(dispc_reg_table[i].name , "DISPC_TIMING_H1"); + dispc_reg_table[i++].addr = DISPC_TIMING_H1; + strcpy(dispc_reg_table[i].name , "DISPC_TIMING_V1"); + dispc_reg_table[i++].addr = DISPC_TIMING_V1; + strcpy(dispc_reg_table[i].name , "DISPC_POL_FREQ1"); + dispc_reg_table[i++].addr = DISPC_POL_FREQ1; + strcpy(dispc_reg_table[i].name , "DISPC_DIVISOR1"); + dispc_reg_table[i++].addr = DISPC_DIVISOR1; + strcpy(dispc_reg_table[i].name , "DISPC_GLOBAL_ALPHA"); + dispc_reg_table[i++].addr = DISPC_GLOBAL_ALPHA; + strcpy(dispc_reg_table[i].name , "DISPC_SIZE_TV"); + dispc_reg_table[i++].addr = DISPC_SIZE_TV; + strcpy(dispc_reg_table[i].name , "DISPC_SIZE_LCD1"); + dispc_reg_table[i++].addr = DISPC_SIZE_LCD1; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_BA_0"); + dispc_reg_table[i++].addr = DISPC_GFX_BA_0; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_BA_1"); + dispc_reg_table[i++].addr = DISPC_GFX_BA_1; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_POSITION"); + dispc_reg_table[i++].addr = DISPC_GFX_POSITION; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_SIZE"); + dispc_reg_table[i++].addr = DISPC_GFX_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_ATTRIBUTES"); + dispc_reg_table[i++].addr = DISPC_GFX_ATTRIBUTES; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_BUF_THRESHOLD"); + dispc_reg_table[i++].addr = DISPC_GFX_BUF_THRESHOLD; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_BUF_SIZE_STATUS"); + dispc_reg_table[i++].addr = DISPC_GFX_BUF_SIZE_STATUS; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_ROW_INC"); + dispc_reg_table[i++].addr = DISPC_GFX_ROW_INC; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_PIXEL_INC"); + dispc_reg_table[i++].addr = DISPC_GFX_PIXEL_INC; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_WINDOW_SKIP"); + dispc_reg_table[i++].addr = DISPC_GFX_WINDOW_SKIP; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_TABLE_BA"); + dispc_reg_table[i++].addr = DISPC_GFX_TABLE_BA; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_BA_0"); + dispc_reg_table[i++].addr = DISPC_VID1_BA_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_BA_1"); + dispc_reg_table[i++].addr = DISPC_VID1_BA_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_POSITION"); + dispc_reg_table[i++].addr = DISPC_VID1_POSITION; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_SIZE"); + dispc_reg_table[i++].addr = DISPC_VID1_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_ATTRIBUTES"); + dispc_reg_table[i++].addr = DISPC_VID1_ATTRIBUTES; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_BUF_THRESHOLD"); + dispc_reg_table[i++].addr = DISPC_VID1_BUF_THRESHOLD; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_BUF_SIZE_STATUS"); + dispc_reg_table[i++].addr = DISPC_VID1_BUF_SIZE_STATUS; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_ROW_INC"); + dispc_reg_table[i++].addr = DISPC_VID1_ROW_INC; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_PIXEL_INC"); + dispc_reg_table[i++].addr = DISPC_VID1_PIXEL_INC; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_PICTURE_SIZE"); + dispc_reg_table[i++].addr = DISPC_VID1_PICTURE_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_ACCU_0"); + dispc_reg_table[i++].addr = DISPC_VID1_ACCU_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_ACCU_1"); + dispc_reg_table[i++].addr = DISPC_VID1_ACCU_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_CONV_COEF0"); + dispc_reg_table[i++].addr = DISPC_VID1_CONV_COEF0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_CONV_COEF1"); + dispc_reg_table[i++].addr = DISPC_VID1_CONV_COEF1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_CONV_COEF2"); + dispc_reg_table[i++].addr = DISPC_VID1_CONV_COEF2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_CONV_COEF3"); + dispc_reg_table[i++].addr = DISPC_VID1_CONV_COEF3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_CONV_COEF4"); + dispc_reg_table[i++].addr = DISPC_VID1_CONV_COEF4; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_BA_0"); + dispc_reg_table[i++].addr = DISPC_VID2_BA_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_BA_1"); + dispc_reg_table[i++].addr = DISPC_VID2_BA_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_POSITION"); + dispc_reg_table[i++].addr = DISPC_VID2_POSITION; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_SIZE"); + dispc_reg_table[i++].addr = DISPC_VID2_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_ATTRIBUTES"); + dispc_reg_table[i++].addr = DISPC_VID2_ATTRIBUTES; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_BUF_THRESHOLD"); + dispc_reg_table[i++].addr = DISPC_VID2_BUF_THRESHOLD; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_BUF_SIZE_STATUS"); + dispc_reg_table[i++].addr = DISPC_VID2_BUF_SIZE_STATUS; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_ROW_INC"); + dispc_reg_table[i++].addr = DISPC_VID2_ROW_INC; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_PIXEL_INC"); + dispc_reg_table[i++].addr = DISPC_VID2_PIXEL_INC; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_PICTURE_SIZE"); + dispc_reg_table[i++].addr = DISPC_VID2_PICTURE_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_ACCU_0"); + dispc_reg_table[i++].addr = DISPC_VID2_ACCU_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_ACCU_1"); + dispc_reg_table[i++].addr = DISPC_VID2_ACCU_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_CONV_COEF0"); + dispc_reg_table[i++].addr = DISPC_VID2_CONV_COEF0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_CONV_COEF1"); + dispc_reg_table[i++].addr = DISPC_VID2_CONV_COEF1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_CONV_COEF2"); + dispc_reg_table[i++].addr = DISPC_VID2_CONV_COEF2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_CONV_COEF3"); + dispc_reg_table[i++].addr = DISPC_VID2_CONV_COEF3; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_CONV_COEF4"); + dispc_reg_table[i++].addr = DISPC_VID2_CONV_COEF4; + strcpy(dispc_reg_table[i].name , "DISPC_DATA1_CYCLE1"); + dispc_reg_table[i++].addr = DISPC_DATA1_CYCLE1; + strcpy(dispc_reg_table[i].name , "DISPC_DATA1_CYCLE2"); + dispc_reg_table[i++].addr = DISPC_DATA1_CYCLE2; + strcpy(dispc_reg_table[i].name , "DISPC_DATA1_CYCLE3"); + dispc_reg_table[i++].addr = DISPC_DATA1_CYCLE3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_CPR1_COEF_R"); + dispc_reg_table[i++].addr = DISPC_CPR1_COEF_R; + strcpy(dispc_reg_table[i].name , "DISPC_CPR1_COEF_G"); + dispc_reg_table[i++].addr = DISPC_CPR1_COEF_G; + strcpy(dispc_reg_table[i].name , "DISPC_CPR1_COEF_B"); + dispc_reg_table[i++].addr = DISPC_CPR1_COEF_B; + strcpy(dispc_reg_table[i].name , "DISPC_GFX_PRELOAD"); + dispc_reg_table[i++].addr = DISPC_GFX_PRELOAD; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_PRELOAD"); + dispc_reg_table[i++].addr = DISPC_VID1_PRELOAD; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_PRELOAD"); + dispc_reg_table[i++].addr = DISPC_VID2_PRELOAD; + strcpy(dispc_reg_table[i].name , "DISPC_CONTROL2"); + dispc_reg_table[i++].addr = DISPC_CONTROL2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_ACCU_0"); + dispc_reg_table[i++].addr = DISPC_VID3_ACCU_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_ACCU_1"); + dispc_reg_table[i++].addr = DISPC_VID3_ACCU_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_BA_0"); + dispc_reg_table[i++].addr = DISPC_VID3_BA_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_BA_1"); + dispc_reg_table[i++].addr = DISPC_VID3_BA_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_ATTRIBUTES"); + dispc_reg_table[i++].addr = DISPC_VID3_ATTRIBUTES; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_CONV_COEF0"); + dispc_reg_table[i++].addr = DISPC_VID3_CONV_COEF0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_CONV_COEF1"); + dispc_reg_table[i++].addr = DISPC_VID3_CONV_COEF1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_CONV_COEF2"); + dispc_reg_table[i++].addr = DISPC_VID3_CONV_COEF2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_CONV_COEF3"); + dispc_reg_table[i++].addr = DISPC_VID3_CONV_COEF3; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_CONV_COEF4"); + dispc_reg_table[i++].addr = DISPC_VID3_CONV_COEF4; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_BUF_SIZE_STATUS"); + dispc_reg_table[i++].addr = DISPC_VID3_BUF_SIZE_STATUS; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_BUF_THRESHOLD"); + dispc_reg_table[i++].addr = DISPC_VID3_BUF_THRESHOLD; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_PICTURE_SIZE"); + dispc_reg_table[i++].addr = DISPC_VID3_PICTURE_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_PIXEL_INC"); + dispc_reg_table[i++].addr = DISPC_VID3_PIXEL_INC; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_POSITION"); + dispc_reg_table[i++].addr = DISPC_VID3_POSITION; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_PRELOAD"); + dispc_reg_table[i++].addr = DISPC_VID3_PRELOAD; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_ROW_INC"); + dispc_reg_table[i++].addr = DISPC_VID3_ROW_INC; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_SIZE"); + dispc_reg_table[i++].addr = DISPC_VID3_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_DEFAULT_COLOR2"); + dispc_reg_table[i++].addr = DISPC_DEFAULT_COLOR2; + strcpy(dispc_reg_table[i].name , "DISPC_TRANS_COLOR2"); + dispc_reg_table[i++].addr = DISPC_TRANS_COLOR2; + strcpy(dispc_reg_table[i].name , "DISPC_CPR2_COEF_B"); + dispc_reg_table[i++].addr = DISPC_CPR2_COEF_B; + strcpy(dispc_reg_table[i].name , "DISPC_CPR2_COEF_G"); + dispc_reg_table[i++].addr = DISPC_CPR2_COEF_G; + strcpy(dispc_reg_table[i].name , "DISPC_CPR2_COEF_R"); + dispc_reg_table[i++].addr = DISPC_CPR2_COEF_R; + strcpy(dispc_reg_table[i].name , "DISPC_DATA2_CYCLE1"); + dispc_reg_table[i++].addr = DISPC_DATA2_CYCLE1; + strcpy(dispc_reg_table[i].name , "DISPC_DATA2_CYCLE2"); + dispc_reg_table[i++].addr = DISPC_DATA2_CYCLE2; + strcpy(dispc_reg_table[i].name , "DISPC_DATA2_CYCLE3"); + dispc_reg_table[i++].addr = DISPC_DATA2_CYCLE3; + strcpy(dispc_reg_table[i].name , "DISPC_SIZE_LCD2"); + dispc_reg_table[i++].addr = DISPC_SIZE_LCD2; + strcpy(dispc_reg_table[i].name , "DISPC_TIMING_H2"); + dispc_reg_table[i++].addr = DISPC_TIMING_H2; + strcpy(dispc_reg_table[i].name , "DISPC_TIMING_V2"); + dispc_reg_table[i++].addr = DISPC_TIMING_V2; + strcpy(dispc_reg_table[i].name , "DISPC_POL_FREQ2"); + dispc_reg_table[i++].addr = DISPC_POL_FREQ2; + strcpy(dispc_reg_table[i].name , "DISPC_DIVISOR2"); + dispc_reg_table[i++].addr = DISPC_DIVISOR2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_ACCU_0"); + dispc_reg_table[i++].addr = DISPC_WB_ACCU_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_ACCU_1"); + dispc_reg_table[i++].addr = DISPC_WB_ACCU_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_BA_0"); + dispc_reg_table[i++].addr = DISPC_WB_BA_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_BA_1"); + dispc_reg_table[i++].addr = DISPC_WB_BA_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_WB_FIR_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_WB_ATTRIBUTES"); + dispc_reg_table[i++].addr = DISPC_WB_ATTRIBUTES; + strcpy(dispc_reg_table[i].name , "DISPC_WB_CONV_COEF0"); + dispc_reg_table[i++].addr = DISPC_WB_CONV_COEF0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_CONV_COEF1"); + dispc_reg_table[i++].addr = DISPC_WB_CONV_COEF1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_CONV_COEF2"); + dispc_reg_table[i++].addr = DISPC_WB_CONV_COEF2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_CONV_COEF3"); + dispc_reg_table[i++].addr = DISPC_WB_CONV_COEF3; + strcpy(dispc_reg_table[i].name , "DISPC_WB_CONV_COEF4"); + dispc_reg_table[i++].addr = DISPC_WB_CONV_COEF4; + strcpy(dispc_reg_table[i].name , "DISPC_WB_BUF_SIZE_STATUS"); + dispc_reg_table[i++].addr = DISPC_WB_BUF_SIZE_STATUS; + strcpy(dispc_reg_table[i].name , "DISPC_WB_BUF_THRESHOLD"); + dispc_reg_table[i++].addr = DISPC_WB_BUF_THRESHOLD; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR"); + dispc_reg_table[i++].addr = DISPC_WB_FIR; + strcpy(dispc_reg_table[i].name , "DISPC_WB_PICTURE_SIZE"); + dispc_reg_table[i++].addr = DISPC_WB_PICTURE_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_WB_PIXEL_INC"); + dispc_reg_table[i++].addr = DISPC_WB_PIXEL_INC; + strcpy(dispc_reg_table[i].name , "DISPC_WB_ROW_INC"); + dispc_reg_table[i++].addr = DISPC_WB_ROW_INC; + strcpy(dispc_reg_table[i].name , "DISPC_WB_SIZE"); + dispc_reg_table[i++].addr = DISPC_WB_SIZE; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_BA_UV_0"); + dispc_reg_table[i++].addr = DISPC_VID1_BA_UV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_BA_UV_1"); + dispc_reg_table[i++].addr = DISPC_VID1_BA_UV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_BA_UV_0"); + dispc_reg_table[i++].addr = DISPC_VID2_BA_UV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_BA_UV_1"); + dispc_reg_table[i++].addr = DISPC_VID2_BA_UV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_BA_UV_0"); + dispc_reg_table[i++].addr = DISPC_VID3_BA_UV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_BA_UV_1"); + dispc_reg_table[i++].addr = DISPC_VID3_BA_UV_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_BA_UV_0"); + dispc_reg_table[i++].addr = DISPC_WB_BA_UV_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_BA_UV_1"); + dispc_reg_table[i++].addr = DISPC_WB_BA_UV_1; + strcpy(dispc_reg_table[i].name , "DISPC_CONFIG2"); + dispc_reg_table[i++].addr = DISPC_CONFIG2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_ATTRIBUTES2"); + dispc_reg_table[i++].addr = DISPC_VID1_ATTRIBUTES2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_ATTRIBUTES2"); + dispc_reg_table[i++].addr = DISPC_VID2_ATTRIBUTES2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_ATTRIBUTES2"); + dispc_reg_table[i++].addr = DISPC_VID3_ATTRIBUTES2; + strcpy(dispc_reg_table[i].name , "DISPC_GAMMA_TABLE0"); + dispc_reg_table[i++].addr = DISPC_GAMMA_TABLE0; + strcpy(dispc_reg_table[i].name , "DISPC_GAMMA_TABLE1"); + dispc_reg_table[i++].addr = DISPC_GAMMA_TABLE1; + strcpy(dispc_reg_table[i].name , "DISPC_GAMMA_TABLE2"); + dispc_reg_table[i++].addr = DISPC_GAMMA_TABLE2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_ACCU2_0"); + dispc_reg_table[i++].addr = DISPC_VID1_ACCU2_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_ACCU2_1"); + dispc_reg_table[i++].addr = DISPC_VID1_ACCU2_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID1_FIR2_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_VID1_FIR2_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_ACCU2_0"); + dispc_reg_table[i++].addr = DISPC_VID2_ACCU2_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_ACCU2_1"); + dispc_reg_table[i++].addr = DISPC_VID2_ACCU2_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID2_FIR2_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_VID2_FIR2_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_ACCU2_0"); + dispc_reg_table[i++].addr = DISPC_VID3_ACCU2_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_ACCU2_1"); + dispc_reg_table[i++].addr = DISPC_VID3_ACCU2_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_VID3_FIR2_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_VID3_FIR2_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_ACCU2_0"); + dispc_reg_table[i++].addr = DISPC_WB_ACCU2_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_ACCU2_1"); + dispc_reg_table[i++].addr = DISPC_WB_ACCU2_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_0"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_1"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_2"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_3"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_3; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_4"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_4; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_5"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_5; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_6"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_6; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_H_7"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_H_7; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_0"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_1"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_2"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_3"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_3; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_4"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_4; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_5"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_5; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_6"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_6; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_HV_7"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_HV_7; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_0"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_0; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_1"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_1; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_2"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_2; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_3"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_3; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_4"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_4; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_5"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_5; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_6"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_6; + strcpy(dispc_reg_table[i].name , "DISPC_WB_FIR2_COEF_V_7"); + dispc_reg_table[i++].addr = DISPC_WB_FIR2_COEF_V_7; + strcpy(dispc_reg_table[i].name , "DISPC_GLOBAL_BUFFER"); + dispc_reg_table[i++].addr = DISPC_GLOBAL_BUFFER; + strcpy(dispc_reg_table[i].name , "DISPC_DIVISOR"); + dispc_reg_table[i++].addr = DISPC_DIVISOR; + strcpy(dispc_reg_table[i].name , "DISPC_WB_ATTRIBUTES2"); + dispc_reg_table[i++].addr = DISPC_WB_ATTRIBUTES2; + strcpy(dispc_reg_table[i].name, "END"); + dispc_reg_table[i].addr = 0; + + init_done = 1; + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION display44xx_name2addr + * @BRIEF retrieve physical address of a register, given its name. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @param[in,out] name: register name + * @param[in,out] addr: register address + * @DESCRIPTION retrieve physical address of a register, given its name. + *//*------------------------------------------------------------------------ */ +int display44xx_name2addr(char *name, unsigned int *addr) +{ + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (!init_done) + display44xx_init_regtable(); + + if (name2addr(name, addr, dss_reg_table) == 0) + return name2addr(name, addr, dss_reg_table); + else if (name2addr(name, addr, dsi1_reg_table) == 0) + return name2addr(name, addr, dsi1_reg_table); + else if (name2addr(name, addr, dsi1_pll_reg_table) == 0) + return name2addr(name, addr, dsi1_pll_reg_table); + else if (name2addr(name, addr, dsi1_phy_reg_table) == 0) + return name2addr(name, addr, dsi1_phy_reg_table); + else if (name2addr(name, addr, dsi2_reg_table) == 0) + return name2addr(name, addr, dsi2_reg_table); + else if (name2addr(name, addr, dsi2_pll_reg_table) == 0) + return name2addr(name, addr, dsi2_pll_reg_table); + else if (name2addr(name, addr, dsi2_phy_reg_table) == 0) + return name2addr(name, addr, dsi2_phy_reg_table); + else if (name2addr(name, addr, rfbi_reg_table) == 0) + return name2addr(name, addr, rfbi_reg_table); + else if (name2addr(name, addr, venc_reg_table) == 0) + return name2addr(name, addr, venc_reg_table); + else if (name2addr(name, addr, dispc_reg_table) == 0) + return name2addr(name, addr, dispc_reg_table); + else + return -1; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION display44xx_clock_is_running + * @BRIEF check if selected display clock is running or not. + * @RETURNS 1 if selected clock is running, + * 0 if clock is gated or erroneous id. + * @param[in] id: module to be dump (i.e. user-entered argv[3]) + * @DESCRIPTION check if selected display clock is running or not. + *//*------------------------------------------------------------------------ */ +unsigned char display44xx_clock_is_running(display44xx_clock_id id) +{ + unsigned char running; + unsigned int cm_dss_clkstctrl, cm_dss_dss_clkctrl; + int ret; + + CHECK_CPU(44xx, 0); + + ret = mem_read(OMAP4430_CM_DSS_CLKSTCTRL, &cm_dss_clkstctrl); + ret |= mem_read(OMAP4430_CM_DSS_DSS_CLKCTRL, &cm_dss_dss_clkctrl); + if (ret != 0) { + running = 0; + goto display44xx_clock_is_running_end; + } + + switch (id) { + case HDMI_PHY_48MHz_FCLK: + running = extract_bit(cm_dss_clkstctrl, 11); + break; + case DSS_ALWON_SYS_CLK: + running = extract_bit(cm_dss_clkstctrl, 10); + break; + case DSS_FCLK: + running = extract_bit(cm_dss_clkstctrl, 9); + break; + case DSS_L3_ICLK: + running = extract_bit(cm_dss_clkstctrl, 8); + break; + case OPTFCLK_TV_FCLK: + running = extract_bit(cm_dss_dss_clkctrl, 11); + break; + case OPTFCLK_SYS_CLK: + running = extract_bit(cm_dss_dss_clkctrl, 10); + break; + case OPTFCLK_48MHZ_CLK: + running = extract_bit(cm_dss_dss_clkctrl, 9); + break; + case OPTFCLK_DSSCLK: + running = extract_bit(cm_dss_dss_clkctrl, 8); + break; + default: + fprintf(stderr, "%s(): erroneous id (%d)!!!\n", __func__, id); + running = 0; + } + +display44xx_clock_is_running_end: + return running; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION display44xx_dump + * @BRIEF dump display module registers + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @param[in] display_mod: module to be dump + * (i.e. user-entered argv[3]) + * @DESCRIPTION dump display module registers + *//*------------------------------------------------------------------------ */ +int display44xx_dump(char *display_mod) +{ + int ret; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (!display44xx_clock_is_running(DSS_L3_ICLK)) { + printf("DSS L3 ICLK stopped, registers not accessible.\n\n"); + ret = OMAPCONF_ERR_REG_ACCESS; + goto display44xx_dump_end; + } + + if (!init_done) + display44xx_init_regtable(); + + ret = OMAPCONF_ERR_ARG; + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dss") == 0)) + ret = dumpregs(dss_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dispc") == 0)) + ret = dumpregs(dispc_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dsi1") == 0)) + ret = dumpregs(dsi1_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dsi1_phy") == 0)) + ret = dumpregs(dsi1_phy_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dsi1_pll") == 0)) + ret = dumpregs(dsi1_pll_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dsi2") == 0)) + ret = dumpregs(dsi2_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dsi2_phy") == 0)) + ret = dumpregs(dsi2_phy_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "dsi2_pll") == 0)) + ret = dumpregs(dsi2_pll_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "rfbi") == 0)) + ret = dumpregs(rfbi_reg_table); + + if ((strcmp(display_mod, "all") == 0) || + (strcmp(display_mod, "venc") == 0)) + ret = dumpregs(venc_reg_table); + + if (ret == OMAPCONF_ERR_ARG) + help(HELP_DISPLAY); + +display44xx_dump_end: + return ret; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/display44xx.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/display44xx.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/display44xx.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/display44xx.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,651 @@ +/* + * + * @Component OMAPCONF + * @Filename display44xx.h + * @Description OMAP4 Display Configuration + * @Author Erwan Petillon (e-petillon@ti.com) + * @Date 2011 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __DISPLAY44XX_H__ +#define __DISPLAY44XX_H__ + + +/* DSS Physical address */ +#define DSS_REVISION 0x58000000 +#define DSS_SYSSTATUS 0x58000014 +#define DSS_CTRL 0x58000040 +#define DSS_STATUS 0x5800005C + + +/* DISPC Physical address */ +#define DISPC_REVISION 0x58001000 +#define DISPC_SYSCONFIG 0x58001010 +#define DISPC_SYSSTATUS 0x58001014 +#define DISPC_IRQSTATUS 0x58001018 +#define DISPC_IRQENABLE 0x5800101C +#define DISPC_CONTROL1 0x58001040 +#define DISPC_CONFIG1 0x58001044 +#define DISPC_DEFAULT_COLOR0 0x5800104C +#define DISPC_DEFAULT_COLOR1 0x58001050 +#define DISPC_TRANS_COLOR0 0x58001054 +#define DISPC_TRANS_COLOR1 0x58001058 +#define DISPC_LINE_STATUS 0x5800105C +#define DISPC_LINE_NUMBER 0x58001060 +#define DISPC_TIMING_H1 0x58001064 +#define DISPC_TIMING_V1 0x58001068 +#define DISPC_POL_FREQ1 0x5800106C +#define DISPC_DIVISOR1 0x58001070 +#define DISPC_GLOBAL_ALPHA 0x58001074 +#define DISPC_SIZE_TV 0x58001078 +#define DISPC_SIZE_LCD1 0x5800107C +#define DISPC_GFX_BA_0 0x58001080 +#define DISPC_GFX_BA_1 0x58001084 +#define DISPC_GFX_POSITION 0x58001088 +#define DISPC_GFX_SIZE 0x5800108C +#define DISPC_GFX_ATTRIBUTES 0x580010A0 +#define DISPC_GFX_BUF_THRESHOLD 0x580010A4 +#define DISPC_GFX_BUF_SIZE_STATUS 0x580010A8 +#define DISPC_GFX_ROW_INC 0x580010AC +#define DISPC_GFX_PIXEL_INC 0x580010B0 +#define DISPC_GFX_WINDOW_SKIP 0x580010B4 +#define DISPC_GFX_TABLE_BA 0x580010B8 +#define DISPC_VID1_BA_0 0x580010BC +#define DISPC_VID1_BA_1 0x580010C0 +#define DISPC_VID1_POSITION 0x580010C4 +#define DISPC_VID1_SIZE 0x580010C8 +#define DISPC_VID1_ATTRIBUTES 0x580010CC +#define DISPC_VID1_BUF_THRESHOLD 0x580010D0 +#define DISPC_VID1_BUF_SIZE_STATUS 0x580010D4 +#define DISPC_VID1_ROW_INC 0x580010D8 +#define DISPC_VID1_PIXEL_INC 0x580010DC +#define DISPC_VID1_FIR 0x580010E0 +#define DISPC_VID1_PICTURE_SIZE 0x580010E4 +#define DISPC_VID1_ACCU_0 0x580010E8 +#define DISPC_VID1_ACCU_1 0x580010EC +#define DISPC_VID1_FIR_COEF_H_0 0x580010F0 +#define DISPC_VID1_FIR_COEF_H_1 0x580010F8 +#define DISPC_VID1_FIR_COEF_H_2 0x58001100 +#define DISPC_VID1_FIR_COEF_H_3 0x58001108 +#define DISPC_VID1_FIR_COEF_H_4 0x58001110 +#define DISPC_VID1_FIR_COEF_H_5 0x58001118 +#define DISPC_VID1_FIR_COEF_H_6 0x58001120 +#define DISPC_VID1_FIR_COEF_H_7 0x58001128 +#define DISPC_VID1_FIR_COEF_HV_0 0x580010F4 +#define DISPC_VID1_FIR_COEF_HV_1 0x580010FC +#define DISPC_VID1_FIR_COEF_HV_2 0x58001104 +#define DISPC_VID1_FIR_COEF_HV_3 0x5800110C +#define DISPC_VID1_FIR_COEF_HV_4 0x58001114 +#define DISPC_VID1_FIR_COEF_HV_5 0x5800111C +#define DISPC_VID1_FIR_COEF_HV_6 0x58001124 +#define DISPC_VID1_FIR_COEF_HV_7 0x5800112C +#define DISPC_VID1_CONV_COEF0 0x58001130 +#define DISPC_VID1_CONV_COEF1 0x58001134 +#define DISPC_VID1_CONV_COEF2 0x58001138 +#define DISPC_VID1_CONV_COEF3 0x5800113C +#define DISPC_VID1_CONV_COEF4 0x58001140 +#define DISPC_VID2_BA_0 0x5800114C +#define DISPC_VID2_BA_1 0x58001150 +#define DISPC_VID2_POSITION 0x58001154 +#define DISPC_VID2_SIZE 0x58001158 +#define DISPC_VID2_ATTRIBUTES 0x5800115C +#define DISPC_VID2_BUF_THRESHOLD 0x58001160 +#define DISPC_VID2_BUF_SIZE_STATUS 0x58001164 +#define DISPC_VID2_ROW_INC 0x58001168 +#define DISPC_VID2_PIXEL_INC 0x5800116C +#define DISPC_VID2_FIR 0x58001170 +#define DISPC_VID2_PICTURE_SIZE 0x58001174 +#define DISPC_VID2_ACCU_0 0x58001178 +#define DISPC_VID2_ACCU_1 0x5800117C +#define DISPC_VID2_FIR_COEF_H_0 0x58001180 +#define DISPC_VID2_FIR_COEF_H_1 0x58001188 +#define DISPC_VID2_FIR_COEF_H_2 0x58001190 +#define DISPC_VID2_FIR_COEF_H_3 0x58001198 +#define DISPC_VID2_FIR_COEF_H_4 0x580011A0 +#define DISPC_VID2_FIR_COEF_H_5 0x580011A8 +#define DISPC_VID2_FIR_COEF_H_6 0x580011B0 +#define DISPC_VID2_FIR_COEF_H_7 0x580011B8 +#define DISPC_VID2_FIR_COEF_HV_0 0x58001184 +#define DISPC_VID2_FIR_COEF_HV_1 0x5800118C +#define DISPC_VID2_FIR_COEF_HV_2 0x58001194 +#define DISPC_VID2_FIR_COEF_HV_3 0x5800119C +#define DISPC_VID2_FIR_COEF_HV_4 0x580011A4 +#define DISPC_VID2_FIR_COEF_HV_5 0x580011AC +#define DISPC_VID2_FIR_COEF_HV_6 0x580011B4 +#define DISPC_VID2_FIR_COEF_HV_7 0x580011BC +#define DISPC_VID2_CONV_COEF0 0x580011C0 +#define DISPC_VID2_CONV_COEF1 0x580011C4 +#define DISPC_VID2_CONV_COEF2 0x580011C8 +#define DISPC_VID2_CONV_COEF3 0x580011CC +#define DISPC_VID2_CONV_COEF4 0x580011D0 +#define DISPC_DATA1_CYCLE1 0x580011D4 +#define DISPC_DATA1_CYCLE2 0x580011D8 +#define DISPC_DATA1_CYCLE3 0x580011DC +#define DISPC_VID1_FIR_COEF_V_0 0x580011E0 +#define DISPC_VID1_FIR_COEF_V_1 0x580011E4 +#define DISPC_VID1_FIR_COEF_V_2 0x580011E8 +#define DISPC_VID1_FIR_COEF_V_3 0x580011EC +#define DISPC_VID1_FIR_COEF_V_4 0x580011F0 +#define DISPC_VID1_FIR_COEF_V_5 0x580011F4 +#define DISPC_VID1_FIR_COEF_V_6 0x580011F8 +#define DISPC_VID1_FIR_COEF_V_7 0x580011FC +#define DISPC_VID2_FIR_COEF_V_0 0x58001200 +#define DISPC_VID2_FIR_COEF_V_1 0x58001204 +#define DISPC_VID2_FIR_COEF_V_2 0x58001208 +#define DISPC_VID2_FIR_COEF_V_3 0x5800120C +#define DISPC_VID2_FIR_COEF_V_4 0x58001210 +#define DISPC_VID2_FIR_COEF_V_5 0x58001214 +#define DISPC_VID2_FIR_COEF_V_6 0x58001218 +#define DISPC_VID2_FIR_COEF_V_7 0x5800121C +#define DISPC_CPR1_COEF_R 0x58001220 +#define DISPC_CPR1_COEF_G 0x58001224 +#define DISPC_CPR1_COEF_B 0x58001228 +#define DISPC_GFX_PRELOAD 0x5800122C +#define DISPC_VID1_PRELOAD 0x58001230 +#define DISPC_VID2_PRELOAD 0x58001234 +#define DISPC_CONTROL2 0x58001238 +#define DISPC_VID3_ACCU_0 0x58001300 +#define DISPC_VID3_ACCU_1 0x58001304 +#define DISPC_VID3_BA_0 0x58001308 +#define DISPC_VID3_BA_1 0x5800130C +#define DISPC_VID3_FIR_COEF_H_0 0x58001310 +#define DISPC_VID3_FIR_COEF_H_1 0x58001318 +#define DISPC_VID3_FIR_COEF_H_2 0x58001320 +#define DISPC_VID3_FIR_COEF_H_3 0x58001328 +#define DISPC_VID3_FIR_COEF_H_4 0x58001330 +#define DISPC_VID3_FIR_COEF_H_5 0x58001338 +#define DISPC_VID3_FIR_COEF_H_6 0x58001340 +#define DISPC_VID3_FIR_COEF_H_7 0x58001348 +#define DISPC_VID3_FIR_COEF_HV_0 0x58001314 +#define DISPC_VID3_FIR_COEF_HV_1 0x5800131C +#define DISPC_VID3_FIR_COEF_HV_2 0x58001324 +#define DISPC_VID3_FIR_COEF_HV_3 0x5800132C +#define DISPC_VID3_FIR_COEF_HV_4 0x58001334 +#define DISPC_VID3_FIR_COEF_HV_5 0x5800133C +#define DISPC_VID3_FIR_COEF_HV_6 0x58001344 +#define DISPC_VID3_FIR_COEF_HV_7 0x5800134C +#define DISPC_VID3_FIR_COEF_V_0 0x58001350 +#define DISPC_VID3_FIR_COEF_V_1 0x58001354 +#define DISPC_VID3_FIR_COEF_V_2 0x58001358 +#define DISPC_VID3_FIR_COEF_V_3 0x5800135C +#define DISPC_VID3_FIR_COEF_V_4 0x58001360 +#define DISPC_VID3_FIR_COEF_V_5 0x58001364 +#define DISPC_VID3_FIR_COEF_V_6 0x58001368 +#define DISPC_VID3_FIR_COEF_V_7 0x5800136C +#define DISPC_VID3_ATTRIBUTES 0x58001370 +#define DISPC_VID3_CONV_COEF0 0x58001374 +#define DISPC_VID3_CONV_COEF1 0x58001378 +#define DISPC_VID3_CONV_COEF2 0x5800137C +#define DISPC_VID3_CONV_COEF3 0x58001380 +#define DISPC_VID3_CONV_COEF4 0x58001384 +#define DISPC_VID3_BUF_SIZE_STATUS 0x58001388 +#define DISPC_VID3_BUF_THRESHOLD 0x5800138C +#define DISPC_VID3_FIR 0x58001390 +#define DISPC_VID3_PICTURE_SIZE 0x58001394 +#define DISPC_VID3_PIXEL_INC 0x58001398 +#define DISPC_VID3_POSITION 0x5800139C +#define DISPC_VID3_PRELOAD 0x580013A0 +#define DISPC_VID3_ROW_INC 0x580013A4 +#define DISPC_VID3_SIZE 0x580013A8 +#define DISPC_DEFAULT_COLOR2 0x580013AC +#define DISPC_TRANS_COLOR2 0x580013B0 +#define DISPC_CPR2_COEF_B 0x580013B4 +#define DISPC_CPR2_COEF_G 0x580013B8 +#define DISPC_CPR2_COEF_R 0x580013BC +#define DISPC_DATA2_CYCLE1 0x580013C0 +#define DISPC_DATA2_CYCLE2 0x580013C4 +#define DISPC_DATA2_CYCLE3 0x580013C8 +#define DISPC_SIZE_LCD2 0x580013CC +#define DISPC_TIMING_H2 0x58001400 +#define DISPC_TIMING_V2 0x58001404 +#define DISPC_POL_FREQ2 0x58001408 +#define DISPC_DIVISOR2 0x5800140C +#define DISPC_WB_ACCU_0 0x58001500 +#define DISPC_WB_ACCU_1 0x58001504 +#define DISPC_WB_BA_0 0x58001508 +#define DISPC_WB_BA_1 0x5800150C +#define DISPC_WB_FIR_COEF_H_0 0x58001510 +#define DISPC_WB_FIR_COEF_H_1 0x58001518 +#define DISPC_WB_FIR_COEF_H_2 0x58001520 +#define DISPC_WB_FIR_COEF_H_3 0x58001528 +#define DISPC_WB_FIR_COEF_H_4 0x58001530 +#define DISPC_WB_FIR_COEF_H_5 0x58001538 +#define DISPC_WB_FIR_COEF_H_6 0x58001540 +#define DISPC_WB_FIR_COEF_H_7 0x58001548 +#define DISPC_WB_FIR_COEF_HV_0 0x58001514 +#define DISPC_WB_FIR_COEF_HV_1 0x5800151C +#define DISPC_WB_FIR_COEF_HV_2 0x58001524 +#define DISPC_WB_FIR_COEF_HV_3 0x5800152C +#define DISPC_WB_FIR_COEF_HV_4 0x58001534 +#define DISPC_WB_FIR_COEF_HV_5 0x5800153C +#define DISPC_WB_FIR_COEF_HV_6 0x58001544 +#define DISPC_WB_FIR_COEF_HV_7 0x5800154C +#define DISPC_WB_FIR_COEF_V_0 0x58001550 +#define DISPC_WB_FIR_COEF_V_1 0x58001554 +#define DISPC_WB_FIR_COEF_V_2 0x58001558 + +#define DISPC_WB_FIR_COEF_V_3 0x5800155C +#define DISPC_WB_FIR_COEF_V_4 0x58001560 +#define DISPC_WB_FIR_COEF_V_5 0x58001564 +#define DISPC_WB_FIR_COEF_V_6 0x58001568 +#define DISPC_WB_FIR_COEF_V_7 0x5800156C +#define DISPC_WB_ATTRIBUTES 0x58001570 +#define DISPC_WB_CONV_COEF0 0x58001574 +#define DISPC_WB_CONV_COEF1 0x58001578 +#define DISPC_WB_CONV_COEF2 0x5800157C +#define DISPC_WB_CONV_COEF3 0x58001580 +#define DISPC_WB_CONV_COEF4 0x58001584 +#define DISPC_WB_BUF_SIZE_STATUS 0x58001588 +#define DISPC_WB_BUF_THRESHOLD 0x5800158C +#define DISPC_WB_FIR 0x58001590 +#define DISPC_WB_PICTURE_SIZE 0x58001594 +#define DISPC_WB_PIXEL_INC 0x58001598 +#define DISPC_WB_ROW_INC 0x580015A4 +#define DISPC_WB_SIZE 0x580015A8 +#define DISPC_VID1_BA_UV_0 0x58001600 +#define DISPC_VID1_BA_UV_1 0x58001604 +#define DISPC_VID2_BA_UV_0 0x58001608 +#define DISPC_VID2_BA_UV_1 0x5800160C +#define DISPC_VID3_BA_UV_0 0x58001610 +#define DISPC_VID3_BA_UV_1 0x58001614 +#define DISPC_WB_BA_UV_0 0x58001618 +#define DISPC_WB_BA_UV_1 0x5800161C +#define DISPC_CONFIG2 0x58001620 +#define DISPC_VID1_ATTRIBUTES2 0x58001624 +#define DISPC_VID2_ATTRIBUTES2 0x58001628 +#define DISPC_VID3_ATTRIBUTES2 0x5800162C +#define DISPC_GAMMA_TABLE0 0x58001630 +#define DISPC_GAMMA_TABLE1 0x58001634 +#define DISPC_GAMMA_TABLE2 0x58001638 +#define DISPC_VID1_FIR2 0x5800163C +#define DISPC_VID1_ACCU2_0 0x58001640 +#define DISPC_VID1_ACCU2_1 0x58001644 +#define DISPC_VID1_FIR2_COEF_H_0 0x58001648 +#define DISPC_VID1_FIR2_COEF_H_1 0x58001650 +#define DISPC_VID1_FIR2_COEF_H_2 0x58001658 +#define DISPC_VID1_FIR2_COEF_H_3 0x58001660 +#define DISPC_VID1_FIR2_COEF_H_4 0x58001668 +#define DISPC_VID1_FIR2_COEF_H_5 0x58001670 +#define DISPC_VID1_FIR2_COEF_H_6 0x58001678 +#define DISPC_VID1_FIR2_COEF_H_7 0x58001680 +#define DISPC_VID1_FIR2_COEF_HV_0 0x5800164C +#define DISPC_VID1_FIR2_COEF_HV_1 0x58001654 +#define DISPC_VID1_FIR2_COEF_HV_2 0x5800165C +#define DISPC_VID1_FIR2_COEF_HV_3 0x58001664 +#define DISPC_VID1_FIR2_COEF_HV_4 0x5800166C +#define DISPC_VID1_FIR2_COEF_HV_5 0x58001674 +#define DISPC_VID1_FIR2_COEF_HV_6 0x5800167C +#define DISPC_VID1_FIR2_COEF_HV_7 0x58001684 +#define DISPC_VID1_FIR2_COEF_V_0 0x58001688 +#define DISPC_VID1_FIR2_COEF_V_1 0x5800168C +#define DISPC_VID1_FIR2_COEF_V_2 0x58001690 +#define DISPC_VID1_FIR2_COEF_V_3 0x58001694 +#define DISPC_VID1_FIR2_COEF_V_4 0x58001698 +#define DISPC_VID1_FIR2_COEF_V_5 0x5800169C +#define DISPC_VID1_FIR2_COEF_V_6 0x580016A0 +#define DISPC_VID1_FIR2_COEF_V_7 0x580016A4 +#define DISPC_VID2_FIR2 0x580016A8 +#define DISPC_VID2_ACCU2_0 0x580016AC +#define DISPC_VID2_ACCU2_1 0x580016B0 +#define DISPC_VID2_FIR2_COEF_H_0 0x580016B4 +#define DISPC_VID2_FIR2_COEF_H_1 0x580016BC +#define DISPC_VID2_FIR2_COEF_H_2 0x580016C4 +#define DISPC_VID2_FIR2_COEF_H_3 0x580016CC +#define DISPC_VID2_FIR2_COEF_H_4 0x580016D4 +#define DISPC_VID2_FIR2_COEF_H_5 0x580016DC +#define DISPC_VID2_FIR2_COEF_H_6 0x580016E4 +#define DISPC_VID2_FIR2_COEF_H_7 0x580016EC +#define DISPC_VID2_FIR2_COEF_HV_0 0x580016B8 +#define DISPC_VID2_FIR2_COEF_HV_1 0x580016C0 +#define DISPC_VID2_FIR2_COEF_HV_2 0x580016C8 +#define DISPC_VID2_FIR2_COEF_HV_3 0x580016D0 +#define DISPC_VID2_FIR2_COEF_HV_4 0x580016D8 +#define DISPC_VID2_FIR2_COEF_HV_5 0x580016E0 +#define DISPC_VID2_FIR2_COEF_HV_6 0x580016E8 +#define DISPC_VID2_FIR2_COEF_HV_7 0x580016F0 +#define DISPC_VID2_FIR2_COEF_V_0 0x580016F4 +#define DISPC_VID2_FIR2_COEF_V_1 0x580016F8 +#define DISPC_VID2_FIR2_COEF_V_2 0x580016FC +#define DISPC_VID2_FIR2_COEF_V_3 0x58001700 +#define DISPC_VID2_FIR2_COEF_V_4 0x58001704 +#define DISPC_VID2_FIR2_COEF_V_5 0x58001708 +#define DISPC_VID2_FIR2_COEF_V_6 0x5800170C +#define DISPC_VID2_FIR2_COEF_V_7 0x58001710 +#define DISPC_VID3_FIR2 0x58001724 +#define DISPC_VID3_ACCU2_0 0x58001728 +#define DISPC_VID3_ACCU2_1 0x5800172C +#define DISPC_VID3_FIR2_COEF_H_0 0x58001730 +#define DISPC_VID3_FIR2_COEF_H_1 0x58001738 +#define DISPC_VID3_FIR2_COEF_H_2 0x58001740 +#define DISPC_VID3_FIR2_COEF_H_3 0x58001748 +#define DISPC_VID3_FIR2_COEF_H_4 0x58001750 +#define DISPC_VID3_FIR2_COEF_H_5 0x58001758 +#define DISPC_VID3_FIR2_COEF_H_6 0x58001760 +#define DISPC_VID3_FIR2_COEF_H_7 0x58001768 +#define DISPC_VID3_FIR2_COEF_HV_0 0x58001734 +#define DISPC_VID3_FIR2_COEF_HV_1 0x5800173C +#define DISPC_VID3_FIR2_COEF_HV_2 0x58001744 +#define DISPC_VID3_FIR2_COEF_HV_3 0x5800174C +#define DISPC_VID3_FIR2_COEF_HV_4 0x58001754 +#define DISPC_VID3_FIR2_COEF_HV_5 0x5800175C +#define DISPC_VID3_FIR2_COEF_HV_6 0x58001764 +#define DISPC_VID3_FIR2_COEF_HV_7 0x5800176C +#define DISPC_VID3_FIR2_COEF_V_0 0x58001770 +#define DISPC_VID3_FIR2_COEF_V_1 0x58001774 +#define DISPC_VID3_FIR2_COEF_V_2 0x58001778 +#define DISPC_VID3_FIR2_COEF_V_3 0x5800177C +#define DISPC_VID3_FIR2_COEF_V_4 0x58001780 +#define DISPC_VID3_FIR2_COEF_V_5 0x58001784 +#define DISPC_VID3_FIR2_COEF_V_6 0x58001788 +#define DISPC_VID3_FIR2_COEF_V_7 0x5800178C +#define DISPC_WB_FIR2 0x58001790 +#define DISPC_WB_ACCU2_0 0x58001794 +#define DISPC_WB_ACCU2_1 0x58001798 +#define DISPC_WB_FIR2_COEF_H_0 0x580017A0 +#define DISPC_WB_FIR2_COEF_H_1 0x580017A8 +#define DISPC_WB_FIR2_COEF_H_2 0x580017B0 +#define DISPC_WB_FIR2_COEF_H_3 0x580017B8 +#define DISPC_WB_FIR2_COEF_H_4 0x580017C0 +#define DISPC_WB_FIR2_COEF_H_5 0x580017C8 +#define DISPC_WB_FIR2_COEF_H_6 0x580017D0 +#define DISPC_WB_FIR2_COEF_H_7 0x580017D8 +#define DISPC_WB_FIR2_COEF_HV_0 0x580017A4 +#define DISPC_WB_FIR2_COEF_HV_1 0x580017AC +#define DISPC_WB_FIR2_COEF_HV_2 0x580017B4 +#define DISPC_WB_FIR2_COEF_HV_3 0x580017BC +#define DISPC_WB_FIR2_COEF_HV_4 0x580017C4 +#define DISPC_WB_FIR2_COEF_HV_5 0x580017CC +#define DISPC_WB_FIR2_COEF_HV_6 0x580017D4 +#define DISPC_WB_FIR2_COEF_HV_7 0x580017DC +#define DISPC_WB_FIR2_COEF_V_0 0x580017E0 +#define DISPC_WB_FIR2_COEF_V_1 0x580017E4 +#define DISPC_WB_FIR2_COEF_V_2 0x580017E8 +#define DISPC_WB_FIR2_COEF_V_3 0x580017EC +#define DISPC_WB_FIR2_COEF_V_4 0x580017F0 +#define DISPC_WB_FIR2_COEF_V_5 0x580017F4 +#define DISPC_WB_FIR2_COEF_V_6 0x580017F8 +#define DISPC_WB_FIR2_COEF_V_7 0x580017FC +#define DISPC_GLOBAL_BUFFER 0x58001800 +#define DISPC_DIVISOR 0x58001804 +#define DISPC_WB_ATTRIBUTES2 0x58001810 + +/* DSI1 Physical address */ +#define DSI1_REVISION 0x58004000 +#define DSI1_SYSCONFIG 0x58004010 +#define DSI1_SYSSTATUS 0x58004014 +#define DSI1_IRQSTATUS 0x58004018 +#define DSI1_IRQENABLE 0x5800401C +#define DSI1_CTRL 0x58004040 +#define DSI1_GNQ 0x58004044 +#define DSI1_COMPLEXIO_CFG1 0x58004048 +#define DSI1_COMPLEXIO_IRQSTATUS 0x5800404C +#define DSI1_COMPLEXIO_IRQENABLE 0x58004050 +#define DSI1_CLK_CTRL 0x58004054 +#define DSI1_TIMING1 0x58004058 +#define DSI1_TIMING2 0x5800405C +#define DSI1_VM_TIMING1 0x58004060 +#define DSI1_VM_TIMING2 0x58004064 +#define DSI1_VM_TIMING3 0x58004068 +#define DSI1_CLK_TIMING 0x5800406C +#define DSI1_TX_FIFO_VC_SIZE 0x58004070 +#define DSI1_RX_FIFO_VC_SIZE 0x58004074 +#define DSI1_COMPLEXIO_CFG2 0x58004078 +#define DSI1_RX_FIFO_VC_FULLNESS 0x5800407C +#define DSI1_VM_TIMING4 0x58004080 +#define DSI1_TX_FIFO_VC_EMPTINESS 0x58004084 +#define DSI1_VM_TIMING5 0x58004088 +#define DSI1_VM_TIMING6 0x5800408C +#define DSI1_VM_TIMING7 0x58004090 +#define DSI1_STOPCLK_TIMING 0x58004094 +#define DSI1_CTRL2 0x58004098 +#define DSI1_VM_TIMING8 0x5800409C +#define DSI1_TE_HSYNC_WIDTH_0 0x580040A0 +#define DSI1_TE_VSYNC_WIDTH_0 0x580040A4 +#define DSI1_TE_HSYNC_NUMBER_0 0x580040A8 +#define DSI1_TE_HSYNC_WIDTH_1 0x580040AC +#define DSI1_TE_VSYNC_WIDTH_1 0x580040B0 +#define DSI1_TE_HSYNC_NUMBER_1 0x580040B4 +#define DSI1_VC_CTRL_1 0x58004100 +#define DSI1_VC_TE_1 0x58004104 +#define DSI1_VC_LONG_PACKET_HEADER_1 0x58004108 +#define DSI1_VC_LONG_PACKET_PAYLOAD_1 0x5800410C +#define DSI1_VC_SHORT_PACKET_HEADER_1 0x58004110 +#define DSI1_VC_IRQSTATUS_1 0x58004118 +#define DSI1_VC_IRQENABLE_1 0x5800411C +#define DSI1_VC_CTRL_2 0x58004120 +#define DSI1_VC_TE_2 0x58004124 +#define DSI1_VC_LONG_PACKET_HEADER_2 0x58004128 +#define DSI1_VC_LONG_PACKET_PAYLOAD_2 0x5800412C +#define DSI1_VC_SHORT_PACKET_HEADER_2 0x58004130 +#define DSI1_VC_IRQSTATUS_2 0x58004138 +#define DSI1_VC_IRQENABLE_2 0x5800413C +#define DSI1_VC_CTRL_3 0x58004140 +#define DSI1_VC_TE_3 0x58004144 +#define DSI1_VC_LONG_PACKET_HEADER_3 0x58004148 +#define DSI1_VC_LONG_PACKET_PAYLOAD_3 0x5800414C +#define DSI1_VC_SHORT_PACKET_HEADER_3 0x58004150 +#define DSI1_VC_IRQSTATUS_3 0x58004158 +#define DSI1_VC_IRQENABLE_3 0x5800415C +#define DSI1_VC_CTRL_4 0x58004160 +#define DSI1_VC_TE_4 0x58004164 +#define DSI1_VC_LONG_PACKET_HEADER_4 0x58004168 +#define DSI1_VC_LONG_PACKET_PAYLOAD_4 0x5800416C +#define DSI1_VC_SHORT_PACKET_HEADER_4 0x58004170 +#define DSI1_VC_IRQSTATUS_4 0x58004178 +#define DSI1_VC_IRQENABLE_4 0x5800417C + +/* DSI1 PHY Physical address */ +#define DSI1_PHY_REGISTER0 0x58004200 +#define DSI1_PHY_REGISTER1 0x58004204 +#define DSI1_PHY_REGISTER2 0x58004208 +#define DSI1_PHY_REGISTER3 0x5800420C +#define DSI1_PHY_REGISTER4 0x58004210 +#define DSI1_PHY_REGISTER5 0x58004214 + +/* DSI1 PLL Physical address */ +#define DSI1_PLL_CONTROL 0x58004300 +#define DSI1_PLL_STATUS 0x58004304 +#define DSI1_PLL_GO 0x58004308 +#define DSI1_PLL_CONFIGURATION1 0x5800430C +#define DSI1_PLL_CONFIGURATION2 0x58004310 +#define DSI1_PLL_CONFIGURATION3 0x58004314 +#define DSI1_PLL_SSC_CONFIGURATION1 0x58004318 +#define DSI1_PLL_SSC_CONFIGURATION2 0x5800431C +#define DSI1_PLL_CONFIG 0x58004320 + +/* DSI2 Physical address */ +#define DSI2_REVISION 0x58005000 +#define DSI2_SYSCONFIG 0x58005010 +#define DSI2_SYSSTATUS 0x58005014 +#define DSI2_IRQSTATUS 0x58005018 +#define DSI2_IRQENABLE 0x5800501C +#define DSI2_CTRL 0x58005040 +#define DSI2_GNQ 0x58005044 +#define DSI2_COMPLEXIO_CFG1 0x58005048 +#define DSI2_COMPLEXIO_IRQSTATUS 0x5800504C +#define DSI2_COMPLEXIO_IRQENABLE 0x58005050 +#define DSI2_CLK_CTRL 0x58005054 +#define DSI2_TIMING1 0x58005058 +#define DSI2_TIMING2 0x5800505C +#define DSI2_VM_TIMING1 0x58005060 +#define DSI2_VM_TIMING2 0x58005064 +#define DSI2_VM_TIMING3 0x58005068 +#define DSI2_CLK_TIMING 0x5800506C +#define DSI2_TX_FIFO_VC_SIZE 0x58005070 +#define DSI2_RX_FIFO_VC_SIZE 0x58005074 +#define DSI2_COMPLEXIO_CFG2 0x58005078 +#define DSI2_RX_FIFO_VC_FULLNESS 0x5800507C +#define DSI2_VM_TIMING4 0x58005080 +#define DSI2_TX_FIFO_VC_EMPTINESS 0x58005084 +#define DSI2_VM_TIMING5 0x58005088 +#define DSI2_VM_TIMING6 0x5800508C +#define DSI2_VM_TIMING7 0x58005090 +#define DSI2_STOPCLK_TIMING 0x58005094 +#define DSI2_CTRL2 0x58005098 +#define DSI2_VM_TIMING8 0x5800509C +#define DSI2_TE_HSYNC_WIDTH_0 0x580050A0 +#define DSI2_TE_VSYNC_WIDTH_0 0x580050A4 +#define DSI2_TE_HSYNC_NUMBER_0 0x580050A8 +#define DSI2_TE_HSYNC_WIDTH_1 0x580050AC +#define DSI2_TE_VSYNC_WIDTH_1 0x580050B0 +#define DSI2_TE_HSYNC_NUMBER_1 0x580050B4 +#define DSI2_VC_CTRL_1 0x58005100 +#define DSI2_VC_TE_1 0x58005104 +#define DSI2_VC_LONG_PACKET_HEADER_1 0x58005108 +#define DSI2_VC_LONG_PACKET_PAYLOAD_1 0x5800510C +#define DSI2_VC_SHORT_PACKET_HEADER_1 0x58005110 +#define DSI2_VC_IRQSTATUS_1 0x58005118 +#define DSI2_VC_IRQENABLE_1 0x5800511C +#define DSI2_VC_CTRL_2 0x58005120 +#define DSI2_VC_TE_2 0x58005124 +#define DSI2_VC_LONG_PACKET_HEADER_2 0x58005128 +#define DSI2_VC_LONG_PACKET_PAYLOAD_2 0x5800512C +#define DSI2_VC_SHORT_PACKET_HEADER_2 0x58005130 +#define DSI2_VC_IRQSTATUS_2 0x58005138 +#define DSI2_VC_IRQENABLE_2 0x5800513C +#define DSI2_VC_CTRL_3 0x58005140 +#define DSI2_VC_TE_3 0x58005144 +#define DSI2_VC_LONG_PACKET_HEADER_3 0x58005148 +#define DSI2_VC_LONG_PACKET_PAYLOAD_3 0x5800514C +#define DSI2_VC_SHORT_PACKET_HEADER_3 0x58005150 +#define DSI2_VC_IRQSTATUS_3 0x58005158 +#define DSI2_VC_IRQENABLE_3 0x5800515C +#define DSI2_VC_CTRL_4 0x58005160 +#define DSI2_VC_TE_4 0x58005164 +#define DSI2_VC_LONG_PACKET_HEADER_4 0x58005168 +#define DSI2_VC_LONG_PACKET_PAYLOAD_4 0x5800516C +#define DSI2_VC_SHORT_PACKET_HEADER_4 0x58005170 +#define DSI2_VC_IRQSTATUS_4 0x58005178 +#define DSI2_VC_IRQENABLE_4 0x5800517C + +/* DSI2 PHY Physical address */ +#define DSI2_PHY_REGISTER0 0x58005200 +#define DSI2_PHY_REGISTER1 0x58005204 +#define DSI2_PHY_REGISTER2 0x58005208 +#define DSI2_PHY_REGISTER3 0x5800520C +#define DSI2_PHY_REGISTER4 0x58005210 +#define DSI2_PHY_REGISTER5 0x58005214 + +/* DSI2 PLL Physical address */ +#define DSI2_PLL_CONTROL 0x58005300 +#define DSI2_PLL_STATUS 0x58005304 +#define DSI2_PLL_GO 0x58005308 +#define DSI2_PLL_CONFIGURATION1 0x5800530C +#define DSI2_PLL_CONFIGURATION2 0x58005310 +#define DSI2_PLL_CONFIGURATION3 0x58005314 +#define DSI2_PLL_SSC_CONFIGURATION1 0x58005318 +#define DSI2_PLL_SSC_CONFIGURATION2 0x5800531C +#define DSI2_PLL_CONFIG 0x58005320 + +/* RFBI Physical address */ +#define RFBI_REVISION 0x58002000 +#define RFBI_SYSCONFIG 0x58002010 +#define RFBI_SYSSTATUS 0x58002014 +#define RFBI_CONTROL 0x58002040 +#define RFBI_PIXEL_CNT 0x58002044 +#define RFBI_LINE_NUMBER 0x58002048 +#define RFBI_CMD 0x5800204C +#define RFBI_PARAM 0x58002050 +#define RFBI_DATA 0x58002054 +#define RFBI_READ 0x58002058 +#define RFBI_STATUS 0x5800205C +#define RFBI_CONFIG 0x58002060 +#define RFBI_ONOFF_TIME 0x58002064 +#define RFBI_CYCLE_TIME 0x58002068 +#define RFBI_DATA_CYCLE0 0x5800206C +#define RFBI_DATA_CYCLE1 0x58002070 +#define RFBI_DATA_CYCLE2 0x58002074 +#define RFBI_DATA_CYCLE3 0x58002078 +#define RFBI_DATA_CYCLE4 0x5800207C +#define RFBI_DATA_CYCLE5 0x58002080 +#define RFBI_DATA_CYCLE6 0x58002084 +#define RFBI_DATA_CYCLE7 0x58002088 +#define RFBI_VSYNC_WIDTH 0x58002090 +#define RFBI_HSYNC_WIDTH 0x58002094 + +/* VENC Physical address */ +#define VENC_REV_ID 0x58003000 +#define VENC_STATUS 0x58003004 +#define VENC_F_CONTROL 0x58003008 +#define VENC_VIDOUT_CTRL 0x58003010 +#define VENC_SYNC_CTRL 0x58003014 +#define VENC_LLEN 0x5800301C +#define VENC_FLENS 0x58003020 +#define VENC_HFLTR_CTRL 0x58003024 +#define VENC_CC_CARR_WSS_CARR 0x58003028 +#define VENC_C_PHASE 0x5800302C +#define VENC_GAIN_U 0x58003030 +#define VENC_GAIN_V 0x58003034 +#define VENC_GAIN_Y 0x58003038 +#define VENC_BLACK_LEVEL 0x5800303C +#define VENC_BLANK_LEVEL 0x58003040 +#define VENC_X_COLOR 0x58003044 +#define VENC_M_CONTROL 0x58003048 +#define VENC_BSTAMP_WSS_DATA 0x5800304C +#define VENC_S_CARR 0x58003050 +#define VENC_LINE21 0x58003054 +#define VENC_LN_SEL 0x58003058 +#define VENC_L21_WC_CTL 0x5800305C +#define VENC_HTRIGGER_VTRIGGER 0x58003060 +#define VENC_SAVID_EAVID 0x58003064 +#define VENC_FLEN_FAL 0x58003068 +#define VENC_LAL_PHASE_RESET 0x5800306C +#define VENC_HS_INT_START_STOP_X 0x58003070 +#define VENC_HS_EXT_START_STOP_X 0x58003074 +#define VENC_VS_INT_START_X 0x58003078 +#define VENC_VS_INT_STOP_X_VS_INT_START_Y 0x5800307C +#define VENC_VS_INT_STOP_Y_VS_EXT_START_X 0x58003080 +#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y 0x58003084 +#define VENC_VS_EXT_STOP_Y 0x58003088 +#define VENC_AVID_START_STOP_X 0x58003090 +#define VENC_AVID_START_STOP_Y 0x58003094 +#define VENC_FID_INT_START_X_FID_INT_START_Y 0x580030A0 +#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X 0x580030A4 +#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y 0x580030A8 +#define VENC_TVDETGP_INT_START_STOP_X 0x580030B0 +#define VENC_TVDETGP_INT_START_STOP_Y 0x580030B4 +#define VENC_GEN_CTRL 0x580030B8 +#define VENC_OUTPUT_CONTROL 0x580030C4 +#define VENC_OUTPUT_TEST 0x580030C8 + + +int display44xx_name2addr(char *name, unsigned int *addr); +int display44xx_dump(char *display_mod); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll4430-data-38_4MHz.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll4430-data-38_4MHz.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll4430-data-38_4MHz.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll4430-data-38_4MHz.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,519 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll4430-data-38_4MHz.c + * @Description OMAP4430 DPLL Golden Settings + * (with 38.4MHz system clock) + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include + + +const dpll44xx_audit_settings dpll4430_MPU_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = 1, + .M2_clkout_rate = 196.608, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_MPU_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 7, + .fdpll = 1200, + .M2 = 2, + .M2_clkout_rate = 300, + .X2_M2_clkdcoldo_rate = 600, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_MPU_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 7, + .fdpll = 1200, + .M2 = 1, + .M2_clkout_rate = 600, + .X2_M2_clkdcoldo_rate = 1200, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_MPU_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 1, + .M2_clkout_rate = 800, + .X2_M2_clkdcoldo_rate = 1600, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_MPU_golden_settings_38_4MHz_opp_nitro = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 625, + .N = 23, + .fdpll = 2000, + .M2 = 1, + .M2_clkout_rate = 1000, + .X2_M2_clkdcoldo_rate = 2000, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_MPU_golden_settings_38_4MHz_opp_nitrosb = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 3, + .fdpll = 2400, + .M2 = 1, + .M2_clkout_rate = 1200, + .X2_M2_clkdcoldo_rate = 2400, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4430_MPU_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4430_MPU_golden_settings_38_4MHz_dpll_casc, + &dpll4430_MPU_golden_settings_38_4MHz_opp50, + &dpll4430_MPU_golden_settings_38_4MHz_opp100, + &dpll4430_MPU_golden_settings_38_4MHz_opp_turbo, + &dpll4430_MPU_golden_settings_38_4MHz_opp_nitro, + &dpll4430_MPU_golden_settings_38_4MHz_opp_nitrosb}; + + +const dpll44xx_audit_settings dpll4430_IVA_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {98.304, 98.304, -1, -1} }; + + +const dpll44xx_audit_settings dpll4430_IVA_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 291, + .N = 11, + .fdpll = 1862.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {8, 14, -1, -1}, + .hsdiv_rate = {232.8, 133, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_IVA_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 291, + .N = 11, + .fdpll = 1862.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {4, 7, -1, -1}, + .hsdiv_rate = {465.6, 266.1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_IVA_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 155, + .N = 11, + .fdpll = 992, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {2, 3, -1, -1}, + .hsdiv_rate = {496, 330.7, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4430_IVA_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4430_IVA_golden_settings_38_4MHz_dpll_casc, + &dpll4430_IVA_golden_settings_38_4MHz_opp50, + &dpll4430_IVA_golden_settings_38_4MHz_opp100, + &dpll4430_IVA_golden_settings_38_4MHz_opp_turbo, + (dpll44xx_audit_settings *) NULL, + (dpll44xx_audit_settings *) NULL}; + + +const dpll44xx_audit_settings dpll4430_CORE_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_DISABLED, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = 196.608, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 8, + .X2_M3_rate = 24.576, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {196.608, 196.608, 196.608, 196.608} }; + +const dpll44xx_audit_settings dpll4430_CORE_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 2, + .M2_clkout_rate = 400, + .X2_M2_clkdcoldo_rate = 800, + .M3 = 8, + .X2_M3_rate = 200, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 8, 8, 12}, + .hsdiv_rate = {200, 200, 200, 133.3} }; + +const dpll44xx_audit_settings dpll4430_CORE_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 1, + .M2_clkout_rate = 800, + .X2_M2_clkdcoldo_rate = 1600, + .M3 = 5, + .X2_M3_rate = 320, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 4, 6, 6}, + .hsdiv_rate = {200, 400, 266.7, 266.7} }; + +const dpll44xx_audit_settings + *dpll4430_CORE_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4430_CORE_golden_settings_38_4MHz_dpll_casc, + &dpll4430_CORE_golden_settings_38_4MHz_opp50, + &dpll4430_CORE_golden_settings_38_4MHz_opp100, + (dpll44xx_audit_settings *) NULL, + (dpll44xx_audit_settings *) NULL, + (dpll44xx_audit_settings *) NULL}; + + +const dpll44xx_audit_settings dpll4430_PER_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 98.304, + .M3 = 8, + .X2_M3_rate = 0, /* 24.576MHz but output is gated */ + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {98.304, 98.304, 98.304, 98.304} }; + +const dpll44xx_audit_settings dpll4430_PER_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 8, + .X2_M3_rate = 192, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 8, 10}, + .hsdiv_rate = {128, 170.7, 192, 153.6} }; + +const dpll44xx_audit_settings dpll4430_PER_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 6, + .X2_M3_rate = 256, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 4, 5}, + .hsdiv_rate = {128, 170.7, 384, 307.2} }; + +const dpll44xx_audit_settings + *dpll4430_PER_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4430_PER_golden_settings_38_4MHz_dpll_casc, + &dpll4430_PER_golden_settings_38_4MHz_opp50, + &dpll4430_PER_golden_settings_38_4MHz_opp100, + (dpll44xx_audit_settings *) NULL, + (dpll44xx_audit_settings *) NULL, + (dpll44xx_audit_settings *) NULL}; + + +const dpll44xx_audit_settings dpll4430_ABE_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_DISABLED, + .lpmode = 1, + .regm4xen = 1, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 750, + .N = 0, + .fdpll = 196.608, + .M2 = 1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 1, + .X2_M3_rate = 196.608, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_ABE_golden_settings_38_4MHz_all_opp = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 1, + .regm4xen = 1, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 750, + .N = 0, + .fdpll = 196.608, + .M2 = 1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 1, + .X2_M3_rate = 196.608, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4430_ABE_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4430_ABE_golden_settings_38_4MHz_dpll_casc, + &dpll4430_ABE_golden_settings_38_4MHz_all_opp, + &dpll4430_ABE_golden_settings_38_4MHz_all_opp, + &dpll4430_ABE_golden_settings_38_4MHz_all_opp, + &dpll4430_ABE_golden_settings_38_4MHz_all_opp, + &dpll4430_ABE_golden_settings_38_4MHz_all_opp}; + + +const dpll44xx_audit_settings dpll4430_USB_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_STOPPED, + .mode = DPLL_LOW_POWER_STOP, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4430_USB_golden_settings_38_4MHz_all_opp = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 400, + .N = 15, + .fdpll = 960, + .M2 = 2, + .M2_clkout_rate = 480, + .X2_M2_clkdcoldo_rate = 960, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + + +const dpll44xx_audit_settings + *dpll4430_USB_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4430_USB_golden_settings_38_4MHz_dpll_casc, + &dpll4430_USB_golden_settings_38_4MHz_all_opp, + &dpll4430_USB_golden_settings_38_4MHz_all_opp, + &dpll4430_USB_golden_settings_38_4MHz_all_opp, + &dpll4430_USB_golden_settings_38_4MHz_all_opp, + &dpll4430_USB_golden_settings_38_4MHz_all_opp}; + + +const dpll44xx_audit_settings **dpll4430_golden_settings_38_4MHz[DPLL44XX_ID_MAX] = { + (const dpll44xx_audit_settings **) &dpll4430_MPU_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4430_IVA_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4430_CORE_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4430_PER_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4430_ABE_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4430_USB_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) NULL, + (const dpll44xx_audit_settings **) NULL}; diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll4460-data-38_4MHz.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll4460-data-38_4MHz.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll4460-data-38_4MHz.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll4460-data-38_4MHz.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,598 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll4460-data-38_4MHz.c + * @Description OMAP4460 DPLL Golden Settings + * (with 38.4MHz system clock) + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include + + +const dpll44xx_audit_settings dpll4460_MPU_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = 1, + .M2_clkout_rate = 196.608, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_MPU_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 73, + .N = 3, + .fdpll = 1401.6, + .M2 = 2, + .M2_clkout_rate = 350.4, + .X2_M2_clkdcoldo_rate = 700.8, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_MPU_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 73, + .N = 3, + .fdpll = 1401.6, + .M2 = 1, + .M2_clkout_rate = 700.8, + .X2_M2_clkdcoldo_rate = 1401.6, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_MPU_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 24, + .N = 0, + .fdpll = 1843.2, + .M2 = 1, + .M2_clkout_rate = 921.6, + .X2_M2_clkdcoldo_rate = 1843.2, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_MPU_golden_settings_38_4MHz_opp_nitro = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 1, + .dcc_count = 2.5, + .M = 125, + .N = 7, + .fdpll = 1200, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = 1, + .X2_M3_rate = 1200, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_MPU_golden_settings_38_4MHz_opp_nitrosb = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 1, + .dcc_count = 2.5, + .M = 39, + .N = 1, + .fdpll = 1497.6, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = 1, + .X2_M3_rate = 1497.6, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4460_MPU_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4460_MPU_golden_settings_38_4MHz_dpll_casc, + &dpll4460_MPU_golden_settings_38_4MHz_opp50, + &dpll4460_MPU_golden_settings_38_4MHz_opp100, + &dpll4460_MPU_golden_settings_38_4MHz_opp_turbo, + &dpll4460_MPU_golden_settings_38_4MHz_opp_nitro, + &dpll4460_MPU_golden_settings_38_4MHz_opp_nitrosb}; + + +const dpll44xx_audit_settings dpll4460_IVA_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {98.304, 98.304, -1, -1} }; + + +const dpll44xx_audit_settings dpll4460_IVA_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 97, + .N = 3, + .fdpll = 1862.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {8, 14, -1, -1}, + .hsdiv_rate = {232.8, 133, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_IVA_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 97, + .N = 3, + .fdpll = 1862.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {4, 7, -1, -1}, + .hsdiv_rate = {465.6, 266.1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_IVA_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 155, + .N = 11, + .fdpll = 992, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {2, 3, -1, -1}, + .hsdiv_rate = {496, 330.7, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_IVA_golden_settings_38_4MHz_opp_nitro = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 56, + .N = 4, + .fdpll = 860.2, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {2, 2, -1, -1}, + .hsdiv_rate = {430.1, 430.1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_IVA_golden_settings_38_4MHz_opp_nitrosb = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 13, + .N = 0, + .fdpll = 998.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {2, 2, -1, -1}, + .hsdiv_rate = {499.2, 499.2, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4460_IVA_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4460_IVA_golden_settings_38_4MHz_dpll_casc, + &dpll4460_IVA_golden_settings_38_4MHz_opp50, + &dpll4460_IVA_golden_settings_38_4MHz_opp100, + &dpll4460_IVA_golden_settings_38_4MHz_opp_turbo, + &dpll4460_IVA_golden_settings_38_4MHz_opp_nitro, + &dpll4460_IVA_golden_settings_38_4MHz_opp_nitrosb}; + + +const dpll44xx_audit_settings dpll4460_CORE_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_DISABLED, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = 196.608, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 8, + .X2_M3_rate = 24.576, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {196.608, 196.608, 196.608, 196.608} }; + +const dpll44xx_audit_settings dpll4460_CORE_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 2, + .M2_clkout_rate = 400, + .X2_M2_clkdcoldo_rate = 800, + .M3 = 8, + .X2_M3_rate = 200, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 8, 8, 12}, + .hsdiv_rate = {200, 200, 200, 133.3} }; + +const dpll44xx_audit_settings dpll4460_CORE_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 1, + .M2_clkout_rate = 800, + .X2_M2_clkdcoldo_rate = 1600, + .M3 = 5, + .X2_M3_rate = 320, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 4, 6, 6}, + .hsdiv_rate = {200, 400, 266.7, 266.7} }; + +const dpll44xx_audit_settings dpll4460_CORE_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 1, + .M2_clkout_rate = 800, + .X2_M2_clkdcoldo_rate = 1600, + .M3 = 5, + .X2_M3_rate = 320, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 4, 6, 6}, + .hsdiv_rate = {200, 400, 266.7, 266.7} }; + +const dpll44xx_audit_settings + *dpll4460_CORE_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4460_CORE_golden_settings_38_4MHz_dpll_casc, + &dpll4460_CORE_golden_settings_38_4MHz_opp50, + &dpll4460_CORE_golden_settings_38_4MHz_opp100, + &dpll4460_CORE_golden_settings_38_4MHz_opp_turbo, + (dpll44xx_audit_settings *) NULL, + (dpll44xx_audit_settings *) NULL}; + + +const dpll44xx_audit_settings dpll4460_PER_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 98.304, + .M3 = 8, + .X2_M3_rate = 0, /* 24.576MHz but output is gated */ + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {98.304, 98.304, 98.304, 98.304} }; + +const dpll44xx_audit_settings dpll4460_PER_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 8, + .X2_M3_rate = 192, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 8, 10}, + .hsdiv_rate = {128, 170.7, 192, 153.6} }; + +const dpll44xx_audit_settings dpll4460_PER_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 6, + .X2_M3_rate = 256, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 4, 5}, + .hsdiv_rate = {128, 170.7, 384, 307.2} }; + +const dpll44xx_audit_settings dpll4460_PER_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 6, + .X2_M3_rate = 256, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 4, 4}, + .hsdiv_rate = {128, 170.7, 384, 384} }; + +const dpll44xx_audit_settings + *dpll4460_PER_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4460_PER_golden_settings_38_4MHz_dpll_casc, + &dpll4460_PER_golden_settings_38_4MHz_opp50, + &dpll4460_PER_golden_settings_38_4MHz_opp100, + &dpll4460_PER_golden_settings_38_4MHz_opp_turbo, + (dpll44xx_audit_settings *) NULL, + (dpll44xx_audit_settings *) NULL}; + + +const dpll44xx_audit_settings dpll4460_ABE_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_DISABLED, + .lpmode = 1, + .regm4xen = 1, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 750, + .N = 0, + .fdpll = 196.608, + .M2 = 1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 1, + .X2_M3_rate = 196.608, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_ABE_golden_settings_38_4MHz_all_opp = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 1, + .regm4xen = 1, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 750, + .N = 0, + .fdpll = 196.608, + .M2 = 1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 1, + .X2_M3_rate = 196.608, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4460_ABE_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4460_ABE_golden_settings_38_4MHz_dpll_casc, + &dpll4460_ABE_golden_settings_38_4MHz_all_opp, + &dpll4460_ABE_golden_settings_38_4MHz_all_opp, + &dpll4460_ABE_golden_settings_38_4MHz_all_opp, + &dpll4460_ABE_golden_settings_38_4MHz_all_opp, + &dpll4460_ABE_golden_settings_38_4MHz_all_opp}; + + +const dpll44xx_audit_settings dpll4460_USB_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_STOPPED, + .mode = DPLL_LOW_POWER_STOP, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4460_USB_golden_settings_38_4MHz_all_opp = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 400, + .N = 15, + .fdpll = 960, + .M2 = 2, + .M2_clkout_rate = 480, + .X2_M2_clkdcoldo_rate = 960, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4460_USB_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4460_USB_golden_settings_38_4MHz_dpll_casc, + &dpll4460_USB_golden_settings_38_4MHz_all_opp, + &dpll4460_USB_golden_settings_38_4MHz_all_opp, + &dpll4460_USB_golden_settings_38_4MHz_all_opp, + &dpll4460_USB_golden_settings_38_4MHz_all_opp, + &dpll4460_USB_golden_settings_38_4MHz_all_opp}; + + +const dpll44xx_audit_settings **dpll4460_golden_settings_38_4MHz[DPLL44XX_ID_MAX] = { + (const dpll44xx_audit_settings **) &dpll4460_MPU_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4460_IVA_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4460_CORE_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4460_PER_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4460_ABE_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4460_USB_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) NULL, + (const dpll44xx_audit_settings **) NULL}; diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll4470-data-38_4MHz.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll4470-data-38_4MHz.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll4470-data-38_4MHz.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll4470-data-38_4MHz.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,681 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll4470-data-38_4MHz.c + * @Description OMAP4470 DPLL Golden Settings + * (with 38.4MHz system clock) + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include + + +const dpll44xx_audit_settings dpll4470_MPU_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = 1, + .M2_clkout_rate = 196.608, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + + +const dpll44xx_audit_settings dpll4470_MPU_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 2, + .M2_clkout_rate = 400, + .X2_M2_clkdcoldo_rate = 800, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_MPU_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 1, + .M2_clkout_rate = 800, + .X2_M2_clkdcoldo_rate = 1600, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_MPU_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 1, + .dcc_count = 2.5, + .M = 43, + .N = 2, + .fdpll = 1100.8, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = 1, + .X2_M3_rate = 1100.8, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_MPU_golden_settings_38_4MHz_opp_nitro = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 1, + .dcc_count = 2.5, + .M = 169, + .N = 9, + .fdpll = 1297.9, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = 1, + .X2_M3_rate = 1297.9, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_MPU_golden_settings_38_4MHz_opp_nitrosb = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 1, + .dcc_count = 2.5, + .M = 39, + .N = 1, + .fdpll = 1497.6, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = 1, + .X2_M3_rate = 1497.6, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4470_MPU_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4470_MPU_golden_settings_38_4MHz_dpll_casc, + &dpll4470_MPU_golden_settings_38_4MHz_opp50, + &dpll4470_MPU_golden_settings_38_4MHz_opp100, + &dpll4470_MPU_golden_settings_38_4MHz_opp_turbo, + &dpll4470_MPU_golden_settings_38_4MHz_opp_nitro, + &dpll4470_MPU_golden_settings_38_4MHz_opp_nitrosb}; + + +const dpll44xx_audit_settings dpll4470_IVA_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {98.304, 98.304, -1, -1} }; + + +const dpll44xx_audit_settings dpll4470_IVA_golden_settings_38_4MHz_opp50 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 97, + .N = 3, + .fdpll = 1862.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {8, 14, -1, -1}, + .hsdiv_rate = {232.8, 133, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_IVA_golden_settings_38_4MHz_opp100 = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 97, + .N = 3, + .fdpll = 1862.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {4, 7, -1, -1}, + .hsdiv_rate = {465.6, 266.1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_IVA_golden_settings_38_4MHz_opp_turbo = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 155, + .N = 11, + .fdpll = 992, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {2, 3, -1, -1}, + .hsdiv_rate = {496, 330.7, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_IVA_golden_settings_38_4MHz_opp_nitro = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 56, + .N = 4, + .fdpll = 860.2, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {2, 2, -1, -1}, + .hsdiv_rate = {430.1, 430.1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_IVA_golden_settings_38_4MHz_opp_nitrosb = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 13, + .N = 0, + .fdpll = 998.4, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {1, 1, -1, -1}, + .hsdiv = {2, 2, -1, -1}, + .hsdiv_rate = {499.2, 499.2, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4470_IVA_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4470_IVA_golden_settings_38_4MHz_dpll_casc, + &dpll4470_IVA_golden_settings_38_4MHz_opp50, + &dpll4470_IVA_golden_settings_38_4MHz_opp100, + &dpll4470_IVA_golden_settings_38_4MHz_opp_turbo, + &dpll4470_IVA_golden_settings_38_4MHz_opp_nitro, + &dpll4470_IVA_golden_settings_38_4MHz_opp_nitrosb}; + + +const dpll44xx_audit_settings dpll4470_CORE_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_DISABLED, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = 196.608, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 8, + .X2_M3_rate = 24.576, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {196.608, 196.608, 196.608, 196.608} }; + + +const dpll44xx_audit_settings dpll4470_CORE_golden_settings_38_4MHz_opp50_low = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 2, + .M2_clkout_rate = 400, + .X2_M2_clkdcoldo_rate = 800, + .M3 = 8, + .X2_M3_rate = 200, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 8, 8, 9}, + .hsdiv_rate = {200, 200, 200, 177.8} }; + +const dpll44xx_audit_settings dpll4470_CORE_golden_settings_38_4MHz_opp50_high = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 97, + .N = 3, + .fdpll = 1862.4, + .M2 = 2, + .M2_clkout_rate = 465.6, + .X2_M2_clkdcoldo_rate = 931.2, + .M3 = 9, + .X2_M3_rate = 206.9, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 8, 9, 10}, + .hsdiv_rate = {232.8, 232.8, 206.9, 186.2} }; + +const dpll44xx_audit_settings dpll4470_CORE_golden_settings_38_4MHz_opp100_low = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 1, + .M2_clkout_rate = 800, + .X2_M2_clkdcoldo_rate = 1600, + .M3 = 5, + .X2_M3_rate = 320, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 4, 6, 6}, + .hsdiv_rate = {200, 400, 266.7, 266.7} }; + +const dpll44xx_audit_settings dpll4470_CORE_golden_settings_38_4MHz_opp119_low = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 125, + .N = 5, + .fdpll = 1600, + .M2 = 1, + .M2_clkout_rate = 800, + .X2_M2_clkdcoldo_rate = 1600, + .M3 = 5, + .X2_M3_rate = 320, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 4, 6, 5}, + .hsdiv_rate = {200, 400, 266.7, 320} }; + +const dpll44xx_audit_settings dpll4470_CORE_golden_settings_38_4MHz_opp119_high = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 97, + .N = 3, + .fdpll = 1862.4, + .M2 = 1, + .M2_clkout_rate = 931.2, + .X2_M2_clkdcoldo_rate = 1862.4, + .M3 = 6, + .X2_M3_rate = 310.4, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {8, 4, 6, 5}, + .hsdiv_rate = {232.8, 465.6, 310.4, 372.5} }; + +const dpll44xx_audit_settings + *dpll4470_CORE_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4470_CORE_golden_settings_38_4MHz_dpll_casc, + &dpll4470_CORE_golden_settings_38_4MHz_opp50_low, + &dpll4470_CORE_golden_settings_38_4MHz_opp50_high, + &dpll4470_CORE_golden_settings_38_4MHz_opp100_low, + &dpll4470_CORE_golden_settings_38_4MHz_opp119_low, + &dpll4470_CORE_golden_settings_38_4MHz_opp119_high}; + + +const dpll44xx_audit_settings dpll4470_PER_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_BYPASSED, + .mode = DPLL_LOW_POWER_BYPASS, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 98.304, + .M3 = 8, + .X2_M3_rate = 0, /* 24.576MHz but output is gated */ + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {98.304, 98.304, 98.304, 98.304} }; + + +const dpll44xx_audit_settings dpll4470_PER_golden_settings_38_4MHz_opp50_low = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 8, + .X2_M3_rate = 192, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 8, 8}, + .hsdiv_rate = {128, 170.7, 192, 192} }; + +const dpll44xx_audit_settings dpll4470_PER_golden_settings_38_4MHz_opp50_high = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 8, + .X2_M3_rate = 192, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 8, 8}, + .hsdiv_rate = {128, 170.7, 192, 192} }; + +const dpll44xx_audit_settings dpll4470_PER_golden_settings_38_4MHz_opp100_low = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 6, + .X2_M3_rate = 256, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 5, 5}, + .hsdiv_rate = {128, 170.7, 307.2, 307.2} }; + +const dpll44xx_audit_settings dpll4470_PER_golden_settings_38_4MHz_opp119_low = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 6, + .X2_M3_rate = 256, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 4, 4}, + .hsdiv_rate = {128, 170.7, 384, 384} }; + +const dpll44xx_audit_settings dpll4470_PER_golden_settings_38_4MHz_opp119_high = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 40, + .N = 1, + .fdpll = 1536, + .M2 = 8, + .M2_clkout_rate = 96, + .X2_M2_clkdcoldo_rate = 192, + .M3 = 6, + .X2_M3_rate = 256, + .hsdiv_present = {1, 1, 1, 1}, + .hsdiv = {12, 9, 4, 4}, + .hsdiv_rate = {128, 170.7, 384, 384} }; + +const dpll44xx_audit_settings + *dpll4470_PER_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4470_PER_golden_settings_38_4MHz_dpll_casc, + &dpll4470_PER_golden_settings_38_4MHz_opp50_low, + &dpll4470_PER_golden_settings_38_4MHz_opp50_high, + &dpll4470_PER_golden_settings_38_4MHz_opp100_low, + &dpll4470_PER_golden_settings_38_4MHz_opp119_low, + &dpll4470_PER_golden_settings_38_4MHz_opp119_high}; + + +const dpll44xx_audit_settings dpll4470_ABE_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_DISABLED, + .lpmode = 1, + .regm4xen = 1, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 750, + .N = 0, + .fdpll = 196.608, + .M2 = 1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 1, + .X2_M3_rate = 196.608, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_ABE_golden_settings_38_4MHz_all_opp = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 1, + .regm4xen = 1, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 750, + .N = 0, + .fdpll = 196.608, + .M2 = 1, + .M2_clkout_rate = 98.304, + .X2_M2_clkdcoldo_rate = 196.608, + .M3 = 1, + .X2_M3_rate = 196.608, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4470_ABE_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4470_ABE_golden_settings_38_4MHz_dpll_casc, + &dpll4470_ABE_golden_settings_38_4MHz_all_opp, + &dpll4470_ABE_golden_settings_38_4MHz_all_opp, + &dpll4470_ABE_golden_settings_38_4MHz_all_opp, + &dpll4470_ABE_golden_settings_38_4MHz_all_opp, + &dpll4470_ABE_golden_settings_38_4MHz_all_opp}; + + +const dpll44xx_audit_settings dpll4470_USB_golden_settings_38_4MHz_dpll_casc = { + .status = DPLL_STATUS_STOPPED, + .mode = DPLL_LOW_POWER_STOP, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = -1, + .N = -1, + .fdpll = -1, + .M2 = -1, + .M2_clkout_rate = -1, + .X2_M2_clkdcoldo_rate = -1, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings dpll4470_USB_golden_settings_38_4MHz_all_opp = { + .status = DPLL_STATUS_LOCKED, + .mode = DPLL_LOCK, + .autoidle_mode = DPLL_AUTO_LOW_POWER_STOP, + .lpmode = 0, + .regm4xen = 0, + .dcc_en = 0, + .dcc_count = 2.5, + .M = 400, + .N = 15, + .fdpll = 960, + .M2 = 2, + .M2_clkout_rate = 480, + .X2_M2_clkdcoldo_rate = 960, + .M3 = -1, + .X2_M3_rate = -1, + .hsdiv_present = {-1, -1, -1, -1}, + .hsdiv = {-1, -1, -1, -1}, + .hsdiv_rate = {-1, -1, -1, -1} }; + +const dpll44xx_audit_settings + *dpll4470_USB_golden_settings_38_4MHz[OPP44XX_ID_MAX] = { + &dpll4470_USB_golden_settings_38_4MHz_dpll_casc, + &dpll4470_USB_golden_settings_38_4MHz_all_opp, + &dpll4470_USB_golden_settings_38_4MHz_all_opp, + &dpll4470_USB_golden_settings_38_4MHz_all_opp, + &dpll4470_USB_golden_settings_38_4MHz_all_opp, + &dpll4470_USB_golden_settings_38_4MHz_all_opp}; + + +const dpll44xx_audit_settings **dpll4470_golden_settings_38_4MHz[DPLL44XX_ID_MAX] = { + (const dpll44xx_audit_settings **) &dpll4470_MPU_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4470_IVA_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4470_CORE_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4470_PER_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4470_ABE_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) &dpll4470_USB_golden_settings_38_4MHz, + (const dpll44xx_audit_settings **) NULL, + (const dpll44xx_audit_settings **) NULL}; diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,344 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll44xx-data.c + * @Description OMAP4 DPLL Definitions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include + + +reg_table dpll44xx_prcm_reg_table[80]; +static unsigned int dpll44xx_prcm_reg_table_init_done = 0; + + +const char dpll44xx_names[DPLL44XX_ID_MAX + 1][DPLL_MAX_NAME_LENGTH] = { + "DPLL_MPU", + "DPLL_IVA", + "DPLL_CORE", + "DPLL_PER", + "DPLL_ABE", + "DPLL_USB", + "DPLL_UNIPRO", + "DPLL_DDRPHY", + "FIXME"}; + + +const char dpll44xx_output_names[DPLL44XX_OUTPUT_ID_MAX + 1][DPLL_OUTPUT_MAX_NAME_LENGTH] = { + "CLKOUT_M2", + "CLKOUTX2_M2", + "CLKOUTX2_M3", + "CLKOUTX2_M4", + "CLKOUTX2_M5", + "CLKOUTX2_M6", + "CLKOUTX2_M7", + "CLK_DCO_LDO", + "FIXME"}; + + +const omap4_dpll_MN_params_regs omap4_dpll_MN_regs[DPLL44XX_ID_MAX] = { + {OMAP4430_CM_CLKSEL_DPLL_MPU, OMAP4430_CM_DIV_M2_DPLL_MPU, 0}, + {OMAP4430_CM_CLKSEL_DPLL_IVA, 0, 0}, + {OMAP4430_CM_CLKSEL_DPLL_CORE, OMAP4430_CM_DIV_M2_DPLL_CORE, OMAP4430_CM_DIV_M3_DPLL_CORE}, + {OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_CM_DIV_M3_DPLL_PER}, + {OMAP4430_CM_CLKSEL_DPLL_ABE, OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_CM_DIV_M3_DPLL_ABE}, + {OMAP4430_CM_CLKSEL_DPLL_USB, OMAP4430_CM_DIV_M2_DPLL_USB, 0}, + {OMAP4430_CM_CLKSEL_DPLL_UNIPRO, OMAP4430_CM_DIV_M2_DPLL_UNIPRO, 0}, + {OMAP4430_CM_CLKSEL_DPLL_DDRPHY, OMAP4430_CM_DIV_M2_DPLL_DDRPHY, 0} +}; + + +const unsigned int omap4_dpll_hs_divider_regs[DPLL44XX_ID_MAX][4] = { + {0, 0, 0, 0}, + {OMAP4430_CM_DIV_M4_DPLL_IVA, OMAP4430_CM_DIV_M5_DPLL_IVA, 0, 0}, + {OMAP4430_CM_DIV_M4_DPLL_CORE, OMAP4430_CM_DIV_M5_DPLL_CORE, OMAP4430_CM_DIV_M6_DPLL_CORE, OMAP4430_CM_DIV_M7_DPLL_CORE}, + {OMAP4430_CM_DIV_M4_DPLL_PER, OMAP4430_CM_DIV_M5_DPLL_PER, OMAP4430_CM_DIV_M6_DPLL_PER, OMAP4430_CM_DIV_M7_DPLL_PER}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {OMAP4430_CM_DIV_M4_DPLL_DDRPHY, OMAP4430_CM_DIV_M5_DPLL_DDRPHY, OMAP4430_CM_DIV_M6_DPLL_DDRPHY, 0} +}; + + +const omap4_dpll_params_regs omap4_dpll_regs[DPLL44XX_ID_MAX] = { + {OMAP4430_CM_CLKMODE_DPLL_MPU, OMAP4430_CM_IDLEST_DPLL_MPU, OMAP4430_CM_AUTOIDLE_DPLL_MPU, OMAP4430_CM_CLKSEL_DPLL_MPU, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CM_DIV_M2_DPLL_MPU, 0}, + {OMAP4430_CM_CLKMODE_DPLL_IVA, OMAP4430_CM_IDLEST_DPLL_IVA, OMAP4430_CM_AUTOIDLE_DPLL_IVA, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_CM_BYPCLK_DPLL_IVA, 0, 0}, + {OMAP4430_CM_CLKMODE_DPLL_CORE, OMAP4430_CM_IDLEST_DPLL_CORE, OMAP4430_CM_AUTOIDLE_DPLL_CORE, OMAP4430_CM_CLKSEL_DPLL_CORE, 0, OMAP4430_CM_DIV_M2_DPLL_CORE, OMAP4430_CM_DIV_M3_DPLL_CORE}, + {OMAP4430_CM_CLKMODE_DPLL_PER, OMAP4430_CM_IDLEST_DPLL_PER, OMAP4430_CM_AUTOIDLE_DPLL_PER, OMAP4430_CM_CLKSEL_DPLL_PER, 0, OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_CM_DIV_M3_DPLL_PER}, + {OMAP4430_CM_CLKMODE_DPLL_ABE, OMAP4430_CM_IDLEST_DPLL_ABE, OMAP4430_CM_AUTOIDLE_DPLL_ABE, OMAP4430_CM_CLKSEL_DPLL_ABE, 0, OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_CM_DIV_M3_DPLL_ABE}, + {OMAP4430_CM_CLKMODE_DPLL_USB, OMAP4430_CM_IDLEST_DPLL_USB, OMAP4430_CM_AUTOIDLE_DPLL_USB, OMAP4430_CM_CLKSEL_DPLL_USB, 0, OMAP4430_CM_DIV_M2_DPLL_USB, 0}, + {OMAP4430_CM_CLKMODE_DPLL_UNIPRO, OMAP4430_CM_IDLEST_DPLL_UNIPRO, OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, OMAP4430_CM_CLKSEL_DPLL_UNIPRO, 0, OMAP4430_CM_DIV_M2_DPLL_UNIPRO, 0}, + {OMAP4430_CM_CLKMODE_DPLL_DDRPHY, OMAP4430_CM_IDLEST_DPLL_DDRPHY, OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY, OMAP4430_CM_CLKSEL_DPLL_DDRPHY, 0, OMAP4430_CM_DIV_M2_DPLL_DDRPHY, 0}, +}; + + +const omap4_dpll_clock_sources omap4_dpll_sources[DPLL44XX_ID_MAX] = { + {OMAP4_MPU_DPLL_ALWON_CLK, OMAP4_MPU_DPLL_HS_CLK, OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX}, + {OMAP4_IVA_DPLL_ALWON_CLK, OMAP4_IVA_DPLL_HS_CLK, OMAP4_CLOCK_ID_MAX, OMAP4_IVA_HSD_BYP_CLK}, + {OMAP4_CORE_DPLL_ALWON_CLK, OMAP4_CORE_DPLL_HS_CLK, OMAP4_CORE_DPLL_HS_CLK, OMAP4_CORE_PHY_HSD_BYP_CLK}, + {OMAP4_PER_DPLL_ALWON_CLK, OMAP4_PER_DPLL_HS_CLK, OMAP4_CLOCK_ID_MAX, OMAP4_PER_HSD_BYP_CLK}, + {OMAP4_ABE_DPLL_ALWON_CLK, OMAP4_ABE_DPLL_BYPASS_CLK, OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX}, + {OMAP4_L3INIT_DPLL_ALWON_CLK, OMAP4_USB_DPLL_HS_CLK, OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX}, + {OMAP4_L3INIT_DPLL_ALWON_CLK, OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX}, + {OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX, OMAP4_CLOCK_ID_MAX} }; + + + +/** + * Function: dpll44xx_init_regtable + * Role: initialize .addr field of reg_table (not possible statically) + * Parameters: + * none + * Return: + * 0 + * OMAPCONF_ERR_CPU + */ +int dpll44xx_init_regtable(void) +{ + unsigned int i = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (dpll44xx_prcm_reg_table_init_done == 1) + return 0; + + /* Init DPLLs registers table */ + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M6_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M6_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M7_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M7_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_CORE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_EMU_OVERRIDE_DPLL_CORE"); + + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M6_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M6_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M7_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M7_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_PER"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_EMU_OVERRIDE_DPLL_PER; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_EMU_OVERRIDE_DPLL_PER"); + + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_MPU"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_MPU"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_MPU"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_MPU"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_MPU"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_MPU"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_MPU"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_BYPCLK_DPLL_MPU; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_BYPCLK_DPLL_MPU"); + + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_IVA"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_BYPCLK_DPLL_IVA; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_BYPCLK_DPLL_IVA"); + + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_ABE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_ABE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_ABE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_ABE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_ABE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_ABE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_ABE"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_ABE"); + + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_USB; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_USB"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_USB; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_USB"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_USB; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_USB"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_USB; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_USB"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_USB; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_USB"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_USB"); + dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB; + strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_USB"); + + if (cpu_is_omap4430() && (cpu_revision_get() == REV_ES1_0)) { + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_CLKMODE_DPLL_UNIPRO; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_CLKMODE_DPLL_UNIPRO"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_IDLEST_DPLL_UNIPRO; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_IDLEST_DPLL_UNIPRO"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_AUTOIDLE_DPLL_UNIPRO"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_CLKSEL_DPLL_UNIPRO; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_CLKSEL_DPLL_UNIPRO"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_DIV_M2_DPLL_UNIPRO; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_DIV_M2_DPLL_UNIPRO"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_SSC_DELTAMSTEP_DPLL_UNIPRO"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_SSC_MODFREQDIV_DPLL_UNIPRO"); + + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_CLKMODE_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_CLKMODE_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_IDLEST_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_IDLEST_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_AUTOIDLE_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_CLKSEL_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_CLKSEL_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_DIV_M2_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_DIV_M2_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_DIV_M4_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_DIV_M4_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_DIV_M5_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_DIV_M5_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_DIV_M6_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_DIV_M6_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_SSC_DELTAMSTEP_DPLL_DDRPHY"); + dpll44xx_prcm_reg_table[i].addr = + OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY; + strcpy(dpll44xx_prcm_reg_table[i++].name, + "CM_SSC_MODFREQDIV_DPLL_DDRPHY"); + } + dpll44xx_prcm_reg_table[i].addr = 0; + strcpy(dpll44xx_prcm_reg_table[i].name, "END"); + + dpll44xx_prcm_reg_table_init_done = 1; + return 0; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx-data.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,150 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll44xx-data.h + * @Description OMAP4 DPLL Definitions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2012 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __DPLL44XX_DATA_H__ +#define __DPLL44XX_DATA_H__ + + +#include +#include +#include +#include + + +typedef struct { + /* Common DPLL type A & B */ + dpll_status status; + dpll_mode mode; + dpll_autoidle_mode autoidle_mode; + int lpmode; + short regm4xen; + int dcc_en; + double dcc_count; /* in us, not relevant if dcc_en != 1 */ + int M; + int N; + double fdpll; + int M2; + double M2_clkout_rate; /* in MHz */ + double X2_M2_clkdcoldo_rate; /* in MHz */ + int M3; + double X2_M3_rate; /* in MHz */ + /* DPLL type A only: HS Dividers (M4 to M7) */ + short hsdiv_present[4]; + int hsdiv[4]; + double hsdiv_rate[4]; /* in MHz */ +} dpll44xx_audit_settings; + + +typedef enum { + DPLL44XX_CLKOUT_M2, + DPLL44XX_CLKOUTX2_M2, + DPLL44XX_CLKOUTX2_M3, + DPLL44XX_CLKOUTX2_M4, + DPLL44XX_CLKOUTX2_M5, + DPLL44XX_CLKOUTX2_M6, + DPLL44XX_CLKOUTX2_M7, + DPLL44XX_CLK_DCO_LDO, + DPLL44XX_OUTPUT_ID_MAX +} dpll44xx_output_id; + + +typedef struct { + unsigned int cm_clksel_dpll; + unsigned int cm_div_m2_dpll; + unsigned int cm_div_m3_dpll; +} omap4_dpll_MN_params_regs; + + +typedef struct { + unsigned int cm_clkmode_dpll; + unsigned int cm_ssc_deltamstep_dpll; +} omap4_dpll_SSC_params_regs; + + +typedef struct { + unsigned int cm_clkmode_dpll; + unsigned int cm_idlest_dpll; + unsigned int cm_autoidle_dpll; + unsigned int cm_clksel_dpll; + unsigned int cm_bypclk_dpll; + unsigned int cm_div_m2_dpll; + unsigned int cm_div_m3_dpll; +} omap4_dpll_params_regs; + + +typedef struct { + clock44xx_id ref_clk; + clock44xx_id byp_clk_m2; + clock44xx_id byp_clk_m3; + clock44xx_id byp_clk_mx; +} omap4_dpll_clock_sources; + + +extern const char dpll44xx_names[DPLL44XX_ID_MAX + 1][DPLL_MAX_NAME_LENGTH]; + +extern const char + dpll44xx_output_names[DPLL44XX_OUTPUT_ID_MAX + 1][DPLL_OUTPUT_MAX_NAME_LENGTH]; + +extern const dpll44xx_audit_settings + **dpll4470_golden_settings_38_4MHz[DPLL44XX_ID_MAX]; +extern const dpll44xx_audit_settings + **dpll4460_golden_settings_38_4MHz[DPLL44XX_ID_MAX]; +extern const dpll44xx_audit_settings + **dpll4430_golden_settings_38_4MHz[DPLL44XX_ID_MAX]; + +extern const omap4_dpll_MN_params_regs omap4_dpll_MN_regs[DPLL44XX_ID_MAX]; + +extern const unsigned int omap4_dpll_hs_divider_regs[DPLL44XX_ID_MAX][4]; + +extern const omap4_dpll_params_regs omap4_dpll_regs[DPLL44XX_ID_MAX]; + +extern const omap4_dpll_clock_sources omap4_dpll_sources[DPLL44XX_ID_MAX]; + +extern reg_table dpll44xx_prcm_reg_table[80]; + + +int dpll44xx_init_regtable(void); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,1822 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll44xx.c + * @Description OMAP4 DPLL PRCM Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* +#define DPLL44XX_DPLL_PARAMS_GET_DEBUG +#define DPLL44XX_PARAMS_GET_DEBUG +#define DPLL44XX_HS_DIVIDER_PARAMS_GET_DEBUG +#define DPLL44XX_MN_PARAMS_GET_DEBUG +#define DPLL44XX_SPEEDS_GET_DEBUG +#define DPLL44XX_CONFIG_SHOW_DEBUG +*/ +#ifdef DPLL44XX_CONFIG_SHOW_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + + +#define DPLL44XX_AUDIT_SHOW_STATUS(curr, golden) \ + if (curr == golden) { \ + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "Pass"); \ + } else { \ + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "FAIL"); \ + (*err_nbr)++; \ + } + +#define DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING(setting, defval, gotolabel) \ + if (setting == defval) {\ + /* Golden setting not available */\ + snprintf(table[row][2], TABLE_MAX_ELT_LEN,\ + "Not available");\ + snprintf(table[row][3], TABLE_MAX_ELT_LEN, "warn.");\ + (*wng_nbr)++;\ + row++;\ + goto gotolabel;\ + } + + +static int dpll44xx_MN_params_get(dpll44xx_id dpll_id, + omap4_dpll_MN_params *dpll_MN_params); +static int dpll44xx_SSC_params_get(dpll44xx_id dpll_id, + omap4_dpll_SSC_params *dpll_SSC_params); +static int dpll44xx_hs_divider_params_get(dpll44xx_id dpll_id, + omap4_dpll_hs_divider_params dpll_hs_divider_params[4]); +static int dpll44xx_speeds_get(omap4_dpll_params *dpll_params, + unsigned short ignore_stop_status); + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_name2addr + * @BRIEF retrieve physical address of a register, given its name. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @param[in] name: register name + * @param[in] addr: register address + * @DESCRIPTION retrieve physical address of a register, given its name. + *//*------------------------------------------------------------------------ */ +int dpll44xx_name2addr(char *name, unsigned int *addr) +{ + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + dpll44xx_init_regtable(); + + return name2addr(name, addr, dpll44xx_prcm_reg_table); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_dump + * @BRIEF dump PLLs PRCM registers + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @DESCRIPTION dump PLLs PRCM registers + *//*------------------------------------------------------------------------ */ +int dpll44xx_dump(void) +{ + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + dpll44xx_init_regtable(); + + return dumpregs(dpll44xx_prcm_reg_table); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_name_get + * @BRIEF return DPLL name. + * @RETURNS DPLL name on success + * "FIXME" string in case of error + * @param[in] id: DPLL ID + * @DESCRIPTION return DPLL name. + *//*------------------------------------------------------------------------ */ +const char *dpll44xx_name_get(dpll44xx_id id) +{ + if (id < DPLL44XX_ID_MAX) + return dpll44xx_names[id]; + else + return dpll44xx_names[DPLL44XX_ID_MAX]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_output_name_get + * @BRIEF return DPLL output name. + * @RETURNS DPLL name on success + * "FIXME" string in case of error + * @param[in] id: DPLL output ID + * @DESCRIPTION return DPLL output name. + *//*------------------------------------------------------------------------ */ +const char *dpll44xx_output_name_get(dpll44xx_output_id id) +{ + if (id < DPLL44XX_OUTPUT_ID_MAX) + return dpll44xx_output_names[id]; + else + return dpll44xx_output_names[DPLL44XX_OUTPUT_ID_MAX]; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_dcc_count2us + * @BRIEF convert DCC COUNT MAX RAW value into micro-seconds + * @RETURNS DCC COUNT value into micro-seconds + * -1 in case of error. + * @param[in] dcc_count: DCC COUNT MAX RAW value + * @DESCRIPTION convert DCC COUNT MAX RAW value into micro-seconds + *//*------------------------------------------------------------------------ */ +double dpll44xx_dcc_count2us(unsigned int dcc_count) +{ + return 32 * dcc_count / clk44xx_get_clock_speed(OMAP4_L4_ICLK1, 0); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_MN_params_get + * @BRIEF get M/N parameters and compute the output speed + * @RETURNS 0 on success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_INTERNAL + * @param[in] dpll_id: DPLL ID + * @param[in,out] dpll_MN_params: pre-allocated structure where to store + * DPLL parameters + * @DESCRIPTION get M/N parameters and compute the output speed + *//*------------------------------------------------------------------------ */ +static int dpll44xx_MN_params_get(dpll44xx_id dpll_id, + omap4_dpll_MN_params *dpll_MN_params) +{ + unsigned int cm_clksel_dpll, cm_div_m2_dpll, cm_div_m3_dpll; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (dpll_id >= DPLL44XX_ID_MAX) + return OMAPCONF_ERR_ARG; + + if (dpll_MN_params == NULL) { + fprintf(stderr, "omapconf internal error: " + "dpll44xx_MN_params_get() called with " + "NULL pointer!\n"); + return OMAPCONF_ERR_ARG; + } + + #ifdef DPLL44XX_MN_PARAMS_GET_DEBUG + printf("dpll44xx_MN_params_get(): dpll_id = %d\n", dpll_id); + #endif + + if (mem_read(omap4_dpll_MN_regs[dpll_id].cm_clksel_dpll, + &cm_clksel_dpll) < 0) + return OMAPCONF_ERR_REG_ACCESS; + dpll_MN_params->M = extract_bitfield(cm_clksel_dpll, 8, 11); + dpll_MN_params->N = extract_bitfield(cm_clksel_dpll, 0, 7); + + + if (omap4_dpll_MN_regs[dpll_id].cm_div_m2_dpll != 0) { + if (mem_read(omap4_dpll_MN_regs[dpll_id].cm_div_m2_dpll, + &cm_div_m2_dpll) < 0) + return OMAPCONF_ERR_REG_ACCESS; + dpll_MN_params->M2 = extract_bitfield(cm_div_m2_dpll, 0, 5); + } else { + dpll_MN_params->M2 = 1; + } + + if (omap4_dpll_MN_regs[dpll_id].cm_div_m3_dpll != 0) { + if (mem_read(omap4_dpll_MN_regs[dpll_id].cm_div_m3_dpll, + &cm_div_m3_dpll) < 0) + return OMAPCONF_ERR_REG_ACCESS; + dpll_MN_params->M3 = extract_bitfield(cm_div_m3_dpll, 0, 5); + } else { + dpll_MN_params->M3 = 1; + } + + #ifdef DPLL44XX_MN_PARAMS_GET_DEBUG + printf("dpll44xx_MN_params_get(): DPLL%d\n", dpll_id); + printf("dpll44xx_MN_params_get(): " + "cm_clksel_dpll addr = 0x%08X, cm_clksel_dpll = 0x%08X\n", + omap4_dpll_MN_regs[dpll_id].cm_clksel_dpll, cm_clksel_dpll); + printf("dpll44xx_MN_params_get(): " + "cm_div_m2_dpll addr = 0x%08X, cm_div_m2_dpll = 0x%08X\n", + omap4_dpll_MN_regs[dpll_id].cm_div_m2_dpll, cm_div_m2_dpll); + printf("dpll44xx_MN_params_get(): " + "cm_div_m3_dpll addr = 0x%08X, cm_div_m3_dpll = 0x%08X\n", + omap4_dpll_MN_regs[dpll_id].cm_div_m3_dpll, cm_div_m3_dpll); + printf("dpll44xx_MN_params_get(): M = %d\n", dpll_MN_params->M); + printf("dpll44xx_MN_params_get(): N = %d\n", dpll_MN_params->N); + printf("dpll44xx_MN_params_get(): M2 = %d\n", dpll_MN_params->M2); + printf("dpll44xx_MN_params_get(): M3 = %d\n", dpll_MN_params->M3); + #endif + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_SSC_params_get + * @BRIEF extract SSC parameters from DPLL registers + * @RETURNS 0 + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * @param[in] dpll_id: ID of the DPLL to get parameters + * @param[in,out] dpll_SSC_params: pre-allocated structure where to store + * parameters + * @DESCRIPTION extract SSC parameters from DPLL registers + * and store it into structure. + *//*------------------------------------------------------------------------ */ +static int dpll44xx_SSC_params_get(dpll44xx_id dpll_id, + omap4_dpll_SSC_params *dpll_SSC_params) +{ + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_ARG_LESS_THAN(dpll_id, DPLL44XX_ID_MAX, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(dpll_SSC_params, OMAPCONF_ERR_ARG); + + /* FIXME: implement function */ + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_hs_divider_params_get + * @BRIEF extract HS divider parameters from DPLL registers + * @RETURNS 0 + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * @param[in] dpll_id: ID of the DPLL to get parameters + * @param[in] dpll_hs_divider_params: pre-allocated structure to store + * parameters + * @DESCRIPTION extract HS divider parameters from DPLL registers + * and store it into structure. + *//*------------------------------------------------------------------------ */ +static int dpll44xx_hs_divider_params_get(dpll44xx_id dpll_id, + omap4_dpll_hs_divider_params dpll_hs_divider_params[4]) +{ + int ret = 0; + unsigned int cm_div_m_dpll = 0; + unsigned short i = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_ARG_LESS_THAN(dpll_id, DPLL44XX_ID_MAX, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(dpll_hs_divider_params, ret); + + #ifdef DPLL44XX_HS_DIVIDER_PARAMS_GET_DEBUG + printf("%s(): dpll_id = %d\n", __func__, dpll_id); + #endif + + for (i = 0; i < 4; i++) { + #ifdef DPLL44XX_HS_DIVIDER_PARAMS_GET_DEBUG + printf("%s(): omap4_dpll_hs_divider_regs[%d][0] = 0x%X\n", + __func__, dpll_id, + omap4_dpll_hs_divider_regs[dpll_id][i]); + #endif + + if (omap4_dpll_hs_divider_regs[dpll_id][i] != 0) { + ret = mem_read(omap4_dpll_hs_divider_regs[dpll_id][i], + &cm_div_m_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + dpll_hs_divider_params[i].present = 1; + dpll_hs_divider_params[i].pwdn = + extract_bit(cm_div_m_dpll, 12); + dpll_hs_divider_params[i].status = + extract_bit(cm_div_m_dpll, 9); + dpll_hs_divider_params[i].autogating = + !extract_bit(cm_div_m_dpll, 8); + dpll_hs_divider_params[i].div = + extract_bitfield(cm_div_m_dpll, 0, 5); + } else { + dpll_hs_divider_params[i].present = 0; + } + + #ifdef DPLL44XX_HS_DIVIDER_PARAMS_GET_DEBUG + if (dpll_hs_divider_params[i].present) { + printf("CM_DIV_M%d_DPLL = 0x%08X\n", + 4 + i, cm_div_m_dpll); + printf("DPLL%d_M%d.pwdn = %d\n", + dpll_id, 4 + i, + dpll_hs_divider_params[i].pwdn); + printf("DPLL%d_M%d.status = %d\n", + dpll_id, 4 + i, + dpll_hs_divider_params[i].status); + printf("DPLL%d_M%d.autogating = %d\n", + dpll_id, 4 + i, + dpll_hs_divider_params[i].autogating); + printf("DPLL%d_M%d.div = %d\n", + dpll_id, 4 + i, dpll_hs_divider_params[i].div); + } else + printf("DPLL%d_M%d not present\n", dpll_id, 4 + i); + #endif + } + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_dpll_params_get + * @BRIEF extract parameters from DPLL registers + * @RETURNS 0 + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_INTERNAL + * @param[in] dpll_id: ID of the DPLL to get parameters + * @param[in,out] dpll_params: pre-allocated structure where to store + * parameters + * @param[in] ignore_stop_status: do not consider DPLL STOP status. + * Useful for functions that needs the DPLL output + * frequencies even when DPLL is stopped + * (e.g. audit, clock tree, OPP detection, etc) + * @DESCRIPTION extract parameters from DPLL registers + * and store it into structure. + *//*------------------------------------------------------------------------ */ +int dpll44xx_dpll_params_get(dpll44xx_id dpll_id, + omap4_dpll_params *dpll_params, unsigned short ignore_stop_status) +{ + int ret = 0; + unsigned int cm_clkmode_dpll = 0; + unsigned int cm_autoidle_dpll = 0; + unsigned int cm_clksel_dpll = 0; + unsigned int cm_div_m2_dpll = 0; + unsigned int cm_div_m3_dpll = 0; + unsigned int cm_idlest_dpll = 0; + unsigned int cm_bypclk_dpll = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_ARG_LESS_THAN(dpll_id, DPLL44XX_ID_MAX, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(dpll_params, OMAPCONF_ERR_ARG); + + dpll_params->id = dpll_id; + #ifdef DPLL44XX_DPLL_PARAMS_GET_DEBUG + printf("%s(): DPLL is %s\n", __func__, + dpll44xx_names[dpll_params->id]); + printf("%s(): omap4_dpll_regs[%s].cm_clkmode_dpll = 0x%X\n", __func__, + dpll44xx_names[dpll_id], + omap4_dpll_regs[dpll_id].cm_clkmode_dpll); + printf("%s(): omap4_dpll_regs[%s].cm_autoidle_dpll = 0x%X\n", __func__, + dpll44xx_names[dpll_id], + omap4_dpll_regs[dpll_id].cm_autoidle_dpll); + printf("%s(): omap4_dpll_regs[%s].cm_clksel_dpll = 0x%X\n", __func__, + dpll44xx_names[dpll_id], + omap4_dpll_regs[dpll_id].cm_clksel_dpll); + printf("%s(): omap4_dpll_regs[%s].cm_bypclk_dpll = 0x%X\n", __func__, + dpll44xx_names[dpll_id], + omap4_dpll_regs[dpll_id].cm_bypclk_dpll); + printf("%s(): omap4_dpll_regs[%s].cm_div_m2_dpll = 0x%X\n", __func__, + dpll44xx_names[dpll_id], + omap4_dpll_regs[dpll_id].cm_div_m2_dpll); + printf("%s(): omap4_dpll_regs[%s].cm_div_m3_dpll = 0x%X\n", __func__, + dpll44xx_names[dpll_id], + omap4_dpll_regs[dpll_id].cm_div_m3_dpll); + printf("%s(): omap4_dpll_regs[%s].cm_idlest_dpll = 0x%X\n", __func__, + dpll44xx_names[dpll_id], + omap4_dpll_regs[dpll_id].cm_idlest_dpll); + #endif + + if (omap4_dpll_regs[dpll_id].cm_clkmode_dpll != 0) { + ret = mem_read(omap4_dpll_regs[dpll_id].cm_clkmode_dpll, + &cm_clkmode_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + } + if (omap4_dpll_regs[dpll_id].cm_autoidle_dpll != 0) { + ret = mem_read(omap4_dpll_regs[dpll_id].cm_autoidle_dpll, + &cm_autoidle_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + } + if (omap4_dpll_regs[dpll_id].cm_clksel_dpll != 0) { + ret = mem_read(omap4_dpll_regs[dpll_id].cm_clksel_dpll, + &cm_clksel_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + } + if (omap4_dpll_regs[dpll_id].cm_bypclk_dpll != 0) { + ret = mem_read(omap4_dpll_regs[dpll_id].cm_bypclk_dpll, + &cm_bypclk_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + } + if (omap4_dpll_regs[dpll_id].cm_div_m2_dpll != 0) { + ret = mem_read(omap4_dpll_regs[dpll_id].cm_div_m2_dpll, + &cm_div_m2_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + dpll_params->M2_present = 1; + } else + dpll_params->M2_present = 0; + + switch (dpll_id) { + case DPLL44XX_MPU: + if (!cpu_is_omap4430()) { + /* + * In case of OMAP4460 and beyond, + * X2_M3 output is used for frequencies > 1GHz. + * But there is no CM_DIV_M3_DPLL_MPU register, + * divider is hard-coded to 1. + * Need to emulate register. + */ + dpll_params->M3_present = 1; + cm_div_m3_dpll = 0x00000201; + } else { + dpll_params->M3_present = 0; + } + break; + default: + if (omap4_dpll_regs[dpll_id].cm_div_m3_dpll != 0) { + ret = mem_read(omap4_dpll_regs[dpll_id].cm_div_m3_dpll, + &cm_div_m3_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + dpll_params->M3_present = 1; + } else { + dpll_params->M3_present = 0; + } + } + + if (omap4_dpll_regs[dpll_id].cm_idlest_dpll != 0) { + ret = mem_read(omap4_dpll_regs[dpll_id].cm_idlest_dpll, + &cm_idlest_dpll); + if (ret < 0) + return OMAPCONF_ERR_REG_ACCESS; + } + + dpll_params->lpmode = extract_bit(cm_clkmode_dpll, 10); + dpll_params->relock_ramp_en = extract_bit(cm_clkmode_dpll, 9); + dpll_params->driftguard_en = extract_bit(cm_clkmode_dpll, 8); + dpll_params->ramp_time = 1 << (extract_bitfield(cm_clkmode_dpll, + 5, 3) + 1); + dpll_params->ramp_level = extract_bitfield(cm_clkmode_dpll, 3, 2); + dpll_params->mode = extract_bitfield(cm_clkmode_dpll, 0, 3); + dpll_params->regm4xen = extract_bit(cm_clkmode_dpll, 11); + dpll_params->autoidle_mode = extract_bitfield(cm_autoidle_dpll, 0, 3); + + switch (cm_idlest_dpll) { + case 0x000: + /* + * DPLL is either in bypass or in stop mode + * Must also read DPLL mode and autoidle mode + * to determine status. + */ + switch (dpll_params->mode) { + case DPLL_LOW_POWER_STOP: + case DPLL_FAST_RELOCK_STOP: + dpll_params->status = DPLL_STATUS_STOPPED; + break; + case DPLL_LOW_POWER_BYPASS: + case DPLL_FAST_RELOCK_BYPASS: + case DPLL_MN_BYPASS: + dpll_params->status = DPLL_STATUS_BYPASSED; + break; + case DPLL_LOCK: + /* need to check autoidle mode */ + switch (dpll_params->autoidle_mode) { + case DPLL_AUTO_LOW_POWER_STOP: + case DPLL_AUTO_FAST_RELOCK_STOP: + dpll_params->status = DPLL_STATUS_STOPPED; + break; + case DPLL_AUTO_BYPASS_LOW_POWER: + case DPLL_AUTO_BYPASS_FAST_RELOCK: + dpll_params->status = DPLL_STATUS_BYPASSED; + break; + case DPLL_DISABLED: + default: + /* can't happen ... */ + return OMAPCONF_ERR_INTERNAL; + } + break; + default: + /* can't happen ... */ + return OMAPCONF_ERR_INTERNAL; + } + break; + case 0x001: + /* DPLL is LOCKED */ + dpll_params->status = DPLL_STATUS_LOCKED; + break; + case 0x100: + /* DPLL is MN BYPASSED */ + dpll_params->status = DPLL_STATUS_BYPASSED; + break; + case 0x101: + /* impossible for DPLL to be LOCKED and MN BYPASSED */ + return OMAPCONF_ERR_INTERNAL; + default: + /* unexpected value */ + return OMAPCONF_ERR_UNEXPECTED; + } + + if (!cpu_is_omap4430() && (dpll_id == DPLL44XX_MPU)) { + dpll_params->dcc_en = extract_bit(cm_clksel_dpll, 22); + dpll_params->dcc_count = + extract_bitfield(cm_clksel_dpll, 24, 8); + } else { + dpll_params->dcc_en = 0; + dpll_params->dcc_count = 0; + } + dpll_params->bypass_clk = extract_bit(cm_clksel_dpll, 23); + dpll_params->clkouthif_src = extract_bit(cm_clksel_dpll, 20); + + if (dpll_params->M2_present) { + dpll_params->M2_clkout_st = extract_bit(cm_div_m2_dpll, 9); + dpll_params->M2_autogating = !extract_bit(cm_div_m2_dpll, 8); + dpll_params->X2_M2_clkout_st = extract_bit(cm_div_m2_dpll, 11); + dpll_params->X2_M2_autogating = + !extract_bit(cm_div_m2_dpll, 10); + } + + if (dpll_params->M3_present) { + dpll_params->X2_M3_clkout_st = extract_bit(cm_div_m3_dpll, 9); + dpll_params->X2_M3_autogating = !extract_bit(cm_div_m3_dpll, 8); + } + + if (omap4_dpll_regs[dpll_id].cm_bypclk_dpll != 0) + dpll_params->bypass_clk_div = 1 << + extract_bitfield(cm_bypclk_dpll, 0, 2); + else + dpll_params->bypass_clk_div = 1; + + #ifdef DPLL44XX_PARAMS_GET_DEBUG + printf("%s(): %s cm_clkmode_dpll = 0x%08X\n", __func__, + dpll44xx_names[dpll_id], cm_clkmode_dpll); + printf("%s(): %s dpll_params->lpmode = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->lpmode); + printf("%s(): %s dpll_params->relock_ramp_en = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->relock_ramp_en); + printf("%s(): %s dpll_params->driftguard_en = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->driftguard_en); + printf("%s(): %s dpll_params->ramp_time = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->ramp_time); + printf("%s(): %s dpll_params->ramp_level = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->ramp_level); + printf("%s(): %s dpll_params->mode = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->mode); + printf("%s(): %s dpll_params->regm4xen = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->regm4xen); + + printf("%s(): %s cm_autoidle_dpll = 0x%08X\n", __func__, + dpll44xx_names[dpll_id], cm_autoidle_dpll); + printf("%s(): %s dpll_params->autoidle_mode = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->autoidle_mode); + + printf("%s(): %s cm_clksel_dpll = 0x%08X\n", __func__, + dpll44xx_names[dpll_id], cm_clksel_dpll); + printf("%s(): %s dpll_params->bypass_clk = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->bypass_clk); + printf("%s(): %s dpll_params->clkouthif_src = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->clkouthif_src); + printf("%s(): %s dpll_params->dcc_en = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->dcc_en); + printf("%s(): %s dpll_params->dcc_count = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->dcc_count); + + if (dpll_params->M2_present) { + printf("%s(): %s cm_div_m2_dpll = 0x%08X\n", __func__, + dpll44xx_names[dpll_id], cm_div_m2_dpll); + printf("%s(): %s dpll_params->M2_clkout_st = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->M2_clkout_st); + printf("%s(): %s dpll_params->M2_autogating = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->M2_autogating); + printf("%s(): %s dpll_params->X2_M2_clkout_st = %d\n", __func__, + dpll44xx_names[dpll_id], + dpll_params->X2_M2_clkout_st); + printf("%s(): %s dpll_params->X2_M2_autogating = %d\n", + __func__, dpll44xx_names[dpll_id], + dpll_params->X2_M2_autogating); + } else { + printf("%s(): %s cm_div_m2_dpll does not exist\n", + __func__, dpll44xx_names[dpll_id]); + } + + if (dpll_params->M3_present) { + printf("%s(): %s cm_div_m3_dpll = 0x%08X\n", __func__, + dpll44xx_names[dpll_id], cm_div_m3_dpll); + printf("%s(): %s dpll_params->X2_M3_clkout_st = %d\n", __func__, + dpll44xx_names[dpll_id], + dpll_params->X2_M3_clkout_st); + printf("%s(): %s dpll_params->X2_M3_autogating = %d\n", + __func__, dpll44xx_names[dpll_id], + dpll_params->X2_M3_autogating); + } else { + printf("%s(): %s cm_div_m3_dpll does not exist\n", + __func__, dpll44xx_names[dpll_id]); + } + + printf("%s(): %s cm_idlest_dpll = 0x%08X\n", __func__, + dpll44xx_names[dpll_id], cm_idlest_dpll); + printf("%s(): %s dpll_params->status = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->status); + + printf("%s(): %s cm_bypclk_dpll = 0x%08X\n", __func__, + dpll44xx_names[dpll_id], cm_bypclk_dpll); + printf("%s(): %s dpll_params->bypass_clk_div = %d\n", __func__, + dpll44xx_names[dpll_id], dpll_params->bypass_clk_div); + #endif + + ret = dpll44xx_MN_params_get(dpll_id, &(dpll_params->MN_params)); + ret = dpll44xx_SSC_params_get(dpll_id, + &(dpll_params->SSC_params)); + ret = dpll44xx_hs_divider_params_get(dpll_id, dpll_params->HS_M); + ret = dpll44xx_speeds_get(dpll_params, ignore_stop_status); + + return ret; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_speeds_get + * @BRIEF compute DPLL output speeds in MHz + * @RETURNS 0 on success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_INTERNAL + * @param[in,out] dpll_params: pre-allocated structure where to store DPLL + * parameters + * @param[in] ignore_stop_status: do not consider DPLL STOP status. + * Useful for functions that needs the DPLL output + * frequencies even when DPLL is stopped + * (e.g. audit, clock tree, OPP detection, etc) + * @DESCRIPTION compute DPLL output speeds in MHz + *//*------------------------------------------------------------------------ */ +static int dpll44xx_speeds_get(omap4_dpll_params *dpll_params, + unsigned short ignore_stop_status) +{ + dpll_status dpll_status; + #ifdef DPLL44XX_SPEEDS_GET_DEBUG + char name[CLOCK44XX_MAX_NAME_LENGTH]; + #endif + + CHECK_NULL_ARG(dpll_params, OMAPCONF_ERR_ARG); + + dpll_params->M2_speed = 0.0; + dpll_params->X2_M2_speed = 0.0; + dpll_params->X2_M3_speed = 0.0; + dpll_params->X2_M4_speed = 0.0; + dpll_params->X2_M5_speed = 0.0; + dpll_params->X2_M6_speed = 0.0; + dpll_params->X2_M7_speed = 0.0; + + /* Retrieve DPLL input clocks speed */ + if (omap4_dpll_sources[dpll_params->id].ref_clk != OMAP4_CLOCK_ID_MAX) + dpll_params->fref = clk44xx_get_clock_speed( + omap4_dpll_sources[dpll_params->id].ref_clk, + ignore_stop_status); + if (omap4_dpll_sources[dpll_params->id].byp_clk_m2 != + OMAP4_CLOCK_ID_MAX) + dpll_params->fbyp_clk_m2 = clk44xx_get_clock_speed( + omap4_dpll_sources[dpll_params->id].byp_clk_m2, + ignore_stop_status); + if (omap4_dpll_sources[dpll_params->id].byp_clk_m3 != + OMAP4_CLOCK_ID_MAX) + dpll_params->fbyp_clk_m3 = clk44xx_get_clock_speed( + omap4_dpll_sources[dpll_params->id].byp_clk_m3, + ignore_stop_status); + if (omap4_dpll_sources[dpll_params->id].byp_clk_mx != + OMAP4_CLOCK_ID_MAX) + dpll_params->fbyp_clk_mx = clk44xx_get_clock_speed( + omap4_dpll_sources[dpll_params->id].byp_clk_mx, + ignore_stop_status); + + #ifdef DPLL44XX_SPEEDS_GET_DEBUG + printf("%s(): %s REF_CLK = %lf (source is %s)\n", __func__, + dpll44xx_names[dpll_params->id], + dpll_params->fref, clk44xx_get_name(omap4_dpll_sources[ + dpll_params->id].ref_clk, name)); + if (omap4_dpll_sources[dpll_params->id].byp_clk_m2 != + OMAP4_CLOCK_ID_MAX) + printf("%s(): %s BP Clk M2 = %lf (source is %s)\n", __func__, + dpll44xx_names[dpll_params->id], + dpll_params->fbyp_clk_m2, + clk44xx_get_name(omap4_dpll_sources[ + dpll_params->id].byp_clk_m2, name)); + if (omap4_dpll_sources[dpll_params->id].byp_clk_m3 != + OMAP4_CLOCK_ID_MAX) + printf("%s(): %s BP Clk M3 = %lf (source is %s)\n", __func__, + dpll44xx_names[dpll_params->id], + dpll_params->fbyp_clk_m3, + clk44xx_get_name(omap4_dpll_sources[ + dpll_params->id].byp_clk_m3, name)); + if (omap4_dpll_sources[dpll_params->id].byp_clk_mx != + OMAP4_CLOCK_ID_MAX) + printf("%s(): %s BP Clk Mx = %lf (source is %s)\n", __func__, + dpll44xx_names[dpll_params->id], + dpll_params->fbyp_clk_mx, + clk44xx_get_name(omap4_dpll_sources[ + dpll_params->id].byp_clk_mx, name)); + #endif + + /* Determine DPLL output frequency */ + if ((dpll_params->status == DPLL_STATUS_STOPPED) && + (ignore_stop_status)) + dpll_status = DPLL_STATUS_LOCKED; + else + dpll_status = dpll_params->status; + + switch (dpll_status) { + case DPLL_STATUS_BYPASSED: + dpll_params->fdpll = 0.0; + + if (dpll_params->M2_present) { + dpll_params->X2_M2_speed = dpll_params->fbyp_clk_m2; + dpll_params->M2_speed = dpll_params->fbyp_clk_m2; + } + + if (dpll_params->M3_present) + dpll_params->X2_M3_speed = dpll_params->fbyp_clk_m3 / + (double) dpll_params->MN_params.M3; + + if (dpll_params->HS_M[0].present) + dpll_params->X2_M4_speed = dpll_params->fbyp_clk_mx; + + if (dpll_params->HS_M[1].present) + dpll_params->X2_M5_speed = dpll_params->fbyp_clk_mx; + + if (dpll_params->HS_M[2].present) + dpll_params->X2_M6_speed = dpll_params->fbyp_clk_mx; + + if (dpll_params->HS_M[3].present) + dpll_params->X2_M7_speed = dpll_params->fbyp_clk_mx; + break; + + case DPLL_STATUS_LOCKED: + if (dpll_params->id <= DPLL44XX_ABE) { + if (dpll_params->regm4xen == 0) + dpll_params->fdpll = (dpll_params->fref * 2.0 * + (dpll_params->MN_params.M)) / + ((dpll_params->MN_params.N) + 1); + else + dpll_params->fdpll = (dpll_params->fref * 8.0 * + (dpll_params->MN_params.M)) / + ((dpll_params->MN_params.N) + 1); + if (dpll_params->M2_present) { + dpll_params->X2_M2_speed = dpll_params->fdpll / + (double) dpll_params->MN_params.M2; + dpll_params->M2_speed = + dpll_params->X2_M2_speed / 2.0; + } + } else { + dpll_params->fdpll = (dpll_params->fref * + (dpll_params->MN_params.M)) / + ((dpll_params->MN_params.N) + 1); + /* clkdcoldo */ + dpll_params->X2_M2_speed = dpll_params->fdpll; + /* clkout */ + dpll_params->M2_speed = dpll_params->fdpll / + (double) dpll_params->MN_params.M2; + } + + + if (dpll_params->M3_present) + dpll_params->X2_M3_speed = dpll_params->fdpll / + (double) dpll_params->MN_params.M3; + + if (dpll_params->HS_M[0].present) + dpll_params->X2_M4_speed = dpll_params->fdpll / + (double) dpll_params->HS_M[0].div; + + if (dpll_params->HS_M[1].present) + dpll_params->X2_M5_speed = dpll_params->fdpll / + (double) dpll_params->HS_M[1].div; + + if (dpll_params->HS_M[2].present) + dpll_params->X2_M6_speed = dpll_params->fdpll / + (double) dpll_params->HS_M[2].div; + + if (dpll_params->HS_M[3].present) + dpll_params->X2_M7_speed = dpll_params->fdpll / + (double) dpll_params->HS_M[3].div; + break; + + case DPLL_STATUS_STOPPED: + dpll_params->fdpll = 0.0; + /* all output speeds already set to 0.0 */ + break; + + default: + return OMAPCONF_ERR_INTERNAL; + } + + + #ifdef DPLL44XX_SPEEDS_GET_DEBUG + printf("%s(): %s Fref = %lf KHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->fref); + printf("%s(): %s Fdpll = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->fdpll); + printf("%s(): %s M2_speed = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->M2_speed); + printf("%s(): %s X2_M2_speed = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->X2_M2_speed); + printf("%s(): %s X2_M3_speed = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->X2_M3_speed); + printf("%s(): %s X2_M4_speed = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->X2_M4_speed); + printf("%s(): %s X2_M5_speed = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->X2_M5_speed); + printf("%s(): %s X2_M6_speed = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->X2_M6_speed); + printf("%s(): %s X2_M7_speed = %lf MHz\n", __func__, + dpll44xx_names[dpll_params->id], dpll_params->X2_M7_speed); + #endif + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_config_show + * @BRIEF analyze PLLs configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * @param[in, out] stream: output file + * @DESCRIPTION analyze PLLs configuration + *//*------------------------------------------------------------------------ */ +int dpll44xx_config_show(FILE *stream) +{ + int ret = 0; + double val, val2; + omap4_dpll_params dpll_params, dpll_params_locked; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row, row_max; + dpll44xx_id dpll_id; + unsigned int hsdiv_count; + + autoadjust_table_init(table); + row = 0; + row_max = 0; + strncpy(table[row][0], "DPLL Configuration", TABLE_MAX_ELT_LEN); + + for (dpll_id = DPLL44XX_MPU; dpll_id <= DPLL44XX_USB; dpll_id++) { + row = 0; + snprintf(table[row++][dpll_id + 1], TABLE_MAX_ELT_LEN, "%s", + dpll44xx_name_get(dpll_id)); + ret = dpll44xx_dpll_params_get(dpll_id, &dpll_params, 0); + if (ret < 0) { + dprintf("%s(): error while getting DPLL %d " + "parameters! (%d)", __func__, dpll_id, ret); + break; + } + + /* + * Also get DPLL params ignoring DPLL STOPPED status to also + * show all output speeds when DPLL is locked. + * No need to check return value as it just already returned ok. + */ + dpll44xx_dpll_params_get(dpll_id, &dpll_params_locked, 1); + + strncpy(table[row][0], "Status", TABLE_MAX_ELT_LEN); + strncpy(table[row][dpll_id + 1], + dpll_status_name_get((dpll_status) dpll_params.status), + TABLE_MAX_ELT_LEN); + row += 2; + + strncpy(table[row][0], "Mode", TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + dpll_mode_name_get((dpll_mode) dpll_params.mode), + TABLE_MAX_ELT_LEN); + + strncpy(table[row][0], "Automatic Control", TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + dpll_autoidle_mode_name_get( + (dpll_autoidle_mode) dpll_params.autoidle_mode), + TABLE_MAX_ELT_LEN); + + strncpy(table[row++][0], " LPST = Low-Power STop", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][0], " FRST = Fast-Relock STop", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][0], " LPBP = Low-Power ByPass", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][0], " FRBP = Fast-Relock ByPass", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][0], " MNBP = MN ByPass", + TABLE_MAX_ELT_LEN); + + strncpy(table[row][0], "Low-Power Mode", TABLE_MAX_ELT_LEN); + strncpy(table[row][dpll_id + 1], + (dpll_params.lpmode == 1) ? "Enabled" : "Disabled", + TABLE_MAX_ELT_LEN); + row += 2; + + strncpy(table[row][0], "Automatic Recalibration", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.driftguard_en == 1) ? + "Enabled" : "Disabled", TABLE_MAX_ELT_LEN); + + strncpy(table[row][0], "Clock Ramping during Relock", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.relock_ramp_en == 1) ? + "Enabled" : "Disabled", TABLE_MAX_ELT_LEN); + + strncpy(table[row][0], "Ramping Rate (x REFCLK(s))", + TABLE_MAX_ELT_LEN); + snprintf(table[row++][dpll_id + 1], TABLE_MAX_ELT_LEN, "%d", + dpll_params.ramp_time); + + strncpy(table[row][0], "Ramping Levels", TABLE_MAX_ELT_LEN); + strncpy(table[row][dpll_id + 1], + dpll_ramp_level_name_get( + (dpll_ramp_level) dpll_params.ramp_level), + TABLE_MAX_ELT_LEN); + row += 2; + + strncpy(table[row][0], "Bypass Clock", TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.bypass_clk == 1) ? "CLKINPULOW" : "CLKINP", + TABLE_MAX_ELT_LEN); + + strncpy(table[row][0], "Bypass Clock Divider", + TABLE_MAX_ELT_LEN); + if (omap4_dpll_regs[dpll_id].cm_bypclk_dpll != 0) + snprintf(table[row][dpll_id + 1], TABLE_MAX_ELT_LEN, + "%d", dpll_params.bypass_clk_div); + row++; + + strncpy(table[row][0], "REGM4XEN Mode", + TABLE_MAX_ELT_LEN); + if (dpll_params.regm4xen == 0) + snprintf(table[row][dpll_id + 1], TABLE_MAX_ELT_LEN, + "Disabled"); + else + snprintf(table[row][dpll_id + 1], TABLE_MAX_ELT_LEN, + "Enabled"); + row++; + + if (!cpu_is_omap4430()) { + strncpy(table[row][0], "Duty Cycle Correction (DCC)", + TABLE_MAX_ELT_LEN); + if (dpll_id == DPLL44XX_MPU) { + if (dpll_params.dcc_en == 1) { + val = dpll44xx_dcc_count2us( + dpll_params.dcc_count); + snprintf(table[row][dpll_id + 1], + TABLE_MAX_ELT_LEN, + "%d (%.1lfus)", + dpll_params.dcc_count, val); + } else { + snprintf(table[row][dpll_id + 1], + TABLE_MAX_ELT_LEN, + "Disabled"); + } + } + row += 2; + } else { + row++; + } + + strncpy(table[row][0], "M Multiplier Factor", + TABLE_MAX_ELT_LEN); + snprintf(table[row++][dpll_id + 1], TABLE_MAX_ELT_LEN, "%d", + dpll_params.MN_params.M); + + strncpy(table[row][0], "N Divider Factor", TABLE_MAX_ELT_LEN); + snprintf(table[row++][dpll_id + 1], TABLE_MAX_ELT_LEN, "%d", + dpll_params.MN_params.N); + + strncpy(table[row][0], "Lock Frequency (MHz)", + TABLE_MAX_ELT_LEN); + if (dpll_params.status == DPLL_STATUS_LOCKED) + snprintf(table[row][dpll_id + 1], TABLE_MAX_ELT_LEN, + "%d", (unsigned int) dpll_params.fdpll); + else + snprintf(table[row][dpll_id + 1], TABLE_MAX_ELT_LEN, + "%d (%d)", + (unsigned int) dpll_params.fdpll, + (unsigned int) dpll_params_locked.fdpll); + row += 2; + + strncpy(table[row][0], "M2 Output", TABLE_MAX_ELT_LEN); + row++; + if ((dpll_params.M2_present) && (dpll_params.dcc_en == 0)) { + strncpy(table[row][0], " Status", TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.M2_clkout_st == 1) ? + "Enabled" : "Gated", + TABLE_MAX_ELT_LEN); + strncpy(table[row][0], " Clock Divider", + TABLE_MAX_ELT_LEN); + snprintf(table[row++][dpll_id + 1], TABLE_MAX_ELT_LEN, + "%-5d (x2)", dpll_params.MN_params.M2); + strncpy(table[row][0], " Clock Speed (MHz)", + TABLE_MAX_ELT_LEN); + if (dpll_params.status == DPLL_STATUS_LOCKED) + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d", + (unsigned int) dpll_params.M2_speed); + else + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d (%d)", + (unsigned int) dpll_params.M2_speed, + (unsigned int) dpll_params_locked.M2_speed); + strncpy(table[row][0], " Autogating", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.M2_autogating == 1) ? + "Enabled" : "Disabled", TABLE_MAX_ELT_LEN); + } else { + row += 4; + } + row++; + + strncpy(table[row++][0], "X2_M2 Output", TABLE_MAX_ELT_LEN); + if ((dpll_id != DPLL44XX_MPU) && (dpll_params.M2_present)) { + strncpy(table[row][0], " Status", TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.X2_M2_clkout_st == 1) ? + "Enabled" : "Gated", + TABLE_MAX_ELT_LEN); + strncpy(table[row][0], " Clock Divider", + TABLE_MAX_ELT_LEN); + snprintf(table[row++][dpll_id + 1], TABLE_MAX_ELT_LEN, + "%-5d", dpll_params.MN_params.M2); + strncpy(table[row][0], " Clock Speed (MHz)", + TABLE_MAX_ELT_LEN); + if (dpll_params.status == DPLL_STATUS_LOCKED) + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d", + (unsigned int) dpll_params.X2_M2_speed); + else + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d (%d)", + (unsigned int) dpll_params.X2_M2_speed, + (unsigned int) + dpll_params_locked.X2_M2_speed); + strncpy(table[row][0], " Autogating", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.X2_M2_autogating == 1) ? + "Enabled" : "Disabled", TABLE_MAX_ELT_LEN); + } else { + row += 4; + } + row++; + + strncpy(table[row++][0], "X2_M3 Output", TABLE_MAX_ELT_LEN); + if (((dpll_id != DPLL44XX_MPU) && (dpll_params.M3_present)) || + ((dpll_id == DPLL44XX_MPU) && (dpll_params.dcc_en == 1))) { + strncpy(table[row][0], " Status", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.X2_M3_clkout_st == 1) ? + "Enabled" : "Gated", + TABLE_MAX_ELT_LEN); + strncpy(table[row][0], " Clock Divider", + TABLE_MAX_ELT_LEN); + snprintf(table[row++][dpll_id + 1], TABLE_MAX_ELT_LEN, + "%-5d", dpll_params.MN_params.M3); + strncpy(table[row][0], " Clock Speed (MHz)", + TABLE_MAX_ELT_LEN); + if (dpll_params.status == DPLL_STATUS_LOCKED) + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d", + (unsigned int) dpll_params.X2_M3_speed); + else + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d (%d)", + (unsigned int) dpll_params.X2_M3_speed, + (unsigned int) dpll_params_locked.X2_M3_speed); + strncpy(table[row][0], " Autogating", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.X2_M3_autogating == 1) ? + "Enabled" : "Disabled", + TABLE_MAX_ELT_LEN); + } else { + row += 4; + } + row++; + + + for (hsdiv_count = 0; hsdiv_count < 4; hsdiv_count++) { + snprintf(table[row++][0], TABLE_MAX_ELT_LEN, + "X2_M%d Output", hsdiv_count + 4); + + if (dpll_params.HS_M[hsdiv_count].present) { + strncpy(table[row][0], " Status", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.HS_M[hsdiv_count].status == 1) ? + "Enabled" : "Gated", TABLE_MAX_ELT_LEN); + strncpy(table[row][0], " Clock Divider", + TABLE_MAX_ELT_LEN); + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, + "%d", + dpll_params.HS_M[hsdiv_count].div); + strncpy(table[row][0], " Clock Speed (MHz)", + TABLE_MAX_ELT_LEN); + switch (hsdiv_count) { + case 0: + val = dpll_params.X2_M4_speed; + val2 = dpll_params_locked.X2_M4_speed; + break; + case 1: + val = dpll_params.X2_M5_speed; + val2 = dpll_params_locked.X2_M5_speed; + break; + case 2: + val = dpll_params.X2_M6_speed; + val2 = dpll_params_locked.X2_M6_speed; + break; + case 3: + val = dpll_params.X2_M7_speed; + val2 = dpll_params_locked.X2_M7_speed; + break; + default: + fprintf(stderr, + "%s(): cannot happen!\n", + __func__); + } + if (dpll_params.status == DPLL_STATUS_LOCKED) + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d", + (unsigned int) val); + else + snprintf(table[row++][dpll_id + 1], + TABLE_MAX_ELT_LEN, "%d (%d)", + (unsigned int) val, + (unsigned int) val2); + strncpy(table[row][0], " Autogating", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.HS_M[hsdiv_count].autogating == 1) + ? "Enabled" : "Disabled", + TABLE_MAX_ELT_LEN); + if (cpu_is_omap4430()) { + strncpy(table[row][0], + " Auto Power Down", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.HS_M[hsdiv_count].pwdn == 1) ? + "Enabled" : "Disabled", + TABLE_MAX_ELT_LEN); + } else { + strncpy(table[row][0], " Power Status", + TABLE_MAX_ELT_LEN); + strncpy(table[row++][dpll_id + 1], + (dpll_params.HS_M[hsdiv_count].pwdn == 1) ? + "Up" : "Down", + TABLE_MAX_ELT_LEN); + } + } else { + row += 5; + } + if (hsdiv_count != 3) + row++; + } + if (row > row_max) + row_max = row; + } + + if (stream != NULL) + autoadjust_table_fprint(stream, table, row_max, 7); + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_ssc_config_show + * @BRIEF analyze PLLs Spread Spectrum Clocking configuration + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * @param[in] none + * @DESCRIPTION analyze PLLs Spread Spectrum Clocking configuration + *//*------------------------------------------------------------------------ */ +int dpll44xx_ssc_config_show(void) +{ + /* FIXME: implement function */ + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_audit + * @BRIEF OMAP4 DPLLS settings audit. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_REG_ACCESS + * OMAPCONF_ERR_INTERNAL + * @param[in] dpll_id: ID of the DPLL to be audited + * @param[in] opp_id: if != DPLL44XX_ID_MAX, force audit at that OPP + * @param[in] stream: output file (NULL: no output (silent)) + * @param[in,out] err_nbr: audit error number + * @param[in,out] wng_nbr: audit warning number + * @DESCRIPTION OMAP4 DPLLS settings audit. + *//*------------------------------------------------------------------------ */ +int dpll44xx_audit(dpll44xx_id dpll_id, opp44xx_id opp_id, + FILE *stream, unsigned int *err_nbr, unsigned int *wng_nbr) +{ + int ret; + char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; + unsigned int row, i; + dpll44xx_id id; + double sysclk, rate; + opp44xx_id opp_mpu, opp_iva, opp_core, opp; + voltdm44xx_id vdd_id; + omap4_dpll_params settings; + dpll44xx_audit_settings *golden_settings; + static const char s_mode[2][12] = { + "Disabled", + "Enabled"}; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + CHECK_ARG_LESS_THAN(dpll_id, DPLL44XX_ID_MAX + 1, OMAPCONF_ERR_ARG); + CHECK_ARG_LESS_THAN(opp_id, OPP44XX_ID_MAX + 1, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG); + CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG); + + dprintf("dpll_id=%s, opp_id=%s\n", dpll44xx_name_get(dpll_id), + opp44xx_name_get(opp_id, OMAP4_VDD_MPU)); + + *err_nbr = 0; + *wng_nbr = 0; + sysclk = clk44xx_get_system_clock_speed(); + if ((int) sysclk != (int) 38.4) { + if (stream != NULL) + fprintf(stream, + "Sorry, %.1lfMHz sysclk is not supported.\n\n", + sysclk); + (*err_nbr)++; + ret = 0; + goto dpll44xx_audit_end; + } + + if (opp_id != OPP44XX_ID_MAX) { + if (stream != NULL) + fprintf(stream, "WARNING: using forced OPP %s!\n\n", + opp44xx_name_get(opp_id, OMAP4_VDD_MPU)); + opp_mpu = opp_id; + opp_iva = opp_id; + opp_core = opp_id; + (*wng_nbr)++; + } else { + ret = voltdm44xx_get_opp(OMAP4_VDD_MPU, &opp_mpu); + ret |= voltdm44xx_get_opp(OMAP4_VDD_IVA, &opp_iva); + ret |= voltdm44xx_get_opp(OMAP4_VDD_CORE, &opp_core); + + if (ret != 0) { + if (stream != NULL) { + fprintf(stream, + "Sorry, OPP could not be detected, " + "audit cannot be completed.\n"); + fprintf(stream, "Option \"-opp " + "[dpll_casc|opp50|opp100|opp_turbo|" + "opp_nitro|opp_nitrosb]\" may be " + "considered until OPP is properly setup" + ".\n\n"); + } + (*err_nbr)++; + ret = 0; + goto dpll44xx_audit_end; + } + } + + for (id = DPLL44XX_MPU; id <= DPLL44XX_USB; id++) { + if ((dpll_id != DPLL44XX_ID_MAX) && (id != dpll_id)) + continue; + + switch (id) { + case DPLL44XX_MPU: + opp = opp_mpu; + vdd_id = OMAP4_VDD_MPU; + break; + case DPLL44XX_IVA: + opp = opp_iva; + vdd_id = OMAP4_VDD_IVA; + break; + default: + opp = opp_core; + vdd_id = OMAP4_VDD_CORE; + } + + autoadjust_table_init(table); + row = 0; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "%s AUDIT (@OPP %s, sysclk=%.1lfMHz)", + dpll44xx_name_get(id), opp44xx_name_get(opp, vdd_id), + sysclk); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "Current Setting"); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "Expected"); + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "STATUS"); + + ret = dpll44xx_dpll_params_get(id, &settings, 1); + if (ret != 0) { + fprintf(stderr, "Sorry, error (%d) occured while " + "getting %s parameters!", ret, + dpll44xx_name_get(id)); + (*err_nbr)++; + ret = OMAPCONF_ERR_INTERNAL; + goto dpll44xx_audit_end; + } + + golden_settings = NULL; + if (cpu_is_omap4430()) { + if ((dpll44xx_audit_settings **) + dpll4430_golden_settings_38_4MHz[id] == NULL) { + if (stream != NULL) + fprintf(stream, + "WARNING: golden settings not " + "available for %s.\n\n", + dpll44xx_name_get(id)); + (*err_nbr)++; + ret = 0; + goto dpll44xx_audit_end; + } + golden_settings = (dpll44xx_audit_settings *) + dpll4430_golden_settings_38_4MHz[id][opp]; + } else if (cpu_is_omap4460()) { + if ((dpll44xx_audit_settings **) + dpll4460_golden_settings_38_4MHz[id] == NULL) { + if (stream != NULL) + fprintf(stream, + "WARNING: golden settings not " + "available for %s.\n\n", + dpll44xx_name_get(id)); + (*err_nbr)++; + ret = 0; + goto dpll44xx_audit_end; + } + golden_settings = (dpll44xx_audit_settings *) + dpll4460_golden_settings_38_4MHz[id][opp]; + } else if (cpu_is_omap4470()) { + if ((dpll44xx_audit_settings **) + dpll4470_golden_settings_38_4MHz[id] == NULL) { + if (stream != NULL) + fprintf(stream, + "WARNING: golden settings not " + "available for %s.\n\n", + dpll44xx_name_get(id)); + (*wng_nbr)++; + continue; + } + golden_settings = (dpll44xx_audit_settings *) + dpll4470_golden_settings_38_4MHz[id][opp]; + } + if (golden_settings == NULL) { + if (stream != NULL) + fprintf(stream, + "WARNING: golden settings not " + "available for this device.\n\n"); + (*err_nbr)++; + ret = 0; + goto dpll44xx_audit_end; + } + + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "Status"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%s", + dpll_status_name_get(settings.status)); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING(golden_settings->status, + DPLL_STATUS_MAX, dpll44xx_audit_mode); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%s", + dpll_status_name_get(golden_settings->status)); + DPLL44XX_AUDIT_SHOW_STATUS(settings.status, + golden_settings->status); + + if (golden_settings->status == DPLL_STATUS_STOPPED) + /* All other DPLL settings are not relevant */ + goto dpll44xx_audit_table_show; + + if (settings.status == DPLL_STATUS_STOPPED) { + snprintf(table[row - 1][3], TABLE_MAX_ELT_LEN, "warn."); + (*err_nbr)--; + if (stream != NULL) { + fprintf(stream, "WARNING: %s is stopped, audit " + "cannot be completed!\n\n", + dpll44xx_name_get(id)); + autoadjust_table_fprint(stream, table, row, 4); + } + (*wng_nbr)++; + continue; + } + +dpll44xx_audit_mode: + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "Mode"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%s", + dpll_mode_name_get(settings.mode)); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING(golden_settings->mode, + DPLL_MODE_MAX, dpll44xx_audit_autoidle_mode); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%s", + dpll_mode_name_get(golden_settings->mode)); + DPLL44XX_AUDIT_SHOW_STATUS(settings.mode, + golden_settings->mode); + +dpll44xx_audit_autoidle_mode: + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "Autoidle Mode"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%s", + dpll_autoidle_mode_name_get(settings.autoidle_mode)); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->autoidle_mode, + DPLL_AUTOIDLE_MODE_MAX, dpll44xx_audit_lpmode); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%s", + dpll_autoidle_mode_name_get( + golden_settings->autoidle_mode)); + DPLL44XX_AUDIT_SHOW_STATUS(settings.autoidle_mode, + golden_settings->autoidle_mode); + +dpll44xx_audit_lpmode: + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "Low-Power Mode"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%s", + s_mode[settings.lpmode]); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->lpmode, -1, dpll44xx_audit_regm4xen); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%s", + s_mode[golden_settings->lpmode]); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.lpmode, + golden_settings->lpmode); + +dpll44xx_audit_regm4xen: + if ((id != DPLL44XX_ABE) && (opp == OMAP4_OPPDPLL_CASC)) + goto dpll44xx_audit_dcc_en; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "REGM4XEN Mode"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%s", + s_mode[settings.regm4xen]); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->regm4xen, -1, dpll44xx_audit_dcc_en); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%s", + s_mode[golden_settings->regm4xen]); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.regm4xen, + golden_settings->regm4xen); + +dpll44xx_audit_dcc_en: + if ((id != DPLL44XX_ABE) && (opp == OMAP4_OPPDPLL_CASC)) + goto dpll44xx_audit_M; + if (cpu_is_omap4430()) + /* No DCC with OMAP4430 */ + goto dpll44xx_audit_M; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "DCC Mode"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%s", + s_mode[settings.dcc_en]); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->dcc_en, -1, dpll44xx_audit_dcc_count); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%s", + s_mode[golden_settings->dcc_en]); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.dcc_en, + golden_settings->dcc_en); + +dpll44xx_audit_dcc_count: + if (golden_settings->dcc_en != 1) + goto dpll44xx_audit_M; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "DCC Count"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%.3lfus", + dpll44xx_dcc_count2us(settings.dcc_count)); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->dcc_count, -1, dpll44xx_audit_M); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.3lfus", + golden_settings->dcc_count); + if (dpll44xx_dcc_count2us(settings.dcc_count) >= + golden_settings->dcc_count) { + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "PASS"); + } else { + snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "FAIL"); + (*err_nbr)++; + } + +dpll44xx_audit_M: + if ((id != DPLL44XX_ABE) && (opp == OMAP4_OPPDPLL_CASC)) + goto dpll44xx_audit_N; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "M Divider"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u", + settings.MN_params.M); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->M, -1, dpll44xx_audit_N); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u", + golden_settings->M); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.MN_params.M, + golden_settings->M); + +dpll44xx_audit_N: + if ((id != DPLL44XX_ABE) && (opp == OMAP4_OPPDPLL_CASC)) + goto dpll44xx_audit_fdpll; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "N Divider"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u", + settings.MN_params.N); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->N, -1, dpll44xx_audit_fdpll); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u", + golden_settings->N); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.MN_params.N, + golden_settings->N); + +dpll44xx_audit_fdpll: + if ((id != DPLL44XX_ABE) && (opp == OMAP4_OPPDPLL_CASC)) + goto dpll44xx_audit_M2; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "Lock Frequency"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%.1lfMHz", + settings.fdpll); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->fdpll, -1, dpll44xx_audit_M2); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.1lfMHz", + golden_settings->fdpll); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.fdpll, + (int) golden_settings->fdpll); + +dpll44xx_audit_M2: + if ((id != DPLL44XX_ABE) && (opp == OMAP4_OPPDPLL_CASC)) + goto dpll44xx_audit_M2_rate; + if (golden_settings->dcc_en == 1) + goto dpll44xx_audit_M3; + if (settings.M2_present == 0) + goto dpll44xx_audit_M3; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "M2 Divider"); + if (id <= DPLL44XX_ABE) + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u (x2)", + settings.MN_params.M2); + else + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u", + settings.MN_params.M2); + + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->M2, -1, dpll44xx_audit_M2_rate); + if (golden_settings->dcc_en == 1) + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u (x2)", + golden_settings->M2); + else + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u", + golden_settings->M2); + + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.MN_params.M2, + golden_settings->M2); + +dpll44xx_audit_M2_rate: + if (id == DPLL44XX_IVA) + goto dpll44xx_audit_switch_A_B; + if (id <= DPLL44XX_ABE) + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "M2 Output Rate"); + else + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "CLKOUT Output Rate"); + + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%.1lfMHz", + settings.M2_speed); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->M2_clkout_rate, -1, + dpll44xx_audit_X2_M2_rate); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.1lfMHz", + golden_settings->M2_clkout_rate); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.M2_speed, + (int) golden_settings->M2_clkout_rate); + +dpll44xx_audit_X2_M2_rate: + if (id <= DPLL44XX_ABE) + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "X2_M2 Output Rate"); + else + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "CLKDCOLDO Output Rate"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%.1lfMHz", + settings.X2_M2_speed); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->X2_M2_clkdcoldo_rate, -1, + dpll44xx_audit_M3); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.1lfMHz", + golden_settings->X2_M2_clkdcoldo_rate); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.X2_M2_speed, + (int) golden_settings->X2_M2_clkdcoldo_rate); + + +dpll44xx_audit_M3: + if ((settings.M3_present == 0) && + (golden_settings->dcc_en != 1)) + goto dpll44xx_audit_switch_A_B; + if ((id == DPLL44XX_MPU) && (golden_settings->dcc_en != 1)) + goto dpll44xx_audit_switch_A_B; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "M3 Divider"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u", + settings.MN_params.M3); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->M3, -1, dpll44xx_audit_X2_M3_rate); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u", + golden_settings->M3); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.MN_params.M3, + golden_settings->M3); + +dpll44xx_audit_X2_M3_rate: + snprintf(table[row][0], TABLE_MAX_ELT_LEN, "X2_M3 Output Rate"); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%.1lfMHz", + settings.X2_M3_speed); + DPLL44XX_AUDIT_CHECK_GOLDEN_SETTING( + golden_settings->X2_M3_rate, -1, + dpll44xx_audit_switch_A_B); + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.1lfMHz", + golden_settings->X2_M3_rate); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.X2_M3_speed, + (int) golden_settings->X2_M3_rate); + +dpll44xx_audit_switch_A_B: + if (id <= DPLL44XX_ABE) + goto dpll44xx_audit_hsdiv; + else + goto dpll44xx_audit_table_show; + + +dpll44xx_audit_hsdiv: + for (i = 0; i < 4; i++) { + if (settings.HS_M[i].present != 1) + continue; + if ((id != DPLL44XX_ABE) && (opp == OMAP4_OPPDPLL_CASC)) + goto dpll44xx_audit_hsdiv_rate; + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "M%u Divider", i + 4); + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%u", + settings.HS_M[i].div); + if (golden_settings->hsdiv[i] == -1) { + /* Golden setting not available */ + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "Not available"); + snprintf(table[row][3], TABLE_MAX_ELT_LEN, + "warn."); + (*wng_nbr)++; + row++; + goto dpll44xx_audit_hsdiv_rate; + } + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%u", + golden_settings->hsdiv[i]); + DPLL44XX_AUDIT_SHOW_STATUS((int) settings.HS_M[i].div, + golden_settings->hsdiv[i]); + +dpll44xx_audit_hsdiv_rate: + snprintf(table[row][0], TABLE_MAX_ELT_LEN, + "X2_M%u Output Rate", i + 4); + switch (i) { + case 0: + rate = settings.X2_M4_speed; + break; + case 1: + rate = settings.X2_M5_speed; + break; + case 2: + rate = settings.X2_M6_speed; + break; + case 3: + rate = settings.X2_M7_speed; + break; + default: + rate = 0; + fprintf(stderr, "%s(): i=%u cannot happen!\n", + __func__, i); + return OMAPCONF_ERR_INTERNAL; + } + snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%.1lfMHz", + rate); + + if (golden_settings->hsdiv_rate[i] == -1) { + /* Golden setting not available */ + snprintf(table[row][2], TABLE_MAX_ELT_LEN, + "Not available"); + snprintf(table[row][3], TABLE_MAX_ELT_LEN, + "warn."); + (*wng_nbr)++; + row++; + continue; + } + snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.1lfMHz", + golden_settings->hsdiv_rate[i]); + DPLL44XX_AUDIT_SHOW_STATUS((int) rate, + (int) golden_settings->hsdiv_rate[i]); + } + +dpll44xx_audit_table_show: + if (stream != NULL) + autoadjust_table_fprint(stream, table, row, 4); + } + ret = 0; + + +dpll44xx_audit_end: + return ret; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_s2id + * @BRIEF convert string to valid DPLL ID. + * @RETURNS DPLL44XX_MPU if s == "mpu" + * DPLL44XX_IVA if s == "iva" + * DPLL44XX_CORE if s == "core" + * DPLL44XX_PER if s == "per" + * DPLL44XX_ABE if s == "abe" + * DPLL44XX_USB if s == "usb" + * DPLL44XX_UNIPRO if s == "unipro1" + * DPLL44XX_DDRPHY if s == "ddrphy" + * DPLL44XX_ID_MAX otherwise + * @param[in] s: string + * @DESCRIPTION convert string to valid DPLL ID. + *//*------------------------------------------------------------------------ */ +dpll44xx_id dpll44xx_s2id(char *s) +{ + CHECK_NULL_ARG(s, DPLL44XX_ID_MAX); + + if (strcmp(s, "mpu") == 0) + return DPLL44XX_MPU; + else if (strcmp(s, "iva") == 0) + return DPLL44XX_IVA; + else if (strcmp(s, "core") == 0) + return DPLL44XX_CORE; + else if (strcmp(s, "per") == 0) + return DPLL44XX_PER; + else if (strcmp(s, "abe") == 0) + return DPLL44XX_ABE; + else if (strcmp(s, "usb") == 0) + return DPLL44XX_USB; + else if (strcmp(s, "unipro") == 0) + return DPLL44XX_UNIPRO; + else if (strcmp(s, "ddrphy") == 0) + return DPLL44XX_DDRPHY; + else + return DPLL44XX_ID_MAX; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION dpll44xx_main + * @BRIEF call function corresponding to shell arguments + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in] argc: shell input argument number + * @param[in] argv: shell input argument(s) + * @DESCRIPTION call function corresponding to shell arguments + *//*------------------------------------------------------------------------ */ +int dpll44xx_main(int argc, char *argv[]) +{ + int ret; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (argc == 2) { + if (strcmp(argv[1], "dump") == 0) { + ret = dpll44xx_dump(); + } else if (strcmp(argv[1], "cfg") == 0) { + ret = dpll44xx_config_show(stdout); + } else { + help(HELP_DPLL); + ret = 0; + } + } else { + help(HELP_DPLL); + ret = 0; + } + + return ret; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/dpll/dpll44xx.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/dpll/dpll44xx.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,150 @@ +/* + * + * @Component OMAPCONF + * @Filename dpll44xx.h + * @Description OMAP4 DPLL PRCM Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __DPLL44XX_H__ +#define __DPLL44XX_H__ + + +#include +#include +#include + + +typedef enum { + DPLL44XX_MPU = 0, + DPLL44XX_IVA = 1, + DPLL44XX_CORE = 2, + DPLL44XX_PER = 3, + DPLL44XX_ABE = 4, + DPLL44XX_USB = 5, + DPLL44XX_UNIPRO = 6, + DPLL44XX_DDRPHY = 7, + DPLL44XX_ID_MAX = 8 +} dpll44xx_id; + + +typedef struct { + char type[12]; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_TYPE */ + unsigned short downspread; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_DOWNSPREAD */ + unsigned short mode; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_EN */ + unsigned short status; /* CM_CLKMODE_DPLL_xxx.DPLL_SSC_ACK */ + unsigned int deltaMStep; /* CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP */ + unsigned int exponent; /* CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDIV_MANTISSA */ + unsigned int mantissa; /* CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDIV_MANTISSA */ + double fm; /* Modulation Frequency = [DPLL_REFCLK/4]/MODFREQDIV */ + /* MODFREQDIV = MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT */ +} omap4_dpll_SSC_params; + +typedef struct { + unsigned short present; /* 0 if DPLL_xyz if does not exist in CM_DIV_Mx_DPLL_xyz, 1 otherwise */ + unsigned short pwdn; /* CM_DIV_Mx_DPLL_xyz.HSDIVIDER_CLKOUTx_PWDN */ + unsigned short status; /* CM_DIV_Mx_DPLL_xyz.ST_HSDIVIDER_CLKOUTx */ + unsigned short autogating; /* CM_DIV_Mx_DPLL_xyz.HSDIVIDER_CLKOUTx_GATE_CTRL */ + unsigned int div; /* CM_DIV_Mx_DPLL_xyz.HSDIVIDER_CLKOUTx_DIV */ +} omap4_dpll_hs_divider_params; + +typedef struct { + unsigned int N; /* CM_CLKSEL_DPLL_xyz.DPLL_MULT */ + unsigned int M; /* CM_CLKSEL_DPLL_xyz.DPLL_DIV */ + unsigned int M2; /* CM_DIV_M2_DPLL_xyz.DPLL_CLKOUT_DIV */ + unsigned int M3; /* CM_DIV_M3_DPLL_xyz.DPLL_CLKOUT_DIV */ +} omap4_dpll_MN_params; + +typedef struct { + dpll44xx_id id; /* DPLL ID */ + unsigned int lpmode; /* CM_CLKMODE_DPLL_xyz.DPLL_LPMODE_EN */ + unsigned int relock_ramp_en; /* CM_CLKMODE_DPLL_xyz.DPLL_RELOCK_RAMP_EN */ + unsigned int driftguard_en; /* CM_CLKMODE_DPLL_xyz.DPLL_DRIFTGUARD_EN */ + unsigned int ramp_time; /* CM_CLKMODE_DPLL_xyz.DPLL_RAMP_RATE */ + unsigned int ramp_level; /* CM_CLKMODE_DPLL_xyz.DPLL_RAMP_LEVEL */ + unsigned short mode; /* CM_CLKMODE_DPLL_xyz.DPLL_EN */ + unsigned short regm4xen; /* CM_CLKMODE_DPLL_xyz.DPLL_REGM4XEN */ + unsigned int dcc_en; /* CM_CLKSEL_DPLL_xyz.DCC_EN */ + unsigned int dcc_count; /* CM_CLKSEL_DPLL_xyz.DCC_COUNT_MAX */ + dpll_status status; /* CM_IDLEST_DPLL_xyz.ST_DPLL_CLK + CM_IDLEST_DPLL_xyz.ST_MN_BYPASS */ + unsigned short autoidle_mode; /* CM_AUTOIDLE_DPLL_xyz.AUTO_DPLL_MODE */ + unsigned short bypass_clk; /* CM_CLKSEL_DPLL_xyz.DPLL_BYP_CLKSEL */ + unsigned short bypass_clk_div; /* CM_BYPCLK_DPLL_xyz.CLKSEL */ + unsigned short clkouthif_src; /* CM_CLKSEL_DPLL_xyz.DPLL_CLKOUTHIF_CLKSEL */ + unsigned short M2_present; /* 0 if DPLL_xyz if does not exist in CM_DIV_Mx_DPLL_xyz, 1 otherwise */ + unsigned short M2_clkout_st; /* CM_DIV_M2_DPLL_xyz.ST_DPLL_CLKOUT */ + unsigned short M2_autogating; /* CM_DIV_M2_DPLL_xyz.DPLL_CLKOUT_GATE_CTRL */ + unsigned short X2_M2_clkout_st; /* CM_DIV_M2_DPLL_xyz.ST_DPLL_CLKOUTX2 */ + unsigned short X2_M2_autogating;/* CM_DIV_M2_DPLL_xyz.DPLL_CLKOUTX2_GATE_CTRL */ + unsigned short M3_present; /* 0 if DPLL_xyz if does not exist in CM_DIV_Mx_DPLL_xyz, 1 otherwise */ + unsigned short X2_M3_clkout_st; /* CM_DIV_M3_DPLL_xyz.ST_DPLL_CLKOUT */ + unsigned short X2_M3_autogating;/* CM_DIV_M3_DPLL_xyz.DPLL_CLKOUT_GATE_CTRL */ + omap4_dpll_SSC_params SSC_params; + omap4_dpll_MN_params MN_params; + omap4_dpll_hs_divider_params HS_M[4]; + + double fref; /* REF_CLK, in KHz */ + double fbyp_clk_m2; /* M2 output bypass clock, in KHz */ + double fbyp_clk_m3; /* M3 output bypass clock, in KHz */ + double fbyp_clk_mx; /* HS dividers output bypass clock, in KHz */ + double fdpll; /* in MHz */ + double M2_speed; /* in MHz */ + double X2_M2_speed; /* in MHz */ + double X2_M3_speed; /* in MHz */ + double X2_M4_speed; /* in MHz */ + double X2_M5_speed; /* in MHz */ + double X2_M6_speed; /* in MHz */ + double X2_M7_speed; /* in MHz */ +} omap4_dpll_params; + + +const char *dpll44xx_name_get(dpll44xx_id id); +int dpll44xx_dpll_params_get(dpll44xx_id dpll_id, + omap4_dpll_params *dpll_params, unsigned short ignore_stop_status); +int dpll44xx_name2addr(char *name, unsigned int *addr); +int dpll44xx_dump(void); +int dpll44xx_main(int argc, char *argv[]); +int dpll44xx_config_show(FILE *stream); +int dpll44xx_audit(dpll44xx_id dpll_id, opp44xx_id opp_id, + FILE *stream, unsigned int *err_nbr, unsigned int *wng_nbr); +dpll44xx_id dpll44xx_s2id(char *s); +double dpll44xx_dcc_count2us(unsigned int dcc_count); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/emif44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/emif44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/emif44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/emif44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,634 @@ +/* + * + * @Component OMAPCONF + * @Filename emif44xx.c + * @Description OMAP4 EMIF PRCM Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include + +/* #define EMIF44XX_DEBUG */ +#ifdef EMIF44XX_DEBUG +#define dprintf(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dprintf(format, ...) +#endif + +#define EMIF_REG_TABLE_SIZE 53 + +reg_table emif1_reg_table[EMIF_REG_TABLE_SIZE]; +reg_table emif2_reg_table[EMIF_REG_TABLE_SIZE]; +static unsigned int init_done = 0; + +static const unsigned int + emifs_perf_cnts[EMIF44XX_MAX][EMIF44XX_PERF_CNT_MAX] = { + {OMAP44XX_EMIF1_PERF_CNT_1, OMAP44XX_EMIF1_PERF_CNT_2}, + {OMAP44XX_EMIF2_PERF_CNT_1, OMAP44XX_EMIF2_PERF_CNT_2} }; + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_init_regtable + * @BRIEF initialize regtable + * @RETURNS 0 + * OMAPCONF_ERR_CPU + * @param[in] none + * @DESCRIPTION initialize regtable + *//*------------------------------------------------------------------------ */ +int emif44xx_init_regtable(void) +{ + int i = 0; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + /* Init EMIF1 registers table */ + strcpy(emif1_reg_table[i].name, "EMIF1_MOD_ID_REV"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_MOD_ID_REV; + strcpy(emif1_reg_table[i].name, "EMIF1_STATUS"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_STATUS; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_CONFIG"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_CONFIG; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_CONFIG_2"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_CONFIG_2; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_REF_CTRL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_REF_CTRL; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_REF_CTRL_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_REF_CTRL_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_TIM_1"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_TIM_1; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_TIM_1_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_TIM_1_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_TIM_2"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_TIM_2; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_TIM_2_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_TIM_2_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_TIM_3"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_TIM_3; + strcpy(emif1_reg_table[i].name, "EMIF1_SDRAM_TIM_3_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_SDRAM_TIM_3_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_LPDDR2_NVM_TIM"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_LPDDR2_NVM_TIM; + strcpy(emif1_reg_table[i].name, "EMIF1_LPDDR2_NVM_TIM_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_LPDDR2_NVM_TIM_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_PWR_MGMT_CTRL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_PWR_MGMT_CTRL; + strcpy(emif1_reg_table[i].name, "EMIF1_PWR_MGMT_CTRL_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_PWR_MGMT_CTRL_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_LPDDR2_MODE_REG_DATA"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_LPDDR2_MODE_REG_DATA; + strcpy(emif1_reg_table[i].name, "EMIF1_LPDDR2_MODE_REG_CFG"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_LPDDR2_MODE_REG_CFG; + strcpy(emif1_reg_table[i].name, "EMIF1_OCP_CONFIG"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_OCP_CONFIG; + strcpy(emif1_reg_table[i].name, "EMIF1_OCP_CFG_VAL_1"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_OCP_CFG_VAL_1; + strcpy(emif1_reg_table[i].name, "EMIF1_OCP_CFG_VAL_2"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_OCP_CFG_VAL_2; + strcpy(emif1_reg_table[i].name, "EMIF1_IODFT_TLGC"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IODFT_TLGC; + strcpy(emif1_reg_table[i].name, "EMIF1_IODFT_CTRL_MISR_RSLT"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IODFT_CTRL_MISR_RSLT; + strcpy(emif1_reg_table[i].name, "EMIF1_IODFT_ADDR_MISR_RSLT"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IODFT_ADDR_MISR_RSLT; + strcpy(emif1_reg_table[i].name, "EMIF1_IODFT_DATA_MISR_RSLT_1"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IODFT_DATA_MISR_RSLT_1; + strcpy(emif1_reg_table[i].name, "EMIF1_IODFT_DATA_MISR_RSLT_2"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IODFT_DATA_MISR_RSLT_2; + strcpy(emif1_reg_table[i].name, "EMIF1_IODFT_DATA_MISR_RSLT_3"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IODFT_DATA_MISR_RSLT_3; + strcpy(emif1_reg_table[i].name, "EMIF1_PERF_CNT_1"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_PERF_CNT_1; + strcpy(emif1_reg_table[i].name, "EMIF1_PERF_CNT_2"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_PERF_CNT_2; + strcpy(emif1_reg_table[i].name, "EMIF1_PERF_CNT_CFG"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_PERF_CNT_CFG; + strcpy(emif1_reg_table[i].name, "EMIF1_PERF_CNT_SEL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_PERF_CNT_SEL; + strcpy(emif1_reg_table[i].name, "EMIF1_PERF_CNT_TIM"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_PERF_CNT_TIM; + strcpy(emif1_reg_table[i].name, "EMIF1_READ_IDLE_CTRL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_READ_IDLE_CTRL; + strcpy(emif1_reg_table[i].name, "EMIF1_READ_IDLE_CTRL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_READ_IDLE_CTRL; + strcpy(emif1_reg_table[i].name, "EMIF1_READ_IDLE_CTRL_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_READ_IDLE_CTRL_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQ_EOI"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQ_EOI; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQSTATUS_RAW_SYS"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQSTATUS_RAW_SYS; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQSTATUS_RAW_LL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQSTATUS_RAW_LL; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQSTATUS_SYS"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQSTATUS_SYS; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQSTATUS_LL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQSTATUS_LL; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQENABLE_SET_SYS"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQENABLE_SET_SYS; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQENABLE_SET_LL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQENABLE_SET_LL; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQENABLE_SET_LL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQENABLE_SET_LL; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQENABLE_CLR_SYS"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQENABLE_CLR_SYS; + strcpy(emif1_reg_table[i].name, "EMIF1_IRQENABLE_CLR_LL"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_IRQENABLE_CLR_LL; + strcpy(emif1_reg_table[i].name, "EMIF1_ZQ_CONFIG"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_ZQ_CONFIG; + strcpy(emif1_reg_table[i].name, "EMIF1_TEMP_ALERT_CONFIG"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_TEMP_ALERT_CONFIG; + strcpy(emif1_reg_table[i].name, "EMIF1_OCP_ERR_LOG"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_OCP_ERR_LOG; + strcpy(emif1_reg_table[i].name, "EMIF1_DDR_PHY_CTRL_1"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_DDR_PHY_CTRL_1; + strcpy(emif1_reg_table[i].name, "EMIF1_DDR_PHY_CTRL_1_SHDW"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_DDR_PHY_CTRL_1_SHDW; + strcpy(emif1_reg_table[i].name, "EMIF1_DDR_PHY_CTRL_2"); + emif1_reg_table[i++].addr = OMAP44XX_EMIF1_DDR_PHY_CTRL_2; + strcpy(emif1_reg_table[i].name, "END"); + emif1_reg_table[i].addr = 0; + dprintf("emif1_reg_table last index=%d, size=%d\n", i, i + 1); + + /* Init EMIF2 registers table */ + i = 0; + strcpy(emif2_reg_table[i].name, "EMIF2_MOD_ID_REV"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_MOD_ID_REV; + strcpy(emif2_reg_table[i].name, "EMIF2_STATUS"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_STATUS; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_CONFIG"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_CONFIG; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_CONFIG_2"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_CONFIG_2; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_REF_CTRL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_REF_CTRL; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_REF_CTRL_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_REF_CTRL_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_TIM_1"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_TIM_1; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_TIM_1_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_TIM_1_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_TIM_2"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_TIM_2; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_TIM_2_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_TIM_2_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_TIM_3"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_TIM_3; + strcpy(emif2_reg_table[i].name, "EMIF2_SDRAM_TIM_3_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_SDRAM_TIM_3_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_LPDDR2_NVM_TIM"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_LPDDR2_NVM_TIM; + strcpy(emif2_reg_table[i].name, "EMIF2_LPDDR2_NVM_TIM_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_LPDDR2_NVM_TIM_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_PWR_MGMT_CTRL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_PWR_MGMT_CTRL; + strcpy(emif2_reg_table[i].name, "EMIF2_PWR_MGMT_CTRL_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_PWR_MGMT_CTRL_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_LPDDR2_MODE_REG_DATA"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_LPDDR2_MODE_REG_DATA; + strcpy(emif2_reg_table[i].name, "EMIF2_LPDDR2_MODE_REG_CFG"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_LPDDR2_MODE_REG_CFG; + strcpy(emif2_reg_table[i].name, "EMIF2_OCP_CONFIG"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_OCP_CONFIG; + strcpy(emif2_reg_table[i].name, "EMIF2_OCP_CFG_VAL_1"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_OCP_CFG_VAL_1; + strcpy(emif2_reg_table[i].name, "EMIF2_OCP_CFG_VAL_2"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_OCP_CFG_VAL_2; + strcpy(emif2_reg_table[i].name, "EMIF2_IODFT_TLGC"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IODFT_TLGC; + strcpy(emif2_reg_table[i].name, "EMIF2_IODFT_CTRL_MISR_RSLT"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IODFT_CTRL_MISR_RSLT; + strcpy(emif2_reg_table[i].name, "EMIF2_IODFT_ADDR_MISR_RSLT"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IODFT_ADDR_MISR_RSLT; + strcpy(emif2_reg_table[i].name, "EMIF2_IODFT_DATA_MISR_RSLT_1"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IODFT_DATA_MISR_RSLT_1; + strcpy(emif2_reg_table[i].name, "EMIF2_IODFT_DATA_MISR_RSLT_2"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IODFT_DATA_MISR_RSLT_2; + strcpy(emif2_reg_table[i].name, "EMIF2_IODFT_DATA_MISR_RSLT_3"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IODFT_DATA_MISR_RSLT_3; + strcpy(emif2_reg_table[i].name, "EMIF2_PERF_CNT_1"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_PERF_CNT_1; + strcpy(emif2_reg_table[i].name, "EMIF2_PERF_CNT_2"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_PERF_CNT_2; + strcpy(emif2_reg_table[i].name, "EMIF2_PERF_CNT_CFG"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_PERF_CNT_CFG; + strcpy(emif2_reg_table[i].name, "EMIF2_PERF_CNT_SEL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_PERF_CNT_SEL; + strcpy(emif2_reg_table[i].name, "EMIF2_PERF_CNT_TIM"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_PERF_CNT_TIM; + strcpy(emif2_reg_table[i].name, "EMIF2_READ_IDLE_CTRL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_READ_IDLE_CTRL; + strcpy(emif2_reg_table[i].name, "EMIF2_READ_IDLE_CTRL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_READ_IDLE_CTRL; + strcpy(emif2_reg_table[i].name, "EMIF2_READ_IDLE_CTRL_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_READ_IDLE_CTRL_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQ_EOI"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQ_EOI; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQSTATUS_RAW_SYS"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQSTATUS_RAW_SYS; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQSTATUS_RAW_LL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQSTATUS_RAW_LL; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQSTATUS_SYS"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQSTATUS_SYS; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQSTATUS_LL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQSTATUS_LL; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQENABLE_SET_SYS"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQENABLE_SET_SYS; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQENABLE_SET_LL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQENABLE_SET_LL; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQENABLE_SET_LL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQENABLE_SET_LL; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQENABLE_CLR_SYS"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQENABLE_CLR_SYS; + strcpy(emif2_reg_table[i].name, "EMIF2_IRQENABLE_CLR_LL"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_IRQENABLE_CLR_LL; + strcpy(emif2_reg_table[i].name, "EMIF2_ZQ_CONFIG"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_ZQ_CONFIG; + strcpy(emif2_reg_table[i].name, "EMIF2_TEMP_ALERT_CONFIG"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_TEMP_ALERT_CONFIG; + strcpy(emif2_reg_table[i].name, "EMIF2_OCP_ERR_LOG"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_OCP_ERR_LOG; + strcpy(emif2_reg_table[i].name, "EMIF2_DDR_PHY_CTRL_1"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_DDR_PHY_CTRL_1; + strcpy(emif2_reg_table[i].name, "EMIF2_DDR_PHY_CTRL_1_SHDW"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_DDR_PHY_CTRL_1_SHDW; + strcpy(emif2_reg_table[i].name, "EMIF2_DDR_PHY_CTRL_2"); + emif2_reg_table[i++].addr = OMAP44XX_EMIF2_DDR_PHY_CTRL_2; + strcpy(emif2_reg_table[i].name, "END"); + emif2_reg_table[i].addr = 0; + + init_done = 1; + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_name2addr + * @BRIEF retrieve physical address of a register, given its name. + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @param[in] name: register name + * @param[in,out] addr: register address + * @DESCRIPTION retrieve physical address of a register, given its name. + *//*------------------------------------------------------------------------ */ +int emif44xx_name2addr(char *name, unsigned int *addr) +{ + int ret; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (!init_done) + emif44xx_init_regtable(); + + ret = name2addr(name, addr, emif1_reg_table); + if (ret == 0) + return ret; + else + return name2addr(name, addr, emif2_reg_table); +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_perf_cnt_configure + * @BRIEF configure emif performance counter + * @RETURNS 0 in case of success + * @param[in] emif_id: EMIF instance + * @param[in] cnt_id: performance counter ID + * @param[in] filter: filter value + * @param[in] conn_id: Also filter on connection (master) ID. + * -1 is disabled. + * @param[in] addr_sel: Address space (chip select) filtering. + * Refer to ENUM + * @DESCRIPTION configure emif performance counter + *//*------------------------------------------------------------------------ */ +int emif44xx_perf_cnt_configure(emif44xx_ids emif_id, + emif44xx_perf_cnt_ids cnt_id, emif44xx_perf_cnt_filter_ids filter, + int conn_id, emif44xx_memaddrspace addr_sel) +{ + unsigned int addr, data, shift; + unsigned int enable_conn_id_filtering, enable_addr_filtering; + unsigned int unsigned_conn_id; + emif44xx_memaddrspace unsigned_addr_id; + int ret; + + switch (emif_id) { + case EMIF44XX_0: + addr = OMAP44XX_EMIF1_PERF_CNT_CFG; + switch (cnt_id) { + case EMIF44XX_PERF_CNT_0: + shift = 0; + break; + case EMIF44XX_PERF_CNT_1: + shift = 16; + break; + default: + fprintf(stderr, "%s(): bad CNT instance! (%u)!\n", + __func__, cnt_id); + return OMAPCONF_ERR_ARG; + } + break; + case EMIF44XX_1: + addr = OMAP44XX_EMIF2_PERF_CNT_CFG; + switch (cnt_id) { + case EMIF44XX_PERF_CNT_0: + shift = 0; + break; + case EMIF44XX_PERF_CNT_1: + shift = 16; + break; + default: + fprintf(stderr, "%s(): bad CNT instance! (%u)!\n", + __func__, cnt_id); + return OMAPCONF_ERR_ARG; + } + break; + default: + fprintf(stderr, "%s(): bad EMIF instance! (%u)!\n", + __func__, emif_id); + return OMAPCONF_ERR_ARG; + } + + ret = mem_read(addr, &data); + if (ret != 0) { + fprintf(stderr, "%s(): error reading EMIF_PERF_CNT_CFG reg!\n", + __func__); + return OMAPCONF_ERR_REG_ACCESS; + } + dprintf("%s(%d, %d, %d, %d, %d):\n", __func__, + emif_id, cnt_id, filter, conn_id, addr_sel); + + enable_conn_id_filtering = 0; + unsigned_conn_id = 0x0; + if (conn_id >= 0 && conn_id <= 255) { + unsigned_conn_id = conn_id << 8; + enable_conn_id_filtering = 1; + } + dprintf(" Conn ID Filtering? = 0x%x, 0x%X\n", + enable_conn_id_filtering, unsigned_conn_id); + + enable_addr_filtering = 0; + unsigned_addr_id = EMIF44XX_MEMADDRSPACE_CS1ANDCS0; + if (addr_sel < EMIF44XX_MEMADDRSPACE_DISABLED) { + unsigned_addr_id = addr_sel << 0; + enable_addr_filtering = 1; + } + dprintf(" Addr Filtering? = 0x%x, 0x%X\n", + enable_addr_filtering, unsigned_addr_id); + + enable_conn_id_filtering = (enable_conn_id_filtering << 15) << shift; + enable_addr_filtering = (enable_addr_filtering << 14) << shift; + filter = filter << shift; + dprintf(" filter = 0x%08X\n", filter); + dprintf(" EMIF_PERF_CNT_CFG = 0x%08X\n", data); + + data = data & ~(0xFFFF << shift); + dprintf(" EMIF_PERF_CNT_CFG cleared = 0x%08X\n", data); + data = data | filter | enable_conn_id_filtering | enable_addr_filtering; + dprintf(" EMIF_PERF_CNT_CFG | filter = 0x%08X\n", data); + + ret = mem_write(addr, data); + if (ret != 0) { + fprintf(stderr, "%s(): error writing EMIF_PERF_CNT_CFG reg!\n", + __func__); + return OMAPCONF_ERR_REG_ACCESS; + } + + /* + * Increment addr from OMAP44XX_EMIFn_PERF_CNT_CFG to + * OMAP44XX_EMIFn_PERF_CNT_SEL register + */ + addr = addr + 0x4; + ret = mem_read(addr, &data); + if (ret != 0) { + fprintf(stderr, "%s(): error reading EMIF_PERF_CNT_SEL reg!\n", + __func__); + return OMAPCONF_ERR_REG_ACCESS; + } + filter = (unsigned_conn_id | unsigned_addr_id) << shift; + + dprintf(" EMIF_PERF_CNT_SEL = 0x%08X\n", data); + data = data & ~(0xFFFF << shift); + dprintf(" EMIF_PERF_CNT_SEL cleared = 0x%08X\n", data); + data = data | filter ; + dprintf(" EMIF_PERF_CNT_SEL | filter = 0x%08X\n", data); + ret = mem_write(addr, data); + if (ret != 0) { + fprintf(stderr, "%s(): error writing EMIF_PERF_CNT_SEL reg!\n", + __func__); + return OMAPCONF_ERR_REG_ACCESS; + } + + + return 0; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_perf_cnt_get_time + * @BRIEF return L3 clock cycles elapsed since EMIF is brought + * out of reset + * @RETURNS L3 clock cycles elapsed since EMIF was reset + * 0 in case of error + * @param[in] emif_id: EMIF instance + * @DESCRIPTION return L3 clock cycles elapsed since EMIF is brought + * out of reset + *//*------------------------------------------------------------------------ */ +unsigned int emif44xx_perf_cnt_get_time(emif44xx_ids emif_id) +{ + int ret; + unsigned int addr; + unsigned int time; + + switch (emif_id) { + case EMIF44XX_0: + addr = OMAP44XX_EMIF1_PERF_CNT_TIM; + break; + case EMIF44XX_1: + addr = OMAP44XX_EMIF2_PERF_CNT_TIM; + break; + default: + fprintf(stderr, "%s(): bad EMIF instance! (%u)!\n", + __func__, emif_id); + return 0; + } + + ret = mem_read(addr, &time); + if (ret != 0) { + fprintf(stderr, "%s(): error reading PERF_CNT_TIM register!\n", + __func__); + return 0; + } + + return time; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_perf_cnt_get_count + * @BRIEF retrieve performance counter value as configured (filtered) + * @RETURNS performance counter value as configured + * 0 in case of error + * @param[in] emif_id: EMIF instance + * @param[in] cnt_id: performance counter ID + * @DESCRIPTION retrieve performance counter value as configured (filtered) + *//*------------------------------------------------------------------------ */ +unsigned int emif44xx_perf_cnt_get_count(emif44xx_ids emif_id, + emif44xx_perf_cnt_ids cnt_id) +{ + int ret; + unsigned int count; + + #ifdef EMIF44XX_DEBUG + if ((emif_id >= EMIF44XX_MAX) || (cnt_id >= EMIF44XX_PERF_CNT_MAX)) { + fprintf(stderr, "%s(): (emif_id (%u) >= EMIF44XX_MAX (%u)) || " + "(cnt_id (%u) >= EMIF44XX_PERF_CNT_MAX (%u))\n", + __func__, emif_id, EMIF44XX_MAX, + cnt_id, EMIF44XX_PERF_CNT_MAX); + return 0; + } + #endif + + ret = mem_read(emifs_perf_cnts[emif_id][cnt_id], &count); + if (ret != 0) { + fprintf(stderr, "%s(): error reading EMIF_PERF_CNT register!\n", + __func__); + return 0; + } + + dprintf("%s(%u, %u) = %u\n", __func__, emif_id, cnt_id, count); + return count; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_cs_count_get + * @BRIEF return the number of Chip Select (CS) used + * @RETURNS number of Chip Select (CS) used (1 or 2) + * @DESCRIPTION return the number of Chip Select (CS) used by analyzing + * EMIF[1-2]_SDRAM_CONFIG configuration. + *//*------------------------------------------------------------------------ */ +unsigned char emif44xx_cs_count_get(void) +{ + unsigned int emif1_config, emif2_config; + + CHECK_CPU(44xx, 1); + + /* Read EMIF SDRAM CONFIG register */ + if ((mem_read(OMAP44XX_EMIF1_SDRAM_CONFIG, &emif1_config) != 0) || + (mem_read(OMAP44XX_EMIF2_SDRAM_CONFIG, &emif2_config) != 0)) { + fprintf(stderr, "%s(): could not read EMIF[0-1]_SDRAM_CONFIG!", + __func__); + return 1; + } + + if ((emif1_config & 0x8) != (emif2_config & 0x8)) { + fprintf(stderr, "%s(): number of chip-selects used by " + "EMIF1 and EMIF2 do not match!", __func__); + return 1; + } + + if (emif1_config & 0x8) + return 2; + else + return 1; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_dump + * @BRIEF dump EMIF[1-2] registers + * @RETURNS 0 in case of success + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_REG_ACCESS + * @DESCRIPTION dump EMIF[1-2] registers + *//*------------------------------------------------------------------------ */ +int emif44xx_dump(void) +{ + int ret; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (!init_done) + emif44xx_init_regtable(); + + ret = dumpregs(emif1_reg_table); + ret |= dumpregs(emif2_reg_table); + return ret; +} + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION emif44xx_main + * @BRIEF EMIF main menu + * @RETURNS 0 in case of success + * OMAPCONF_ERR_ARG + * OMAPCONF_ERR_CPU + * OMAPCONF_ERR_INTERNAL + * @param[in] argc: shell input argument number + * @param[in] argv: shell input argument(s) + * @DESCRIPTION + *//*------------------------------------------------------------------------ */ +int emif44xx_main(int argc, char *argv[]) +{ + int ret; + + CHECK_CPU(44xx, OMAPCONF_ERR_CPU); + + if (argc == 2) { + if (strcmp(argv[1], "dump") == 0) { + if (!init_done) + emif44xx_init_regtable(); + ret = dumpregs(emif1_reg_table); + ret = dumpregs(emif2_reg_table); + } else { + help(HELP_EMIF); + ret = OMAPCONF_ERR_ARG; + } + } else { + help(HELP_EMIF); + ret = OMAPCONF_ERR_ARG; + } + + return ret; +} diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/emif44xx.h tiomapconf-1.61.1/arch/arm/mach-omap/omap4/emif44xx.h --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/emif44xx.h 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/emif44xx.h 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,304 @@ +/* + * + * @Component OMAPCONF + * @Filename emif44xx.h + * @Description OMAP4 EMIF PRCM Definitions & Functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __EMIF44XX_H__ +#define __EMIF44XX_H__ + +#include + + +/* Base address */ +#define OMAP44XX_EMIF1_BASE 0x4c000000 +#define OMAP44XX_EMIF2_BASE 0x4d000000 + +/* Registers offset */ +#define OMAP44XX_EMIF_MOD_ID_REV 0x0000 +#define OMAP44XX_EMIF_STATUS 0x0004 +#define OMAP44XX_EMIF_SDRAM_CONFIG 0x0008 +#define OMAP44XX_EMIF_SDRAM_CONFIG_2 0x000c +#define OMAP44XX_EMIF_SDRAM_REF_CTRL 0x0010 +#define OMAP44XX_EMIF_SDRAM_REF_CTRL_SHDW 0x0014 +#define OMAP44XX_EMIF_SDRAM_TIM_1 0x0018 +#define OMAP44XX_EMIF_SDRAM_TIM_1_SHDW 0x001c +#define OMAP44XX_EMIF_SDRAM_TIM_2 0x0020 +#define OMAP44XX_EMIF_SDRAM_TIM_2_SHDW 0x0024 +#define OMAP44XX_EMIF_SDRAM_TIM_3 0x0028 +#define OMAP44XX_EMIF_SDRAM_TIM_3_SHDW 0x002c +#define OMAP44XX_EMIF_LPDDR2_NVM_TIM 0x0030 +#define OMAP44XX_EMIF_LPDDR2_NVM_TIM_SHDW 0x0034 +#define OMAP44XX_EMIF_PWR_MGMT_CTRL 0x0038 +#define OMAP44XX_EMIF_PWR_MGMT_CTRL_SHDW 0x003c +#define OMAP44XX_EMIF_LPDDR2_MODE_REG_DATA 0x0040 +#define OMAP44XX_EMIF_LPDDR2_MODE_REG_CFG 0x0050 +#define OMAP44XX_EMIF_OCP_CONFIG 0x0054 +#define OMAP44XX_EMIF_OCP_CFG_VAL_1 0x0058 +#define OMAP44XX_EMIF_OCP_CFG_VAL_2 0x005c +#define OMAP44XX_EMIF_IODFT_TLGC 0x0060 +#define OMAP44XX_EMIF_IODFT_CTRL_MISR_RSLT 0x0064 +#define OMAP44XX_EMIF_IODFT_ADDR_MISR_RSLT 0x0068 +#define OMAP44XX_EMIF_IODFT_DATA_MISR_RSLT_1 0x006c +#define OMAP44XX_EMIF_IODFT_DATA_MISR_RSLT_2 0x0070 +#define OMAP44XX_EMIF_IODFT_DATA_MISR_RSLT_3 0x0074 +#define OMAP44XX_EMIF_PERF_CNT_1 0x0080 +#define OMAP44XX_EMIF_PERF_CNT_2 0x0084 +#define OMAP44XX_EMIF_PERF_CNT_CFG 0x0088 +#define OMAP44XX_EMIF_PERF_CNT_SEL 0x008c +#define OMAP44XX_EMIF_PERF_CNT_TIM 0x0090 +#define OMAP44XX_EMIF_READ_IDLE_CTRL 0x0098 +#define OMAP44XX_EMIF_READ_IDLE_CTRL_SHDW 0x009c +#define OMAP44XX_EMIF_IRQ_EOI 0x00a0 +#define OMAP44XX_EMIF_IRQSTATUS_RAW_SYS 0x00a4 +#define OMAP44XX_EMIF_IRQSTATUS_RAW_LL 0x00a8 +#define OMAP44XX_EMIF_IRQSTATUS_SYS 0x00ac +#define OMAP44XX_EMIF_IRQSTATUS_LL 0x00b0 +#define OMAP44XX_EMIF_IRQENABLE_SET_SYS 0x00b4 +#define OMAP44XX_EMIF_IRQENABLE_SET_LL 0x00b8 +#define OMAP44XX_EMIF_IRQENABLE_CLR_SYS 0x00bc +#define OMAP44XX_EMIF_IRQENABLE_CLR_LL 0x00c0 +#define OMAP44XX_EMIF_ZQ_CONFIG 0x00c8 +#define OMAP44XX_EMIF_TEMP_ALERT_CONFIG 0x00cc +#define OMAP44XX_EMIF_OCP_ERR_LOG 0x00d0 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1 0x00e4 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_2 0x00ec + +#define OMAP44XX_EMIF_REGADDR(module, reg) ((module) + (reg)) + +/* EMIF1 Registers */ +#define OMAP44XX_EMIF1_MOD_ID_REV OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0000) +#define OMAP44XX_EMIF1_STATUS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0004) +#define OMAP44XX_EMIF1_SDRAM_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0008) +#define OMAP44XX_EMIF1_SDRAM_CONFIG_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x000c) +#define OMAP44XX_EMIF1_SDRAM_REF_CTRL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0010) +#define OMAP44XX_EMIF1_SDRAM_REF_CTRL_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0014) +#define OMAP44XX_EMIF1_SDRAM_TIM_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0018) +#define OMAP44XX_EMIF1_SDRAM_TIM_1_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x001c) +#define OMAP44XX_EMIF1_SDRAM_TIM_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0020) +#define OMAP44XX_EMIF1_SDRAM_TIM_2_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0024) +#define OMAP44XX_EMIF1_SDRAM_TIM_3 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0028) +#define OMAP44XX_EMIF1_SDRAM_TIM_3_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x002c) +#define OMAP44XX_EMIF1_LPDDR2_NVM_TIM OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0030) +#define OMAP44XX_EMIF1_LPDDR2_NVM_TIM_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0034) +#define OMAP44XX_EMIF1_PWR_MGMT_CTRL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0038) +#define OMAP44XX_EMIF1_PWR_MGMT_CTRL_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x003c) +#define OMAP44XX_EMIF1_LPDDR2_MODE_REG_DATA OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0040) +#define OMAP44XX_EMIF1_LPDDR2_MODE_REG_CFG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0050) +#define OMAP44XX_EMIF1_OCP_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0054) +#define OMAP44XX_EMIF1_OCP_CFG_VAL_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0058) +#define OMAP44XX_EMIF1_OCP_CFG_VAL_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x005c) +#define OMAP44XX_EMIF1_IODFT_TLGC OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0060) +#define OMAP44XX_EMIF1_IODFT_CTRL_MISR_RSLT OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0064) +#define OMAP44XX_EMIF1_IODFT_ADDR_MISR_RSLT OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0068) +#define OMAP44XX_EMIF1_IODFT_DATA_MISR_RSLT_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x006c) +#define OMAP44XX_EMIF1_IODFT_DATA_MISR_RSLT_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0070) +#define OMAP44XX_EMIF1_IODFT_DATA_MISR_RSLT_3 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0074) +#define OMAP44XX_EMIF1_PERF_CNT_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0080) +#define OMAP44XX_EMIF1_PERF_CNT_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0084) +#define OMAP44XX_EMIF1_PERF_CNT_CFG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0088) +#define OMAP44XX_EMIF1_PERF_CNT_SEL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x008c) +#define OMAP44XX_EMIF1_PERF_CNT_TIM OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0090) +#define OMAP44XX_EMIF1_READ_IDLE_CTRL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x0098) +#define OMAP44XX_EMIF1_READ_IDLE_CTRL_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x009c) +#define OMAP44XX_EMIF1_IRQ_EOI OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00a0) +#define OMAP44XX_EMIF1_IRQSTATUS_RAW_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00a4) +#define OMAP44XX_EMIF1_IRQSTATUS_RAW_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00a8) +#define OMAP44XX_EMIF1_IRQSTATUS_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00ac) +#define OMAP44XX_EMIF1_IRQSTATUS_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00b0) +#define OMAP44XX_EMIF1_IRQENABLE_SET_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00b4) +#define OMAP44XX_EMIF1_IRQENABLE_SET_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00b8) +#define OMAP44XX_EMIF1_IRQENABLE_CLR_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00bc) +#define OMAP44XX_EMIF1_IRQENABLE_CLR_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00c0) +#define OMAP44XX_EMIF1_ZQ_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00c8) +#define OMAP44XX_EMIF1_TEMP_ALERT_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00cc) +#define OMAP44XX_EMIF1_OCP_ERR_LOG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00d0) +#define OMAP44XX_EMIF1_DDR_PHY_CTRL_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00e4) +#define OMAP44XX_EMIF1_DDR_PHY_CTRL_1_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00e8) +#define OMAP44XX_EMIF1_DDR_PHY_CTRL_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF1_BASE, 0x00ec) + + +/* EMIF2 Registers */ +#define OMAP44XX_EMIF2_MOD_ID_REV OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0000) +#define OMAP44XX_EMIF2_STATUS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0004) +#define OMAP44XX_EMIF2_SDRAM_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0008) +#define OMAP44XX_EMIF2_SDRAM_CONFIG_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x000c) +#define OMAP44XX_EMIF2_SDRAM_REF_CTRL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0010) +#define OMAP44XX_EMIF2_SDRAM_REF_CTRL_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0014) +#define OMAP44XX_EMIF2_SDRAM_TIM_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0018) +#define OMAP44XX_EMIF2_SDRAM_TIM_1_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x001c) +#define OMAP44XX_EMIF2_SDRAM_TIM_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0020) +#define OMAP44XX_EMIF2_SDRAM_TIM_2_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0024) +#define OMAP44XX_EMIF2_SDRAM_TIM_3 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0028) +#define OMAP44XX_EMIF2_SDRAM_TIM_3_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x002c) +#define OMAP44XX_EMIF2_LPDDR2_NVM_TIM OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0030) +#define OMAP44XX_EMIF2_LPDDR2_NVM_TIM_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0034) +#define OMAP44XX_EMIF2_PWR_MGMT_CTRL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0038) +#define OMAP44XX_EMIF2_PWR_MGMT_CTRL_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x003c) +#define OMAP44XX_EMIF2_LPDDR2_MODE_REG_DATA OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0040) +#define OMAP44XX_EMIF2_LPDDR2_MODE_REG_CFG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0050) +#define OMAP44XX_EMIF2_OCP_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0054) +#define OMAP44XX_EMIF2_OCP_CFG_VAL_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0058) +#define OMAP44XX_EMIF2_OCP_CFG_VAL_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x005c) +#define OMAP44XX_EMIF2_IODFT_TLGC OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0060) +#define OMAP44XX_EMIF2_IODFT_CTRL_MISR_RSLT OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0064) +#define OMAP44XX_EMIF2_IODFT_ADDR_MISR_RSLT OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0068) +#define OMAP44XX_EMIF2_IODFT_DATA_MISR_RSLT_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x006c) +#define OMAP44XX_EMIF2_IODFT_DATA_MISR_RSLT_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0070) +#define OMAP44XX_EMIF2_IODFT_DATA_MISR_RSLT_3 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0074) +#define OMAP44XX_EMIF2_PERF_CNT_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0080) +#define OMAP44XX_EMIF2_PERF_CNT_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0084) +#define OMAP44XX_EMIF2_PERF_CNT_CFG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0088) +#define OMAP44XX_EMIF2_PERF_CNT_SEL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x008c) +#define OMAP44XX_EMIF2_PERF_CNT_TIM OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0090) +#define OMAP44XX_EMIF2_READ_IDLE_CTRL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x0098) +#define OMAP44XX_EMIF2_READ_IDLE_CTRL_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x009c) +#define OMAP44XX_EMIF2_IRQ_EOI OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00a0) +#define OMAP44XX_EMIF2_IRQSTATUS_RAW_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00a4) +#define OMAP44XX_EMIF2_IRQSTATUS_RAW_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00a8) +#define OMAP44XX_EMIF2_IRQSTATUS_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00ac) +#define OMAP44XX_EMIF2_IRQSTATUS_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00b0) +#define OMAP44XX_EMIF2_IRQENABLE_SET_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00b4) +#define OMAP44XX_EMIF2_IRQENABLE_SET_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00b8) +#define OMAP44XX_EMIF2_IRQENABLE_CLR_SYS OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00bc) +#define OMAP44XX_EMIF2_IRQENABLE_CLR_LL OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00c0) +#define OMAP44XX_EMIF2_ZQ_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00c8) +#define OMAP44XX_EMIF2_TEMP_ALERT_CONFIG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00cc) +#define OMAP44XX_EMIF2_OCP_ERR_LOG OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00d0) +#define OMAP44XX_EMIF2_DDR_PHY_CTRL_1 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00e4) +#define OMAP44XX_EMIF2_DDR_PHY_CTRL_1_SHDW OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00e8) +#define OMAP44XX_EMIF2_DDR_PHY_CTRL_2 OMAP44XX_EMIF_REGADDR(OMAP44XX_EMIF2_BASE, 0x00ec) + + +typedef enum { + EMIF44XX_0 = 0, + EMIF44XX_1 = 1, + EMIF44XX_MAX = 2 +} emif44xx_ids; + + +typedef enum { + EMIF44XX_PERF_CNT_0 = 0, + EMIF44XX_PERF_CNT_1 = 1, + EMIF44XX_PERF_CNT_MAX = 2 +} emif44xx_perf_cnt_ids; + + +/* + * NB: When MReqDbg (cemudbg) is set to '1' for a command on the + * EMIF bus, perf. counters will not increment for + * counts of filter type 0,1,2,3 and A. + * NB: Filter types 0,1,2,3 and 8 work when MConnID(MSTID) filtering enabled. + * Filter types 2,3,8 work when region MAddrSpace(crsel) filtering + * is enabled. + */ + +typedef enum { + EMIF44XX_PERF_CNT_FILTER_TOTAL_ACCESS = 0x0, + EMIF44XX_PERF_CNT_FILTER_TOTAL_ACT = 0x1, + EMIF44XX_PERF_CNT_FILTER_TOTAL_READ = 0x2, + EMIF44XX_PERF_CNT_FILTER_TOTAL_WRITE = 0x3, + EMIF44XX_PERF_CNT_FILTER_CMDFIFO_FULL_CYC = 0x4, + EMIF44XX_PERF_CNT_FILTER_WRBUF_FULL_CYC = 0x5, + EMIF44XX_PERF_CNT_FILTER_RDFIFO_FULL_CYC = 0x6, + EMIF44XX_PERF_CNT_FILTER_WSFIFO_FULL_CYC = 0x7, + EMIF44XX_PERF_CNT_FILTER_PRIORITY_ELEV_CNT = 0x8, + EMIF44XX_PERF_CNT_FILTER_CMD_PENDING_CYC = 0x9, + EMIF44XX_PERF_CNT_FILTER_DATA_TRANSFER_CYCLES = 0xA, + EMIF44XX_PERF_CNT_FILTER_DISABLED = 0x10, /* Like MAX below, this value is not used in the EMIF. */ + EMIF44XX_PERF_CNT_FILTER_MAX = 0x11 /* Value is not used. */ +} emif44xx_perf_cnt_filter_ids; + + +typedef enum { + EMIF44XX_MEMADDRSPACE_CS1ANDCS0 = 0x0, /* These match EMIF fields (i.e. enum numbering is intentional.) */ + EMIF44XX_MEMADDRSPACE_CS0 = 0x1, + EMIF44XX_MEMADDRSPACE_RESERVED = 0x2, + EMIF44XX_MEMADDRSPACE_INTERNAL = 0x3, + EMIF44XX_MEMADDRSPACE_DISABLED = 0x4, /* Like MAX below, this value is not used in the EMIF. */ + EMIF44XX_MEMADDRSPACE_MAX = 0x5 /* Value is not used. */ +} emif44xx_memaddrspace; + + +static const name_desc_val_table emif_event_counters[] = { + {"TOTAL_ACCESS", "Total SDRAM Accesses.", EMIF44XX_PERF_CNT_FILTER_TOTAL_ACCESS}, + {"TOTAL_ACT", "Total SDRAM Activates.", EMIF44XX_PERF_CNT_FILTER_TOTAL_ACT}, + {"TOTAL_READ", "Total READs.", EMIF44XX_PERF_CNT_FILTER_TOTAL_READ}, + {"TOTAL_WRITE", "Total WRITES.", EMIF44XX_PERF_CNT_FILTER_TOTAL_WRITE}, + {"CMDFIFO_FULL", "Number of m_clk cycles OCP Command FIFO is full.", EMIF44XX_PERF_CNT_FILTER_CMDFIFO_FULL_CYC}, + {"WRBUF_FULL", "Number of m_clk cycles OCP Write Data FIFO is full.", EMIF44XX_PERF_CNT_FILTER_WRBUF_FULL_CYC}, + {"RDFIFO_FULL", "Number of m_clk cycles OCP Read Data FIFO is full.", EMIF44XX_PERF_CNT_FILTER_RDFIFO_FULL_CYC}, + {"WSFIFO_FULL", "Number of m_clk cycles OCP Return Command FIFO is full.", EMIF44XX_PERF_CNT_FILTER_WSFIFO_FULL_CYC}, + {"PRIORITY_ELEV", "Number of priority elevations.", EMIF44XX_PERF_CNT_FILTER_PRIORITY_ELEV_CNT}, + {"CMD_PENDING", "Number of m_clk cycles that a command was pending.", EMIF44XX_PERF_CNT_FILTER_CMD_PENDING_CYC}, + {"DATA_TRANSFER", "Number of m_clk cycles memory bus xferring data.", EMIF44XX_PERF_CNT_FILTER_DATA_TRANSFER_CYCLES}, + {"DISABLED", "Counts Disabled.", EMIF44XX_PERF_CNT_FILTER_DISABLED}, + /* END OF TABLE IS REQUIRED! */ + {"END", "End of Table.", 0} }; + + +static const name_desc_val_table emif_event_memaddrspace[] = { + {"CS_1_AND_0", "Count for access to PAD_CS_N[1] and PAD_CS_N[0] regions.", EMIF44XX_MEMADDRSPACE_CS1ANDCS0}, + {"CS_0", "Count for access to PAD_CS_N[0] region.", EMIF44XX_MEMADDRSPACE_CS0}, + {"RESERVED", "Reserved. Usage is unpredictable.", EMIF44XX_MEMADDRSPACE_RESERVED}, + {"INTERNAL", "Count for access to internal registers.", EMIF44XX_MEMADDRSPACE_INTERNAL}, + {"DISABLED", "Count All. Region filtering is disabled.", EMIF44XX_MEMADDRSPACE_DISABLED}, + /* END OF TABLEIS REQUIRED! */ + {"END", "End of Table.", 0} }; + + +int emif44xx_name2addr(char *name, unsigned int *addr); +int emif44xx_dump(void); +int emif44xx_main(int argc, char *argv[]); + +int emif44xx_perf_cnt_configure(emif44xx_ids emif_id, + emif44xx_perf_cnt_ids cnt_id, emif44xx_perf_cnt_filter_ids filter, + int conn_id, emif44xx_memaddrspace addr_sel); +unsigned int emif44xx_perf_cnt_get_time(emif44xx_ids emif_id); +unsigned int emif44xx_perf_cnt_get_count(emif44xx_ids emif_id, + emif44xx_perf_cnt_ids cnt_id); + + +unsigned char emif44xx_cs_count_get(void); + + +#endif diff -Nru tiomapconf-1.52.0/arch/arm/mach-omap/omap4/help44xx.c tiomapconf-1.61.1/arch/arm/mach-omap/omap4/help44xx.c --- tiomapconf-1.52.0/arch/arm/mach-omap/omap4/help44xx.c 1970-01-01 00:00:00.000000000 +0000 +++ tiomapconf-1.61.1/arch/arm/mach-omap/omap4/help44xx.c 2012-12-13 15:13:55.000000000 +0000 @@ -0,0 +1,585 @@ +/* + * + * @Component OMAPCONF + * @Filename help44xx.c + * @Description Help for OMAP4-specific functions + * @Author Patrick Titiano (p-titiano@ti.com) + * @Date 2010 + * @Copyright Texas Instruments Incorporated + * + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* ------------------------------------------------------------------------*//** + * @FUNCTION help44xx + * @BRIEF display omap4conf help + * @param[in] cat: help category to display + * @DESCRIPTION display omap4conf help + *//*------------------------------------------------------------------------ */ +void help44xx(help_category cat, char *context) +{ + unsigned int i; + int ret; + char name[64]; + char desc[128]; + + if (cat >= HELP_CATEGORY_MAX) { + fprintf(stderr, "%s(): incorrect category!!! (%u)\n", + __func__, cat); + return; + } + + if ((cat == HELP_ALL) || (cat == HELP_EXPORT)) { + printf("\n\tomapconf export ctt []\n"); + printf("\t Export PRCM registers in .rd1 format for Clock " + "Tree Tool (CTT, ), to " + " or stdout if omitted.\n"); + + printf("\n\tomapconf export pct []\n"); + printf("\t Export PRCM registers in .rd1 format for Pad " + "Configuration Tool (PCT, " + ")," + " to or stdout if omitted.\n"); + } + + if ((cat == HELP_ALL) || (cat == HELP_SOC_PWST)) { + printf("\n\tomapconf show pwst\n"); + printf("\t Print OMAP power status (OPP, voltage/power/clock" + " domains states, and modules status).\n"); + } + + if ((cat == HELP_ALL) || (cat == HELP_SOC_OPP)) { + printf("\n\tomapconf show opp\n"); + printf("\t Print OMAP current OPerating Points (OPP)" + "(voltage, frequency) for MPU/IVA/CORE voltage " + "domains), including main modules frequencies.\n"); + } + + if ((cat == HELP_ALL) || (cat == HELP_TEMPERATURE)) { + printf("\n\tomapconf show temp []\n"); + printf( + "\t Print temperature reported by , in celcius degrees.\n"); + printf( + "\t Supported : bandgap, hotspot, mem1, mem2, pcb.\n"); + printf( + "\t If is omitted, all available sensors will be printed in a table, with both celcius and fahrenheit degrees.\n"); + } + + if ((cat == HELP_ALL) || (cat == HELP_VOLT)) { + printf("\n\tomapconf set volt \n"); + printf("\t Set voltage to .\n"); + printf("\t Supported : mpu, iva, core.\n"); + printf("\t is in volts.\n"); + printf("\t ### WARNING ###: do it at your own risk. " + "Unsupported voltage may crash or damage device!\n"); + printf("\t e.g. omapconf set volt mpu 1.25\n"); + + printf("\n\tomapconf search vmin