#*****************************************************************************************
# Vivado (TM) v2023.1.1 (64-bit)
#
# recreate-version-20230921.tcl: Tcl script for re-creating project 'project_RP-SPMC-RedPACPLL-202308-test'
#
# Generated by Vivado on Thu Sep 21 00:58:16 EDT 2023
# IP Build 3900379 on Sat Jun 17 05:28:05 MDT 2023
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (recreate-version-20230921.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# 3. The following remote source files that were added to the original project:-
#
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/QControl.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/controller_pi.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/amplitude_good.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/phase_unwrap.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_dc_filter.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_decimator.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/lms_phase_amplitude_detector.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/PulseForm.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_FIR.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_4s_combine.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/McBSP_io_connect.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/McBSP_controller.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_bram_push.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_ctrlsrc_select.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_spm_control.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/gvp.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/AD5791_io_connect.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_AD5791.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/VolumeAdjuster16_14.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/Volume_QControl_Mixer.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/LED_connect.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_sc28_to_14.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_bram_stream_srcs.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/system_wrapper.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/cores/axi_cfg_register_v1_0/axi_cfg_register.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/cores/axis_averager_v1_0/axis_averager.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/cores/axis_constant_v1_0/axis_constant.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/cores/axis_red_pitaya_dac_v1_0/axis_red_pitaya_dac.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/cores/axis_red_pitaya_adc_v1_0/axis_red_pitaya_adc.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/ScaleAndAdjust.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/comparator.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/logic_or.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_axis_select.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_ram_writer.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/signal_combine.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/split_signal.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/SineSDB64.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/Signed16toQ22.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/SignedQ31toQ22.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/ArrithmeticShift.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/port_slicer.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/cfg/ports.xdc"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/cfg/clocks.xdc"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/sim/tb_spm_ad.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/sim/lms_phase_amplitude_detector_tb.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/sim/McBSP_tb.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/sim/axis_4s_combine_tb.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/sim/controller_pi_tb.v"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/sim/tb_spm_ad_behav.wcfg"
#    "/home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/sim/ad5791_tb.v"
#
#*****************************************************************************************

# Check file required for this script exists
proc checkRequiredFiles { origin_dir} {
  set status true

  set files [list \
 "[file normalize "$origin_dir/rtl/QControl.v"]"\
 "[file normalize "$origin_dir/rtl/cfg_select.v"]"\
 "[file normalize "$origin_dir/rtl/cfg_to_axis.v"]"\
 "[file normalize "$origin_dir/rtl/controller_pi.v"]"\
 "[file normalize "$origin_dir/rtl/amplitude_good.v"]"\
 "[file normalize "$origin_dir/rtl/phase_unwrap.v"]"\
 "[file normalize "$origin_dir/rtl/axis_dc_filter.v"]"\
 "[file normalize "$origin_dir/rtl/axis_decimator.v"]"\
 "[file normalize "$origin_dir/rtl/lms_phase_amplitude_detector.v"]"\
 "[file normalize "$origin_dir/rtl/PulseForm.v"]"\
 "[file normalize "$origin_dir/rtl/axis_FIR.v"]"\
 "[file normalize "$origin_dir/rtl/axis_4s_combine.v"]"\
 "[file normalize "$origin_dir/rtl/McBSP_io_connect.v"]"\
 "[file normalize "$origin_dir/rtl/McBSP_controller.v"]"\
 "[file normalize "$origin_dir/rtl/axis_bram_push.v"]"\
 "[file normalize "$origin_dir/rtl/axis_ctrlsrc_select.v"]"\
 "[file normalize "$origin_dir/rtl/axis_spm_control.v"]"\
 "[file normalize "$origin_dir/rtl/gvp.v"]"\
 "[file normalize "$origin_dir/rtl/AD5791_io_connect.v"]"\
 "[file normalize "$origin_dir/rtl/axis_AD5791.v"]"\
 "[file normalize "$origin_dir/rtl/VolumeAdjuster16_14.v"]"\
 "[file normalize "$origin_dir/rtl/Volume_QControl_Mixer.v"]"\
 "[file normalize "$origin_dir/rtl/LED_connect.v"]"\
 "[file normalize "$origin_dir/rtl/axis_sc28_to_14.v"]"\
 "[file normalize "$origin_dir/rtl/axis_bram_stream_srcs.v"]"\
 "[file normalize "$origin_dir/rtl/axis_splitter.v"]"\
 "[file normalize "$origin_dir/rtl/system_wrapper.v"]"\
 "[file normalize "$origin_dir/cores/axi_cfg_register_v1_0/axi_cfg_register.v"]"\
 "[file normalize "$origin_dir/cores/axis_averager_v1_0/axis_averager.v"]"\
 "[file normalize "$origin_dir/cores/axis_constant_v1_0/axis_constant.v"]"\
 "[file normalize "$origin_dir/cores/axis_red_pitaya_dac_v1_0/axis_red_pitaya_dac.v"]"\
 "[file normalize "$origin_dir/cores/axis_red_pitaya_adc_v1_0/axis_red_pitaya_adc.v"]"\
 "[file normalize "$origin_dir/rtl/ScaleAndAdjust.v"]"\
 "[file normalize "$origin_dir/rtl/comparator.v"]"\
 "[file normalize "$origin_dir/rtl/logic_or.v"]"\
 "[file normalize "$origin_dir/rtl/cfg_axis_select.v"]"\
 "[file normalize "$origin_dir/rtl/axis_ram_writer.v"]"\
 "[file normalize "$origin_dir/rtl/signal_combine.v"]"\
 "[file normalize "$origin_dir/rtl/split_signal.v"]"\
 "[file normalize "$origin_dir/rtl/SineSDB64.v"]"\
 "[file normalize "$origin_dir/rtl/Signed16toQ22.v"]"\
 "[file normalize "$origin_dir/rtl/SignedQ31toQ22.v"]"\
 "[file normalize "$origin_dir/rtl/ArrithmeticShift.v"]"\
 "[file normalize "$origin_dir/rtl/port_slicer.v"]"\
 "[file normalize "$origin_dir/cfg/ports.xdc"]"\
 "[file normalize "$origin_dir/cfg/clocks.xdc"]"\
 "[file normalize "$origin_dir/sim/tb_spm_ad.v"]"\
 "[file normalize "$origin_dir/sim/lms_phase_amplitude_detector_tb.v"]"\
 "[file normalize "$origin_dir/sim/McBSP_tb.v"]"\
 "[file normalize "$origin_dir/sim/axis_4s_combine_tb.v"]"\
 "[file normalize "$origin_dir/sim/controller_pi_tb.v"]"\
 "[file normalize "$origin_dir/sim/tb_spm_ad_behav.wcfg"]"\
 "[file normalize "$origin_dir/sim/ad5791_tb.v"]"\
  ]
  foreach ifile $files {
    if { ![file isfile $ifile] } {
      puts " Could not find remote file $ifile "
      set status false
    }
  }

  set paths [list \
 "[file normalize "$origin_dir/[file normalize "$origin_dir/tmp/cores"]"]"\
  ]
  foreach ipath $paths {
    if { ![file isdirectory $ipath] } {
      puts " Could not access $ipath "
      set status false
    }
  }

  return $status
}
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."

# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}

# Set the project name
set _xil_proj_name_ "project_RP-SPMC-RedPACPLL-202309821-7z020-spmc-pacpll"

# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
  set _xil_proj_name_ $::user_project_name
}

variable script_file
set script_file "recreate-version-20230921.tcl"

# Help information for this script
proc print_help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--project_name <name>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--project_name <name>\] Create project with the specified name. Default"
  puts "                       name is the name of the project from where this"
  puts "                       script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}

if { $::argc > 0 } {
  for {set i 0} {$i < $::argc} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
      "--help"         { print_help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/project_RP-SPMC-RedPACPLL-202308-test"]"

# Check for paths and files needed for project creation
set validate_required 0
if { $validate_required } {
  if { [checkRequiredFiles $origin_dir] } {
    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
  } else {
    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
    return
  }
}

# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Reconstruct message rules
# None

# Set project properties
set obj [current_project]
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_resource_estimation" -value "0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xc7z020clg400-1" -objects $obj
set_property -name "platform.num_compute_units" -value "16" -objects $obj
set_property -name "revised_directory_structure" -value "1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "sim_compile_state" -value "1" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "19" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "10" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "19" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "19" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "19" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "19" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "19" -objects $obj
set_property -name "webtalk.xsim_launch_sim" -value "711" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set IP repository paths
set obj [get_filesets sources_1]
if { $obj != {} } {
   set_property "ip_repo_paths" "[file normalize "$origin_dir/tmp/cores"]" $obj

   # Rebuild user ip_repo's index before adding any source files
   update_ip_catalog -rebuild
}

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 [file normalize "${origin_dir}/rtl/QControl.v"] \
 [file normalize "${origin_dir}/rtl/cfg_select.v"] \
 [file normalize "${origin_dir}/rtl/cfg_to_axis.v"] \
 [file normalize "${origin_dir}/rtl/controller_pi.v"] \
 [file normalize "${origin_dir}/rtl/amplitude_good.v"] \
 [file normalize "${origin_dir}/rtl/phase_unwrap.v"] \
 [file normalize "${origin_dir}/rtl/axis_dc_filter.v"] \
 [file normalize "${origin_dir}/rtl/axis_decimator.v"] \
 [file normalize "${origin_dir}/rtl/lms_phase_amplitude_detector.v"] \
 [file normalize "${origin_dir}/rtl/PulseForm.v"] \
 [file normalize "${origin_dir}/rtl/axis_FIR.v"] \
 [file normalize "${origin_dir}/rtl/axis_4s_combine.v"] \
 [file normalize "${origin_dir}/rtl/McBSP_io_connect.v"] \
 [file normalize "${origin_dir}/rtl/McBSP_controller.v"] \
 [file normalize "${origin_dir}/rtl/axis_bram_push.v"] \
 [file normalize "${origin_dir}/rtl/axis_ctrlsrc_select.v"] \
 [file normalize "${origin_dir}/rtl/axis_spm_control.v"] \
 [file normalize "${origin_dir}/rtl/gvp.v"] \
 [file normalize "${origin_dir}/rtl/AD5791_io_connect.v"] \
 [file normalize "${origin_dir}/rtl/axis_AD5791.v"] \
 [file normalize "${origin_dir}/rtl/VolumeAdjuster16_14.v"] \
 [file normalize "${origin_dir}/rtl/Volume_QControl_Mixer.v"] \
 [file normalize "${origin_dir}/rtl/LED_connect.v"] \
 [file normalize "${origin_dir}/rtl/axis_sc28_to_14.v"] \
 [file normalize "${origin_dir}/rtl/axis_bram_stream_srcs.v"] \
 [file normalize "${origin_dir}/rtl/axis_splitter.v"] \
 [file normalize "${origin_dir}/rtl/system_wrapper.v"] \
 [file normalize "${origin_dir}/cores/axi_cfg_register_v1_0/axi_cfg_register.v"] \
 [file normalize "${origin_dir}/cores/axis_averager_v1_0/axis_averager.v"] \
 [file normalize "${origin_dir}/cores/axis_constant_v1_0/axis_constant.v"] \
 [file normalize "${origin_dir}/cores/axis_red_pitaya_dac_v1_0/axis_red_pitaya_dac.v"] \
 [file normalize "${origin_dir}/cores/axis_red_pitaya_adc_v1_0/axis_red_pitaya_adc.v"] \
 [file normalize "${origin_dir}/rtl/ScaleAndAdjust.v"] \
 [file normalize "${origin_dir}/rtl/comparator.v"] \
 [file normalize "${origin_dir}/rtl/logic_or.v"] \
 [file normalize "${origin_dir}/rtl/cfg_axis_select.v"] \
 [file normalize "${origin_dir}/rtl/axis_ram_writer.v"] \
 [file normalize "${origin_dir}/rtl/signal_combine.v"] \
 [file normalize "${origin_dir}/rtl/split_signal.v"] \
 [file normalize "${origin_dir}/rtl/SineSDB64.v"] \
 [file normalize "${origin_dir}/rtl/Signed16toQ22.v"] \
 [file normalize "${origin_dir}/rtl/SignedQ31toQ22.v"] \
 [file normalize "${origin_dir}/rtl/ArrithmeticShift.v"] \
 [file normalize "${origin_dir}/rtl/port_slicer.v"] \
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
# None

# Set 'sources_1' fileset file properties for local files
# None

# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
set_property -name "top" -value "system_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "verilog_define" -value "TOOL_VIVADO" -objects $obj

# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}

# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/cfg/ports.xdc"]"
set file_added [add_files -norecurse -fileset $obj [list $file]]
set file "$origin_dir/cfg/ports.xdc"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/cfg/clocks.xdc"]"
set file_added [add_files -norecurse -fileset $obj [list $file]]
set file "$origin_dir/cfg/clocks.xdc"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "target_constrs_file" -value "[file normalize "$origin_dir/cfg/clocks.xdc"]" -objects $obj
set_property -name "target_part" -value "xc7z020clg400-1" -objects $obj
set_property -name "target_ucf" -value "[file normalize "$origin_dir/cfg/clocks.xdc"]" -objects $obj

# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}

# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
 [file normalize "${origin_dir}/sim/tb_spm_ad.v"] \
 [file normalize "${origin_dir}/sim/lms_phase_amplitude_detector_tb.v"] \
 [file normalize "${origin_dir}/sim/McBSP_tb.v"] \
 [file normalize "${origin_dir}/sim/axis_4s_combine_tb.v"] \
 [file normalize "${origin_dir}/sim/controller_pi_tb.v"] \
 [file normalize "${origin_dir}/sim/tb_spm_ad_behav.wcfg"] \
]
add_files -norecurse -fileset $obj $files

# Set 'sim_1' fileset file properties for remote files
# None

# Set 'sim_1' fileset file properties for local files
# None

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "tb_spm_ad" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj

# Create 'sim_ad5791' fileset (if not found)
if {[string equal [get_filesets -quiet sim_ad5791] ""]} {
  create_fileset -simset sim_ad5791
}

# Set 'sim_ad5791' fileset object
set obj [get_filesets sim_ad5791]
set files [list \
 [file normalize "${origin_dir}/sim/ad5791_tb.v"] \
]
add_files -norecurse -fileset $obj $files

# Set 'sim_ad5791' fileset file properties for remote files
# None

# Set 'sim_ad5791' fileset file properties for local files
# None

# Set 'sim_ad5791' fileset properties
set obj [get_filesets sim_ad5791]
set_property -name "top" -value "ad5791_tb" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj


# Adding sources referenced in BDs, if not already added
if { [get_files QControl.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/QControl.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files controller_pi.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/controller_pi.v
}
if { [get_files amplitude_good.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/amplitude_good.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files phase_unwrap.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/phase_unwrap.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files controller_pi.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/controller_pi.v
}
if { [get_files axis_dc_filter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_dc_filter.v
}
if { [get_files axis_decimator.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_decimator.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files lms_phase_amplitude_detector.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/lms_phase_amplitude_detector.v
}
if { [get_files PulseForm.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/PulseForm.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files axis_FIR.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_FIR.v
}
if { [get_files axis_FIR.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_FIR.v
}
if { [get_files axis_FIR.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_FIR.v
}
if { [get_files axis_FIR.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_FIR.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files controller_pi.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/controller_pi.v
}
if { [get_files axis_4s_combine.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_4s_combine.v
}
if { [get_files McBSP_io_connect.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/McBSP_io_connect.v
}
if { [get_files McBSP_controller.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/McBSP_controller.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files axis_bram_push.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_bram_push.v
}
if { [get_files cfg_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_select.v
}
if { [get_files axis_ctrlsrc_select.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_ctrlsrc_select.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files controller_pi.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/controller_pi.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files cfg_to_axis.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/cfg_to_axis.v
}
if { [get_files axis_spm_control.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_spm_control.v
}
if { [get_files gvp.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/gvp.v
}
if { [get_files AD5791_io_connect.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/AD5791_io_connect.v
}
if { [get_files axis_AD5791.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_AD5791.v
}
if { [get_files VolumeAdjuster16_14.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/VolumeAdjuster16_14.v
}
if { [get_files Volume_QControl_Mixer.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/Volume_QControl_Mixer.v
}
if { [get_files LED_connect.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/LED_connect.v
}
if { [get_files axis_sc28_to_14.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_sc28_to_14.v
}
if { [get_files axis_bram_stream_srcs.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_bram_stream_srcs.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}
if { [get_files axis_splitter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/pzahl/SVN/Gxsm4/plug-ins/hard/RPSPMC/rtl/axis_splitter.v
}


# Proc to create BD system
proc cr_bd_system { parentCell } {
# The design that will be created by this Tcl proc contains the following 
# module references:
# VolumeAdjuster16_14, Volume_QControl_Mixer, led_connect, axis_sc28_to_14, QControl, cfg_select, cfg_to_axis, cfg_to_axis, axis_dc_filter, axis_decimator, cfg_select, cfg_select, cfg_select, cfg_select, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, lms_phase_amplitude_detector, axis_splitter, axis_4s_combine, McBSP_io_connect, McBSP_controller, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, axis_bram_push, axis_FIR, axis_FIR, axis_FIR, axis_FIR, axis_splitter, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, AD5791_io_connect, axis_AD5791, gvp, axis_bram_stream_srcs, axis_spm_control, axis_splitter, axis_splitter, axis_splitter, axis_splitter, axis_splitter, axis_splitter, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, controller_pi, amplitude_good, cfg_select, phase_unwrap, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, controller_pi, PulseForm, cfg_to_axis, cfg_to_axis, cfg_select, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, controller_pi, cfg_select, axis_ctrlsrc_select, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, cfg_to_axis, controller_pi



  # CHANGE DESIGN NAME HERE
  set design_name system

  common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."

  create_bd_design $design_name

  set bCheckIPsPassed 1
  ##################################################################
  # CHECK IPs
  ##################################################################
  set bCheckIPs 1
  if { $bCheckIPs == 1 } {
     set list_check_ips "\ 
  pavel-demin:user:axis_red_pitaya_adc:1.0\
  pavel-demin:user:axis_red_pitaya_dac:1.0\
  xilinx.com:ip:clk_wiz:6.0\
  xilinx.com:ip:util_ds_buf:2.2\
  xilinx.com:ip:xlconcat:2.1\
  xilinx.com:ip:xlslice:1.0\
  xilinx.com:ip:dds_compiler:6.0\
  xilinx.com:ip:cordic:6.0\
  anton-potocnik:user:axi_bram_reader:1.0\
  pavel-demin:user:axi_cfg_register:1.0\
  xilinx.com:ip:processing_system7:5.5\
  xilinx.com:ip:proc_sys_reset:5.0\
  xilinx.com:ip:axi_gpio:2.0\
  xilinx.com:ip:blk_mem_gen:8.4\
  xilinx.com:ip:xlconstant:1.1\
  xilinx.com:ip:floating_point:7.1\
  "

   set list_ips_missing ""
   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

  }

  ##################################################################
  # CHECK Modules
  ##################################################################
  set bCheckModules 1
  if { $bCheckModules == 1 } {
     set list_check_mods "\ 
  VolumeAdjuster16_14\
  Volume_QControl_Mixer\
  led_connect\
  axis_sc28_to_14\
  QControl\
  cfg_select\
  cfg_to_axis\
  cfg_to_axis\
  axis_dc_filter\
  axis_decimator\
  cfg_select\
  cfg_select\
  cfg_select\
  cfg_select\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  lms_phase_amplitude_detector\
  axis_splitter\
  axis_4s_combine\
  McBSP_io_connect\
  McBSP_controller\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  axis_bram_push\
  axis_FIR\
  axis_FIR\
  axis_FIR\
  axis_FIR\
  axis_splitter\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  AD5791_io_connect\
  axis_AD5791\
  gvp\
  axis_bram_stream_srcs\
  axis_spm_control\
  axis_splitter\
  axis_splitter\
  axis_splitter\
  axis_splitter\
  axis_splitter\
  axis_splitter\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  controller_pi\
  amplitude_good\
  cfg_select\
  phase_unwrap\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  controller_pi\
  PulseForm\
  cfg_to_axis\
  cfg_to_axis\
  cfg_select\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  controller_pi\
  cfg_select\
  axis_ctrlsrc_select\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  cfg_to_axis\
  controller_pi\
  "

   set list_mods_missing ""
   common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."

   foreach mod_vlnv $list_check_mods {
      if { [can_resolve_reference $mod_vlnv] == 0 } {
         lappend list_mods_missing $mod_vlnv
      }
   }

   if { $list_mods_missing ne "" } {
      catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
      common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
      set bCheckIPsPassed 0
   }
}

  if { $bCheckIPsPassed != 1 } {
    common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
    return 3
  }

  
# Hierarchical cell: controller_zservo
proc create_hier_cell_controller_zservo { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_controller_zservo() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL2

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_PASS


  # Create pins
  create_bd_pin -dir I -type clk a_clk
  create_bd_pin -dir I -from 1023 -to 0 cfg1
  create_bd_pin -dir O enable
  create_bd_pin -dir O -from 31 -to 0 mon_control
  create_bd_pin -dir I -from 31 -to 0 Din
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_PASS_tdata1

  # Create instance: cfg_select_zservo_control, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_zservo_control
  if { [catch {set cfg_select_zservo_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_zservo_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_SWBIT {0} \
    CONFIG.SRC_ADDR {19} \
  ] $cfg_select_zservo_control


  # Create instance: const_zero_32b, and set properties
  set const_zero_32b [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_zero_32b ]
  set_property -dict [list \
    CONFIG.CONST_VAL {0} \
    CONFIG.CONST_WIDTH {32} \
  ] $const_zero_32b


  # Create instance: floating_point_log, and set properties
  set floating_point_log [ create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_log ]
  set_property -dict [list \
    CONFIG.C_Latency {23} \
    CONFIG.C_Mult_Usage {Medium_Usage} \
    CONFIG.C_Rate {1} \
    CONFIG.C_Result_Exponent_Width {8} \
    CONFIG.C_Result_Fraction_Width {24} \
    CONFIG.Operation_Type {Logarithm} \
    CONFIG.Result_Precision_Type {Single} \
  ] $floating_point_log


  # Create instance: xlslice_servo_hold, and set properties
  set xlslice_servo_hold [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_servo_hold ]

  # Create instance: xlconstant_0, and set properties
  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]

  # Create instance: xlconstant_select0, and set properties
  set xlconstant_select0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_select0 ]
  set_property -dict [list \
    CONFIG.CONST_VAL {0} \
    CONFIG.CONST_WIDTH {2} \
  ] $xlconstant_select0


  # Create instance: axis_ctrlsrc_select_0, and set properties
  set block_name axis_ctrlsrc_select
  set block_cell_name axis_ctrlsrc_select_0
  if { [catch {set axis_ctrlsrc_select_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_ctrlsrc_select_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: cfg_to_transport_zservo_ci, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_zservo_ci
  if { [catch {set cfg_to_transport_zservo_ci [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_zservo_ci eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {12} \
  ] $cfg_to_transport_zservo_ci


  # Create instance: cfg_to_transport_zservo_cp, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_zservo_cp
  if { [catch {set cfg_to_transport_zservo_cp [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_zservo_cp eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {11} \
  ] $cfg_to_transport_zservo_cp


  # Create instance: cfg_to_transport_zservo_lower, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_zservo_lower
  if { [catch {set cfg_to_transport_zservo_lower [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_zservo_lower eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {15} \
  ] $cfg_to_transport_zservo_lower


  # Create instance: cfg_to_transport_zservo_set, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_zservo_set
  if { [catch {set cfg_to_transport_zservo_set [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_zservo_set eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {10} \
  ] $cfg_to_transport_zservo_set


  # Create instance: cfg_to_transport_zservo_upper, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_zservo_upper
  if { [catch {set cfg_to_transport_zservo_upper [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_zservo_upper eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {13} \
  ] $cfg_to_transport_zservo_upper


  # Create instance: controller_z_servo, and set properties
  set block_name controller_pi
  set block_cell_name controller_z_servo
  if { [catch {set controller_z_servo [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $controller_z_servo eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.AXIS_TDATA_WIDTH {32} \
    CONFIG.CONTROL_W {32} \
    CONFIG.IN_Q {24} \
    CONFIG.IN_W {25} \
    CONFIG.M_AXIS_CONTROL2_TDATA_WIDTH {32} \
    CONFIG.M_AXIS_CONTROL_TDATA_WIDTH {32} \
    CONFIG.USE_RESET_DATA_INPUT {0} \
  ] $controller_z_servo


  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axis_ctrlsrc_select_0/S_AXIS] [get_bd_intf_pins S_AXIS]
  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins controller_z_servo/M_AXIS_PASS] [get_bd_intf_pins M_AXIS_PASS]
  connect_bd_intf_net -intf_net axis_ctrlsrc_select_0_M_AXIS [get_bd_intf_pins controller_z_servo/S_AXIS] [get_bd_intf_pins axis_ctrlsrc_select_0/M_AXIS]
  connect_bd_intf_net -intf_net axis_ctrlsrc_select_0_M_AXIS_FLOAT [get_bd_intf_pins axis_ctrlsrc_select_0/M_AXIS_FLOAT] [get_bd_intf_pins floating_point_log/S_AXIS_A]
  connect_bd_intf_net -intf_net controller_pi_dfreq_M_AXIS_CONTROL [get_bd_intf_pins M_AXIS_CONTROL] [get_bd_intf_pins controller_z_servo/M_AXIS_CONTROL]
  connect_bd_intf_net -intf_net controller_pi_dfreq_M_AXIS_CONTROL2 [get_bd_intf_pins M_AXIS_CONTROL2] [get_bd_intf_pins controller_z_servo/M_AXIS_CONTROL2]
  connect_bd_intf_net -intf_net floating_point_log_M_AXIS_RESULT [get_bd_intf_pins floating_point_log/M_AXIS_RESULT] [get_bd_intf_pins axis_ctrlsrc_select_0/S_AXIS_LG]

  # Create port connections
  connect_bd_net -net Din_1 [get_bd_pins Din] [get_bd_pins xlslice_servo_hold/Din]
  connect_bd_net -net PS_cfg_data [get_bd_pins cfg1] [get_bd_pins cfg_select_zservo_control/cfg] [get_bd_pins cfg_to_transport_zservo_ci/cfg] [get_bd_pins cfg_to_transport_zservo_cp/cfg] [get_bd_pins cfg_to_transport_zservo_lower/cfg] [get_bd_pins cfg_to_transport_zservo_set/cfg] [get_bd_pins cfg_to_transport_zservo_upper/cfg]
  connect_bd_net -net PS_data_transport_status [get_bd_pins cfg_select_zservo_control/status] [get_bd_pins enable] [get_bd_pins controller_z_servo/enable]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk1 [get_bd_pins a_clk] [get_bd_pins floating_point_log/aclk] [get_bd_pins axis_ctrlsrc_select_0/a_clk] [get_bd_pins cfg_to_transport_zservo_ci/a_clk] [get_bd_pins cfg_to_transport_zservo_cp/a_clk] [get_bd_pins cfg_to_transport_zservo_lower/a_clk] [get_bd_pins cfg_to_transport_zservo_set/a_clk] [get_bd_pins cfg_to_transport_zservo_upper/a_clk] [get_bd_pins controller_z_servo/aclk]
  connect_bd_net -net cfg_to_transport_dfreq_ci_data [get_bd_pins cfg_to_transport_zservo_ci/data] [get_bd_pins controller_z_servo/ci]
  connect_bd_net -net cfg_to_transport_dfreq_cp_data [get_bd_pins cfg_to_transport_zservo_cp/data] [get_bd_pins controller_z_servo/cp]
  connect_bd_net -net cfg_to_transport_dfreq_lower_data [get_bd_pins cfg_to_transport_zservo_lower/data] [get_bd_pins controller_z_servo/limit_lower]
  connect_bd_net -net cfg_to_transport_dfreq_upper_data [get_bd_pins cfg_to_transport_zservo_upper/data] [get_bd_pins controller_z_servo/limit_upper]
  connect_bd_net -net cfg_to_transport_tau_dfreq_data [get_bd_pins cfg_to_transport_zservo_set/data] [get_bd_pins controller_z_servo/setpoint]
  connect_bd_net -net const_zero_32b_dout [get_bd_pins const_zero_32b/dout] [get_bd_pins controller_z_servo/S_AXIS_reset_tdata]
  connect_bd_net -net gpio_io_6_x13_1 [get_bd_pins controller_z_servo/mon_control] [get_bd_pins mon_control]
  connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins controller_z_servo/S_AXIS_reset_tvalid]
  connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconstant_select0/dout] [get_bd_pins axis_ctrlsrc_select_0/selection]
  connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_servo_hold/Dout] [get_bd_pins controller_z_servo/control_hold]

  # Perform GUI Layout
  regenerate_bd_layout -hierarchy [get_bd_cells /SPM_control_logic/controller_zservo] -layout_string {
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"1.09787",
   "Default View_TopLeft":"-1826,-7",
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
#  -string -flagsOSRD
preplace port M_AXIS_CONTROL -pg 1 -lvl 4 -x 1210 -y 580 -defaultsOSRD
preplace port M_AXIS_CONTROL2 -pg 1 -lvl 4 -x 1210 -y 610 -defaultsOSRD
preplace port S_AXIS -pg 1 -lvl 0 -x -10 -y 980 -defaultsOSRD
preplace port M_AXIS_PASS -pg 1 -lvl 4 -x 1210 -y 550 -defaultsOSRD
preplace port port-id_a_clk -pg 1 -lvl 0 -x -10 -y 1010 -defaultsOSRD
preplace port port-id_enable -pg 1 -lvl 4 -x 1210 -y 870 -defaultsOSRD
preplace portBus cfg1 -pg 1 -lvl 0 -x -10 -y 1240 -defaultsOSRD
preplace portBus mon_control -pg 1 -lvl 4 -x 1210 -y 730 -defaultsOSRD
preplace portBus Din -pg 1 -lvl 0 -x -10 -y 270 -defaultsOSRD
preplace portBus M_AXIS_PASS_tdata1 -pg 1 -lvl 4 -x 1210 -y 670 -defaultsOSRD
preplace inst cfg_select_zservo_control -pg 1 -lvl 2 -x 480 -y 1150 -defaultsOSRD
preplace inst const_zero_32b -pg 1 -lvl 2 -x 480 -y 50 -defaultsOSRD
preplace inst floating_point_log -pg 1 -lvl 1 -x 160 -y 1070 -defaultsOSRD
preplace inst xlslice_servo_hold -pg 1 -lvl 2 -x 480 -y 270 -defaultsOSRD
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 480 -y 610 -defaultsOSRD
preplace inst xlconstant_select0 -pg 1 -lvl 1 -x 160 -y 1180 -defaultsOSRD
preplace inst axis_ctrlsrc_select_0 -pg 1 -lvl 2 -x 480 -y 1020 -defaultsOSRD
preplace inst cfg_to_transport_zservo_ci -pg 1 -lvl 2 -x 480 -y 380 -defaultsOSRD
preplace inst cfg_to_transport_zservo_cp -pg 1 -lvl 2 -x 480 -y 160 -defaultsOSRD
preplace inst cfg_to_transport_zservo_lower -pg 1 -lvl 2 -x 480 -y 740 -defaultsOSRD
preplace inst cfg_to_transport_zservo_set -pg 1 -lvl 2 -x 480 -y 500 -defaultsOSRD
preplace inst cfg_to_transport_zservo_upper -pg 1 -lvl 2 -x 480 -y 860 -defaultsOSRD
preplace inst controller_z_servo -pg 1 -lvl 3 -x 940 -y 730 -defaultsOSRD
preplace netloc Din_1 1 0 2 NJ 270 NJ
preplace netloc PS_cfg_data 1 0 2 10J 1250 320
preplace netloc PS_data_transport_status 1 2 2 710 920 1190J
preplace netloc axis_red_pitaya_adc_0_adc_clk1 1 0 3 10 1000 310 670 650J
preplace netloc cfg_to_transport_dfreq_ci_data 1 2 1 660 390n
preplace netloc cfg_to_transport_dfreq_cp_data 1 2 1 700 170n
preplace netloc cfg_to_transport_dfreq_lower_data 1 2 1 630 750n
preplace netloc cfg_to_transport_dfreq_upper_data 1 2 1 690 780n
preplace netloc cfg_to_transport_tau_dfreq_data 1 2 1 680 510n
preplace netloc const_zero_32b_dout 1 2 1 710 50n
preplace netloc gpio_io_6_x13_1 1 3 1 1170J 730n
preplace netloc xlconstant_0_dout 1 2 1 690J 610n
preplace netloc xlconstant_1_dout 1 1 1 330J 1050n
preplace netloc xlslice_0_Dout 1 2 1 640J 270n
preplace netloc Conn1 1 0 2 NJ 980 300J
preplace netloc Conn2 1 3 1 1180 550n
preplace netloc axis_ctrlsrc_select_0_M_AXIS 1 2 1 670 620n
preplace netloc axis_ctrlsrc_select_0_M_AXIS_FLOAT 1 0 3 20 1240 NJ 1240 630
preplace netloc controller_pi_dfreq_M_AXIS_CONTROL 1 3 1 1170J 580n
preplace netloc controller_pi_dfreq_M_AXIS_CONTROL2 1 3 1 1190J 610n
preplace netloc floating_point_log_M_AXIS_RESULT 1 1 1 300 1010n
levelinfo -pg 1 -10 160 480 940 1210
pagesize -pg 1 -db -bbox -sgen -150 -10 1440 1260
"
}

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: controller_dfreq
proc create_hier_cell_controller_dfreq { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_controller_dfreq() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL2

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS


  # Create pins
  create_bd_pin -dir I -from 31 -to 0 S_AXIS_reset_tdata
  create_bd_pin -dir I -type clk a_clk
  create_bd_pin -dir I -from 1023 -to 0 cfg
  create_bd_pin -dir I -from 1023 -to 0 cfg1
  create_bd_pin -dir I control_hold
  create_bd_pin -dir O enable
  create_bd_pin -dir O -from 31 -to 0 mon_control

  # Create instance: cfg_select_dfreq_control, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_dfreq_control
  if { [catch {set cfg_select_dfreq_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_dfreq_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_SWBIT {8} \
    CONFIG.SRC_ADDR {3} \
  ] $cfg_select_dfreq_control


  # Create instance: xlconstant_0, and set properties
  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]

  # Create instance: cfg_to_transport_dfreq_ci, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_dfreq_ci
  if { [catch {set cfg_to_transport_dfreq_ci [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_dfreq_ci eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {2} \
  ] $cfg_to_transport_dfreq_ci


  # Create instance: cfg_to_transport_dfreq_cp, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_dfreq_cp
  if { [catch {set cfg_to_transport_dfreq_cp [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_dfreq_cp eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {1} \
  ] $cfg_to_transport_dfreq_cp


  # Create instance: cfg_to_transport_dfreq_lower, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_dfreq_lower
  if { [catch {set cfg_to_transport_dfreq_lower [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_dfreq_lower eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {5} \
  ] $cfg_to_transport_dfreq_lower


  # Create instance: cfg_to_transport_dfreq_set, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_dfreq_set
  if { [catch {set cfg_to_transport_dfreq_set [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_dfreq_set eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {0} \
  ] $cfg_to_transport_dfreq_set


  # Create instance: cfg_to_transport_dfreq_upper, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_dfreq_upper
  if { [catch {set cfg_to_transport_dfreq_upper [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_dfreq_upper eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.SRC_ADDR {3} \
  ] $cfg_to_transport_dfreq_upper


  # Create instance: controller_pi_dfreq, and set properties
  set block_name controller_pi
  set block_cell_name controller_pi_dfreq
  if { [catch {set controller_pi_dfreq [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $controller_pi_dfreq eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CONTROL_W {32} \
    CONFIG.IN_Q {24} \
    CONFIG.IN_W {25} \
    CONFIG.M_AXIS_CONTROL2_TDATA_WIDTH {32} \
    CONFIG.M_AXIS_CONTROL_TDATA_WIDTH {32} \
    CONFIG.USE_RESET_DATA_INPUT {0} \
  ] $controller_pi_dfreq


  # Create interface connections
  connect_bd_intf_net -intf_net PS_data_transport_M_AXIS_DFREQ_DEC2 [get_bd_intf_pins S_AXIS] [get_bd_intf_pins controller_pi_dfreq/S_AXIS]
  connect_bd_intf_net -intf_net controller_pi_dfreq_M_AXIS_CONTROL [get_bd_intf_pins M_AXIS_CONTROL] [get_bd_intf_pins controller_pi_dfreq/M_AXIS_CONTROL]
  connect_bd_intf_net -intf_net controller_pi_dfreq_M_AXIS_CONTROL2 [get_bd_intf_pins M_AXIS_CONTROL2] [get_bd_intf_pins controller_pi_dfreq/M_AXIS_CONTROL2]

  # Create port connections
  connect_bd_net -net PS_Dout [get_bd_pins cfg] [get_bd_pins cfg_to_transport_dfreq_ci/cfg] [get_bd_pins cfg_to_transport_dfreq_cp/cfg] [get_bd_pins cfg_to_transport_dfreq_lower/cfg] [get_bd_pins cfg_to_transport_dfreq_set/cfg] [get_bd_pins cfg_to_transport_dfreq_upper/cfg]
  connect_bd_net -net PS_cfg_data [get_bd_pins cfg1] [get_bd_pins cfg_select_dfreq_control/cfg]
  connect_bd_net -net PS_data_transport_dout [get_bd_pins S_AXIS_reset_tdata] [get_bd_pins controller_pi_dfreq/S_AXIS_reset_tdata]
  connect_bd_net -net PS_data_transport_dout1 [get_bd_pins control_hold] [get_bd_pins controller_pi_dfreq/control_hold]
  connect_bd_net -net PS_data_transport_status [get_bd_pins cfg_select_dfreq_control/status] [get_bd_pins enable] [get_bd_pins controller_pi_dfreq/enable]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk1 [get_bd_pins a_clk] [get_bd_pins cfg_to_transport_dfreq_ci/a_clk] [get_bd_pins cfg_to_transport_dfreq_cp/a_clk] [get_bd_pins cfg_to_transport_dfreq_lower/a_clk] [get_bd_pins cfg_to_transport_dfreq_set/a_clk] [get_bd_pins cfg_to_transport_dfreq_upper/a_clk] [get_bd_pins controller_pi_dfreq/aclk]
  connect_bd_net -net cfg_to_transport_dfreq_ci_data [get_bd_pins cfg_to_transport_dfreq_ci/data] [get_bd_pins controller_pi_dfreq/ci]
  connect_bd_net -net cfg_to_transport_dfreq_cp_data [get_bd_pins cfg_to_transport_dfreq_cp/data] [get_bd_pins controller_pi_dfreq/cp]
  connect_bd_net -net cfg_to_transport_dfreq_lower_data [get_bd_pins cfg_to_transport_dfreq_lower/data] [get_bd_pins controller_pi_dfreq/limit_lower]
  connect_bd_net -net cfg_to_transport_dfreq_upper_data [get_bd_pins cfg_to_transport_dfreq_upper/data] [get_bd_pins controller_pi_dfreq/limit_upper]
  connect_bd_net -net cfg_to_transport_tau_dfreq_data [get_bd_pins cfg_to_transport_dfreq_set/data] [get_bd_pins controller_pi_dfreq/setpoint]
  connect_bd_net -net gpio_io_6_x13_1 [get_bd_pins controller_pi_dfreq/mon_control] [get_bd_pins mon_control]
  connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins controller_pi_dfreq/S_AXIS_reset_tvalid]

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: PulseFormer
proc create_hier_cell_PulseFormer { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_PulseFormer() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS


  # Create pins
  create_bd_pin -dir I -type clk a_clk
  create_bd_pin -dir I -from 1023 -to 0 cfg2
  create_bd_pin -dir I -from 2 -to 0 zero_spcp

  # Create instance: PulseForm_0, and set properties
  set block_name PulseForm
  set block_cell_name PulseForm_0
  if { [catch {set PulseForm_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $PulseForm_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: cfg2_to_pulse_12_delay, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg2_to_pulse_12_delay
  if { [catch {set cfg2_to_pulse_12_delay [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg2_to_pulse_12_delay eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {0} \
    CONFIG.SRC_BITS {32} \
  ] $cfg2_to_pulse_12_delay


  # Create instance: cfg2_to_pulse_12_width_height_array, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg2_to_pulse_12_width_height_array
  if { [catch {set cfg2_to_pulse_12_width_height_array [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg2_to_pulse_12_width_height_array eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {448} \
    CONFIG.MAXIS_TDATA_WIDTH {448} \
    CONFIG.SRC_ADDR {1} \
    CONFIG.SRC_BITS {448} \
  ] $cfg2_to_pulse_12_width_height_array


  # Create interface connections
  connect_bd_intf_net -intf_net PulseForm_0_M_AXIS [get_bd_intf_pins M_AXIS] [get_bd_intf_pins PulseForm_0/M_AXIS]

  # Create port connections
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk [get_bd_pins a_clk] [get_bd_pins PulseForm_0/a_clk] [get_bd_pins cfg2_to_pulse_12_delay/a_clk] [get_bd_pins cfg2_to_pulse_12_width_height_array/a_clk]
  connect_bd_net -net cfg2_1 [get_bd_pins cfg2] [get_bd_pins cfg2_to_pulse_12_delay/cfg] [get_bd_pins cfg2_to_pulse_12_width_height_array/cfg]
  connect_bd_net -net cfg2_to_pulse_12_width_height_array_data [get_bd_pins cfg2_to_pulse_12_width_height_array/data] [get_bd_pins PulseForm_0/pulse_12_width_height_array]
  connect_bd_net -net cfg2_to_pulse_delay1_data [get_bd_pins cfg2_to_pulse_12_delay/data] [get_bd_pins PulseForm_0/pulse_12_delay]
  connect_bd_net -net zero_spcp_1 [get_bd_pins zero_spcp] [get_bd_pins PulseForm_0/zero_spcp]

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: PS_Phase_Controller
proc create_hier_cell_PS_Phase_Controller { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_PS_Phase_Controller() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL2

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL3

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_PASS

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_PASS2

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_AMPL


  # Create pins
  create_bd_pin -dir I -type clk aclk
  create_bd_pin -dir I -from 1023 -to 0 cfg
  create_bd_pin -dir I -from 1023 -to 0 cfg1
  create_bd_pin -dir O -from 47 -to 0 data_lower
  create_bd_pin -dir I enable
  create_bd_pin -dir O -from 31 -to 0 mon_control
  create_bd_pin -dir O -from 31 -to 0 mon_control_B
  create_bd_pin -dir O -from 31 -to 0 mon_control_lower32
  create_bd_pin -dir O -from 31 -to 0 mon_error
  create_bd_pin -dir O -from 31 -to 0 mon_signal
  create_bd_pin -dir O status_max
  create_bd_pin -dir O status_min

  # Create instance: amplitude_good_check, and set properties
  set block_name amplitude_good
  set block_cell_name amplitude_good_check
  if { [catch {set amplitude_good_check [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $amplitude_good_check eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.AXIS_TDATA_WIDTH {24} $amplitude_good_check


  # Create instance: cfg_select_phase_unwrapping, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_phase_unwrapping
  if { [catch {set cfg_select_phase_unwrapping [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_phase_unwrapping eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_SWBIT {2} \
    CONFIG.SRC_ADDR {3} \
  ] $cfg_select_phase_unwrapping


  # Create instance: phase_unwrap, and set properties
  set block_name phase_unwrap
  set block_cell_name phase_unwrap
  if { [catch {set phase_unwrap [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $phase_unwrap eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.PHU_DISABLE {1} $phase_unwrap


  # Create instance: cfg_to_am_threashold, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_am_threashold
  if { [catch {set cfg_to_am_threashold [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_am_threashold eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_WIDTH {1024} \
    CONFIG.DST_WIDTH {24} \
    CONFIG.MAXIS_TDATA_WIDTH {24} \
    CONFIG.SRC_ADDR {8} \
  ] $cfg_to_am_threashold


  # Create instance: cfg_to_axis_PhaseInc, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_PhaseInc
  if { [catch {set cfg_to_axis_PhaseInc [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_PhaseInc eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {48} \
    CONFIG.MAXIS_TDATA_WIDTH {48} \
    CONFIG.SRC_BITS {64} \
  ] $cfg_to_axis_PhaseInc


  # Create instance: cfg_to_ph_ci, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_ph_ci
  if { [catch {set cfg_to_ph_ci [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_ph_ci eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {12} \
    CONFIG.SRC_BITS {32} \
  ] $cfg_to_ph_ci


  # Create instance: cfg_to_ph_cp, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_ph_cp
  if { [catch {set cfg_to_ph_cp [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_ph_cp eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {11} \
    CONFIG.SRC_BITS {32} \
  ] $cfg_to_ph_cp


  # Create instance: cfg_to_ph_lower, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_ph_lower
  if { [catch {set cfg_to_ph_lower [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_ph_lower eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {48} \
    CONFIG.MAXIS_TDATA_WIDTH {48} \
    CONFIG.SRC_ADDR {15} \
    CONFIG.SRC_BITS {64} \
  ] $cfg_to_ph_lower


  # Create instance: cfg_to_ph_setpoint, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_ph_setpoint
  if { [catch {set cfg_to_ph_setpoint [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_ph_setpoint eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {10} \
  ] $cfg_to_ph_setpoint


  # Create instance: cfg_to_ph_upper, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_ph_upper
  if { [catch {set cfg_to_ph_upper [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_ph_upper eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {48} \
    CONFIG.MAXIS_TDATA_WIDTH {48} \
    CONFIG.SRC_ADDR {13} \
    CONFIG.SRC_BITS {64} \
  ] $cfg_to_ph_upper


  # Create instance: phase_controller, and set properties
  set block_name controller_pi
  set block_cell_name phase_controller
  if { [catch {set phase_controller [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $phase_controller eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.AMCONTROL_ALLOW_NEG_SPECIAL {0} \
    CONFIG.AUTO_RESET_AT_LIMIT {0} \
    CONFIG.AXIS_TDATA_WIDTH {32} \
    CONFIG.CONTROL2_W {44} \
    CONFIG.IN_Q {21} \
    CONFIG.IN_W {24} \
    CONFIG.M_AXIS_CONTROL2_TDATA_WIDTH {48} \
    CONFIG.M_AXIS_CONTROL_TDATA_WIDTH {48} \
    CONFIG.RDECI {8} \
  ] $phase_controller


  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M_AXIS_CONTROL2] [get_bd_intf_pins phase_controller/M_AXIS_CONTROL2]
  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M_AXIS_PASS2] [get_bd_intf_pins phase_controller/M_AXIS_PASS2]
  connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins M_AXIS_CONTROL3] [get_bd_intf_pins phase_controller/M_AXIS_CONTROL3]
  connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins S_AXIS_AMPL] [get_bd_intf_pins amplitude_good_check/S_AXIS_AM]
  connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins S_AXIS] [get_bd_intf_pins phase_unwrap/S_AXIS]
  connect_bd_intf_net -intf_net cfg_to_axis_PhaseInc_M_AXIS [get_bd_intf_pins cfg_to_axis_PhaseInc/M_AXIS] [get_bd_intf_pins phase_controller/S_AXIS_reset]
  connect_bd_intf_net -intf_net cfg_to_transport_dfreq_ci_M_AXIS [get_bd_intf_pins amplitude_good_check/S_AXIS_AMTHR] [get_bd_intf_pins cfg_to_am_threashold/M_AXIS]
  connect_bd_intf_net -intf_net phase_controller_M_AXIS_CONTROL [get_bd_intf_pins M_AXIS_CONTROL] [get_bd_intf_pins phase_controller/M_AXIS_CONTROL]
  connect_bd_intf_net -intf_net phase_controller_M_AXIS_PASS [get_bd_intf_pins M_AXIS_PASS] [get_bd_intf_pins phase_controller/M_AXIS_PASS]
  connect_bd_intf_net -intf_net phase_unwrap_0_M_AXIS [get_bd_intf_pins phase_controller/S_AXIS] [get_bd_intf_pins phase_unwrap/M_AXIS]

  # Create port connections
  connect_bd_net -net Net [get_bd_pins cfg] [get_bd_pins cfg_select_phase_unwrapping/cfg] [get_bd_pins cfg_to_axis_PhaseInc/cfg] [get_bd_pins cfg_to_ph_ci/cfg] [get_bd_pins cfg_to_ph_cp/cfg] [get_bd_pins cfg_to_ph_lower/cfg] [get_bd_pins cfg_to_ph_setpoint/cfg] [get_bd_pins cfg_to_ph_upper/cfg]
  connect_bd_net -net amplitude_good_0_out [get_bd_pins amplitude_good_check/hold] [get_bd_pins phase_controller/control_hold]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk [get_bd_pins aclk] [get_bd_pins amplitude_good_check/aclk] [get_bd_pins phase_unwrap/aclk] [get_bd_pins cfg_to_am_threashold/a_clk] [get_bd_pins cfg_to_axis_PhaseInc/a_clk] [get_bd_pins cfg_to_ph_ci/a_clk] [get_bd_pins cfg_to_ph_cp/a_clk] [get_bd_pins cfg_to_ph_lower/a_clk] [get_bd_pins cfg_to_ph_setpoint/a_clk] [get_bd_pins cfg_to_ph_upper/a_clk] [get_bd_pins phase_controller/aclk]
  connect_bd_net -net cfg1_1 [get_bd_pins cfg1] [get_bd_pins cfg_to_am_threashold/cfg]
  connect_bd_net -net cfg_select_phase_unwrapping_status [get_bd_pins cfg_select_phase_unwrapping/status] [get_bd_pins phase_unwrap/enable]
  connect_bd_net -net cfg_to_am_setpoint_data [get_bd_pins cfg_to_ph_setpoint/data] [get_bd_pins phase_controller/setpoint]
  connect_bd_net -net cfg_to_ph_ci_data [get_bd_pins cfg_to_ph_ci/data] [get_bd_pins phase_controller/ci]
  connect_bd_net -net cfg_to_ph_cp_data [get_bd_pins cfg_to_ph_cp/data] [get_bd_pins phase_controller/cp]
  connect_bd_net -net cfg_to_ph_lower_data [get_bd_pins cfg_to_ph_upper/data] [get_bd_pins phase_controller/limit_upper]
  connect_bd_net -net cfg_to_ph_upper_data [get_bd_pins cfg_to_ph_lower/data] [get_bd_pins data_lower] [get_bd_pins phase_controller/limit_lower]
  connect_bd_net -net enable_1 [get_bd_pins enable] [get_bd_pins phase_controller/enable]
  connect_bd_net -net phase_controller_mon_control [get_bd_pins phase_controller/mon_control] [get_bd_pins mon_control]
  connect_bd_net -net phase_controller_mon_control_B [get_bd_pins phase_controller/mon_control_B] [get_bd_pins mon_control_B]
  connect_bd_net -net phase_controller_mon_control_lower32 [get_bd_pins phase_controller/mon_control_lower32] [get_bd_pins mon_control_lower32]
  connect_bd_net -net phase_controller_mon_error [get_bd_pins phase_controller/mon_error] [get_bd_pins mon_error]
  connect_bd_net -net phase_controller_mon_signal [get_bd_pins phase_controller/mon_signal] [get_bd_pins mon_signal]
  connect_bd_net -net phase_controller_status_max [get_bd_pins phase_controller/status_max] [get_bd_pins status_max]
  connect_bd_net -net phase_controller_status_min [get_bd_pins phase_controller/status_min] [get_bd_pins status_min]

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: PS_Amplitude_Controller
proc create_hier_cell_PS_Amplitude_Controller { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_PS_Amplitude_Controller() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL2

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_PASS

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_PASS2

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS


  # Create pins
  create_bd_pin -dir I -type clk aclk
  create_bd_pin -dir I -from 1023 -to 0 cfg
  create_bd_pin -dir I enable
  create_bd_pin -dir O -from 31 -to 0 mon_control
  create_bd_pin -dir O -from 31 -to 0 mon_control_lower32
  create_bd_pin -dir O -from 31 -to 0 mon_signal
  create_bd_pin -dir O status_max
  create_bd_pin -dir O status_min

  # Create instance: const_zero, and set properties
  set const_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_zero ]
  set_property CONFIG.CONST_VAL {0} $const_zero


  # Create instance: cfg_to_am_ci, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_am_ci
  if { [catch {set cfg_to_am_ci [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_am_ci eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {22} \
  ] $cfg_to_am_ci


  # Create instance: cfg_to_am_cp, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_am_cp
  if { [catch {set cfg_to_am_cp [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_am_cp eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {21} \
  ] $cfg_to_am_cp


  # Create instance: cfg_to_am_lower, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_am_lower
  if { [catch {set cfg_to_am_lower [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_am_lower eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {16} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {25} \
  ] $cfg_to_am_lower


  # Create instance: cfg_to_am_setpoint, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_am_setpoint
  if { [catch {set cfg_to_am_setpoint [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_am_setpoint eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {24} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {20} \
  ] $cfg_to_am_setpoint


  # Create instance: cfg_to_am_upper, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_am_upper
  if { [catch {set cfg_to_am_upper [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_am_upper eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {16} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {23} \
  ] $cfg_to_am_upper


  # Create instance: cfg_to_axis_volume, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_volume
  if { [catch {set cfg_to_axis_volume [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_volume eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {16} \
    CONFIG.MAXIS_TDATA_WIDTH {16} \
    CONFIG.SRC_ADDR {2} \
  ] $cfg_to_axis_volume


  # Create instance: amplitude_controller, and set properties
  set block_name controller_pi
  set block_cell_name amplitude_controller
  if { [catch {set amplitude_controller [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $amplitude_controller eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.AMCONTROL_ALLOW_NEG_SPECIAL {1} \
    CONFIG.AXIS_TDATA_WIDTH {24} \
    CONFIG.CONTROL2_W {32} \
    CONFIG.CONTROL_Q {15} \
    CONFIG.CONTROL_W {16} \
    CONFIG.IN_Q {23} \
    CONFIG.IN_W {24} \
    CONFIG.M_AXIS_CONTROL2_TDATA_WIDTH {32} \
    CONFIG.M_AXIS_CONTROL_TDATA_WIDTH {16} \
  ] $amplitude_controller


  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M_AXIS_CONTROL2] [get_bd_intf_pins amplitude_controller/M_AXIS_CONTROL2]
  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M_AXIS_PASS2] [get_bd_intf_pins amplitude_controller/M_AXIS_PASS2]
  connect_bd_intf_net -intf_net amplitude_controller_M_AXIS_CONTROL [get_bd_intf_pins M_AXIS_CONTROL] [get_bd_intf_pins amplitude_controller/M_AXIS_CONTROL]
  connect_bd_intf_net -intf_net amplitude_controller_M_AXIS_PASS [get_bd_intf_pins M_AXIS_PASS] [get_bd_intf_pins amplitude_controller/M_AXIS_PASS]
  connect_bd_intf_net -intf_net cfg_to_axis_volume_M_AXIS [get_bd_intf_pins amplitude_controller/S_AXIS_reset] [get_bd_intf_pins cfg_to_axis_volume/M_AXIS]
  connect_bd_intf_net -intf_net cordic_sqrt_M_AXIS_DOUT [get_bd_intf_pins S_AXIS] [get_bd_intf_pins amplitude_controller/S_AXIS]

  # Create port connections
  connect_bd_net -net PS_cfg_data [get_bd_pins cfg] [get_bd_pins cfg_to_am_ci/cfg] [get_bd_pins cfg_to_am_cp/cfg] [get_bd_pins cfg_to_am_lower/cfg] [get_bd_pins cfg_to_am_setpoint/cfg] [get_bd_pins cfg_to_am_upper/cfg] [get_bd_pins cfg_to_axis_volume/cfg]
  connect_bd_net -net amplitude_controller_mon_control [get_bd_pins amplitude_controller/mon_control] [get_bd_pins mon_control]
  connect_bd_net -net amplitude_controller_mon_control_lower32 [get_bd_pins amplitude_controller/mon_control_lower32] [get_bd_pins mon_control_lower32]
  connect_bd_net -net amplitude_controller_mon_signal [get_bd_pins amplitude_controller/mon_signal] [get_bd_pins mon_signal]
  connect_bd_net -net amplitude_controller_status_max [get_bd_pins amplitude_controller/status_max] [get_bd_pins status_max]
  connect_bd_net -net amplitude_controller_status_min [get_bd_pins amplitude_controller/status_min] [get_bd_pins status_min]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk [get_bd_pins aclk] [get_bd_pins cfg_to_am_ci/a_clk] [get_bd_pins cfg_to_am_cp/a_clk] [get_bd_pins cfg_to_am_lower/a_clk] [get_bd_pins cfg_to_am_setpoint/a_clk] [get_bd_pins cfg_to_am_upper/a_clk] [get_bd_pins cfg_to_axis_volume/a_clk] [get_bd_pins amplitude_controller/aclk]
  connect_bd_net -net cfg_to_am_ci_data [get_bd_pins cfg_to_am_ci/data] [get_bd_pins amplitude_controller/ci]
  connect_bd_net -net cfg_to_am_cp_data [get_bd_pins cfg_to_am_cp/data] [get_bd_pins amplitude_controller/cp]
  connect_bd_net -net cfg_to_am_lower_data [get_bd_pins cfg_to_am_lower/data] [get_bd_pins amplitude_controller/limit_lower]
  connect_bd_net -net cfg_to_am_setpoint_data [get_bd_pins cfg_to_am_setpoint/data] [get_bd_pins amplitude_controller/setpoint]
  connect_bd_net -net cfg_to_am_upper_data [get_bd_pins cfg_to_am_upper/data] [get_bd_pins amplitude_controller/limit_upper]
  connect_bd_net -net enable_1 [get_bd_pins enable] [get_bd_pins amplitude_controller/enable]
  connect_bd_net -net xlconstant_0_dout [get_bd_pins const_zero/dout] [get_bd_pins amplitude_controller/control_hold]

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: SPM_control_logic
proc create_hier_cell_SPM_control_logic { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_SPM_control_logic() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:bram_rtl:1.0 BRAM_PORTB

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_ch9s

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_chAs

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_chBs

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_chCs

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_chEs

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_ch5s


  # Create pins
  create_bd_pin -dir I -type clk a_clk
  create_bd_pin -dir I -from 1023 -to 0 cfg3
  create_bd_pin -dir IO -from 7 -to 0 exp_p_io
  create_bd_pin -dir I -from 1023 -to 0 cfg1
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_PASS_tdata
  create_bd_pin -dir O gvp_finished
  create_bd_pin -dir O enable
  create_bd_pin -dir O -from 31 -to 0 data
  create_bd_pin -dir O gvp_hold
  create_bd_pin -dir O -from 31 -to 0 dbg_i
  create_bd_pin -dir O -from 31 -to 0 section
  create_bd_pin -dir O -from 31 -to 0 dbg_status
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_ZSMON_tdata
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_X0MON_tdata
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_XSMON_tdata
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_YSMON_tdata
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_Z0MON_tdata
  create_bd_pin -dir IO -from 7 -to 0 exp_n_io
  create_bd_pin -dir O -from 31 -to 0 mon3
  create_bd_pin -dir O -from 31 -to 0 mon0
  create_bd_pin -dir O -from 31 -to 0 mon1
  create_bd_pin -dir O -from 31 -to 0 mon2
  create_bd_pin -dir O -from 15 -to 0 last_write_addr
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_Z_tdata

  # Create instance: xlslice_cfg_dac_mode, and set properties
  set xlslice_cfg_dac_mode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_cfg_dac_mode ]
  set_property -dict [list \
    CONFIG.DIN_FROM {3} \
    CONFIG.DIN_TO {3} \
  ] $xlslice_cfg_dac_mode


  # Create instance: xlslice_cfg_dac_send, and set properties
  set xlslice_cfg_dac_send [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_cfg_dac_send ]
  set_property -dict [list \
    CONFIG.DIN_FROM {4} \
    CONFIG.DIN_TO {4} \
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_cfg_dac_send


  # Create instance: xlslice_gvp_reset, and set properties
  set xlslice_gvp_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_gvp_reset ]
  set_property -dict [list \
    CONFIG.DIN_FROM {0} \
    CONFIG.DIN_TO {0} \
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_gvp_reset


  # Create instance: xlslice_gvp_setvec, and set properties
  set xlslice_gvp_setvec [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_gvp_setvec ]
  set_property -dict [list \
    CONFIG.DIN_FROM {1} \
    CONFIG.DIN_TO {1} \
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_gvp_setvec


  # Create instance: xlslice_cfg_dac_axis, and set properties
  set xlslice_cfg_dac_axis [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_cfg_dac_axis ]
  set_property CONFIG.DIN_FROM {2} $xlslice_cfg_dac_axis


  # Create instance: controller_zservo
  create_hier_cell_controller_zservo $hier_obj controller_zservo

  # Create instance: cfg3_to_cfg_dac_axis, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_cfg_dac_axis
  if { [catch {set cfg3_to_cfg_dac_axis [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_cfg_dac_axis eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {17} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_cfg_dac_axis


  # Create instance: cfg3_to_cfg_dac_control, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_cfg_dac_control
  if { [catch {set cfg3_to_cfg_dac_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_cfg_dac_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {18} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_cfg_dac_control


  # Create instance: cfg3_to_gvp_program_vector, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_gvp_program_vector
  if { [catch {set cfg3_to_gvp_program_vector [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_gvp_program_vector eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {512} \
    CONFIG.MAXIS_TDATA_WIDTH {512} \
    CONFIG.SRC_ADDR {1} \
    CONFIG.SRC_BITS {512} \
  ] $cfg3_to_gvp_program_vector


  # Create instance: cfg3_to_gvp_setvector, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_gvp_setvector
  if { [catch {set cfg3_to_gvp_setvector [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_gvp_setvector eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {0} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_gvp_setvector


  # Create instance: cfg3_to_rotmxx, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_rotmxx
  if { [catch {set cfg3_to_rotmxx [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_rotmxx eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {20} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_rotmxx


  # Create instance: cfg3_to_rotmxy, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_rotmxy
  if { [catch {set cfg3_to_rotmxy [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_rotmxy eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {21} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_rotmxy


  # Create instance: cfg3_to_slope_x, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_slope_x
  if { [catch {set cfg3_to_slope_x [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_slope_x eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {22} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_slope_x


  # Create instance: cfg3_to_slope_y, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_slope_y
  if { [catch {set cfg3_to_slope_y [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_slope_y eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {23} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_slope_y


  # Create instance: cfg3_to_x0, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_x0
  if { [catch {set cfg3_to_x0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_x0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {24} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_x0


  # Create instance: cfg3_to_y0, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_y0
  if { [catch {set cfg3_to_y0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_y0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {25} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_y0


  # Create instance: cfg3_to_z0, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_z0
  if { [catch {set cfg3_to_z0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_z0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {26} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_z0


  # Create instance: xlslice_gvp_pause, and set properties
  set xlslice_gvp_pause [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_gvp_pause ]
  set_property -dict [list \
    CONFIG.DIN_FROM {2} \
    CONFIG.DIN_TO {2} \
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_gvp_pause


  # Create instance: cfg3_to_bias, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_bias
  if { [catch {set cfg3_to_bias [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_bias eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {27} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_bias


  # Create instance: cfg3_to_xy_move_step, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_xy_move_step
  if { [catch {set cfg3_to_xy_move_step [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_xy_move_step eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {28} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_xy_move_step


  # Create instance: cfg3_to_z_move_step, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg3_to_z_move_step
  if { [catch {set cfg3_to_z_move_step [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg3_to_z_move_step eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {29} \
    CONFIG.SRC_BITS {32} \
  ] $cfg3_to_z_move_step


  # Create instance: xlslice_gvp_reset_options, and set properties
  set xlslice_gvp_reset_options [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_gvp_reset_options ]
  set_property -dict [list \
    CONFIG.DIN_FROM {31} \
    CONFIG.DIN_TO {16} \
    CONFIG.DOUT_WIDTH {16} \
  ] $xlslice_gvp_reset_options


  # Create instance: AD5791_io_connect_0, and set properties
  set block_name AD5791_io_connect
  set block_cell_name AD5791_io_connect_0
  if { [catch {set AD5791_io_connect_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $AD5791_io_connect_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_AD5791_0, and set properties
  set block_name axis_AD5791
  set block_cell_name axis_AD5791_0
  if { [catch {set axis_AD5791_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_AD5791_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: blk_mem_gen_spmc, and set properties
  set blk_mem_gen_spmc [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_spmc ]
  set_property -dict [list \
    CONFIG.Algorithm {Minimum_Area} \
    CONFIG.Enable_32bit_Address {false} \
    CONFIG.Enable_A {Always_Enabled} \
    CONFIG.Enable_B {Use_ENB_Pin} \
    CONFIG.Fill_Remaining_Memory_Locations {true} \
    CONFIG.Load_Init_File {false} \
    CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
    CONFIG.Operating_Mode_A {WRITE_FIRST} \
    CONFIG.Port_B_Clock {100} \
    CONFIG.Port_B_Enable_Rate {100} \
    CONFIG.Read_Width_B {32} \
    CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \
    CONFIG.Remaining_Memory_Locations {cccccccc} \
    CONFIG.Use_Byte_Write_Enable {false} \
    CONFIG.Use_RSTB_Pin {false} \
    CONFIG.Write_Depth_A {16384} \
    CONFIG.Write_Width_A {32} \
    CONFIG.Write_Width_B {32} \
    CONFIG.use_bram_block {Stand_Alone} \
  ] $blk_mem_gen_spmc


  # Create instance: gvp_main, and set properties
  set block_name gvp
  set block_cell_name gvp_main
  if { [catch {set gvp_main [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $gvp_main eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_bram_stream_srcs, and set properties
  set block_name axis_bram_stream_srcs
  set block_cell_name axis_bram_stream_srcs
  if { [catch {set axis_bram_stream_srcs [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_bram_stream_srcs eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.BRAM_ADDR_WIDTH {14} $axis_bram_stream_srcs


  # Create instance: axis_spm_control, and set properties
  set block_name axis_spm_control
  set block_cell_name axis_spm_control
  if { [catch {set axis_spm_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_spm_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_splitter_U, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_U
  if { [catch {set axis_splitter_U [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_U eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_splitter_Z, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_Z
  if { [catch {set axis_splitter_Z [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_Z eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_splitter_Y, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_Y
  if { [catch {set axis_splitter_Y [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_Y eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_splitter_X, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_X
  if { [catch {set axis_splitter_X [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_X eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_splitter_CH0_S16_to_S32, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_CH0_S16_to_S32
  if { [catch {set axis_splitter_CH0_S16_to_S32 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_CH0_S16_to_S32 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.SAXIS_TDATA_WIDTH {16} $axis_splitter_CH0_S16_to_S32


  # Create instance: axis_splitter_ZControlSignalPass, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_ZControlSignalPass
  if { [catch {set axis_splitter_ZControlSignalPass [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_ZControlSignalPass eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create interface connections
  connect_bd_intf_net -intf_net BRAM_PORTB_1 [get_bd_intf_pins BRAM_PORTB] [get_bd_intf_pins blk_mem_gen_spmc/BRAM_PORTB]
  connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins S_AXIS] [get_bd_intf_pins controller_zservo/S_AXIS]
  connect_bd_intf_net -intf_net S_AXIS_ch5s_1 [get_bd_intf_pins S_AXIS_ch5s] [get_bd_intf_pins axis_splitter_CH0_S16_to_S32/S_AXIS]
  connect_bd_intf_net -intf_net S_AXIS_ch9s_1 [get_bd_intf_pins S_AXIS_ch9s] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_ch9s]
  connect_bd_intf_net -intf_net S_AXIS_chAs_1 [get_bd_intf_pins S_AXIS_chAs] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_chAs]
  connect_bd_intf_net -intf_net S_AXIS_chBs_1 [get_bd_intf_pins S_AXIS_chBs] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_chBs]
  connect_bd_intf_net -intf_net S_AXIS_chCs_1 [get_bd_intf_pins S_AXIS_chCs] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_chCs]
  connect_bd_intf_net -intf_net S_AXIS_chEs_1 [get_bd_intf_pins S_AXIS_chEs] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_chEs]
  connect_bd_intf_net -intf_net axis_splitter_0_M_AXIS [get_bd_intf_pins axis_splitter_CH0_S16_to_S32/M_AXIS] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_ch5s]
  connect_bd_intf_net -intf_net axis_splitter_U_M_AXIS [get_bd_intf_pins axis_splitter_U/M_AXIS] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_ch4s]
  connect_bd_intf_net -intf_net axis_splitter_U_M_AXIS2 [get_bd_intf_pins axis_splitter_U/M_AXIS2] [get_bd_intf_pins axis_AD5791_0/S_AXIS4]
  connect_bd_intf_net -intf_net axis_splitter_X_M_AXIS [get_bd_intf_pins axis_splitter_X/M_AXIS] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_ch1s]
  connect_bd_intf_net -intf_net axis_splitter_X_M_AXIS2 [get_bd_intf_pins axis_splitter_X/M_AXIS2] [get_bd_intf_pins axis_spm_control/S_AXIS_Xs]
  connect_bd_intf_net -intf_net axis_splitter_Y_M_AXIS [get_bd_intf_pins axis_splitter_Y/M_AXIS] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_ch2s]
  connect_bd_intf_net -intf_net axis_splitter_Y_M_AXIS2 [get_bd_intf_pins axis_splitter_Y/M_AXIS2] [get_bd_intf_pins axis_spm_control/S_AXIS_Ys]
  connect_bd_intf_net -intf_net axis_splitter_ZControlSignalPass_M_AXIS [get_bd_intf_pins axis_splitter_ZControlSignalPass/M_AXIS] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_ch6s]
  connect_bd_intf_net -intf_net axis_splitter_Z_M_AXIS [get_bd_intf_pins axis_splitter_Z/M_AXIS] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_ch3s]
  connect_bd_intf_net -intf_net axis_splitter_Z_M_AXIS2 [get_bd_intf_pins axis_splitter_Z/M_AXIS2] [get_bd_intf_pins axis_AD5791_0/S_AXIS3]
  connect_bd_intf_net -intf_net axis_spm_control_0_M_AXIS1 [get_bd_intf_pins axis_spm_control/M_AXIS1] [get_bd_intf_pins axis_AD5791_0/S_AXIS1]
  connect_bd_intf_net -intf_net axis_spm_control_0_M_AXIS2 [get_bd_intf_pins axis_spm_control/M_AXIS2] [get_bd_intf_pins axis_AD5791_0/S_AXIS2]
  connect_bd_intf_net -intf_net axis_spm_control_M_AXIS3 [get_bd_intf_pins axis_spm_control/M_AXIS3] [get_bd_intf_pins axis_splitter_Z/S_AXIS]
  connect_bd_intf_net -intf_net axis_spm_control_M_AXIS4 [get_bd_intf_pins axis_spm_control/M_AXIS4] [get_bd_intf_pins axis_splitter_U/S_AXIS]
  connect_bd_intf_net -intf_net cfg3_to_cfg_dac_axis_M_AXIS [get_bd_intf_pins cfg3_to_cfg_dac_axis/M_AXIS] [get_bd_intf_pins axis_AD5791_0/S_AXISCFG]
  connect_bd_intf_net -intf_net controller_zservo_M_AXIS_CONTROL [get_bd_intf_pins controller_zservo/M_AXIS_CONTROL] [get_bd_intf_pins axis_spm_control/S_AXIS_Z]
  connect_bd_intf_net -intf_net controller_zservo_M_AXIS_PASS [get_bd_intf_pins controller_zservo/M_AXIS_PASS] [get_bd_intf_pins axis_splitter_ZControlSignalPass/S_AXIS]
  connect_bd_intf_net -intf_net gvp_main_M_AXIS_SRCS [get_bd_intf_pins gvp_main/M_AXIS_SRCS] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_srcs]
  connect_bd_intf_net -intf_net gvp_main_M_AXIS_U [get_bd_intf_pins gvp_main/M_AXIS_U] [get_bd_intf_pins axis_spm_control/S_AXIS_U]
  connect_bd_intf_net -intf_net gvp_main_M_AXIS_X [get_bd_intf_pins gvp_main/M_AXIS_X] [get_bd_intf_pins axis_splitter_X/S_AXIS]
  connect_bd_intf_net -intf_net gvp_main_M_AXIS_Y [get_bd_intf_pins gvp_main/M_AXIS_Y] [get_bd_intf_pins axis_splitter_Y/S_AXIS]
  connect_bd_intf_net -intf_net gvp_main_M_AXIS_Z [get_bd_intf_pins gvp_main/M_AXIS_Z] [get_bd_intf_pins axis_spm_control/S_AXIS_Zs]
  connect_bd_intf_net -intf_net gvp_main_M_AXIS_gvp_time [get_bd_intf_pins gvp_main/M_AXIS_gvp_time] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_gvp_time]
  connect_bd_intf_net -intf_net gvp_main_M_AXIS_index [get_bd_intf_pins gvp_main/M_AXIS_index] [get_bd_intf_pins axis_bram_stream_srcs/S_AXIS_index]

  # Create port connections
  connect_bd_net -net Net [get_bd_pins exp_n_io] [get_bd_pins AD5791_io_connect_0/exp_n_io]
  connect_bd_net -net Net1 -boundary_type lower [get_bd_pins exp_p_io]
  connect_bd_net -net PS_cfg_data_reg_3 [get_bd_pins cfg3] [get_bd_pins cfg3_to_cfg_dac_axis/cfg] [get_bd_pins cfg3_to_cfg_dac_control/cfg] [get_bd_pins cfg3_to_gvp_program_vector/cfg] [get_bd_pins cfg3_to_gvp_setvector/cfg] [get_bd_pins cfg3_to_rotmxx/cfg] [get_bd_pins cfg3_to_rotmxy/cfg] [get_bd_pins cfg3_to_slope_x/cfg] [get_bd_pins cfg3_to_slope_y/cfg] [get_bd_pins cfg3_to_x0/cfg] [get_bd_pins cfg3_to_y0/cfg] [get_bd_pins cfg3_to_z0/cfg] [get_bd_pins cfg3_to_bias/cfg] [get_bd_pins cfg3_to_xy_move_step/cfg] [get_bd_pins cfg3_to_z_move_step/cfg]
  connect_bd_net -net a_clk [get_bd_pins a_clk] [get_bd_pins controller_zservo/a_clk] [get_bd_pins cfg3_to_cfg_dac_axis/a_clk] [get_bd_pins cfg3_to_cfg_dac_control/a_clk] [get_bd_pins cfg3_to_gvp_program_vector/a_clk] [get_bd_pins cfg3_to_gvp_setvector/a_clk] [get_bd_pins cfg3_to_rotmxx/a_clk] [get_bd_pins cfg3_to_rotmxy/a_clk] [get_bd_pins cfg3_to_slope_x/a_clk] [get_bd_pins cfg3_to_slope_y/a_clk] [get_bd_pins cfg3_to_x0/a_clk] [get_bd_pins cfg3_to_y0/a_clk] [get_bd_pins cfg3_to_z0/a_clk] [get_bd_pins cfg3_to_bias/a_clk] [get_bd_pins cfg3_to_z_move_step/a_clk] [get_bd_pins cfg3_to_xy_move_step/a_clk] [get_bd_pins axis_AD5791_0/a_clk] [get_bd_pins gvp_main/a_clk] [get_bd_pins axis_bram_stream_srcs/a2_clk] [get_bd_pins axis_spm_control/a_clk] [get_bd_pins axis_splitter_U/a_clk] [get_bd_pins axis_splitter_Z/a_clk] [get_bd_pins axis_splitter_Y/a_clk] [get_bd_pins axis_splitter_X/a_clk] [get_bd_pins axis_splitter_CH0_S16_to_S32/a_clk] [get_bd_pins axis_splitter_ZControlSignalPass/a_clk]
  connect_bd_net -net axis_AD5791_0_mon0 [get_bd_pins axis_AD5791_0/mon0] [get_bd_pins mon0]
  connect_bd_net -net axis_AD5791_0_mon1 [get_bd_pins axis_AD5791_0/mon1] [get_bd_pins mon1]
  connect_bd_net -net axis_AD5791_0_mon2 [get_bd_pins axis_AD5791_0/mon2] [get_bd_pins mon2]
  connect_bd_net -net axis_AD5791_0_mon3 [get_bd_pins axis_AD5791_0/mon3] [get_bd_pins mon3]
  connect_bd_net -net axis_AD5791_0_wire_PMD_clk [get_bd_pins axis_AD5791_0/wire_PMD_clk] [get_bd_pins AD5791_io_connect_0/PMD_clk]
  connect_bd_net -net axis_AD5791_0_wire_PMD_dac [get_bd_pins axis_AD5791_0/wire_PMD_dac] [get_bd_pins AD5791_io_connect_0/PMD_dac]
  connect_bd_net -net axis_AD5791_0_wire_PMD_sync [get_bd_pins axis_AD5791_0/wire_PMD_sync] [get_bd_pins AD5791_io_connect_0/PMD_sync]
  connect_bd_net -net axis_bram_stream_srcs_0_BRAM_PORTA_addr [get_bd_pins axis_bram_stream_srcs/BRAM_PORTA_addr] [get_bd_pins blk_mem_gen_spmc/addra]
  connect_bd_net -net axis_bram_stream_srcs_0_BRAM_PORTA_clk [get_bd_pins axis_bram_stream_srcs/BRAM_PORTA_clk] [get_bd_pins blk_mem_gen_spmc/clka]
  connect_bd_net -net axis_bram_stream_srcs_0_BRAM_PORTA_din [get_bd_pins axis_bram_stream_srcs/BRAM_PORTA_din] [get_bd_pins blk_mem_gen_spmc/dina]
  connect_bd_net -net axis_bram_stream_srcs_0_BRAM_PORTA_we [get_bd_pins axis_bram_stream_srcs/BRAM_PORTA_we] [get_bd_pins blk_mem_gen_spmc/wea]
  connect_bd_net -net axis_bram_stream_srcs_last_write_addr [get_bd_pins axis_bram_stream_srcs/last_write_addr] [get_bd_pins last_write_addr]
  connect_bd_net -net axis_splitter_ZControlSignalPass_monitor [get_bd_pins axis_splitter_ZControlSignalPass/monitor] [get_bd_pins M_AXIS_PASS_tdata]
  connect_bd_net -net axis_splitter_Z_monitor [get_bd_pins axis_splitter_Z/monitor] [get_bd_pins M_AXIS_Z_tdata]
  connect_bd_net -net axis_spm_control_0_M_AXIS_X0MON_tdata [get_bd_pins axis_spm_control/M_AXIS_X0MON_tdata] [get_bd_pins M_AXIS_X0MON_tdata]
  connect_bd_net -net axis_spm_control_0_M_AXIS_XSMON_tdata [get_bd_pins axis_spm_control/M_AXIS_XSMON_tdata] [get_bd_pins M_AXIS_XSMON_tdata]
  connect_bd_net -net axis_spm_control_0_M_AXIS_YSMON_tdata [get_bd_pins axis_spm_control/M_AXIS_YSMON_tdata] [get_bd_pins M_AXIS_YSMON_tdata]
  connect_bd_net -net axis_spm_control_0_M_AXIS_Z0MON_tdata [get_bd_pins axis_spm_control/M_AXIS_Z0MON_tdata] [get_bd_pins M_AXIS_Z0MON_tdata]
  connect_bd_net -net axis_spm_control_0_M_AXIS_ZSMON_tdata [get_bd_pins axis_spm_control/M_AXIS_ZSMON_tdata] [get_bd_pins M_AXIS_ZSMON_tdata]
  connect_bd_net -net cfg1_1 [get_bd_pins cfg1] [get_bd_pins controller_zservo/cfg1]
  connect_bd_net -net cfg3_to_bias1_data [get_bd_pins cfg3_to_xy_move_step/data] [get_bd_pins axis_spm_control/xy_offset_step]
  connect_bd_net -net cfg3_to_bias2_data [get_bd_pins cfg3_to_z_move_step/data] [get_bd_pins axis_spm_control/z_offset_step]
  connect_bd_net -net cfg3_to_bias_data [get_bd_pins cfg3_to_bias/data] [get_bd_pins axis_spm_control/u0]
  connect_bd_net -net cfg3_to_cfg_dac_axis_data [get_bd_pins cfg3_to_cfg_dac_axis/data] [get_bd_pins data]
  connect_bd_net -net cfg3_to_cfg_dac_control_data [get_bd_pins cfg3_to_cfg_dac_control/data] [get_bd_pins xlslice_cfg_dac_mode/Din] [get_bd_pins xlslice_cfg_dac_send/Din] [get_bd_pins xlslice_cfg_dac_axis/Din]
  connect_bd_net -net cfg3_to_gvp_program_vector_data [get_bd_pins cfg3_to_gvp_program_vector/data] [get_bd_pins gvp_main/vp_set]
  connect_bd_net -net cfg3_to_gvp_setvector_data [get_bd_pins cfg3_to_gvp_setvector/data] [get_bd_pins xlslice_gvp_reset/Din] [get_bd_pins xlslice_gvp_setvec/Din] [get_bd_pins xlslice_gvp_pause/Din] [get_bd_pins xlslice_gvp_reset_options/Din]
  connect_bd_net -net cfg3_to_rotmxx_data [get_bd_pins cfg3_to_rotmxx/data] [get_bd_pins axis_spm_control/rotmxx]
  connect_bd_net -net cfg3_to_rotmxy_data [get_bd_pins cfg3_to_rotmxy/data] [get_bd_pins axis_spm_control/rotmxy]
  connect_bd_net -net cfg3_to_slope_x_data [get_bd_pins cfg3_to_slope_x/data] [get_bd_pins axis_spm_control/slope_x]
  connect_bd_net -net cfg3_to_slope_y_data [get_bd_pins cfg3_to_slope_y/data] [get_bd_pins axis_spm_control/slope_y]
  connect_bd_net -net cfg3_to_x0_data [get_bd_pins cfg3_to_x0/data] [get_bd_pins axis_spm_control/x0]
  connect_bd_net -net cfg3_to_y0_data [get_bd_pins cfg3_to_y0/data] [get_bd_pins axis_spm_control/y0]
  connect_bd_net -net cfg3_to_z0_data [get_bd_pins cfg3_to_z0/data] [get_bd_pins axis_spm_control/z0]
  connect_bd_net -net controller_zservo_enable [get_bd_pins controller_zservo/enable] [get_bd_pins enable]
  connect_bd_net -net gvp_0_options [get_bd_pins gvp_main/options] [get_bd_pins controller_zservo/Din]
  connect_bd_net -net gvp_main_dbg_i -boundary_type lower [get_bd_pins dbg_i]
  connect_bd_net -net gvp_main_dbg_status [get_bd_pins gvp_main/dbg_status] [get_bd_pins dbg_status]
  connect_bd_net -net gvp_main_gvp_finished [get_bd_pins gvp_main/gvp_finished] [get_bd_pins gvp_finished]
  connect_bd_net -net gvp_main_gvp_hold [get_bd_pins gvp_main/gvp_hold] [get_bd_pins gvp_hold]
  connect_bd_net -net gvp_main_section -boundary_type lower [get_bd_pins section]
  connect_bd_net -net gvp_main_store_data [get_bd_pins gvp_main/store_data] [get_bd_pins axis_bram_stream_srcs/push_next]
  connect_bd_net -net xlslice_cfg_dac_axis_Dout [get_bd_pins xlslice_cfg_dac_axis/Dout] [get_bd_pins axis_AD5791_0/configuration_axis]
  connect_bd_net -net xlslice_cfg_dac_mode_Dout [get_bd_pins xlslice_cfg_dac_mode/Dout] [get_bd_pins axis_AD5791_0/configuration_mode]
  connect_bd_net -net xlslice_cfg_dac_send_Dout [get_bd_pins xlslice_cfg_dac_send/Dout] [get_bd_pins axis_AD5791_0/configuration_send]
  connect_bd_net -net xlslice_gvp_reset1_Dout [get_bd_pins xlslice_gvp_reset_options/Dout] [get_bd_pins gvp_main/reset_options]
  connect_bd_net -net xlslice_gvp_reset_Dout [get_bd_pins xlslice_gvp_reset/Dout] [get_bd_pins gvp_main/reset] [get_bd_pins axis_bram_stream_srcs/reset]
  connect_bd_net -net xlslice_gvp_setvec_1_Dout [get_bd_pins xlslice_gvp_pause/Dout] [get_bd_pins gvp_main/pause]
  connect_bd_net -net xlslice_gvp_setvec_Dout [get_bd_pins xlslice_gvp_setvec/Dout] [get_bd_pins gvp_main/setvec]

  # Perform GUI Layout
  regenerate_bd_layout -hierarchy [get_bd_cells /SPM_control_logic] -layout_string {
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"2.44015",
   "Default View_TopLeft":"-329,617",
   "ExpandedHierarchyInLayout":"/SPM_control_logic/controller_zservo",
   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
#  -string -flagsOSRD
preplace port S_AXIS -pg 1 -lvl 0 -x 0 -y 960 -defaultsOSRD
preplace port BRAM_PORTB -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD
preplace port S_AXIS_ch9s -pg 1 -lvl 0 -x 0 -y 780 -defaultsOSRD
preplace port S_AXIS_chAs -pg 1 -lvl 0 -x 0 -y 810 -defaultsOSRD
preplace port S_AXIS_chBs -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD
preplace port S_AXIS_chCs -pg 1 -lvl 0 -x 0 -y 870 -defaultsOSRD
preplace port S_AXIS_chEs -pg 1 -lvl 0 -x 0 -y 900 -defaultsOSRD
preplace port S_AXIS_ch5s -pg 1 -lvl 0 -x 0 -y 750 -defaultsOSRD
preplace port port-id_a_clk -pg 1 -lvl 0 -x 0 -y 1250 -defaultsOSRD
preplace port port-id_gvp_finished -pg 1 -lvl 10 -x 4970 -y 1730 -defaultsOSRD
preplace port port-id_enable -pg 1 -lvl 10 -x 4970 -y 990 -defaultsOSRD
preplace port port-id_gvp_hold -pg 1 -lvl 10 -x 4970 -y 1990 -defaultsOSRD
preplace portBus cfg3 -pg 1 -lvl 0 -x 0 -y 1330 -defaultsOSRD
preplace portBus exp_p_io -pg 1 -lvl 10 -x 4970 -y 50 -defaultsOSRD
preplace portBus cfg1 -pg 1 -lvl 0 -x 0 -y 230 -defaultsOSRD
preplace portBus M_AXIS_PASS_tdata -pg 1 -lvl 10 -x 4970 -y 1030 -defaultsOSRD
preplace portBus data -pg 1 -lvl 10 -x 4970 -y 740 -defaultsOSRD
preplace portBus dbg_i -pg 1 -lvl 10 -x 4970 -y 20 -defaultsOSRD
preplace portBus section -pg 1 -lvl 10 -x 4970 -y 80 -defaultsOSRD
preplace portBus dbg_status -pg 1 -lvl 10 -x 4970 -y 1520 -defaultsOSRD
preplace portBus M_AXIS_ZSMON_tdata -pg 1 -lvl 10 -x 4970 -y 1460 -defaultsOSRD
preplace portBus M_AXIS_X0MON_tdata -pg 1 -lvl 10 -x 4970 -y 1280 -defaultsOSRD
preplace portBus M_AXIS_XSMON_tdata -pg 1 -lvl 10 -x 4970 -y 1320 -defaultsOSRD
preplace portBus M_AXIS_YSMON_tdata -pg 1 -lvl 10 -x 4970 -y 1380 -defaultsOSRD
preplace portBus M_AXIS_Z0MON_tdata -pg 1 -lvl 10 -x 4970 -y 1420 -defaultsOSRD
preplace portBus exp_n_io -pg 1 -lvl 10 -x 4970 -y 500 -defaultsOSRD
preplace portBus mon3 -pg 1 -lvl 10 -x 4970 -y 670 -defaultsOSRD
preplace portBus mon0 -pg 1 -lvl 10 -x 4970 -y 580 -defaultsOSRD
preplace portBus mon1 -pg 1 -lvl 10 -x 4970 -y 610 -defaultsOSRD
preplace portBus mon2 -pg 1 -lvl 10 -x 4970 -y 640 -defaultsOSRD
preplace portBus last_write_addr -pg 1 -lvl 10 -x 4970 -y 860 -defaultsOSRD
preplace portBus M_AXIS_Z_tdata -pg 1 -lvl 10 -x 4970 -y 220 -defaultsOSRD
preplace inst xlslice_cfg_dac_mode -pg 1 -lvl 7 -x 2680 -y 400 -defaultsOSRD
preplace inst xlslice_cfg_dac_send -pg 1 -lvl 7 -x 2680 -y 500 -defaultsOSRD
preplace inst xlslice_gvp_reset -pg 1 -lvl 2 -x 420 -y 1030 -defaultsOSRD
preplace inst xlslice_gvp_setvec -pg 1 -lvl 2 -x 420 -y 1230 -defaultsOSRD
preplace inst xlslice_cfg_dac_axis -pg 1 -lvl 7 -x 2680 -y 300 -defaultsOSRD
preplace inst controller_zservo -pg 1 -lvl 8 -x 3300 -y 990 -defaultsOSRD
preplace inst cfg3_to_cfg_dac_axis -pg 1 -lvl 7 -x 2680 -y 640 -defaultsOSRD
preplace inst cfg3_to_cfg_dac_control -pg 1 -lvl 6 -x 2180 -y 490 -defaultsOSRD
preplace inst cfg3_to_gvp_program_vector -pg 1 -lvl 2 -x 420 -y 1440 -defaultsOSRD
preplace inst cfg3_to_gvp_setvector -pg 1 -lvl 1 -x 150 -y 1320 -defaultsOSRD
preplace inst cfg3_to_rotmxx -pg 1 -lvl 6 -x 2180 -y 1020 -defaultsOSRD
preplace inst cfg3_to_rotmxy -pg 1 -lvl 6 -x 2180 -y 1260 -defaultsOSRD
preplace inst cfg3_to_slope_x -pg 1 -lvl 6 -x 2180 -y 1400 -defaultsOSRD
preplace inst cfg3_to_slope_y -pg 1 -lvl 6 -x 2180 -y 1540 -defaultsOSRD
preplace inst cfg3_to_x0 -pg 1 -lvl 6 -x 2180 -y 1660 -defaultsOSRD
preplace inst cfg3_to_y0 -pg 1 -lvl 6 -x 2180 -y 1800 -defaultsOSRD
preplace inst cfg3_to_z0 -pg 1 -lvl 6 -x 2180 -y 1920 -defaultsOSRD
preplace inst xlslice_gvp_pause -pg 1 -lvl 2 -x 420 -y 1130 -defaultsOSRD
preplace inst cfg3_to_bias -pg 1 -lvl 6 -x 2180 -y 790 -defaultsOSRD
preplace inst cfg3_to_xy_move_step -pg 1 -lvl 6 -x 2180 -y 2060 -defaultsOSRD
preplace inst cfg3_to_z_move_step -pg 1 -lvl 6 -x 2180 -y 2180 -defaultsOSRD
preplace inst xlslice_gvp_reset_options -pg 1 -lvl 2 -x 420 -y 1330 -defaultsOSRD
preplace inst AD5791_io_connect_0 -pg 1 -lvl 9 -x 4710 -y 510 -defaultsOSRD
preplace inst axis_AD5791_0 -pg 1 -lvl 8 -x 3300 -y 600 -defaultsOSRD
preplace inst blk_mem_gen_spmc -pg 1 -lvl 6 -x 2180 -y 110 -defaultsOSRD
preplace inst gvp_main -pg 1 -lvl 3 -x 770 -y 1140 -defaultsOSRD
preplace inst axis_bram_stream_srcs -pg 1 -lvl 5 -x 1730 -y 830 -defaultsOSRD
preplace inst axis_spm_control -pg 1 -lvl 7 -x 2680 -y 1170 -defaultsOSRD
preplace inst axis_splitter_U -pg 1 -lvl 4 -x 1230 -y 700 -defaultsOSRD
preplace inst axis_splitter_Z -pg 1 -lvl 4 -x 1230 -y 560 -defaultsOSRD
preplace inst axis_splitter_Y -pg 1 -lvl 4 -x 1230 -y 1100 -defaultsOSRD
preplace inst axis_splitter_X -pg 1 -lvl 4 -x 1230 -y 1240 -defaultsOSRD
preplace inst axis_splitter_CH0_S16_to_S32 -pg 1 -lvl 3 -x 770 -y 570 -defaultsOSRD
preplace inst axis_splitter_ZControlSignalPass -pg 1 -lvl 7 -x 2680 -y 1440 -defaultsOSRD
preplace inst controller_zservo|cfg_select_zservo_control -pg 1 -lvl 2 -x 3650 -y 2090 -defaultsOSRD
preplace inst controller_zservo|const_zero_32b -pg 1 -lvl 2 -x 3650 -y 1890 -defaultsOSRD
preplace inst controller_zservo|floating_point_log -pg 1 -lvl 1 -x 3340 -y 1130 -defaultsOSRD
preplace inst controller_zservo|xlslice_servo_hold -pg 1 -lvl 2 -x 3650 -y 2190 -defaultsOSRD
preplace inst controller_zservo|xlconstant_0 -pg 1 -lvl 2 -x 3650 -y 1990 -defaultsOSRD
preplace inst controller_zservo|xlconstant_select0 -pg 1 -lvl 1 -x 3340 -y 990 -defaultsOSRD
preplace inst controller_zservo|axis_ctrlsrc_select_0 -pg 1 -lvl 2 -x 3650 -y 1140 -defaultsOSRD
preplace inst controller_zservo|cfg_to_transport_zservo_ci -pg 1 -lvl 2 -x 3650 -y 1280 -defaultsOSRD
preplace inst controller_zservo|cfg_to_transport_zservo_cp -pg 1 -lvl 2 -x 3650 -y 1400 -defaultsOSRD
preplace inst controller_zservo|cfg_to_transport_zservo_lower -pg 1 -lvl 2 -x 3650 -y 1640 -defaultsOSRD
preplace inst controller_zservo|cfg_to_transport_zservo_set -pg 1 -lvl 2 -x 3650 -y 1520 -defaultsOSRD
preplace inst controller_zservo|cfg_to_transport_zservo_upper -pg 1 -lvl 2 -x 3650 -y 1780 -defaultsOSRD
preplace inst controller_zservo|controller_z_servo -pg 1 -lvl 3 -x 4080 -y 1540 -defaultsOSRD
preplace netloc Net 1 9 1 NJ 500
preplace netloc PS_cfg_data_reg_3 1 0 7 20 1390 280 1510 NJ 1510 NJ 1510 NJ 1510 2030 650 NJ
preplace netloc a_clk 1 0 8 20 1250 290 970 580 490 1050 890 1460 1150 2020 630 2380 800 3020
preplace netloc axis_AD5791_0_mon0 1 8 2 NJ 590 4950J
preplace netloc axis_AD5791_0_mon1 1 8 2 NJ 610 NJ
preplace netloc axis_AD5791_0_mon2 1 8 2 NJ 630 4950J
preplace netloc axis_AD5791_0_mon3 1 8 2 NJ 650 4950J
preplace netloc axis_AD5791_0_wire_PMD_clk 1 8 1 4480 490n
preplace netloc axis_AD5791_0_wire_PMD_dac 1 8 1 4500 530n
preplace netloc axis_AD5791_0_wire_PMD_sync 1 8 1 4490 510n
preplace netloc axis_spm_control_0_M_AXIS_X0MON_tdata 1 7 3 3000J 820 NJ 820 4930J
preplace netloc axis_spm_control_0_M_AXIS_XSMON_tdata 1 7 3 2990J 810 NJ 810 4940J
preplace netloc axis_spm_control_0_M_AXIS_YSMON_tdata 1 7 3 3040J 830 NJ 830 4910J
preplace netloc axis_spm_control_0_M_AXIS_Z0MON_tdata 1 7 3 3060J 880 NJ 880 4860J
preplace netloc axis_spm_control_0_M_AXIS_ZSMON_tdata 1 7 3 3050J 870 NJ 870 4870J
preplace netloc cfg1_1 1 0 8 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 2970J
preplace netloc cfg3_to_bias1_data 1 6 1 2450 1300n
preplace netloc cfg3_to_bias2_data 1 6 1 2460 1320n
preplace netloc cfg3_to_bias_data 1 6 1 2350 800n
preplace netloc cfg3_to_cfg_dac_axis_data 1 7 3 2950J 740 NJ 740 NJ
preplace netloc cfg3_to_cfg_dac_control_data 1 6 1 2380 300n
preplace netloc cfg3_to_gvp_program_vector_data 1 2 1 560 1170n
preplace netloc cfg3_to_gvp_setvector_data 1 1 1 280 1030n
preplace netloc cfg3_to_rotmxx_data 1 6 1 2340 1030n
preplace netloc cfg3_to_rotmxy_data 1 6 1 2390 1160n
preplace netloc cfg3_to_slope_x_data 1 6 1 2400 1180n
preplace netloc cfg3_to_slope_y_data 1 6 1 2410 1200n
preplace netloc cfg3_to_x0_data 1 6 1 2420 1220n
preplace netloc cfg3_to_y0_data 1 6 1 2430 1240n
preplace netloc cfg3_to_z0_data 1 6 1 2440 1260n
preplace netloc controller_zservo_enable 1 8 2 4500J 990 NJ
preplace netloc gvp_0_options 1 3 5 1080J 990 1390J 1140 2040J 950 NJ 950 2930
preplace netloc gvp_main_dbg_status 1 3 7 970J 1000 1410J 1090 1940J 880 2330J 860 NJ 860 NJ 860 4880J
preplace netloc gvp_main_gvp_finished 1 3 7 1090J 980 1400J 1130 1920J 870 2310J 840 NJ 840 NJ 840 4890J
preplace netloc gvp_main_gvp_hold 1 3 7 990J 420 NJ 420 NJ 420 2460J 760 NJ 760 NJ 760 4900J
preplace netloc xlslice_cfg_dac_axis_Dout 1 7 1 3000 300n
preplace netloc xlslice_cfg_dac_mode_Dout 1 7 1 2990 400n
preplace netloc xlslice_cfg_dac_send_Dout 1 7 1 2960 500n
preplace netloc xlslice_gvp_reset1_Dout 1 2 1 570J 1190n
preplace netloc xlslice_gvp_reset_Dout 1 2 3 590 910 NJ 910 1490
preplace netloc xlslice_gvp_setvec_1_Dout 1 2 1 NJ 1130
preplace netloc xlslice_gvp_setvec_Dout 1 2 1 550J 1150n
preplace netloc axis_bram_stream_srcs_0_BRAM_PORTA_addr 1 5 1 1920 80n
preplace netloc axis_bram_stream_srcs_0_BRAM_PORTA_clk 1 5 1 1930 100n
preplace netloc axis_bram_stream_srcs_0_BRAM_PORTA_din 1 5 1 1940 120n
preplace netloc axis_bram_stream_srcs_0_BRAM_PORTA_we 1 5 1 1950 140n
preplace netloc gvp_main_store_data 1 3 2 1060J 930 1480
preplace netloc axis_bram_stream_srcs_last_write_addr 1 5 5 NJ 860 2320J 850 NJ 850 NJ 850 4920J
preplace netloc axis_splitter_Z_monitor 1 4 6 1370J 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ
preplace netloc axis_splitter_ZControlSignalPass_monitor 1 7 3 3030J 800 NJ 800 4950
preplace netloc S_AXIS_1 1 0 8 NJ 960 NJ 960 NJ 960 NJ 960 1470J 1080 1960J 930 NJ 930 NJ
preplace netloc axis_spm_control_0_M_AXIS1 1 7 1 2920 520n
preplace netloc axis_spm_control_0_M_AXIS2 1 7 1 2940 540n
preplace netloc cfg3_to_cfg_dac_axis_M_AXIS 1 7 1 2930 600n
preplace netloc controller_zservo_M_AXIS_CONTROL 1 6 3 2460 780 NJ 780 4480
preplace netloc BRAM_PORTB_1 1 0 6 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ
preplace netloc gvp_main_M_AXIS_SRCS 1 3 2 980 970 1540J
preplace netloc gvp_main_M_AXIS_index 1 3 2 1000 940 NJ
preplace netloc S_AXIS_ch9s_1 1 0 5 NJ 780 NJ 780 NJ 780 NJ 780 1540J
preplace netloc S_AXIS_chAs_1 1 0 5 NJ 810 NJ 810 NJ 810 NJ 810 1540J
preplace netloc S_AXIS_chBs_1 1 0 5 NJ 840 NJ 840 NJ 840 NJ 840 NJ
preplace netloc S_AXIS_chCs_1 1 0 5 20J 860 NJ 860 NJ 860 NJ 860 NJ
preplace netloc gvp_main_M_AXIS_gvp_time 1 3 2 950 920 NJ
preplace netloc S_AXIS_chEs_1 1 0 5 NJ 900 NJ 900 NJ 900 NJ 900 NJ
preplace netloc gvp_main_M_AXIS_X 1 3 1 1010 1070n
preplace netloc gvp_main_M_AXIS_Y 1 3 1 N 1090
preplace netloc axis_splitter_U_M_AXIS 1 4 1 1510 680n
preplace netloc axis_splitter_X_M_AXIS 1 4 1 1500 640n
preplace netloc axis_splitter_Y_M_AXIS 1 4 1 1370 660n
preplace netloc axis_splitter_X_M_AXIS2 1 4 3 NJ 1240 2050J 1090 2310
preplace netloc axis_splitter_Y_M_AXIS2 1 4 3 NJ 1100 NJ 1100 2330
preplace netloc gvp_main_M_AXIS_Z 1 3 4 960 1010 1380J 1120 NJ 1120 2360J
preplace netloc axis_splitter_Z_M_AXIS 1 4 1 1530 540n
preplace netloc axis_spm_control_M_AXIS3 1 3 5 1100 410 NJ 410 NJ 410 2470J 710 2890
preplace netloc axis_splitter_Z_M_AXIS2 1 4 4 NJ 560 NJ 560 NJ 560 N
preplace netloc gvp_main_M_AXIS_U 1 3 4 1070J 1020 1360J 1110 NJ 1110 2320
preplace netloc axis_spm_control_M_AXIS4 1 3 5 1090 470 NJ 470 1960J 720 NJ 720 2900
preplace netloc axis_splitter_U_M_AXIS2 1 4 4 1420J 570 NJ 570 NJ 570 2980
preplace netloc controller_zservo_M_AXIS_PASS 1 6 3 2470 790 NJ 790 4490
preplace netloc axis_splitter_ZControlSignalPass_M_AXIS 1 4 4 1540 580 NJ 580 2440J 730 2910
preplace netloc S_AXIS_ch5s_1 1 0 3 NJ 750 NJ 750 550
preplace netloc axis_splitter_0_M_AXIS 1 3 2 950J 480 1520
preplace netloc controller_zservo|Din_1 1 0 2 NJ 2190 NJ
preplace netloc controller_zservo|PS_cfg_data 1 0 2 NJ 1290 3480
preplace netloc controller_zservo|PS_data_transport_status 1 2 2 3850 1710 NJ
preplace netloc controller_zservo|axis_red_pitaya_adc_0_adc_clk1 1 0 3 3200 1200 3500 1040 3850
preplace netloc controller_zservo|cfg_to_transport_dfreq_ci_data 1 2 1 3820 1290n
preplace netloc controller_zservo|cfg_to_transport_dfreq_cp_data 1 2 1 3810 1410n
preplace netloc controller_zservo|cfg_to_transport_dfreq_lower_data 1 2 1 3820 1610n
preplace netloc controller_zservo|cfg_to_transport_dfreq_upper_data 1 2 1 3810 1590n
preplace netloc controller_zservo|cfg_to_transport_tau_dfreq_data 1 2 1 N 1530
preplace netloc controller_zservo|const_zero_32b_dout 1 2 1 3800J 1470n
preplace netloc controller_zservo|gpio_io_6_x13_1 1 3 1 4300 1570n
preplace netloc controller_zservo|xlconstant_0_dout 1 2 1 3830J 1490n
preplace netloc controller_zservo|xlconstant_1_dout 1 1 1 3480J 990n
preplace netloc controller_zservo|xlslice_0_Dout 1 2 1 3860 1650n
preplace netloc controller_zservo|Conn1 1 0 2 NJ 930 3490
preplace netloc controller_zservo|Conn2 1 3 1 N 1490
preplace netloc controller_zservo|axis_ctrlsrc_select_0_M_AXIS 1 2 1 3830 1130n
preplace netloc controller_zservo|axis_ctrlsrc_select_0_M_AXIS_FLOAT 1 0 3 3200 1050 NJ 1050 3800
preplace netloc controller_zservo|controller_pi_dfreq_M_AXIS_CONTROL 1 3 1 N 1430
preplace netloc controller_zservo|controller_pi_dfreq_M_AXIS_CONTROL2 1 3 1 N 1450
preplace netloc controller_zservo|floating_point_log_M_AXIS_RESULT 1 1 1 N 1130
levelinfo -pg 1 0 150 420 770 1230 1730 2180 2680 3300 4710 4970
levelinfo -hier controller_zservo * 3340 3650 4080 *
pagesize -pg 1 -db -bbox -sgen -150 0 5240 3190
pagesize -hier controller_zservo -db -bbox -sgen 3170 910 4330 2250
"
}

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: PS_data_transport
proc create_hier_cell_PS_data_transport { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_PS_data_transport() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:bram_rtl:1.0 BRAM_PORTB

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_aux

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS1

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS2

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS3

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS4

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS5

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS6

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS7

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS8

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS2

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS3

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS4

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS5

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS6


  # Create pins
  create_bd_pin -dir O McBSP_Frame
  create_bd_pin -dir I -type clk a_clk
  create_bd_pin -dir I -from 1023 -to 0 cfg1
  create_bd_pin -dir I -from 1023 -to 0 cfg0
  create_bd_pin -dir I -from 1023 -to 0 cfg2
  create_bd_pin -dir O -from 31 -to 0 delta_frequency_monitor
  create_bd_pin -dir O enable
  create_bd_pin -dir IO -from 7 -to 0 exp_n_io
  create_bd_pin -dir IO -from 7 -to 0 exp_p_io
  create_bd_pin -dir O -from 31 -to 0 mon_control
  create_bd_pin -dir O -from 31 -to 0 writeposition
  create_bd_pin -dir I -from 2 -to 0 zero_spcp

  # Create instance: PulseFormer
  create_hier_cell_PulseFormer $hier_obj PulseFormer

  # Create instance: controller_dfreq
  create_hier_cell_controller_dfreq $hier_obj controller_dfreq

  # Create instance: blk_mem_gen_pacpll, and set properties
  set blk_mem_gen_pacpll [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_pacpll ]
  set_property -dict [list \
    CONFIG.Algorithm {Minimum_Area} \
    CONFIG.Enable_32bit_Address {false} \
    CONFIG.Enable_B {Use_ENB_Pin} \
    CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
    CONFIG.Operating_Mode_A {NO_CHANGE} \
    CONFIG.Port_B_Clock {100} \
    CONFIG.Port_B_Enable_Rate {100} \
    CONFIG.Read_Width_B {32} \
    CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \
    CONFIG.Use_Byte_Write_Enable {false} \
    CONFIG.Use_RSTB_Pin {false} \
    CONFIG.Write_Depth_A {16384} \
    CONFIG.Write_Width_A {32} \
    CONFIG.Write_Width_B {32} \
    CONFIG.use_bram_block {Stand_Alone} \
  ] $blk_mem_gen_pacpll


  # Create instance: const_zero1, and set properties
  set const_zero1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_zero1 ]
  set_property -dict [list \
    CONFIG.CONST_VAL {0} \
    CONFIG.CONST_WIDTH {32} \
  ] $const_zero1


  # Create instance: const_zero, and set properties
  set const_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_zero ]
  set_property CONFIG.CONST_VAL {0} $const_zero


  # Create instance: axis_4s_combine_decimate, and set properties
  set block_name axis_4s_combine
  set block_cell_name axis_4s_combine_decimate
  if { [catch {set axis_4s_combine_decimate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_4s_combine_decimate eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.BRAM_ADDR_WIDTH {15} \
    CONFIG.BRAM_DATA_WIDTH {64} \
    CONFIG.LCK_ENABLE {1} \
  ] $axis_4s_combine_decimate


  # Create instance: McBSP_io_connect_0, and set properties
  set block_name McBSP_io_connect
  set block_cell_name McBSP_io_connect_0
  if { [catch {set McBSP_io_connect_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $McBSP_io_connect_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: McBSP_controller_0, and set properties
  set block_name McBSP_controller
  set block_cell_name McBSP_controller_0
  if { [catch {set McBSP_controller_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $McBSP_controller_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: cfg18_19_to_transport_auxcenter, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg18_19_to_transport_auxcenter
  if { [catch {set cfg18_19_to_transport_auxcenter [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg18_19_to_transport_auxcenter eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {48} \
    CONFIG.MAXIS_TDATA_WIDTH {48} \
    CONFIG.SRC_ADDR {18} \
    CONFIG.SRC_BITS {64} \
  ] $cfg18_19_to_transport_auxcenter


  # Create instance: cfg_to_transport_channel_select, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_channel_select
  if { [catch {set cfg_to_transport_channel_select [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_channel_select eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {9} \
  ] $cfg_to_transport_channel_select


  # Create instance: cfg_to_transport_control, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_control
  if { [catch {set cfg_to_transport_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {6} \
  ] $cfg_to_transport_control


  # Create instance: cfg_to_transport_decimation, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_decimation
  if { [catch {set cfg_to_transport_decimation [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_decimation eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {8} \
  ] $cfg_to_transport_decimation


  # Create instance: cfg_to_transport_nsamples, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_transport_nsamples
  if { [catch {set cfg_to_transport_nsamples [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_transport_nsamples eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {7} \
  ] $cfg_to_transport_nsamples


  # Create instance: axis_bram_push2ch64, and set properties
  set block_name axis_bram_push
  set block_cell_name axis_bram_push2ch64
  if { [catch {set axis_bram_push2ch64 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_bram_push2ch64 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.BRAM_ADDR_WIDTH {14} \
    CONFIG.BRAM_DATA_WIDTH {32} \
  ] $axis_bram_push2ch64


  # Create instance: axis_FIR_CH1, and set properties
  set block_name axis_FIR
  set block_cell_name axis_FIR_CH1
  if { [catch {set axis_FIR_CH1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_FIR_CH1 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.FIR_DECI {64} \
    CONFIG.FIR_DECI_L {6} \
  ] $axis_FIR_CH1


  # Create instance: axis_FIR_CH2, and set properties
  set block_name axis_FIR
  set block_cell_name axis_FIR_CH2
  if { [catch {set axis_FIR_CH2 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_FIR_CH2 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.FIR_DECI {64} \
    CONFIG.FIR_DECI_L {6} \
  ] $axis_FIR_CH2


  # Create instance: axis_FIR_CH3, and set properties
  set block_name axis_FIR
  set block_cell_name axis_FIR_CH3
  if { [catch {set axis_FIR_CH3 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_FIR_CH3 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.FIR_DECI {64} \
    CONFIG.FIR_DECI_L {6} \
  ] $axis_FIR_CH3


  # Create instance: axis_FIR_CH4, and set properties
  set block_name axis_FIR
  set block_cell_name axis_FIR_CH4
  if { [catch {set axis_FIR_CH4 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_FIR_CH4 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.FIR_DECI {64} \
    CONFIG.FIR_DECI_L {6} \
  ] $axis_FIR_CH4


  # Create instance: axis_splitter_dFreqCrtl, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_dFreqCrtl
  if { [catch {set axis_splitter_dFreqCrtl [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_dFreqCrtl eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S_AXIS7] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS7]
  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S_AXIS8] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS8]
  connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins S_AXIS6] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS6]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_CONTROL2 [get_bd_intf_pins S_AXIS2] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS2]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_PASS2 [get_bd_intf_pins S_AXIS5] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS5]
  connect_bd_intf_net -intf_net PS_BRAM_PORTA [get_bd_intf_pins BRAM_PORTB] [get_bd_intf_pins blk_mem_gen_pacpll/BRAM_PORTB]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_CONTROL2 [get_bd_intf_pins S_AXIS3] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS3]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_PASS2 [get_bd_intf_pins S_AXIS4] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS4]
  connect_bd_intf_net -intf_net PulseForm_0_M_AXIS [get_bd_intf_pins M_AXIS_aux] [get_bd_intf_pins PulseFormer/M_AXIS]
  connect_bd_intf_net -intf_net axis_4s_combine_decimate_M_AXIS_CH1 [get_bd_intf_pins axis_4s_combine_decimate/M_AXIS_CH1] [get_bd_intf_pins axis_FIR_CH1/S_AXIS]
  connect_bd_intf_net -intf_net axis_4s_combine_decimate_M_AXIS_CH2 [get_bd_intf_pins axis_4s_combine_decimate/M_AXIS_CH2] [get_bd_intf_pins axis_FIR_CH2/S_AXIS]
  connect_bd_intf_net -intf_net axis_4s_combine_decimate_M_AXIS_CH3 [get_bd_intf_pins axis_4s_combine_decimate/M_AXIS_CH3] [get_bd_intf_pins axis_FIR_CH3/S_AXIS]
  connect_bd_intf_net -intf_net axis_4s_combine_decimate_M_AXIS_CH4 [get_bd_intf_pins axis_4s_combine_decimate/M_AXIS_CH4] [get_bd_intf_pins axis_FIR_CH4/S_AXIS]
  connect_bd_intf_net -intf_net axis_4s_combine_decimate_M_AXIS_DFREQ_DEC [get_bd_intf_pins axis_4s_combine_decimate/M_AXIS_DFREQ_DEC] [get_bd_intf_pins McBSP_controller_0/S_AXIS5]
  connect_bd_intf_net -intf_net axis_4s_combine_decimate_M_AXIS_DFREQ_DEC2 [get_bd_intf_pins axis_4s_combine_decimate/M_AXIS_DFREQ_DEC2] [get_bd_intf_pins controller_dfreq/S_AXIS]
  connect_bd_intf_net -intf_net axis_FIR_CH1_M_AXIS [get_bd_intf_pins axis_FIR_CH1/M_AXIS] [get_bd_intf_pins McBSP_controller_0/S_AXIS1]
  connect_bd_intf_net -intf_net axis_FIR_CH1_M_AXIS2 [get_bd_intf_pins M_AXIS2] [get_bd_intf_pins axis_FIR_CH1/M_AXIS2]
  connect_bd_intf_net -intf_net axis_FIR_CH2_M_AXIS [get_bd_intf_pins axis_FIR_CH2/M_AXIS] [get_bd_intf_pins McBSP_controller_0/S_AXIS2]
  connect_bd_intf_net -intf_net axis_FIR_CH2_M_AXIS2 [get_bd_intf_pins M_AXIS3] [get_bd_intf_pins axis_FIR_CH2/M_AXIS2]
  connect_bd_intf_net -intf_net axis_FIR_CH3_M_AXIS [get_bd_intf_pins axis_FIR_CH3/M_AXIS] [get_bd_intf_pins McBSP_controller_0/S_AXIS3]
  connect_bd_intf_net -intf_net axis_FIR_CH3_M_AXIS2 [get_bd_intf_pins M_AXIS4] [get_bd_intf_pins axis_FIR_CH3/M_AXIS2]
  connect_bd_intf_net -intf_net axis_FIR_CH4_M_AXIS [get_bd_intf_pins axis_FIR_CH4/M_AXIS] [get_bd_intf_pins McBSP_controller_0/S_AXIS4]
  connect_bd_intf_net -intf_net axis_FIR_CH4_M_AXIS2 [get_bd_intf_pins M_AXIS5] [get_bd_intf_pins axis_FIR_CH4/M_AXIS2]
  connect_bd_intf_net -intf_net axis_splitter_0_M_AXIS [get_bd_intf_pins axis_splitter_dFreqCrtl/M_AXIS] [get_bd_intf_pins McBSP_controller_0/S_AXIS8]
  connect_bd_intf_net -intf_net axis_splitter_0_M_AXIS2 [get_bd_intf_pins M_AXIS6] [get_bd_intf_pins axis_splitter_dFreqCrtl/M_AXIS2]
  connect_bd_intf_net -intf_net controller_dfreq_M_AXIS_CONTROL [get_bd_intf_pins controller_dfreq/M_AXIS_CONTROL] [get_bd_intf_pins axis_splitter_dFreqCrtl/S_AXIS]
  connect_bd_intf_net -intf_net controller_dfreq_M_AXIS_CONTROL2 [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS1S] [get_bd_intf_pins controller_dfreq/M_AXIS_CONTROL2]
  connect_bd_intf_net -intf_net lms_phase_amplitude_detector_0_M_AXIS_SIGNAL [get_bd_intf_pins S_AXIS1] [get_bd_intf_pins axis_4s_combine_decimate/S_AXIS1]

  # Create port connections
  connect_bd_net -net McBSP_controller_0_mcbsp_data_clkr [get_bd_pins McBSP_controller_0/mcbsp_data_clkr] [get_bd_pins McBSP_io_connect_0/McBSP_clkr]
  connect_bd_net -net McBSP_controller_0_mcbsp_data_frm [get_bd_pins McBSP_controller_0/mcbsp_data_frm] [get_bd_pins McBSP_io_connect_0/McBSP_frm] [get_bd_pins McBSP_Frame]
  connect_bd_net -net McBSP_controller_0_mcbsp_data_fsx [get_bd_pins McBSP_controller_0/mcbsp_data_fsx] [get_bd_pins McBSP_io_connect_0/McBSP_fsx]
  connect_bd_net -net McBSP_controller_0_mcbsp_data_tx [get_bd_pins McBSP_controller_0/mcbsp_data_tx] [get_bd_pins McBSP_io_connect_0/McBSP_tx]
  connect_bd_net -net McBSP_controller_0_trigger [get_bd_pins McBSP_controller_0/trigger] [get_bd_pins axis_4s_combine_decimate/ext_trigger]
  connect_bd_net -net McBSP_io_connect_0_McBSP_clk [get_bd_pins McBSP_io_connect_0/McBSP_clk] [get_bd_pins McBSP_controller_0/mcbsp_clk]
  connect_bd_net -net McBSP_io_connect_0_McBSP_fs [get_bd_pins McBSP_io_connect_0/McBSP_fs] [get_bd_pins McBSP_controller_0/mcbsp_frame_start]
  connect_bd_net -net McBSP_io_connect_0_McBSP_nrx [get_bd_pins McBSP_io_connect_0/McBSP_nrx] [get_bd_pins McBSP_controller_0/mcbsp_data_nrx]
  connect_bd_net -net McBSP_io_connect_0_McBSP_rx [get_bd_pins McBSP_io_connect_0/McBSP_rx] [get_bd_pins McBSP_controller_0/mcbsp_data_rx]
  connect_bd_net -net Net [get_bd_pins exp_p_io] [get_bd_pins McBSP_io_connect_0/exp_p_io]
  connect_bd_net -net Net1 [get_bd_pins exp_n_io] [get_bd_pins McBSP_io_connect_0/exp_n_io]
  connect_bd_net -net axis_4s_combine_0_BR_ch1s [get_bd_pins axis_4s_combine_decimate/BR_ch1s] [get_bd_pins axis_bram_push2ch64/ch1s]
  connect_bd_net -net axis_4s_combine_0_BR_ch2s [get_bd_pins axis_4s_combine_decimate/BR_ch2s] [get_bd_pins axis_bram_push2ch64/ch2s]
  connect_bd_net -net axis_4s_combine_0_BR_reset [get_bd_pins axis_4s_combine_decimate/BR_reset] [get_bd_pins axis_bram_push2ch64/reset]
  connect_bd_net -net axis_4s_combine_0_bram_porta_addr [get_bd_pins axis_bram_push2ch64/BRAM_PORTA_addr] [get_bd_pins blk_mem_gen_pacpll/addra]
  connect_bd_net -net axis_4s_combine_0_bram_porta_clk [get_bd_pins axis_bram_push2ch64/BRAM_PORTA_clk] [get_bd_pins blk_mem_gen_pacpll/clka]
  connect_bd_net -net axis_4s_combine_0_bram_porta_en [get_bd_pins axis_bram_push2ch64/BRAM_PORTA_en] [get_bd_pins blk_mem_gen_pacpll/ena]
  connect_bd_net -net axis_4s_combine_0_bram_porta_we [get_bd_pins axis_bram_push2ch64/BRAM_PORTA_we] [get_bd_pins blk_mem_gen_pacpll/wea]
  connect_bd_net -net axis_4s_combine_0_bram_porta_wrdata [get_bd_pins axis_bram_push2ch64/BRAM_PORTA_din] [get_bd_pins blk_mem_gen_pacpll/dina]
  connect_bd_net -net axis_4s_combine_0_writeposition [get_bd_pins axis_4s_combine_decimate/writeposition] [get_bd_pins writeposition]
  connect_bd_net -net axis_4s_combine_decimate_BR_next [get_bd_pins axis_4s_combine_decimate/BR_next] [get_bd_pins axis_bram_push2ch64/push_next]
  connect_bd_net -net axis_4s_combine_decimate_FIR_next [get_bd_pins axis_4s_combine_decimate/FIR_next] [get_bd_pins axis_FIR_CH1/next_dv] [get_bd_pins axis_FIR_CH2/next_dv] [get_bd_pins axis_FIR_CH3/next_dv] [get_bd_pins axis_FIR_CH4/next_dv]
  connect_bd_net -net axis_4s_combine_decimate_delta_frequency_monitor [get_bd_pins axis_4s_combine_decimate/delta_frequency_monitor] [get_bd_pins delta_frequency_monitor]
  connect_bd_net -net axis_bram_push2ch64_last_write_addr [get_bd_pins axis_bram_push2ch64/last_write_addr] [get_bd_pins axis_4s_combine_decimate/BR_wpos]
  connect_bd_net -net axis_bram_push_0_ready [get_bd_pins axis_bram_push2ch64/ready] [get_bd_pins axis_4s_combine_decimate/BR_ready]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk [get_bd_pins a_clk] [get_bd_pins PulseFormer/a_clk] [get_bd_pins controller_dfreq/a_clk] [get_bd_pins axis_4s_combine_decimate/a_clk] [get_bd_pins McBSP_controller_0/a_clk] [get_bd_pins cfg18_19_to_transport_auxcenter/a_clk] [get_bd_pins cfg_to_transport_channel_select/a_clk] [get_bd_pins cfg_to_transport_control/a_clk] [get_bd_pins cfg_to_transport_decimation/a_clk] [get_bd_pins cfg_to_transport_nsamples/a_clk] [get_bd_pins axis_bram_push2ch64/a2_clk] [get_bd_pins axis_FIR_CH1/a_clk] [get_bd_pins axis_FIR_CH2/a_clk] [get_bd_pins axis_FIR_CH3/a_clk] [get_bd_pins axis_FIR_CH4/a_clk] [get_bd_pins axis_splitter_dFreqCrtl/a_clk]
  connect_bd_net -net cfg18_19_to_transport_auxcenter_data [get_bd_pins cfg18_19_to_transport_auxcenter/data] [get_bd_pins axis_4s_combine_decimate/axis3_center]
  connect_bd_net -net cfg2_1 [get_bd_pins cfg2] [get_bd_pins PulseFormer/cfg2]
  connect_bd_net -net cfg_1 [get_bd_pins cfg0] [get_bd_pins controller_dfreq/cfg1] [get_bd_pins cfg18_19_to_transport_auxcenter/cfg] [get_bd_pins cfg_to_transport_channel_select/cfg] [get_bd_pins cfg_to_transport_control/cfg] [get_bd_pins cfg_to_transport_decimation/cfg] [get_bd_pins cfg_to_transport_nsamples/cfg]
  connect_bd_net -net cfg_2 [get_bd_pins cfg1] [get_bd_pins controller_dfreq/cfg]
  connect_bd_net -net cfg_to_channel_select_data [get_bd_pins cfg_to_transport_channel_select/data] [get_bd_pins axis_4s_combine_decimate/channel_selector]
  connect_bd_net -net cfg_to_transport_channel_select1_data [get_bd_pins cfg_to_transport_nsamples/data] [get_bd_pins axis_4s_combine_decimate/nsamples]
  connect_bd_net -net cfg_to_transport_control_data [get_bd_pins cfg_to_transport_control/data] [get_bd_pins axis_4s_combine_decimate/operation]
  connect_bd_net -net cfg_to_transport_data [get_bd_pins cfg_to_transport_decimation/data] [get_bd_pins axis_4s_combine_decimate/ndecimate]
  connect_bd_net -net const_zero1_dout [get_bd_pins const_zero1/dout] [get_bd_pins controller_dfreq/S_AXIS_reset_tdata]
  connect_bd_net -net const_zero_dout [get_bd_pins const_zero/dout] [get_bd_pins controller_dfreq/control_hold]
  connect_bd_net -net controller_dfreq_enable [get_bd_pins controller_dfreq/enable] [get_bd_pins enable]
  connect_bd_net -net controller_dfreq_mon_control [get_bd_pins controller_dfreq/mon_control] [get_bd_pins mon_control]
  connect_bd_net -net zero_spcp_1 [get_bd_pins zero_spcp] [get_bd_pins PulseFormer/zero_spcp]

  # Perform GUI Layout
  regenerate_bd_layout -hierarchy [get_bd_cells /PS_data_transport] -layout_string {
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"1.0",
   "Default View_TopLeft":"-1115,75",
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
#  -string -flagsOSRD
preplace port BRAM_PORTB -pg 1 -lvl 0 -x -50 -y 230 -defaultsOSRD
preplace port M_AXIS_aux -pg 1 -lvl 7 -x 2550 -y 870 -defaultsOSRD
preplace port S_AXIS1 -pg 1 -lvl 0 -x -50 -y 910 -defaultsOSRD
preplace port S_AXIS2 -pg 1 -lvl 0 -x -50 -y 330 -defaultsOSRD
preplace port S_AXIS3 -pg 1 -lvl 0 -x -50 -y 360 -defaultsOSRD
preplace port S_AXIS4 -pg 1 -lvl 0 -x -50 -y 390 -defaultsOSRD
preplace port S_AXIS5 -pg 1 -lvl 0 -x -50 -y 420 -defaultsOSRD
preplace port S_AXIS6 -pg 1 -lvl 0 -x -50 -y 450 -defaultsOSRD
preplace port S_AXIS7 -pg 1 -lvl 0 -x -50 -y 480 -defaultsOSRD
preplace port S_AXIS8 -pg 1 -lvl 0 -x -50 -y 510 -defaultsOSRD
preplace port M_AXIS2 -pg 1 -lvl 7 -x 2550 -y 200 -defaultsOSRD
preplace port M_AXIS3 -pg 1 -lvl 7 -x 2550 -y -110 -defaultsOSRD
preplace port M_AXIS4 -pg 1 -lvl 7 -x 2550 -y -80 -defaultsOSRD
preplace port M_AXIS5 -pg 1 -lvl 7 -x 2550 -y 620 -defaultsOSRD
preplace port M_AXIS6 -pg 1 -lvl 7 -x 2550 -y 770 -defaultsOSRD
preplace port port-id_McBSP_Frame -pg 1 -lvl 7 -x 2550 -y -140 -defaultsOSRD
preplace port port-id_a_clk -pg 1 -lvl 0 -x -50 -y 540 -defaultsOSRD
preplace port port-id_enable -pg 1 -lvl 7 -x 2550 -y 1010 -defaultsOSRD
preplace portBus cfg1 -pg 1 -lvl 0 -x -50 -y 1080 -defaultsOSRD
preplace portBus cfg0 -pg 1 -lvl 0 -x -50 -y 570 -defaultsOSRD
preplace portBus cfg2 -pg 1 -lvl 0 -x -50 -y 1020 -defaultsOSRD
preplace portBus delta_frequency_monitor -pg 1 -lvl 7 -x 2550 -y 530 -defaultsOSRD
preplace portBus exp_n_io -pg 1 -lvl 7 -x 2550 -y 310 -defaultsOSRD
preplace portBus exp_p_io -pg 1 -lvl 7 -x 2550 -y 280 -defaultsOSRD
preplace portBus mon_control -pg 1 -lvl 7 -x 2550 -y 1040 -defaultsOSRD
preplace portBus writeposition -pg 1 -lvl 7 -x 2550 -y 710 -defaultsOSRD
preplace portBus zero_spcp -pg 1 -lvl 0 -x -50 -y 1050 -defaultsOSRD
preplace inst PulseFormer -pg 1 -lvl 6 -x 2330 -y 872 -defaultsOSRD
preplace inst controller_dfreq -pg 1 -lvl 3 -x 1150 -y 1010 -defaultsOSRD
preplace inst blk_mem_gen_pacpll -pg 1 -lvl 5 -x 1990 -y -10 -defaultsOSRD
preplace inst const_zero1 -pg 1 -lvl 2 -x 600 -y 960 -defaultsOSRD
preplace inst const_zero -pg 1 -lvl 2 -x 600 -y 1100 -defaultsOSRD
preplace inst axis_4s_combine_decimate -pg 1 -lvl 2 -x 600 -y 540 -defaultsOSRD
preplace inst McBSP_io_connect_0 -pg 1 -lvl 6 -x 2330 -y 360 -defaultsOSRD
preplace inst McBSP_controller_0 -pg 1 -lvl 5 -x 1990 -y 380 -defaultsOSRD
preplace inst cfg18_19_to_transport_auxcenter -pg 1 -lvl 1 -x 150 -y 740 -defaultsOSRD
preplace inst cfg_to_transport_channel_select -pg 1 -lvl 1 -x 150 -y 160 -defaultsOSRD
preplace inst cfg_to_transport_control -pg 1 -lvl 1 -x 150 -y 980 -defaultsOSRD
preplace inst cfg_to_transport_decimation -pg 1 -lvl 1 -x 150 -y 600 -defaultsOSRD
preplace inst cfg_to_transport_nsamples -pg 1 -lvl 1 -x 150 -y 340 -defaultsOSRD
preplace inst axis_bram_push2ch64 -pg 1 -lvl 3 -x 1150 -y -10 -defaultsOSRD
preplace inst axis_FIR_CH1 -pg 1 -lvl 3 -x 1150 -y 190 -defaultsOSRD
preplace inst axis_FIR_CH2 -pg 1 -lvl 3 -x 1150 -y 330 -defaultsOSRD
preplace inst axis_FIR_CH3 -pg 1 -lvl 3 -x 1150 -y 470 -defaultsOSRD
preplace inst axis_FIR_CH4 -pg 1 -lvl 3 -x 1150 -y 610 -defaultsOSRD
preplace inst axis_splitter_dFreqCrtl -pg 1 -lvl 4 -x 1590 -y 760 -defaultsOSRD
preplace netloc McBSP_controller_0_mcbsp_data_clkr 1 5 1 N 330
preplace netloc McBSP_controller_0_mcbsp_data_frm 1 5 2 2180 -130 2520
preplace netloc McBSP_controller_0_mcbsp_data_fsx 1 5 1 N 370
preplace netloc McBSP_controller_0_mcbsp_data_tx 1 5 1 N 350
preplace netloc McBSP_controller_0_trigger 1 1 5 360 850 NJ 850 NJ 850 N 850 2160
preplace netloc McBSP_io_connect_0_McBSP_clk 1 4 3 1780 160 NJ 160 2490
preplace netloc McBSP_io_connect_0_McBSP_fs 1 4 3 1800 170 NJ 170 2510
preplace netloc McBSP_io_connect_0_McBSP_nrx 1 4 3 1810 180 NJ 180 2500
preplace netloc McBSP_io_connect_0_McBSP_rx 1 4 3 1820 190 NJ 190 2480
preplace netloc Net 1 6 1 2530 280n
preplace netloc Net1 1 6 1 N 310
preplace netloc axis_4s_combine_0_BR_ch1s 1 2 1 840 -50n
preplace netloc axis_4s_combine_0_BR_ch2s 1 2 1 850 -30n
preplace netloc axis_4s_combine_0_BR_reset 1 2 1 830 10n
preplace netloc axis_4s_combine_0_bram_porta_addr 1 3 2 1440 70 1740
preplace netloc axis_4s_combine_0_bram_porta_clk 1 3 2 1450 60 1750
preplace netloc axis_4s_combine_0_bram_porta_en 1 3 2 1420 90 1770
preplace netloc axis_4s_combine_0_bram_porta_we 1 3 2 1410 100 1780
preplace netloc axis_4s_combine_0_bram_porta_wrdata 1 3 2 1430 80 1760
preplace netloc axis_4s_combine_0_writeposition 1 2 5 870J 700 1460J 680 1720 710 NJ 710 NJ
preplace netloc axis_4s_combine_decimate_BR_next 1 2 1 890 -10n
preplace netloc axis_4s_combine_decimate_FIR_next 1 2 1 900 210n
preplace netloc axis_4s_combine_decimate_delta_frequency_monitor 1 2 5 860J 690 1440J 180 1740 150 NJ 150 2520J
preplace netloc axis_bram_push2ch64_last_write_addr 1 1 3 380 770 NJ 770 1370
preplace netloc axis_bram_push_0_ready 1 1 3 370 780 NJ 780 1360
preplace netloc axis_red_pitaya_adc_0_adc_clk 1 0 6 0 810 280 790 930 790 1460J 840 1790 840 2170
preplace netloc cfg18_19_to_transport_auxcenter_data 1 1 1 290 570n
preplace netloc cfg2_1 1 0 6 20J 880 NJ 880 NJ 880 NJ 880 1790 872 NJ
preplace netloc cfg_1 1 0 3 10 1050 380J 1040 NJ
preplace netloc cfg_2 1 0 3 NJ 1080 280J 1030 940J
preplace netloc cfg_to_channel_select_data 1 1 1 320 170n
preplace netloc cfg_to_transport_channel_select1_data 1 1 1 310 350n
preplace netloc cfg_to_transport_control_data 1 1 1 340 590n
preplace netloc cfg_to_transport_data 1 1 1 N 610
preplace netloc const_zero1_dout 1 2 1 820J 960n
preplace netloc const_zero_dout 1 2 1 820J 1060n
preplace netloc controller_dfreq_enable 1 3 4 NJ 1040 1720 1010 NJ 1010 NJ
preplace netloc controller_dfreq_mon_control 1 3 4 NJ 1060 1790 1040 NJ 1040 NJ
preplace netloc zero_spcp_1 1 0 6 -30J 890 NJ 890 NJ 890 NJ 890 1720 892 NJ
preplace netloc Conn1 1 0 2 NJ 480 290J
preplace netloc Conn2 1 0 2 NJ 510 280J
preplace netloc Conn3 1 0 2 NJ 450 300J
preplace netloc PS_Amplitude_Controller_M_AXIS_CONTROL2 1 0 2 -30J 270 340J
preplace netloc PS_Amplitude_Controller_M_AXIS_PASS2 1 0 2 NJ 420 340J
preplace netloc PS_BRAM_PORTA 1 0 5 -30J 90 NJ 90 940J 110 NJ 110 1790
preplace netloc PS_Phase_Controller_M_AXIS_CONTROL2 1 0 2 -10J 430 NJ
preplace netloc PS_Phase_Controller_M_AXIS_PASS2 1 0 2 -30J 440 330J
preplace netloc PulseForm_0_M_AXIS 1 6 1 2490J 870n
preplace netloc axis_4s_combine_decimate_M_AXIS_CH1 1 2 1 860 170n
preplace netloc axis_4s_combine_decimate_M_AXIS_CH2 1 2 1 920 310n
preplace netloc axis_4s_combine_decimate_M_AXIS_CH3 1 2 1 920 430n
preplace netloc axis_4s_combine_decimate_M_AXIS_CH4 1 2 1 910 450n
preplace netloc axis_4s_combine_decimate_M_AXIS_DFREQ_DEC 1 2 3 820 -130 1460J 50 1730
preplace netloc axis_4s_combine_decimate_M_AXIS_DFREQ_DEC2 1 2 1 880 490n
preplace netloc axis_FIR_CH1_M_AXIS 1 3 2 1380 190 1720
preplace netloc axis_FIR_CH2_M_AXIS 1 3 2 1410 280 N
preplace netloc axis_FIR_CH3_M_AXIS 1 3 2 1430 300 N
preplace netloc axis_FIR_CH4_M_AXIS 1 3 2 1460 320 N
preplace netloc controller_dfreq_M_AXIS_CONTROL2 1 1 3 350 900 NJ 900 1360
preplace netloc lms_phase_amplitude_detector_0_M_AXIS_SIGNAL 1 0 2 -20J 410 300J
preplace netloc axis_FIR_CH1_M_AXIS2 1 3 4 NJ 200 N 200 NJ 200 NJ
preplace netloc axis_FIR_CH2_M_AXIS2 1 3 4 1390J 40 1730 -130 2160J -120 2480J
preplace netloc axis_FIR_CH3_M_AXIS2 1 3 4 1400J 30 1720 -140 NJ -140 2500J
preplace netloc axis_FIR_CH4_M_AXIS2 1 3 4 NJ 620 N 620 NJ 620 NJ
preplace netloc controller_dfreq_M_AXIS_CONTROL 1 3 1 1400 750n
preplace netloc axis_splitter_0_M_AXIS 1 4 1 1740 400n
preplace netloc axis_splitter_0_M_AXIS2 1 4 3 NJ 760 NJ 760 2530J
levelinfo -pg 1 -50 150 600 1150 1590 1990 2330 2550
pagesize -pg 1 -db -bbox -sgen -200 -160 3050 1260
"
}

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: PS
proc create_hier_cell_PS { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_PS() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:bram_rtl:1.0 BRAM_PORTA_PACPLL

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR

  create_bd_intf_pin -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:bram_rtl:1.0 BRAM_PORTA_SPMC


  # Create pins
  create_bd_pin -dir O -from 1023 -to 0 cfg_data_reg_0
  create_bd_pin -dir O -from 1023 -to 0 cfg_data_reg_1
  create_bd_pin -dir O -from 1023 -to 0 cfg_data_reg_2
  create_bd_pin -dir O -from 1023 -to 0 cfg_data_reg_3
  create_bd_pin -dir I -from 31 -to 0 gpio_io_0_x1
  create_bd_pin -dir I -from 31 -to 0 gpio_io_0_x2
  create_bd_pin -dir I -from 31 -to 0 gpio_io_1_x3
  create_bd_pin -dir I -from 31 -to 0 gpio_io_1_x4
  create_bd_pin -dir I -from 31 -to 0 gpio_io_2_x5
  create_bd_pin -dir I -from 31 -to 0 gpio_io_2_x6
  create_bd_pin -dir I -from 31 -to 0 gpio_io_3_x7
  create_bd_pin -dir I -from 31 -to 0 gpio_io_3_x8
  create_bd_pin -dir I -from 31 -to 0 gpio_io_4_x9
  create_bd_pin -dir I -from 31 -to 0 gpio_io_4_x10
  create_bd_pin -dir I -from 31 -to 0 gpio_io_5_x11
  create_bd_pin -dir I -from 31 -to 0 gpio_io_5_x12
  create_bd_pin -dir I -from 31 -to 0 gpio_io_7_x15
  create_bd_pin -dir I -from 31 -to 0 gpio_io_7_x16
  create_bd_pin -dir I -from 31 -to 0 gpio_io_8_x17
  create_bd_pin -dir I -from 31 -to 0 gpio_io_8_x18
  create_bd_pin -dir I -from 31 -to 0 gpio_io_6_x13
  create_bd_pin -dir I -from 31 -to 0 gpio_io_6_x14
  create_bd_pin -dir I -from 31 -to 0 gpio_io_9_x19
  create_bd_pin -dir I -from 31 -to 0 gpio2_io_9_x20
  create_bd_pin -dir I -from 15 -to 0 gpio_io_10_x21
  create_bd_pin -dir I -from 31 -to 0 gpio_io_10_x22

  # Create instance: axi_bram_reader_0, and set properties
  set axi_bram_reader_0 [ create_bd_cell -type ip -vlnv anton-potocnik:user:axi_bram_reader:1.0 axi_bram_reader_0 ]
  set_property -dict [list \
    CONFIG.BRAM_ADDR_WIDTH {14} \
    CONFIG.C_S00_AXI_ADDR_WIDTH {16} \
  ] $axi_bram_reader_0


  # Create instance: axi_cfg_register_0, and set properties
  set axi_cfg_register_0 [ create_bd_cell -type ip -vlnv pavel-demin:user:axi_cfg_register:1.0 axi_cfg_register_0 ]
  set_property -dict [list \
    CONFIG.AXI_ADDR_WIDTH {16} \
    CONFIG.AXI_DATA_WIDTH {32} \
    CONFIG.CFG_DATA_WIDTH {3072} \
  ] $axi_cfg_register_0


  # Create instance: processing_system7_Zynq, and set properties
  set processing_system7_Zynq [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_Zynq ]
  set_property -dict [list \
    CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
    CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
    CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
    CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
    CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
    CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
    CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
    CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
    CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {20.000000} \
    CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
    CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
    CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
    CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
    CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {125.000000} \
    CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
    CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
    CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
    CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
    CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
    CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
    CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
    CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
    CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
    CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
    CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
    CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
    CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
    CONFIG.PCW_CLK0_FREQ {100000000} \
    CONFIG.PCW_CLK1_FREQ {20000000} \
    CONFIG.PCW_CLK2_FREQ {10000000} \
    CONFIG.PCW_CLK3_FREQ {10000000} \
    CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
    CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
    CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
    CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
    CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
    CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
    CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
    CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
    CONFIG.PCW_DM_WIDTH {4} \
    CONFIG.PCW_DQS_WIDTH {4} \
    CONFIG.PCW_DQ_WIDTH {32} \
    CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
    CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
    CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
    CONFIG.PCW_ENET0_GRP_MDIO_IO {EMIO} \
    CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
    CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
    CONFIG.PCW_ENET0_RESET_ENABLE {0} \
    CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_ENET_RESET_ENABLE {1} \
    CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
    CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
    CONFIG.PCW_EN_4K_TIMER {0} \
    CONFIG.PCW_EN_CAN0 {0} \
    CONFIG.PCW_EN_CAN1 {0} \
    CONFIG.PCW_EN_CLK0_PORT {1} \
    CONFIG.PCW_EN_CLK1_PORT {1} \
    CONFIG.PCW_EN_CLK2_PORT {0} \
    CONFIG.PCW_EN_CLK3_PORT {0} \
    CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
    CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
    CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
    CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
    CONFIG.PCW_EN_DDR {1} \
    CONFIG.PCW_EN_EMIO_CAN0 {0} \
    CONFIG.PCW_EN_EMIO_CAN1 {0} \
    CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
    CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
    CONFIG.PCW_EN_EMIO_ENET0 {0} \
    CONFIG.PCW_EN_EMIO_ENET1 {0} \
    CONFIG.PCW_EN_EMIO_GPIO {0} \
    CONFIG.PCW_EN_EMIO_I2C0 {0} \
    CONFIG.PCW_EN_EMIO_I2C1 {0} \
    CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
    CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
    CONFIG.PCW_EN_EMIO_PJTAG {0} \
    CONFIG.PCW_EN_EMIO_SDIO0 {0} \
    CONFIG.PCW_EN_EMIO_SDIO1 {0} \
    CONFIG.PCW_EN_EMIO_SPI0 {1} \
    CONFIG.PCW_EN_EMIO_SPI1 {0} \
    CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
    CONFIG.PCW_EN_EMIO_TRACE {0} \
    CONFIG.PCW_EN_EMIO_TTC0 {1} \
    CONFIG.PCW_EN_EMIO_TTC1 {0} \
    CONFIG.PCW_EN_EMIO_UART0 {0} \
    CONFIG.PCW_EN_EMIO_UART1 {0} \
    CONFIG.PCW_EN_EMIO_WDT {0} \
    CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
    CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
    CONFIG.PCW_EN_ENET0 {1} \
    CONFIG.PCW_EN_ENET1 {0} \
    CONFIG.PCW_EN_GPIO {1} \
    CONFIG.PCW_EN_I2C0 {1} \
    CONFIG.PCW_EN_I2C1 {0} \
    CONFIG.PCW_EN_MODEM_UART0 {0} \
    CONFIG.PCW_EN_MODEM_UART1 {0} \
    CONFIG.PCW_EN_PJTAG {0} \
    CONFIG.PCW_EN_PTP_ENET0 {0} \
    CONFIG.PCW_EN_PTP_ENET1 {0} \
    CONFIG.PCW_EN_QSPI {1} \
    CONFIG.PCW_EN_RST0_PORT {1} \
    CONFIG.PCW_EN_RST1_PORT {0} \
    CONFIG.PCW_EN_RST2_PORT {0} \
    CONFIG.PCW_EN_RST3_PORT {0} \
    CONFIG.PCW_EN_SDIO0 {1} \
    CONFIG.PCW_EN_SDIO1 {0} \
    CONFIG.PCW_EN_SMC {0} \
    CONFIG.PCW_EN_SPI0 {1} \
    CONFIG.PCW_EN_SPI1 {1} \
    CONFIG.PCW_EN_TRACE {0} \
    CONFIG.PCW_EN_TTC0 {1} \
    CONFIG.PCW_EN_TTC1 {0} \
    CONFIG.PCW_EN_UART0 {1} \
    CONFIG.PCW_EN_UART1 {1} \
    CONFIG.PCW_EN_USB0 {1} \
    CONFIG.PCW_EN_USB1 {0} \
    CONFIG.PCW_EN_WDT {0} \
    CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
    CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
    CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
    CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {20} \
    CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
    CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \
    CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
    CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
    CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \
    CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
    CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
    CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \
    CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
    CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
    CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
    CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
    CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
    CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
    CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
    CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
    CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
    CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
    CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
    CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_I2C0_RESET_ENABLE {0} \
    CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
    CONFIG.PCW_I2C_RESET_ENABLE {1} \
    CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
    CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
    CONFIG.PCW_IMPORT_BOARD_PRESET {cfg/red_pitaya.xml} \
    CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
    CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
    CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_0_PULLUP {disabled} \
    CONFIG.PCW_MIO_0_SLEW {slow} \
    CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_10_PULLUP {enabled} \
    CONFIG.PCW_MIO_10_SLEW {slow} \
    CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_11_PULLUP {enabled} \
    CONFIG.PCW_MIO_11_SLEW {slow} \
    CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_12_PULLUP {enabled} \
    CONFIG.PCW_MIO_12_SLEW {slow} \
    CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_13_PULLUP {enabled} \
    CONFIG.PCW_MIO_13_SLEW {slow} \
    CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_14_PULLUP {enabled} \
    CONFIG.PCW_MIO_14_SLEW {slow} \
    CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_15_PULLUP {enabled} \
    CONFIG.PCW_MIO_15_SLEW {slow} \
    CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_16_PULLUP {disabled} \
    CONFIG.PCW_MIO_16_SLEW {fast} \
    CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_17_PULLUP {disabled} \
    CONFIG.PCW_MIO_17_SLEW {fast} \
    CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_18_PULLUP {disabled} \
    CONFIG.PCW_MIO_18_SLEW {fast} \
    CONFIG.PCW_MIO_19_IOTYPE {out} \
    CONFIG.PCW_MIO_19_PULLUP {disabled} \
    CONFIG.PCW_MIO_19_SLEW {fast} \
    CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_1_PULLUP {enabled} \
    CONFIG.PCW_MIO_1_SLEW {slow} \
    CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_20_PULLUP {disabled} \
    CONFIG.PCW_MIO_20_SLEW {fast} \
    CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_21_PULLUP {disabled} \
    CONFIG.PCW_MIO_21_SLEW {fast} \
    CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_22_PULLUP {disabled} \
    CONFIG.PCW_MIO_22_SLEW {fast} \
    CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_23_PULLUP {disabled} \
    CONFIG.PCW_MIO_23_SLEW {fast} \
    CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_24_PULLUP {disabled} \
    CONFIG.PCW_MIO_24_SLEW {fast} \
    CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_25_PULLUP {disabled} \
    CONFIG.PCW_MIO_25_SLEW {fast} \
    CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_26_PULLUP {disabled} \
    CONFIG.PCW_MIO_26_SLEW {fast} \
    CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_27_PULLUP {disabled} \
    CONFIG.PCW_MIO_27_SLEW {fast} \
    CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_28_PULLUP {enabled} \
    CONFIG.PCW_MIO_28_SLEW {fast} \
    CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_29_PULLUP {enabled} \
    CONFIG.PCW_MIO_29_SLEW {fast} \
    CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_2_SLEW {slow} \
    CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_30_PULLUP {enabled} \
    CONFIG.PCW_MIO_30_SLEW {fast} \
    CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_31_PULLUP {enabled} \
    CONFIG.PCW_MIO_31_SLEW {fast} \
    CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_32_PULLUP {enabled} \
    CONFIG.PCW_MIO_32_SLEW {fast} \
    CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_33_PULLUP {enabled} \
    CONFIG.PCW_MIO_33_SLEW {fast} \
    CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_34_PULLUP {enabled} \
    CONFIG.PCW_MIO_34_SLEW {fast} \
    CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_35_PULLUP {enabled} \
    CONFIG.PCW_MIO_35_SLEW {fast} \
    CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_36_PULLUP {enabled} \
    CONFIG.PCW_MIO_36_SLEW {fast} \
    CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_37_PULLUP {enabled} \
    CONFIG.PCW_MIO_37_SLEW {fast} \
    CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_38_PULLUP {enabled} \
    CONFIG.PCW_MIO_38_SLEW {fast} \
    CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_39_PULLUP {enabled} \
    CONFIG.PCW_MIO_39_SLEW {fast} \
    CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_3_SLEW {slow} \
    CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_40_PULLUP {enabled} \
    CONFIG.PCW_MIO_40_SLEW {slow} \
    CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_41_PULLUP {enabled} \
    CONFIG.PCW_MIO_41_SLEW {slow} \
    CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_42_PULLUP {enabled} \
    CONFIG.PCW_MIO_42_SLEW {slow} \
    CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_43_PULLUP {enabled} \
    CONFIG.PCW_MIO_43_SLEW {slow} \
    CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_44_PULLUP {enabled} \
    CONFIG.PCW_MIO_44_SLEW {slow} \
    CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_45_PULLUP {enabled} \
    CONFIG.PCW_MIO_45_SLEW {slow} \
    CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_46_PULLUP {enabled} \
    CONFIG.PCW_MIO_46_SLEW {slow} \
    CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_47_PULLUP {enabled} \
    CONFIG.PCW_MIO_47_SLEW {slow} \
    CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_48_PULLUP {enabled} \
    CONFIG.PCW_MIO_48_SLEW {slow} \
    CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_49_PULLUP {enabled} \
    CONFIG.PCW_MIO_49_SLEW {slow} \
    CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_4_SLEW {slow} \
    CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_50_PULLUP {enabled} \
    CONFIG.PCW_MIO_50_SLEW {slow} \
    CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_51_PULLUP {enabled} \
    CONFIG.PCW_MIO_51_SLEW {slow} \
    CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_52_PULLUP {enabled} \
    CONFIG.PCW_MIO_52_SLEW {slow} \
    CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 2.5V} \
    CONFIG.PCW_MIO_53_PULLUP {enabled} \
    CONFIG.PCW_MIO_53_SLEW {slow} \
    CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_5_SLEW {slow} \
    CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_6_SLEW {slow} \
    CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_7_SLEW {slow} \
    CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_8_SLEW {slow} \
    CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
    CONFIG.PCW_MIO_9_PULLUP {enabled} \
    CONFIG.PCW_MIO_9_SLEW {slow} \
    CONFIG.PCW_MIO_PRIMITIVE {54} \
    CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#UART 1#UART 1#SPI 1#SPI 1#SPI 1#SPI 1#UART 0#UART 0#Enet 0#Enet\
0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#GPIO#I2C\
0#I2C 0#GPIO#GPIO} \
    CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#tx#rx#mosi#miso#sclk#ss[0]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#wp#reset#gpio[49]#scl#sda#gpio[52]#gpio[53]}\
\
    CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
    CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
    CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
    CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
    CONFIG.PCW_NAND_CYCLES_T_AR {1} \
    CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
    CONFIG.PCW_NAND_CYCLES_T_RC {11} \
    CONFIG.PCW_NAND_CYCLES_T_REA {1} \
    CONFIG.PCW_NAND_CYCLES_T_RR {1} \
    CONFIG.PCW_NAND_CYCLES_T_WC {11} \
    CONFIG.PCW_NAND_CYCLES_T_WP {1} \
    CONFIG.PCW_NOR_CS0_T_CEOE {1} \
    CONFIG.PCW_NOR_CS0_T_PC {1} \
    CONFIG.PCW_NOR_CS0_T_RC {11} \
    CONFIG.PCW_NOR_CS0_T_TR {1} \
    CONFIG.PCW_NOR_CS0_T_WC {11} \
    CONFIG.PCW_NOR_CS0_T_WP {1} \
    CONFIG.PCW_NOR_CS0_WE_TIME {0} \
    CONFIG.PCW_NOR_CS1_T_CEOE {1} \
    CONFIG.PCW_NOR_CS1_T_PC {1} \
    CONFIG.PCW_NOR_CS1_T_RC {11} \
    CONFIG.PCW_NOR_CS1_T_TR {1} \
    CONFIG.PCW_NOR_CS1_T_WC {11} \
    CONFIG.PCW_NOR_CS1_T_WP {1} \
    CONFIG.PCW_NOR_CS1_WE_TIME {0} \
    CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
    CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
    CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
    CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
    CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
    CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
    CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
    CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
    CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
    CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
    CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
    CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
    CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
    CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
    CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.080} \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.063} \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.057} \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.068} \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.047} \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.025} \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.017} \
    CONFIG.PCW_PACKAGE_NAME {clg400} \
    CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
    CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
    CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
    CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
    CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 2.5V} \
    CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
    CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
    CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
    CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
    CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
    CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
    CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
    CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {125} \
    CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
    CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
    CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} \
    CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
    CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
    CONFIG.PCW_SD0_GRP_WP_IO {MIO 47} \
    CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
    CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
    CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
    CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
    CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
    CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
    CONFIG.PCW_SMC_CYCLE_T0 {NA} \
    CONFIG.PCW_SMC_CYCLE_T1 {NA} \
    CONFIG.PCW_SMC_CYCLE_T2 {NA} \
    CONFIG.PCW_SMC_CYCLE_T3 {NA} \
    CONFIG.PCW_SMC_CYCLE_T4 {NA} \
    CONFIG.PCW_SMC_CYCLE_T5 {NA} \
    CONFIG.PCW_SMC_CYCLE_T6 {NA} \
    CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
    CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
    CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
    CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_SPI0_SPI0_IO {EMIO} \
    CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
    CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
    CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
    CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
    CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_SPI1_SPI1_IO {MIO 10 .. 15} \
    CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
    CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
    CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
    CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
    CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
    CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
    CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
    CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
    CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
    CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
    CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
    CONFIG.PCW_UART0_BAUD_RATE {115200} \
    CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
    CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
    CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
    CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
    CONFIG.PCW_UART1_BAUD_RATE {115200} \
    CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
    CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
    CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \
    CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
    CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
    CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
    CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
    CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
    CONFIG.PCW_UIPARAM_DDR_AL {0} \
    CONFIG.PCW_UIPARAM_DDR_BL {8} \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25} \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25} \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25} \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25} \
    CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {54.563} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {54.563} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {54.563} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {54.563} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {101.239} \
    CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {79.5025} \
    CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {60.536} \
    CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {71.7715} \
    CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \
    CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {104.5365} \
    CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {70.676} \
    CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {59.1615} \
    CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
    CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {81.319} \
    CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
    CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
    CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
    CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
    CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
    CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
    CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
    CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
    CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
    CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
    CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
    CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
    CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
    CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
    CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_USB0_RESET_ENABLE {1} \
    CONFIG.PCW_USB0_RESET_IO {MIO 48} \
    CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
    CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_USB_RESET_ENABLE {1} \
    CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
    CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
    CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
    CONFIG.PCW_USE_AXI_NONSECURE {0} \
    CONFIG.PCW_USE_CORESIGHT {0} \
    CONFIG.PCW_USE_CROSS_TRIGGER {0} \
    CONFIG.PCW_USE_CR_FABRIC {1} \
    CONFIG.PCW_USE_DDR_BYPASS {0} \
    CONFIG.PCW_USE_DEBUG {0} \
    CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
    CONFIG.PCW_USE_DMA0 {0} \
    CONFIG.PCW_USE_DMA1 {0} \
    CONFIG.PCW_USE_DMA2 {0} \
    CONFIG.PCW_USE_DMA3 {0} \
    CONFIG.PCW_USE_EXPANDED_IOP {0} \
    CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
    CONFIG.PCW_USE_HIGH_OCM {0} \
    CONFIG.PCW_USE_M_AXI_GP0 {1} \
    CONFIG.PCW_USE_M_AXI_GP1 {1} \
    CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
    CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
    CONFIG.PCW_USE_S_AXI_ACP {1} \
    CONFIG.PCW_USE_S_AXI_GP0 {0} \
    CONFIG.PCW_USE_S_AXI_GP1 {0} \
    CONFIG.PCW_USE_S_AXI_HP0 {0} \
    CONFIG.PCW_USE_S_AXI_HP1 {0} \
    CONFIG.PCW_USE_S_AXI_HP2 {0} \
    CONFIG.PCW_USE_S_AXI_HP3 {0} \
    CONFIG.PCW_USE_TRACE {0} \
    CONFIG.PCW_VALUE_SILVERSION {3} \
    CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
    CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
  ] $processing_system7_Zynq


  # Create instance: rst_ps7_0_125M, and set properties
  set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]

  # Create instance: xlslice_cfg_reg0, and set properties
  set xlslice_cfg_reg0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_cfg_reg0 ]
  set_property -dict [list \
    CONFIG.DIN_FROM {1023} \
    CONFIG.DIN_WIDTH {3072} \
    CONFIG.DOUT_WIDTH {1024} \
  ] $xlslice_cfg_reg0


  # Create instance: xlslice_cfg_reg1, and set properties
  set xlslice_cfg_reg1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_cfg_reg1 ]
  set_property -dict [list \
    CONFIG.DIN_FROM {2047} \
    CONFIG.DIN_TO {1024} \
    CONFIG.DIN_WIDTH {3072} \
    CONFIG.DOUT_WIDTH {1024} \
  ] $xlslice_cfg_reg1


  # Create instance: xlslice_cfg_reg2, and set properties
  set xlslice_cfg_reg2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_cfg_reg2 ]
  set_property -dict [list \
    CONFIG.DIN_FROM {3071} \
    CONFIG.DIN_TO {2048} \
    CONFIG.DIN_WIDTH {3072} \
    CONFIG.DOUT_WIDTH {1024} \
  ] $xlslice_cfg_reg2


  # Create instance: xlslice_cfg_reg3, and set properties
  set xlslice_cfg_reg3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_cfg_reg3 ]
  set_property -dict [list \
    CONFIG.DIN_FROM {1023} \
    CONFIG.DIN_TO {0} \
    CONFIG.DIN_WIDTH {3072} \
    CONFIG.DOUT_WIDTH {1024} \
  ] $xlslice_cfg_reg3


  # Create instance: axi_gpio_0, and set properties
  set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_0


  # Create instance: axi_gpio_1, and set properties
  set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_1


  # Create instance: axi_gpio_2, and set properties
  set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_2


  # Create instance: axi_gpio_3, and set properties
  set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_3


  # Create instance: axi_gpio_4, and set properties
  set axi_gpio_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_4 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_4


  # Create instance: axi_gpio_5, and set properties
  set axi_gpio_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_5 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_5


  # Create instance: axi_interconnect_0, and set properties
  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
  set_property -dict [list \
    CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
    CONFIG.M06_HAS_DATA_FIFO {1} \
    CONFIG.M13_HAS_DATA_FIFO {1} \
    CONFIG.NUM_MI {15} \
    CONFIG.NUM_SI {2} \
  ] $axi_interconnect_0


  # Create instance: axi_gpio_7, and set properties
  set axi_gpio_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_7 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_7


  # Create instance: axi_gpio_8, and set properties
  set axi_gpio_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_8 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_8


  # Create instance: axi_gpio_6, and set properties
  set axi_gpio_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_6 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_6


  # Create instance: axi_cfg_register_1, and set properties
  set axi_cfg_register_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axi_cfg_register:1.0 axi_cfg_register_1 ]
  set_property -dict [list \
    CONFIG.AXI_ADDR_WIDTH {16} \
    CONFIG.AXI_DATA_WIDTH {32} \
    CONFIG.CFG_DATA_WIDTH {3072} \
  ] $axi_cfg_register_1


  # Create instance: axi_gpio_9, and set properties
  set axi_gpio_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_9 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_9


  # Create instance: axi_bram_reader_1, and set properties
  set axi_bram_reader_1 [ create_bd_cell -type ip -vlnv anton-potocnik:user:axi_bram_reader:1.0 axi_bram_reader_1 ]
  set_property -dict [list \
    CONFIG.BRAM_ADDR_WIDTH {14} \
    CONFIG.C_S00_AXI_ADDR_WIDTH {16} \
  ] $axi_bram_reader_1


  # Create instance: axi_gpio_10, and set properties
  set axi_gpio_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_10 ]
  set_property -dict [list \
    CONFIG.C_ALL_INPUTS {1} \
    CONFIG.C_ALL_INPUTS_2 {1} \
    CONFIG.C_IS_DUAL {1} \
  ] $axi_gpio_10


  # Create interface connections
  connect_bd_intf_net -intf_net axi_bram_reader_0_BRAM_PORTA [get_bd_intf_pins BRAM_PORTA_PACPLL] [get_bd_intf_pins axi_bram_reader_0/BRAM_PORTA]
  connect_bd_intf_net -intf_net axi_bram_reader_1_BRAM_PORTA [get_bd_intf_pins BRAM_PORTA_SPMC] [get_bd_intf_pins axi_bram_reader_1/BRAM_PORTA]
  connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_cfg_register_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_gpio_4/S_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_bram_reader_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins axi_gpio_5/S_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins axi_gpio_6/S_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_pins axi_interconnect_0/M09_AXI] [get_bd_intf_pins axi_gpio_7/S_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_pins axi_interconnect_0/M10_AXI] [get_bd_intf_pins axi_gpio_8/S_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_pins axi_interconnect_0/M11_AXI] [get_bd_intf_pins axi_gpio_9/S_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M12_AXI [get_bd_intf_pins axi_cfg_register_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M12_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M13_AXI [get_bd_intf_pins axi_bram_reader_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M13_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_0_M14_AXI [get_bd_intf_pins axi_interconnect_0/M14_AXI] [get_bd_intf_pins axi_gpio_10/S_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_pins DDR] [get_bd_intf_pins processing_system7_Zynq/DDR]
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_pins FIXED_IO] [get_bd_intf_pins processing_system7_Zynq/FIXED_IO]
  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_Zynq/M_AXI_GP0]
  connect_bd_intf_net -intf_net processing_system7_Zynq_M_AXI_GP1 [get_bd_intf_pins processing_system7_Zynq/M_AXI_GP1] [get_bd_intf_pins axi_interconnect_0/S01_AXI]

  # Create port connections
  connect_bd_net -net Net [get_bd_pins processing_system7_Zynq/FCLK_CLK0] [get_bd_pins axi_bram_reader_0/s00_axi_aclk] [get_bd_pins axi_cfg_register_0/aclk] [get_bd_pins processing_system7_Zynq/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_Zynq/S_AXI_ACP_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_4/s_axi_aclk] [get_bd_pins axi_gpio_5/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_gpio_7/s_axi_aclk] [get_bd_pins axi_gpio_8/s_axi_aclk] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] [get_bd_pins axi_gpio_6/s_axi_aclk] [get_bd_pins axi_cfg_register_1/aclk] [get_bd_pins axi_interconnect_0/M12_ACLK] [get_bd_pins axi_gpio_9/s_axi_aclk] [get_bd_pins axi_interconnect_0/M13_ACLK] [get_bd_pins axi_bram_reader_1/s00_axi_aclk] [get_bd_pins axi_interconnect_0/M14_ACLK] [get_bd_pins axi_gpio_10/s_axi_aclk] [get_bd_pins processing_system7_Zynq/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK]
  connect_bd_net -net axi_cfg_register_0_cfg_data [get_bd_pins axi_cfg_register_0/cfg_data] [get_bd_pins xlslice_cfg_reg2/Din] [get_bd_pins xlslice_cfg_reg1/Din] [get_bd_pins xlslice_cfg_reg0/Din]
  connect_bd_net -net axi_cfg_register_1_cfg_data [get_bd_pins axi_cfg_register_1/cfg_data] [get_bd_pins xlslice_cfg_reg3/Din]
  connect_bd_net -net gpio2_io_i1_1 [get_bd_pins gpio_io_1_x4] [get_bd_pins axi_gpio_1/gpio2_io_i]
  connect_bd_net -net gpio2_io_i1_2 [get_bd_pins gpio_io_6_x14] [get_bd_pins axi_gpio_6/gpio2_io_i]
  connect_bd_net -net gpio2_io_i3_1 [get_bd_pins gpio_io_3_x8] [get_bd_pins axi_gpio_3/gpio2_io_i]
  connect_bd_net -net gpio2_io_i4_1 [get_bd_pins gpio_io_2_x6] [get_bd_pins axi_gpio_2/gpio2_io_i]
  connect_bd_net -net gpio2_io_i_1 [get_bd_pins gpio_io_0_x2] [get_bd_pins axi_gpio_0/gpio2_io_i]
  connect_bd_net -net gpio2_io_i_2 [get_bd_pins gpio_io_4_x10] [get_bd_pins axi_gpio_4/gpio2_io_i]
  connect_bd_net -net gpio2_io_i_3 [get_bd_pins gpio_io_5_x12] [get_bd_pins axi_gpio_5/gpio2_io_i]
  connect_bd_net -net gpio2_io_i_4 [get_bd_pins gpio2_io_9_x20] [get_bd_pins axi_gpio_9/gpio2_io_i]
  connect_bd_net -net gpio2_io_i_5 [get_bd_pins gpio_io_7_x16] [get_bd_pins axi_gpio_7/gpio2_io_i]
  connect_bd_net -net gpio2_io_i_6 [get_bd_pins gpio_io_8_x18] [get_bd_pins axi_gpio_8/gpio2_io_i]
  connect_bd_net -net gpio2_io_i_7 [get_bd_pins gpio_io_10_x22] [get_bd_pins axi_gpio_10/gpio2_io_i]
  connect_bd_net -net gpio_io_i1_1 [get_bd_pins gpio_io_1_x3] [get_bd_pins axi_gpio_1/gpio_io_i]
  connect_bd_net -net gpio_io_i1_2 [get_bd_pins gpio_io_7_x15] [get_bd_pins axi_gpio_7/gpio_io_i]
  connect_bd_net -net gpio_io_i1_3 [get_bd_pins gpio_io_8_x17] [get_bd_pins axi_gpio_8/gpio_io_i]
  connect_bd_net -net gpio_io_i3_1 [get_bd_pins gpio_io_3_x7] [get_bd_pins axi_gpio_3/gpio_io_i]
  connect_bd_net -net gpio_io_i4_1 [get_bd_pins gpio_io_2_x5] [get_bd_pins axi_gpio_2/gpio_io_i]
  connect_bd_net -net gpio_io_i_1 [get_bd_pins gpio_io_0_x1] [get_bd_pins axi_gpio_0/gpio_io_i]
  connect_bd_net -net gpio_io_i_2 [get_bd_pins gpio_io_4_x9] [get_bd_pins axi_gpio_4/gpio_io_i]
  connect_bd_net -net gpio_io_i_3 [get_bd_pins gpio_io_5_x11] [get_bd_pins axi_gpio_5/gpio_io_i]
  connect_bd_net -net gpio_io_i_4 [get_bd_pins gpio_io_6_x13] [get_bd_pins axi_gpio_6/gpio_io_i]
  connect_bd_net -net gpio_io_i_5 [get_bd_pins gpio_io_9_x19] [get_bd_pins axi_gpio_9/gpio_io_i]
  connect_bd_net -net gpio_io_i_6 [get_bd_pins gpio_io_10_x21] [get_bd_pins axi_gpio_10/gpio_io_i]
  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_Zynq/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in]
  connect_bd_net -net rst_ps7_0_125M_interconnect_aresetn [get_bd_pins rst_ps7_0_125M/interconnect_aresetn] [get_bd_pins axi_interconnect_0/ARESETN]
  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins axi_bram_reader_0/s00_axi_aresetn] [get_bd_pins axi_cfg_register_0/aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_4/s_axi_aresetn] [get_bd_pins axi_gpio_5/s_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_gpio_7/s_axi_aresetn] [get_bd_pins axi_gpio_8/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_gpio_6/s_axi_aresetn] [get_bd_pins axi_cfg_register_1/aresetn] [get_bd_pins axi_interconnect_0/M12_ARESETN] [get_bd_pins axi_gpio_9/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M13_ARESETN] [get_bd_pins axi_bram_reader_1/s00_axi_aresetn] [get_bd_pins axi_interconnect_0/M14_ARESETN] [get_bd_pins axi_gpio_10/s_axi_aresetn] [get_bd_pins axi_interconnect_0/S01_ARESETN]
  connect_bd_net -net xlslice_cfg_reg0_Dout [get_bd_pins xlslice_cfg_reg0/Dout] [get_bd_pins cfg_data_reg_0]
  connect_bd_net -net xlslice_cfg_reg1_Dout [get_bd_pins xlslice_cfg_reg1/Dout] [get_bd_pins cfg_data_reg_1]
  connect_bd_net -net xlslice_cfg_reg2_Dout [get_bd_pins xlslice_cfg_reg2/Dout] [get_bd_pins cfg_data_reg_2]
  connect_bd_net -net xlslice_cfg_reg3_Dout [get_bd_pins xlslice_cfg_reg3/Dout] [get_bd_pins cfg_data_reg_3]

  # Perform GUI Layout
  regenerate_bd_layout -hierarchy [get_bd_cells /PS] -layout_string {
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"1.0",
   "Default View_TopLeft":"1003,664",
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
#  -string -flagsOSRD
preplace port BRAM_PORTA_PACPLL -pg 1 -lvl 8 -x 2770 -y 1470 -defaultsOSRD
preplace port DDR -pg 1 -lvl 8 -x 2770 -y 550 -defaultsOSRD
preplace port FIXED_IO -pg 1 -lvl 8 -x 2770 -y 660 -defaultsOSRD
preplace port BRAM_PORTA_SPMC -pg 1 -lvl 8 -x 2770 -y 1740 -defaultsOSRD
preplace portBus cfg_data_reg_0 -pg 1 -lvl 8 -x 2770 -y 810 -defaultsOSRD
preplace portBus cfg_data_reg_1 -pg 1 -lvl 8 -x 2770 -y 910 -defaultsOSRD
preplace portBus cfg_data_reg_2 -pg 1 -lvl 8 -x 2770 -y 1010 -defaultsOSRD
preplace portBus cfg_data_reg_3 -pg 1 -lvl 8 -x 2770 -y 1270 -defaultsOSRD
preplace portBus gpio_io_0_x1 -pg 1 -lvl 0 -x -190 -y 480 -defaultsOSRD
preplace portBus gpio_io_0_x2 -pg 1 -lvl 0 -x -190 -y 660 -defaultsOSRD
preplace portBus gpio_io_1_x3 -pg 1 -lvl 0 -x -190 -y 690 -defaultsOSRD
preplace portBus gpio_io_1_x4 -pg 1 -lvl 0 -x -190 -y 830 -defaultsOSRD
preplace portBus gpio_io_2_x5 -pg 1 -lvl 0 -x -190 -y 860 -defaultsOSRD
preplace portBus gpio_io_2_x6 -pg 1 -lvl 0 -x -190 -y 890 -defaultsOSRD
preplace portBus gpio_io_3_x7 -pg 1 -lvl 0 -x -190 -y 920 -defaultsOSRD
preplace portBus gpio_io_3_x8 -pg 1 -lvl 0 -x -190 -y 950 -defaultsOSRD
preplace portBus gpio_io_4_x9 -pg 1 -lvl 0 -x -190 -y 1550 -defaultsOSRD
preplace portBus gpio_io_4_x10 -pg 1 -lvl 0 -x -190 -y 1900 -defaultsOSRD
preplace portBus gpio_io_5_x11 -pg 1 -lvl 0 -x -190 -y 1930 -defaultsOSRD
preplace portBus gpio_io_5_x12 -pg 1 -lvl 0 -x -190 -y 2040 -defaultsOSRD
preplace portBus gpio_io_7_x15 -pg 1 -lvl 0 -x -190 -y 2580 -defaultsOSRD
preplace portBus gpio_io_7_x16 -pg 1 -lvl 0 -x -190 -y 2760 -defaultsOSRD
preplace portBus gpio_io_8_x17 -pg 1 -lvl 0 -x -190 -y 2260 -defaultsOSRD
preplace portBus gpio_io_8_x18 -pg 1 -lvl 0 -x -190 -y 2420 -defaultsOSRD
preplace portBus gpio_io_6_x13 -pg 1 -lvl 0 -x -190 -y 2070 -defaultsOSRD
preplace portBus gpio_io_6_x14 -pg 1 -lvl 0 -x -190 -y 2230 -defaultsOSRD
preplace portBus gpio_io_9_x19 -pg 1 -lvl 0 -x -190 -y 720 -defaultsOSRD
preplace portBus gpio2_io_9_x20 -pg 1 -lvl 0 -x -190 -y 320 -defaultsOSRD
preplace portBus gpio_io_10_x21 -pg 1 -lvl 0 -x -190 -y 270 -defaultsOSRD
preplace portBus gpio_io_10_x22 -pg 1 -lvl 0 -x -190 -y 2320 -defaultsOSRD
preplace inst axi_bram_reader_0 -pg 1 -lvl 6 -x 2360 -y 1470 -defaultsOSRD
preplace inst axi_cfg_register_0 -pg 1 -lvl 6 -x 2360 -y 920 -defaultsOSRD
preplace inst processing_system7_Zynq -pg 1 -lvl 2 -x 580 -y 1000 -defaultsOSRD
preplace inst rst_ps7_0_125M -pg 1 -lvl 1 -x 160 -y 1440 -defaultsOSRD
preplace inst xlslice_cfg_reg0 -pg 1 -lvl 7 -x 2620 -y 810 -defaultsOSRD
preplace inst xlslice_cfg_reg1 -pg 1 -lvl 7 -x 2620 -y 910 -defaultsOSRD
preplace inst xlslice_cfg_reg2 -pg 1 -lvl 7 -x 2620 -y 1010 -defaultsOSRD
preplace inst xlslice_cfg_reg3 -pg 1 -lvl 7 -x 2620 -y 1270 -defaultsOSRD
preplace inst axi_gpio_0 -pg 1 -lvl 5 -x 1870 -y 440 -defaultsOSRD
preplace inst axi_gpio_1 -pg 1 -lvl 5 -x 1870 -y 630 -defaultsOSRD
preplace inst axi_gpio_2 -pg 1 -lvl 5 -x 1870 -y 860 -defaultsOSRD
preplace inst axi_gpio_3 -pg 1 -lvl 5 -x 1870 -y 1040 -defaultsOSRD
preplace inst axi_gpio_4 -pg 1 -lvl 5 -x 1870 -y 1360 -defaultsOSRD
preplace inst axi_gpio_5 -pg 1 -lvl 5 -x 1870 -y 1520 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 4 -x 1440 -y 1290 -defaultsOSRD
preplace inst axi_gpio_7 -pg 1 -lvl 5 -x 1870 -y 1840 -defaultsOSRD
preplace inst axi_gpio_8 -pg 1 -lvl 5 -x 1870 -y 2000 -defaultsOSRD
preplace inst axi_gpio_6 -pg 1 -lvl 5 -x 1870 -y 1680 -defaultsOSRD
preplace inst axi_cfg_register_1 -pg 1 -lvl 6 -x 2360 -y 1190 -defaultsOSRD
preplace inst axi_gpio_9 -pg 1 -lvl 5 -x 1870 -y 1200 -defaultsOSRD
preplace inst axi_bram_reader_1 -pg 1 -lvl 6 -x 2360 -y 1740 -defaultsOSRD
preplace inst axi_gpio_10 -pg 1 -lvl 5 -x 1870 -y 2210 -defaultsOSRD
preplace netloc Net 1 0 6 -20 1030 370 820 800 950 1290 860 1670 530 2210
preplace netloc axi_cfg_register_0_cfg_data 1 6 1 2500 810n
preplace netloc axi_cfg_register_1_cfg_data 1 6 1 2500 1190n
preplace netloc gpio2_io_i1_1 1 0 6 -170J 710 NJ 710 NJ 710 1060 300 NJ 300 2130
preplace netloc gpio2_io_i1_2 1 0 6 -70J 720 NJ 720 NJ 720 1070 310 NJ 310 2090
preplace netloc gpio2_io_i3_1 1 0 6 -110J 730 NJ 730 NJ 730 1080 320 NJ 320 2110
preplace netloc gpio2_io_i4_1 1 0 6 -80J 790 NJ 790 820J 930 1160 760 NJ 760 2050
preplace netloc gpio2_io_i_1 1 0 6 -170J 470 NJ 470 NJ 470 1010 250 NJ 250 2070
preplace netloc gpio2_io_i_2 1 0 6 -120J 500 NJ 500 NJ 500 1040 280 NJ 280 2150
preplace netloc gpio2_io_i_3 1 0 6 -60J 740 NJ 740 NJ 740 1090 330 NJ 330 2060
preplace netloc gpio2_io_i_4 1 0 6 -70J 510 NJ 510 NJ 510 1050 290 NJ 290 2140
preplace netloc gpio2_io_i_5 1 0 6 NJ 2760 NJ 2760 NJ 2760 N 2760 NJ 2760 2120
preplace netloc gpio2_io_i_6 1 0 6 NJ 2420 NJ 2420 NJ 2420 N 2420 NJ 2420 2070
preplace netloc gpio_io_i1_1 1 0 6 -140J 760 NJ 760 NJ 760 1110 360 1680J 340 2120
preplace netloc gpio_io_i1_2 1 0 6 NJ 2580 NJ 2580 NJ 2580 N 2580 NJ 2580 2010
preplace netloc gpio_io_i1_3 1 0 6 NJ 2260 NJ 2260 NJ 2260 1200 2120 NJ 2120 2050
preplace netloc gpio_io_i3_1 1 0 6 -90J 750 NJ 750 NJ 750 1100 350 NJ 350 2080
preplace netloc gpio_io_i4_1 1 0 6 -100J 780 NJ 780 NJ 780 1130 730 NJ 730 2010
preplace netloc gpio_io_i_1 1 0 6 NJ 480 NJ 480 NJ 480 1020 260 NJ 260 2010
preplace netloc gpio_io_i_2 1 0 6 -160J 450 NJ 450 NJ 450 990 230 NJ 230 2100
preplace netloc gpio_io_i_3 1 0 6 NJ 1930 NJ 1930 NJ 1930 990 1720 1700J 770 2030
preplace netloc gpio_io_i_4 1 0 6 -130J 460 NJ 460 NJ 460 1000 240 NJ 240 2040
preplace netloc gpio_io_i_5 1 0 6 -150J 770 NJ 770 NJ 770 1120 720 NJ 720 2020
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 3 -30 800 NJ 800 790
preplace netloc rst_ps7_0_125M_interconnect_aresetn 1 1 3 340J 810 810 940 990
preplace netloc rst_ps7_0_125M_peripheral_aresetn 1 1 5 NJ 1480 N 1480 1270 850 1680 540 2180
preplace netloc xlslice_cfg_reg0_Dout 1 7 1 N 810
preplace netloc xlslice_cfg_reg1_Dout 1 7 1 N 910
preplace netloc xlslice_cfg_reg2_Dout 1 7 1 N 1010
preplace netloc xlslice_cfg_reg3_Dout 1 7 1 N 1270
preplace netloc gpio_io_i_6 1 0 6 -60J 490 NJ 490 NJ 490 1030 270 NJ 270 2160
preplace netloc gpio2_io_i_7 1 0 6 NJ 2320 NJ 2320 NJ 2320 N 2320 NJ 2320 2040
preplace netloc axi_bram_reader_0_BRAM_PORTA 1 6 2 N 1470 N
preplace netloc axi_interconnect_0_M00_AXI 1 4 2 1620 950 2170
preplace netloc axi_interconnect_0_M01_AXI 1 4 1 1590 420n
preplace netloc axi_interconnect_0_M02_AXI 1 4 1 1600 610n
preplace netloc axi_interconnect_0_M03_AXI 1 4 1 1630 840n
preplace netloc axi_interconnect_0_M04_AXI 1 4 1 1710 1020n
preplace netloc axi_interconnect_0_M05_AXI 1 4 1 1730 1250n
preplace netloc axi_interconnect_0_M06_AXI 1 4 2 1640 2090 2200
preplace netloc axi_interconnect_0_M07_AXI 1 4 1 1710 1290n
preplace netloc axi_interconnect_0_M08_AXI 1 4 1 1690 1310n
preplace netloc axi_interconnect_0_M09_AXI 1 4 1 1630 1330n
preplace netloc axi_interconnect_0_M10_AXI 1 4 1 1620 1350n
preplace netloc axi_interconnect_0_M11_AXI 1 4 1 1720 1180n
preplace netloc processing_system7_0_DDR 1 2 6 NJ 900 1140 740 NJ 740 NJ 740 N 740 2740
preplace netloc processing_system7_0_FIXED_IO 1 2 6 NJ 920 1150 750 NJ 750 NJ 750 N 750 2750
preplace netloc processing_system7_0_M_AXI_GP0 1 2 2 820 960 1170
preplace netloc axi_interconnect_0_M13_AXI 1 4 2 1600J 2110 2220
preplace netloc axi_bram_reader_1_BRAM_PORTA 1 6 2 NJ 1740 NJ
preplace netloc axi_interconnect_0_M14_AXI 1 4 1 1590 1430n
preplace netloc processing_system7_Zynq_M_AXI_GP1 1 2 2 NJ 1000 1280
preplace netloc axi_interconnect_0_M12_AXI 1 4 2 1610 2100 2190J
levelinfo -pg 1 -190 160 580 970 1440 1870 2360 2620 2770
pagesize -pg 1 -db -bbox -sgen -380 -40 4030 4620
"
}

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: PAC_PLL
proc create_hier_cell_PAC_PLL { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_PAC_PLL() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_AC16

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_ACDC

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL2

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_CONTROL3

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_LockInX

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_LockInY

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_PASS2

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_PASS3

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_S01

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SC

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SIGNAL

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_S1

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS2


  # Create pins
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_Aout_tdata
  create_bd_pin -dir O -from 31 -to 0 M_AXIS_Bout_tdata
  create_bd_pin -dir I -type clk aclk
  create_bd_pin -dir I -from 1023 -to 0 cfg
  create_bd_pin -dir I -from 1023 -to 0 cfg1
  create_bd_pin -dir O -from 31 -to 0 dbg_m
  create_bd_pin -dir O -from 31 -to 0 dbg_mdc
  create_bd_pin -dir O enable
  create_bd_pin -dir O enable1
  create_bd_pin -dir O -from 31 -to 0 mon_control
  create_bd_pin -dir O -from 31 -to 0 mon_control1
  create_bd_pin -dir O -from 31 -to 0 mon_control_B
  create_bd_pin -dir O -from 31 -to 0 mon_control_lower32
  create_bd_pin -dir O -from 31 -to 0 mon_control_lower33
  create_bd_pin -dir O -from 31 -to 0 mon_signal
  create_bd_pin -dir O -from 31 -to 0 mon_signal1
  create_bd_pin -dir O status_max
  create_bd_pin -dir O status_max1
  create_bd_pin -dir O status_min
  create_bd_pin -dir O status_min1
  create_bd_pin -dir O -from 2 -to 0 zero_spcp

  # Create instance: PS_Amplitude_Controller
  create_hier_cell_PS_Amplitude_Controller $hier_obj PS_Amplitude_Controller

  # Create instance: PS_Phase_Controller
  create_hier_cell_PS_Phase_Controller $hier_obj PS_Phase_Controller

  # Create instance: axis_dc_filter_0, and set properties
  set block_name axis_dc_filter
  set block_cell_name axis_dc_filter_0
  if { [catch {set axis_dc_filter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_dc_filter_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_decimator_0, and set properties
  set block_name axis_decimator
  set block_cell_name axis_decimator_0
  if { [catch {set axis_decimator_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_decimator_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: cfg_select_amplitude_control, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_amplitude_control
  if { [catch {set cfg_select_amplitude_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_amplitude_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_SWBIT {1} \
    CONFIG.SRC_ADDR {3} \
  ] $cfg_select_amplitude_control


  # Create instance: cfg_select_lck_ampl_control, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_lck_ampl_control
  if { [catch {set cfg_select_lck_ampl_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_lck_ampl_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_SWBIT {4} \
    CONFIG.SRC_ADDR {3} \
  ] $cfg_select_lck_ampl_control


  # Create instance: cfg_select_lck_phase_control1, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_lck_phase_control1
  if { [catch {set cfg_select_lck_phase_control1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_lck_phase_control1 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_SWBIT {5} \
    CONFIG.SRC_ADDR {3} \
  ] $cfg_select_lck_phase_control1


  # Create instance: cfg_select_phase_control, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_phase_control
  if { [catch {set cfg_select_phase_control [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_phase_control eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.SRC_ADDR {3} $cfg_select_phase_control


  # Create instance: dds_compiler_0, and set properties
  set dds_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:dds_compiler:6.0 dds_compiler_0 ]
  set_property -dict [list \
    CONFIG.DATA_Has_TLAST {Not_Required} \
    CONFIG.DDS_Clock_Rate {125} \
    CONFIG.Frequency_Resolution {0.00001} \
    CONFIG.Has_Phase_Out {false} \
    CONFIG.Latency {10} \
    CONFIG.M_DATA_Has_TUSER {Not_Required} \
    CONFIG.Noise_Shaping {Auto} \
    CONFIG.Output_Frequency1 {0} \
    CONFIG.Output_Width {25} \
    CONFIG.PINC1 {0} \
    CONFIG.Phase_Increment {Streaming} \
    CONFIG.Phase_Width {44} \
    CONFIG.Phase_offset {None} \
    CONFIG.S_PHASE_Has_TUSER {Not_Required} \
    CONFIG.Spurious_Free_Dynamic_Range {140} \
  ] $dds_compiler_0


  # Create instance: cordic_atan_xy, and set properties
  set cordic_atan_xy [ create_bd_cell -type ip -vlnv xilinx.com:ip:cordic:6.0 cordic_atan_xy ]
  set_property -dict [list \
    CONFIG.Coarse_Rotation {true} \
    CONFIG.Data_Format {SignedFraction} \
    CONFIG.Functional_Selection {Arc_Tan} \
    CONFIG.Input_Width {28} \
    CONFIG.Output_Width {24} \
    CONFIG.Pipelining_Mode {Optimal} \
    CONFIG.Round_Mode {Nearest_Even} \
  ] $cordic_atan_xy


  # Create instance: cordic_sqrt, and set properties
  set cordic_sqrt [ create_bd_cell -type ip -vlnv xilinx.com:ip:cordic:6.0 cordic_sqrt ]
  set_property -dict [list \
    CONFIG.Coarse_Rotation {false} \
    CONFIG.Data_Format {UnsignedFraction} \
    CONFIG.Functional_Selection {Square_Root} \
    CONFIG.Input_Width {45} \
    CONFIG.Output_Width {24} \
    CONFIG.Pipelining_Mode {Optimal} \
    CONFIG.Round_Mode {Nearest_Even} \
  ] $cordic_sqrt


  # Create instance: cfg_to_axis_Atau, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_Atau
  if { [catch {set cfg_to_axis_Atau [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_Atau eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.SRC_ADDR {27} $cfg_to_axis_Atau


  # Create instance: cfg_to_axis_dc, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_dc
  if { [catch {set cfg_to_axis_dc [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_dc eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {5} \
  ] $cfg_to_axis_dc


  # Create instance: cfg_to_axis_dc_tau, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_dc_tau
  if { [catch {set cfg_to_axis_dc_tau [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_dc_tau eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.SRC_ADDR {28} $cfg_to_axis_dc_tau


  # Create instance: cfg_to_axis_tau, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_tau
  if { [catch {set cfg_to_axis_tau [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_tau eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {32} \
    CONFIG.MAXIS_TDATA_WIDTH {32} \
    CONFIG.SRC_ADDR {4} \
  ] $cfg_to_axis_tau


  # Create instance: lms_phase_amplitude_detector_0, and set properties
  set block_name lms_phase_amplitude_detector
  set block_cell_name lms_phase_amplitude_detector_0
  if { [catch {set lms_phase_amplitude_detector_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $lms_phase_amplitude_detector_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.COMPUTE_LOCKIN {0} \
    CONFIG.SC_DATA_WIDTH {25} \
    CONFIG.USE_DUAL_PAC {2} \
  ] $lms_phase_amplitude_detector_0


  # Create instance: axis_splitter_CH0, and set properties
  set block_name axis_splitter
  set block_cell_name axis_splitter_CH0
  if { [catch {set axis_splitter_CH0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_splitter_CH0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.MAXIS_TDATA_WIDTH {16} \
    CONFIG.SAXIS_TDATA_WIDTH {16} \
  ] $axis_splitter_CH0


  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axis_decimator_0/M_AXIS_S1] [get_bd_intf_pins M_AXIS_S1]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_CONTROL [get_bd_intf_pins M_AXIS_CONTROL] [get_bd_intf_pins PS_Amplitude_Controller/M_AXIS_CONTROL]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_CONTROL2 [get_bd_intf_pins M_AXIS_CONTROL2] [get_bd_intf_pins PS_Amplitude_Controller/M_AXIS_CONTROL2]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_PASS [get_bd_intf_pins PS_Amplitude_Controller/M_AXIS_PASS] [get_bd_intf_pins PS_Phase_Controller/S_AXIS_AMPL]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_PASS2 [get_bd_intf_pins M_AXIS_PASS2] [get_bd_intf_pins PS_Amplitude_Controller/M_AXIS_PASS2]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_CONTROL [get_bd_intf_pins PS_Phase_Controller/M_AXIS_CONTROL] [get_bd_intf_pins dds_compiler_0/S_AXIS_PHASE]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_CONTROL2 [get_bd_intf_pins M_AXIS_CONTROL3] [get_bd_intf_pins PS_Phase_Controller/M_AXIS_CONTROL2]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_CONTROL3 [get_bd_intf_pins PS_Phase_Controller/M_AXIS_CONTROL3] [get_bd_intf_pins lms_phase_amplitude_detector_0/S_AXIS_DDS_dphi]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_PASS2 [get_bd_intf_pins M_AXIS_PASS3] [get_bd_intf_pins PS_Phase_Controller/M_AXIS_PASS2]
  connect_bd_intf_net -intf_net S_AXIS1_1 [get_bd_intf_pins M_AXIS_S01] [get_bd_intf_pins axis_decimator_0/M_AXIS_S01]
  connect_bd_intf_net -intf_net axis_dc_filter_0_M_AXIS [get_bd_intf_pins axis_dc_filter_0/M_AXIS_AC_LMS] [get_bd_intf_pins lms_phase_amplitude_detector_0/S_AXIS_SIGNAL]
  connect_bd_intf_net -intf_net axis_dc_filter_0_M_AXIS_AC16 [get_bd_intf_pins M_AXIS_AC16] [get_bd_intf_pins axis_dc_filter_0/M_AXIS_AC16]
  connect_bd_intf_net -intf_net axis_dc_filter_0_M_AXIS_ACDC [get_bd_intf_pins M_AXIS_ACDC] [get_bd_intf_pins axis_dc_filter_0/M_AXIS_ACDC]
  connect_bd_intf_net -intf_net axis_decimator_0_M_AXIS_S0 [get_bd_intf_pins axis_decimator_0/M_AXIS_S0] [get_bd_intf_pins axis_splitter_CH0/S_AXIS]
  connect_bd_intf_net -intf_net axis_red_pitaya_adc_0_M_AXIS [get_bd_intf_pins S_AXIS_SIGNAL] [get_bd_intf_pins axis_decimator_0/S_AXIS_SIGNAL]
  connect_bd_intf_net -intf_net axis_splitter_0_M_AXIS [get_bd_intf_pins axis_splitter_CH0/M_AXIS] [get_bd_intf_pins axis_dc_filter_0/S_AXIS]
  connect_bd_intf_net -intf_net axis_splitter_0_M_AXIS2 [get_bd_intf_pins M_AXIS2] [get_bd_intf_pins axis_splitter_CH0/M_AXIS2]
  connect_bd_intf_net -intf_net cordic_atan_xy_M_AXIS_DOUT [get_bd_intf_pins PS_Phase_Controller/S_AXIS] [get_bd_intf_pins cordic_atan_xy/M_AXIS_DOUT]
  connect_bd_intf_net -intf_net cordic_sqrt_M_AXIS_DOUT [get_bd_intf_pins PS_Amplitude_Controller/S_AXIS] [get_bd_intf_pins cordic_sqrt/M_AXIS_DOUT]
  connect_bd_intf_net -intf_net dds_compiler_0_M_AXIS_DATA [get_bd_intf_pins dds_compiler_0/M_AXIS_DATA] [get_bd_intf_pins lms_phase_amplitude_detector_0/S_AXIS_SC]
  connect_bd_intf_net -intf_net lms_phase_amplitude_detector_0_M_AXIS_AM2 [get_bd_intf_pins cordic_sqrt/S_AXIS_CARTESIAN] [get_bd_intf_pins lms_phase_amplitude_detector_0/M_AXIS_AM2]
  connect_bd_intf_net -intf_net lms_phase_amplitude_detector_0_M_AXIS_LockInX [get_bd_intf_pins M_AXIS_LockInX] [get_bd_intf_pins lms_phase_amplitude_detector_0/M_AXIS_LockInX]
  connect_bd_intf_net -intf_net lms_phase_amplitude_detector_0_M_AXIS_LockInY [get_bd_intf_pins M_AXIS_LockInY] [get_bd_intf_pins lms_phase_amplitude_detector_0/M_AXIS_LockInY]
  connect_bd_intf_net -intf_net lms_phase_amplitude_detector_0_M_AXIS_SC [get_bd_intf_pins M_AXIS_SC] [get_bd_intf_pins lms_phase_amplitude_detector_0/M_AXIS_SC]
  connect_bd_intf_net -intf_net lms_phase_amplitude_detector_0_M_AXIS_XY [get_bd_intf_pins cordic_atan_xy/S_AXIS_CARTESIAN] [get_bd_intf_pins lms_phase_amplitude_detector_0/M_AXIS_XY]

  # Create port connections
  connect_bd_net -net PS_Amplitude_Controller_mon_control_lower32 [get_bd_pins PS_Amplitude_Controller/mon_control_lower32] [get_bd_pins mon_control_lower32]
  connect_bd_net -net PS_Amplitude_Controller_status_max [get_bd_pins PS_Amplitude_Controller/status_max] [get_bd_pins status_max]
  connect_bd_net -net PS_Amplitude_Controller_status_min [get_bd_pins PS_Amplitude_Controller/status_min] [get_bd_pins status_min]
  connect_bd_net -net PS_Dout [get_bd_pins cfg1] [get_bd_pins PS_Phase_Controller/cfg1]
  connect_bd_net -net PS_Phase_Controller_mon_control_B [get_bd_pins PS_Phase_Controller/mon_control_B] [get_bd_pins mon_control_B]
  connect_bd_net -net PS_Phase_Controller_status_max [get_bd_pins PS_Phase_Controller/status_max] [get_bd_pins status_max1]
  connect_bd_net -net PS_Phase_Controller_status_min [get_bd_pins PS_Phase_Controller/status_min] [get_bd_pins status_min1]
  connect_bd_net -net PS_cfg_data [get_bd_pins cfg] [get_bd_pins PS_Amplitude_Controller/cfg] [get_bd_pins PS_Phase_Controller/cfg] [get_bd_pins cfg_select_amplitude_control/cfg] [get_bd_pins cfg_select_lck_ampl_control/cfg] [get_bd_pins cfg_select_lck_phase_control1/cfg] [get_bd_pins cfg_select_phase_control/cfg] [get_bd_pins cfg_to_axis_Atau/cfg] [get_bd_pins cfg_to_axis_dc/cfg] [get_bd_pins cfg_to_axis_dc_tau/cfg] [get_bd_pins cfg_to_axis_tau/cfg]
  connect_bd_net -net amplitude_controller_mon_signal [get_bd_pins PS_Amplitude_Controller/mon_signal] [get_bd_pins mon_signal]
  connect_bd_net -net axis_dc_filter_0_dbg_m [get_bd_pins axis_dc_filter_0/dbg_m] [get_bd_pins dbg_m]
  connect_bd_net -net axis_dc_filter_0_dbg_mdc [get_bd_pins axis_dc_filter_0/dbg_mdc] [get_bd_pins dbg_mdc]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk1 [get_bd_pins aclk] [get_bd_pins PS_Amplitude_Controller/aclk] [get_bd_pins PS_Phase_Controller/aclk] [get_bd_pins axis_dc_filter_0/aclk] [get_bd_pins axis_decimator_0/aclk] [get_bd_pins axis_decimator_0/adc_clk] [get_bd_pins dds_compiler_0/aclk] [get_bd_pins cordic_atan_xy/aclk] [get_bd_pins cordic_sqrt/aclk] [get_bd_pins cfg_to_axis_Atau/a_clk] [get_bd_pins cfg_to_axis_dc/a_clk] [get_bd_pins cfg_to_axis_dc_tau/a_clk] [get_bd_pins cfg_to_axis_tau/a_clk] [get_bd_pins lms_phase_amplitude_detector_0/aclk] [get_bd_pins axis_splitter_CH0/a_clk]
  connect_bd_net -net cfg_axis_phaseinc_status [get_bd_pins cfg_select_phase_control/status] [get_bd_pins enable] [get_bd_pins PS_Phase_Controller/enable]
  connect_bd_net -net cfg_axis_volume_status [get_bd_pins cfg_select_amplitude_control/status] [get_bd_pins enable1] [get_bd_pins PS_Amplitude_Controller/enable]
  connect_bd_net -net cfg_select_lck_ampl_control_status [get_bd_pins cfg_select_lck_ampl_control/status] [get_bd_pins lms_phase_amplitude_detector_0/lck_ampl]
  connect_bd_net -net cfg_select_lck_phase_control1_status [get_bd_pins cfg_select_lck_phase_control1/status] [get_bd_pins lms_phase_amplitude_detector_0/lck_phase]
  connect_bd_net -net cfg_to_axis_Atau_M_AXIS_tdata [get_bd_pins cfg_to_axis_Atau/M_AXIS_tdata] [get_bd_pins lms_phase_amplitude_detector_0/Atau]
  connect_bd_net -net cfg_to_axis_dc_M_AXIS_tdata [get_bd_pins cfg_to_axis_dc/M_AXIS_tdata] [get_bd_pins axis_dc_filter_0/dc]
  connect_bd_net -net cfg_to_axis_dc_tau_M_AXIS_tdata [get_bd_pins cfg_to_axis_dc_tau/M_AXIS_tdata] [get_bd_pins axis_dc_filter_0/dc_tau]
  connect_bd_net -net cfg_to_axis_tau_M_AXIS_tdata [get_bd_pins cfg_to_axis_tau/M_AXIS_tdata] [get_bd_pins lms_phase_amplitude_detector_0/tau]
  connect_bd_net -net gpio2_io_i_1 [get_bd_pins PS_Phase_Controller/mon_signal] [get_bd_pins mon_signal1]
  connect_bd_net -net gpio_io_3_x7_1 [get_bd_pins PS_Amplitude_Controller/mon_control] [get_bd_pins mon_control]
  connect_bd_net -net gpio_io_3_x8_1 [get_bd_pins PS_Phase_Controller/mon_control] [get_bd_pins mon_control1]
  connect_bd_net -net gpio_io_4_x9_1 [get_bd_pins PS_Phase_Controller/mon_control_lower32] [get_bd_pins mon_control_lower33]
  connect_bd_net -net lms_phase_amplitude_detector_0_dbg_lckX [get_bd_pins lms_phase_amplitude_detector_0/M_AXIS_Aout_tdata] [get_bd_pins M_AXIS_Aout_tdata]
  connect_bd_net -net lms_phase_amplitude_detector_0_dbg_lckY [get_bd_pins lms_phase_amplitude_detector_0/M_AXIS_Bout_tdata] [get_bd_pins M_AXIS_Bout_tdata]
  connect_bd_net -net lms_phase_amplitude_detector_0_sc_zero_x [get_bd_pins lms_phase_amplitude_detector_0/sc_zero_x] [get_bd_pins axis_dc_filter_0/sc_zero]
  connect_bd_net -net lms_phase_amplitude_detector_0_zero_spcp [get_bd_pins lms_phase_amplitude_detector_0/zero_spcp] [get_bd_pins zero_spcp]

  # Perform GUI Layout
  regenerate_bd_layout -hierarchy [get_bd_cells /PAC_PLL] -layout_string {
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"1.0",
   "Default View_TopLeft":"-1695,-724",
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
#  -string -flagsOSRD
preplace port M_AXIS_AC16 -pg 1 -lvl 5 -x 1760 -y 200 -defaultsOSRD
preplace port M_AXIS_ACDC -pg 1 -lvl 5 -x 1760 -y 230 -defaultsOSRD
preplace port M_AXIS_CONTROL -pg 1 -lvl 5 -x 1760 -y 890 -defaultsOSRD
preplace port M_AXIS_CONTROL2 -pg 1 -lvl 5 -x 1760 -y 920 -defaultsOSRD
preplace port M_AXIS_CONTROL3 -pg 1 -lvl 5 -x 1760 -y 1220 -defaultsOSRD
preplace port M_AXIS_LockInX -pg 1 -lvl 5 -x 1760 -y 550 -defaultsOSRD
preplace port M_AXIS_LockInY -pg 1 -lvl 5 -x 1760 -y 580 -defaultsOSRD
preplace port M_AXIS_PASS2 -pg 1 -lvl 5 -x 1760 -y 950 -defaultsOSRD
preplace port M_AXIS_PASS3 -pg 1 -lvl 5 -x 1760 -y 1250 -defaultsOSRD
preplace port M_AXIS_S01 -pg 1 -lvl 5 -x 1760 -y 60 -defaultsOSRD
preplace port M_AXIS_SC -pg 1 -lvl 5 -x 1760 -y 610 -defaultsOSRD
preplace port S_AXIS_SIGNAL -pg 1 -lvl 0 -x 0 -y 50 -defaultsOSRD
preplace port M_AXIS_S1 -pg 1 -lvl 5 -x 1760 -y 90 -defaultsOSRD
preplace port M_AXIS2 -pg 1 -lvl 5 -x 1760 -y -40 -defaultsOSRD
preplace port port-id_aclk -pg 1 -lvl 0 -x 0 -y 270 -defaultsOSRD
preplace port port-id_enable -pg 1 -lvl 5 -x 1760 -y 1460 -defaultsOSRD
preplace port port-id_enable1 -pg 1 -lvl 5 -x 1760 -y 1190 -defaultsOSRD
preplace port port-id_status_max -pg 1 -lvl 5 -x 1760 -y 1070 -defaultsOSRD
preplace port port-id_status_max1 -pg 1 -lvl 5 -x 1760 -y 1400 -defaultsOSRD
preplace port port-id_status_min -pg 1 -lvl 5 -x 1760 -y 1100 -defaultsOSRD
preplace port port-id_status_min1 -pg 1 -lvl 5 -x 1760 -y 1430 -defaultsOSRD
preplace portBus M_AXIS_Aout_tdata -pg 1 -lvl 5 -x 1760 -y 490 -defaultsOSRD
preplace portBus M_AXIS_Bout_tdata -pg 1 -lvl 5 -x 1760 -y 520 -defaultsOSRD
preplace portBus cfg -pg 1 -lvl 0 -x 0 -y 300 -defaultsOSRD
preplace portBus cfg1 -pg 1 -lvl 0 -x 0 -y 1350 -defaultsOSRD
preplace portBus dbg_m -pg 1 -lvl 5 -x 1760 -y 260 -defaultsOSRD
preplace portBus dbg_mdc -pg 1 -lvl 5 -x 1760 -y 290 -defaultsOSRD
preplace portBus mon_control -pg 1 -lvl 5 -x 1760 -y 980 -defaultsOSRD
preplace portBus mon_control1 -pg 1 -lvl 5 -x 1760 -y 1280 -defaultsOSRD
preplace portBus mon_control_B -pg 1 -lvl 5 -x 1760 -y 1310 -defaultsOSRD
preplace portBus mon_control_lower32 -pg 1 -lvl 5 -x 1760 -y 1010 -defaultsOSRD
preplace portBus mon_control_lower33 -pg 1 -lvl 5 -x 1760 -y 1340 -defaultsOSRD
preplace portBus mon_signal -pg 1 -lvl 5 -x 1760 -y 1040 -defaultsOSRD
preplace portBus mon_signal1 -pg 1 -lvl 5 -x 1760 -y 1370 -defaultsOSRD
preplace portBus zero_spcp -pg 1 -lvl 5 -x 1760 -y 730 -defaultsOSRD
preplace inst PS_Amplitude_Controller -pg 1 -lvl 4 -x 1460 -y 1022 -defaultsOSRD
preplace inst PS_Phase_Controller -pg 1 -lvl 2 -x 590 -y 1320 -defaultsOSRD
preplace inst axis_dc_filter_0 -pg 1 -lvl 2 -x 590 -y 250 -defaultsOSRD
preplace inst axis_decimator_0 -pg 1 -lvl 2 -x 590 -y 70 -defaultsOSRD
preplace inst cfg_select_amplitude_control -pg 1 -lvl 2 -x 590 -y 1550 -defaultsOSRD
preplace inst cfg_select_lck_ampl_control -pg 1 -lvl 2 -x 590 -y 660 -defaultsOSRD
preplace inst cfg_select_lck_phase_control1 -pg 1 -lvl 2 -x 590 -y 760 -defaultsOSRD
preplace inst cfg_select_phase_control -pg 1 -lvl 4 -x 1460 -y 1880 -defaultsOSRD
preplace inst dds_compiler_0 -pg 1 -lvl 2 -x 590 -y 550 -defaultsOSRD
preplace inst cordic_atan_xy -pg 1 -lvl 1 -x 200 -y 1200 -defaultsOSRD
preplace inst cordic_sqrt -pg 1 -lvl 2 -x 590 -y 430 -defaultsOSRD
preplace inst cfg_to_axis_Atau -pg 1 -lvl 2 -x 590 -y 880 -defaultsOSRD
preplace inst cfg_to_axis_dc -pg 1 -lvl 1 -x 200 -y 290 -defaultsOSRD
preplace inst cfg_to_axis_dc_tau -pg 1 -lvl 1 -x 200 -y 450 -defaultsOSRD
preplace inst cfg_to_axis_tau -pg 1 -lvl 2 -x 590 -y 1050 -defaultsOSRD
preplace inst lms_phase_amplitude_detector_0 -pg 1 -lvl 4 -x 1460 -y 600 -defaultsOSRD
preplace inst axis_splitter_CH0 -pg 1 -lvl 3 -x 1010 -y -40 -defaultsOSRD
preplace netloc PS_Amplitude_Controller_mon_control_lower32 1 4 1 1720J 1010n
preplace netloc PS_Amplitude_Controller_status_max 1 4 1 1740J 1070n
preplace netloc PS_Amplitude_Controller_status_min 1 4 1 1740J 1100n
preplace netloc PS_Dout 1 0 2 NJ 1350 NJ
preplace netloc PS_Phase_Controller_mon_control_B 1 2 3 NJ 1340 1250 1310 NJ
preplace netloc PS_Phase_Controller_status_max 1 2 3 NJ 1420 1260 1400 NJ
preplace netloc PS_Phase_Controller_status_min 1 2 3 NJ 1440 1260 1430 NJ
preplace netloc PS_cfg_data 1 0 4 20 370 400 360 N 360 1220
preplace netloc amplitude_controller_mon_signal 1 4 1 1730J 1040n
preplace netloc axis_dc_filter_0_dbg_m 1 2 3 NJ 270 1150 260 NJ
preplace netloc axis_dc_filter_0_dbg_mdc 1 2 3 NJ 290 N 290 NJ
preplace netloc axis_red_pitaya_adc_0_adc_clk1 1 0 4 30 210 390 -20 880 80 1240
preplace netloc cfg_axis_phaseinc_status 1 1 4 420 1490 NJ 1490 N 1490 1670
preplace netloc cfg_axis_volume_status 1 2 3 790 1210 1250 1190 NJ
preplace netloc cfg_select_lck_ampl_control_status 1 2 2 NJ 660 1140
preplace netloc cfg_select_lck_phase_control1_status 1 2 2 NJ 760 1140
preplace netloc cfg_to_axis_Atau_M_AXIS_tdata 1 2 2 790 630 N
preplace netloc cfg_to_axis_dc_M_AXIS_tdata 1 1 1 N 290
preplace netloc cfg_to_axis_dc_tau_M_AXIS_tdata 1 1 1 360 270n
preplace netloc cfg_to_axis_tau_M_AXIS_tdata 1 2 2 780 610 N
preplace netloc gpio2_io_i_1 1 2 3 NJ 1400 1240 1370 NJ
preplace netloc gpio_io_3_x7_1 1 4 1 1710J 980n
preplace netloc gpio_io_3_x8_1 1 2 3 NJ 1320 1240 1280 NJ
preplace netloc gpio_io_4_x9_1 1 2 3 NJ 1360 1260 1340 NJ
preplace netloc lms_phase_amplitude_detector_0_dbg_lckX 1 4 1 1680J 490n
preplace netloc lms_phase_amplitude_detector_0_dbg_lckY 1 4 1 1680J 520n
preplace netloc lms_phase_amplitude_detector_0_sc_zero_x 1 1 4 420 350 NJ 350 N 350 1670
preplace netloc lms_phase_amplitude_detector_0_zero_spcp 1 4 1 NJ 730
preplace netloc Conn1 1 2 3 NJ 90 N 90 NJ
preplace netloc PS_Amplitude_Controller_M_AXIS_CONTROL 1 4 1 1680J 890n
preplace netloc PS_Amplitude_Controller_M_AXIS_CONTROL2 1 4 1 1690J 920n
preplace netloc PS_Amplitude_Controller_M_AXIS_PASS 1 1 4 420 1140 NJ 1140 1140 1150 1660
preplace netloc PS_Amplitude_Controller_M_AXIS_PASS2 1 4 1 1700J 950n
preplace netloc PS_Phase_Controller_M_AXIS_CONTROL 1 1 2 420 970 760
preplace netloc PS_Phase_Controller_M_AXIS_CONTROL2 1 2 3 NJ 1220 N 1220 NJ
preplace netloc PS_Phase_Controller_M_AXIS_CONTROL3 1 2 2 770 530 N
preplace netloc PS_Phase_Controller_M_AXIS_PASS2 1 2 3 NJ 1280 1230 1250 NJ
preplace netloc S_AXIS1_1 1 2 3 NJ 70 1170 60 NJ
preplace netloc axis_dc_filter_0_M_AXIS 1 2 2 N 250 1250
preplace netloc axis_dc_filter_0_M_AXIS_AC16 1 2 3 NJ 210 1150 200 NJ
preplace netloc axis_dc_filter_0_M_AXIS_ACDC 1 2 3 NJ 230 N 230 NJ
preplace netloc axis_red_pitaya_adc_0_M_AXIS 1 0 2 NJ 50 NJ
preplace netloc cordic_atan_xy_M_AXIS_DOUT 1 1 1 360 1200n
preplace netloc cordic_sqrt_M_AXIS_DOUT 1 2 2 N 430 1230
preplace netloc dds_compiler_0_M_AXIS_DATA 1 2 2 N 550 N
preplace netloc lms_phase_amplitude_detector_0_M_AXIS_AM2 1 1 4 410 -10 780J 100 N 100 1660
preplace netloc lms_phase_amplitude_detector_0_M_AXIS_LockInX 1 4 1 1690J 550n
preplace netloc lms_phase_amplitude_detector_0_M_AXIS_LockInY 1 4 1 1690J 580n
preplace netloc lms_phase_amplitude_detector_0_M_AXIS_SC 1 4 1 NJ 610
preplace netloc lms_phase_amplitude_detector_0_M_AXIS_XY 1 0 5 40 960 NJ 960 NJ 960 1140 882 1660
preplace netloc axis_decimator_0_M_AXIS_S0 1 2 1 770 -50n
preplace netloc axis_splitter_0_M_AXIS 1 1 3 420 150 NJ 150 1150
preplace netloc axis_splitter_0_M_AXIS2 1 3 2 NJ -40 NJ
levelinfo -pg 1 0 200 590 1010 1460 1760
pagesize -pg 1 -db -bbox -sgen -160 -120 2320 2190
"
}

  # Restore current instance
  current_bd_instance $oldCurInst
}
  
# Hierarchical cell: Block_QControl
proc create_hier_cell_Block_QControl { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_Block_QControl() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SIGNAL_M


  # Create pins
  create_bd_pin -dir I -type clk a_clk
  create_bd_pin -dir I -from 1023 -to 0 cfg

  # Create instance: QControl, and set properties
  set block_name QControl
  set block_cell_name QControl
  if { [catch {set QControl [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $QControl eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: cfg_select_qcontrol, and set properties
  set block_name cfg_select
  set block_cell_name cfg_select_qcontrol
  if { [catch {set cfg_select_qcontrol [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_select_qcontrol eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.CFG_SWBIT {3} \
    CONFIG.SRC_ADDR {3} \
  ] $cfg_select_qcontrol


  # Create instance: cfg_to_axis_qc_delay, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_qc_delay
  if { [catch {set cfg_to_axis_qc_delay [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_qc_delay eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {16} \
    CONFIG.SRC_ADDR {29} \
    CONFIG.SRC_BITS {16} \
  ] $cfg_to_axis_qc_delay


  # Create instance: cfg_to_axis_qc_gain, and set properties
  set block_name cfg_to_axis
  set block_cell_name cfg_to_axis_qc_gain
  if { [catch {set cfg_to_axis_qc_gain [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $cfg_to_axis_qc_gain eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property -dict [list \
    CONFIG.DST_WIDTH {16} \
    CONFIG.SRC_ADDR {29} \
    CONFIG.SRC_BITS {32} \
  ] $cfg_to_axis_qc_gain


  # Create interface connections
  connect_bd_intf_net -intf_net QControl_M_AXIS [get_bd_intf_pins M_AXIS] [get_bd_intf_pins QControl/M_AXIS]
  connect_bd_intf_net -intf_net axis_dc_filter_0_M_AXIS_AC16 [get_bd_intf_pins S_AXIS_SIGNAL_M] [get_bd_intf_pins QControl/S_AXIS_SIGNAL_M]

  # Create port connections
  connect_bd_net -net PS_cfg_data [get_bd_pins cfg] [get_bd_pins cfg_select_qcontrol/cfg] [get_bd_pins cfg_to_axis_qc_delay/cfg] [get_bd_pins cfg_to_axis_qc_gain/cfg]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk1 [get_bd_pins a_clk] [get_bd_pins QControl/a_clk] [get_bd_pins QControl/adc_clk] [get_bd_pins cfg_to_axis_qc_delay/a_clk] [get_bd_pins cfg_to_axis_qc_gain/a_clk]
  connect_bd_net -net cfg_select_qcontrol_status [get_bd_pins cfg_select_qcontrol/status] [get_bd_pins QControl/QC_enable]
  connect_bd_net -net cfg_to_axis_qc_delay_data [get_bd_pins cfg_to_axis_qc_delay/data] [get_bd_pins QControl/QC_delay]
  connect_bd_net -net cfg_to_axis_qc_gain_data [get_bd_pins cfg_to_axis_qc_gain/data] [get_bd_pins QControl/QC_gain]

  # Restore current instance
  current_bd_instance $oldCurInst
}
  variable script_folder

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]

  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]

  set Vaux0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 ]

  set Vaux1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1 ]

  set Vaux8 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 ]

  set Vaux9 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9 ]

  set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ]

  set gpio_rtl_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_rtl_0 ]

  set spi_rtl_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi_rtl_0 ]

  set gpio_rtl_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_rtl_1 ]

  set gpio_rtl_2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_rtl_2 ]


  # Create ports
  set adc_clk_n_i [ create_bd_port -dir I adc_clk_n_i ]
  set adc_clk_p_i [ create_bd_port -dir I adc_clk_p_i ]
  set adc_csn_o [ create_bd_port -dir O adc_csn_o ]
  set adc_dat_a_i [ create_bd_port -dir I -from 13 -to 0 adc_dat_a_i ]
  set adc_dat_b_i [ create_bd_port -dir I -from 13 -to 0 adc_dat_b_i ]
  set adc_enc_n_o [ create_bd_port -dir O adc_enc_n_o ]
  set adc_enc_p_o [ create_bd_port -dir O adc_enc_p_o ]
  set dac_clk_o [ create_bd_port -dir O dac_clk_o ]
  set dac_dat_o [ create_bd_port -dir O -from 13 -to 0 dac_dat_o ]
  set dac_pwm_o [ create_bd_port -dir O -from 3 -to 0 dac_pwm_o ]
  set dac_rst_o [ create_bd_port -dir O dac_rst_o ]
  set dac_sel_o [ create_bd_port -dir O dac_sel_o ]
  set dac_wrt_o [ create_bd_port -dir O dac_wrt_o ]
  set daisy_n_i [ create_bd_port -dir I -from 1 -to 0 daisy_n_i ]
  set daisy_n_o [ create_bd_port -dir O -from 1 -to 0 daisy_n_o ]
  set daisy_p_i [ create_bd_port -dir I -from 1 -to 0 daisy_p_i ]
  set daisy_p_o [ create_bd_port -dir O -from 1 -to 0 daisy_p_o ]
  set exp_n_io [ create_bd_port -dir IO -from 7 -to 0 exp_n_io ]
  set exp_p_io [ create_bd_port -dir IO -from 7 -to 0 exp_p_io ]
  set led_o [ create_bd_port -dir O -from 7 -to 0 led_o ]
  set reset_rtl_0 [ create_bd_port -dir I -type rst reset_rtl_0 ]
  set_property -dict [ list \
   CONFIG.POLARITY {ACTIVE_HIGH} \
 ] $reset_rtl_0

  # Create instance: Block_QControl
  create_hier_cell_Block_QControl [current_bd_instance .] Block_QControl

  # Create instance: PAC_PLL
  create_hier_cell_PAC_PLL [current_bd_instance .] PAC_PLL

  # Create instance: PS
  create_hier_cell_PS [current_bd_instance .] PS

  # Create instance: PS_data_transport
  create_hier_cell_PS_data_transport [current_bd_instance .] PS_data_transport

  # Create instance: SPM_control_logic
  create_hier_cell_SPM_control_logic [current_bd_instance .] SPM_control_logic

  # Create instance: VolumeAdjuster16_14, and set properties
  set block_name VolumeAdjuster16_14
  set block_cell_name VolumeAdjuster16_14
  if { [catch {set VolumeAdjuster16_14 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $VolumeAdjuster16_14 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: Volume_QControl_Mixer, and set properties
  set block_name Volume_QControl_Mixer
  set block_cell_name Volume_QControl_Mixer
  if { [catch {set Volume_QControl_Mixer [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $Volume_QControl_Mixer eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axis_red_pitaya_adc_0, and set properties
  set axis_red_pitaya_adc_0 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_red_pitaya_adc:1.0 axis_red_pitaya_adc_0 ]

  # Create instance: axis_red_pitaya_dac_0, and set properties
  set axis_red_pitaya_dac_0 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_red_pitaya_dac:1.0 axis_red_pitaya_dac_0 ]

  # Create instance: led_connect_0, and set properties
  set block_name led_connect
  set block_cell_name led_connect_0
  if { [catch {set led_connect_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $led_connect_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: clk_wiz_0, and set properties
  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
  set_property -dict [list \
    CONFIG.CLKIN1_JITTER_PS {80.0} \
    CONFIG.CLKIN2_JITTER_PS {166.66} \
    CONFIG.CLKOUT1_JITTER {104.759} \
    CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
    CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {250} \
    CONFIG.CLKOUT2_JITTER {137.150} \
    CONFIG.CLKOUT2_PHASE_ERROR {96.948} \
    CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {62.5} \
    CONFIG.CLKOUT2_USED {true} \
    CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
    CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
    CONFIG.MMCM_CLKIN2_PERIOD {10.000} \
    CONFIG.MMCM_CLKOUT0_DIVIDE_F {4.000} \
    CONFIG.MMCM_CLKOUT1_DIVIDE {16} \
    CONFIG.MMCM_DIVCLK_DIVIDE {1} \
    CONFIG.NUM_OUT_CLKS {2} \
    CONFIG.PRIM_IN_FREQ {125} \
    CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
    CONFIG.USE_INCLK_SWITCHOVER {false} \
    CONFIG.USE_RESET {false} \
  ] $clk_wiz_0


  # Create instance: util_ds_buf_1, and set properties
  set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_1 ]
  set_property CONFIG.C_SIZE {2} $util_ds_buf_1


  # Create instance: util_ds_buf_2, and set properties
  set util_ds_buf_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_2 ]
  set_property -dict [list \
    CONFIG.C_BUF_TYPE {OBUFDS} \
    CONFIG.C_SIZE {2} \
  ] $util_ds_buf_2


  # Create instance: xlconcat_spmc_status, and set properties
  set xlconcat_spmc_status [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_spmc_status ]
  set_property CONFIG.NUM_PORTS {9} $xlconcat_spmc_status


  # Create instance: xlslice_0, and set properties
  set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
  set_property CONFIG.DIN_FROM {23} $xlslice_0


  # Create instance: axis_sc26_to_14_0, and set properties
  set block_name axis_sc28_to_14
  set block_cell_name axis_sc26_to_14_0
  if { [catch {set axis_sc26_to_14_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $axis_sc26_to_14_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
    set_property CONFIG.SRC_BITS {25} $axis_sc26_to_14_0


  # Create interface connections
  connect_bd_intf_net -intf_net PAC_PLL_M_AXIS2 [get_bd_intf_pins PAC_PLL/M_AXIS2] [get_bd_intf_pins SPM_control_logic/S_AXIS_ch5s]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_CONTROL [get_bd_intf_pins PAC_PLL/M_AXIS_CONTROL] [get_bd_intf_pins VolumeAdjuster16_14/SV_AXIS]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_CONTROL2 [get_bd_intf_pins PAC_PLL/M_AXIS_CONTROL2] [get_bd_intf_pins PS_data_transport/S_AXIS2]
  connect_bd_intf_net -intf_net PS_Amplitude_Controller_M_AXIS_PASS2 [get_bd_intf_pins PAC_PLL/M_AXIS_PASS2] [get_bd_intf_pins PS_data_transport/S_AXIS5]
  connect_bd_intf_net -intf_net PS_BRAM_PORTA [get_bd_intf_pins PS/BRAM_PORTA_PACPLL] [get_bd_intf_pins PS_data_transport/BRAM_PORTB]
  connect_bd_intf_net -intf_net PS_BRAM_PORTA1 [get_bd_intf_pins PS/BRAM_PORTA_SPMC] [get_bd_intf_pins SPM_control_logic/BRAM_PORTB]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_CONTROL2 [get_bd_intf_pins PAC_PLL/M_AXIS_CONTROL3] [get_bd_intf_pins PS_data_transport/S_AXIS3]
  connect_bd_intf_net -intf_net PS_Phase_Controller_M_AXIS_PASS2 [get_bd_intf_pins PAC_PLL/M_AXIS_PASS3] [get_bd_intf_pins PS_data_transport/S_AXIS4]
  connect_bd_intf_net -intf_net PS_data_transport_M_AXIS3 [get_bd_intf_pins PS_data_transport/M_AXIS3] [get_bd_intf_pins SPM_control_logic/S_AXIS_chAs]
  connect_bd_intf_net -intf_net PS_data_transport_M_AXIS5 [get_bd_intf_pins PS_data_transport/M_AXIS5] [get_bd_intf_pins SPM_control_logic/S_AXIS_chCs]
  connect_bd_intf_net -intf_net PS_data_transport_M_AXIS6 [get_bd_intf_pins PS_data_transport/M_AXIS6] [get_bd_intf_pins SPM_control_logic/S_AXIS_chEs]
  connect_bd_intf_net -intf_net PS_data_transport_M_AXIS_ADC2 [get_bd_intf_pins PAC_PLL/M_AXIS_S1] [get_bd_intf_pins SPM_control_logic/S_AXIS]
  connect_bd_intf_net -intf_net PS_data_transport_M_AXIS_aux [get_bd_intf_pins PS_data_transport/M_AXIS_aux] [get_bd_intf_pins axis_sc26_to_14_0/S_AXIS_aux]
  connect_bd_intf_net -intf_net QControl_M_AXIS [get_bd_intf_pins Block_QControl/M_AXIS] [get_bd_intf_pins Volume_QControl_Mixer/S_AXIS_QS]
  connect_bd_intf_net -intf_net S_AXIS1_1 [get_bd_intf_pins PAC_PLL/M_AXIS_S01] [get_bd_intf_pins PS_data_transport/S_AXIS1]
  connect_bd_intf_net -intf_net S_AXIS_ch9s_1 [get_bd_intf_pins SPM_control_logic/S_AXIS_ch9s] [get_bd_intf_pins PS_data_transport/M_AXIS2]
  connect_bd_intf_net -intf_net S_AXIS_chBs_1 [get_bd_intf_pins SPM_control_logic/S_AXIS_chBs] [get_bd_intf_pins PS_data_transport/M_AXIS4]
  connect_bd_intf_net -intf_net VolumeAdjuster16_14_M_AXIS [get_bd_intf_pins VolumeAdjuster16_14/M_AXIS] [get_bd_intf_pins Volume_QControl_Mixer/S_AXIS_VS]
  connect_bd_intf_net -intf_net Volume_QControl_Mixer_0_M_AXIS [get_bd_intf_pins Volume_QControl_Mixer/M_AXIS] [get_bd_intf_pins axis_red_pitaya_dac_0/S_AXIS]
  connect_bd_intf_net -intf_net axis_dc_filter_0_M_AXIS_AC16 [get_bd_intf_pins Block_QControl/S_AXIS_SIGNAL_M] [get_bd_intf_pins PAC_PLL/M_AXIS_AC16]
  connect_bd_intf_net -intf_net axis_dc_filter_0_M_AXIS_ACDC [get_bd_intf_pins PAC_PLL/M_AXIS_ACDC] [get_bd_intf_pins PS_data_transport/S_AXIS6]
  connect_bd_intf_net -intf_net axis_red_pitaya_adc_0_M_AXIS [get_bd_intf_pins PAC_PLL/S_AXIS_SIGNAL] [get_bd_intf_pins axis_red_pitaya_adc_0/M_AXIS]
  connect_bd_intf_net -intf_net axis_sc26_to_14_0_M_AXIS [get_bd_intf_pins VolumeAdjuster16_14/S_AXIS] [get_bd_intf_pins axis_sc26_to_14_0/M_AXIS]
  connect_bd_intf_net -intf_net lms_phase_amplitude_detector_0_M_AXIS_SC [get_bd_intf_pins PAC_PLL/M_AXIS_SC] [get_bd_intf_pins axis_sc26_to_14_0/S_AXIS]
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins PS/DDR]
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins PS/FIXED_IO]

  # Create port connections
  connect_bd_net -net Net [get_bd_ports exp_n_io] [get_bd_pins SPM_control_logic/exp_n_io]
  connect_bd_net -net Net1 [get_bd_ports exp_p_io] [get_bd_pins SPM_control_logic/exp_p_io]
  connect_bd_net -net PS_Amplitude_Controller_status_max [get_bd_pins PAC_PLL/status_max] [get_bd_pins led_connect_0/led3]
  connect_bd_net -net PS_Amplitude_Controller_status_min [get_bd_pins PAC_PLL/status_min] [get_bd_pins led_connect_0/led2]
  connect_bd_net -net PS_Dout [get_bd_pins PS/cfg_data_reg_1] [get_bd_pins PAC_PLL/cfg1] [get_bd_pins PS_data_transport/cfg1] [get_bd_pins SPM_control_logic/cfg1]
  connect_bd_net -net PS_Phase_Controller_mon_control_B -boundary_type upper [get_bd_pins PAC_PLL/mon_control_B]
  connect_bd_net -net PS_Phase_Controller_status_max [get_bd_pins PAC_PLL/status_max1] [get_bd_pins led_connect_0/led6]
  connect_bd_net -net PS_Phase_Controller_status_min [get_bd_pins PAC_PLL/status_min1] [get_bd_pins led_connect_0/led5]
  connect_bd_net -net PS_cfg_data [get_bd_pins PS/cfg_data_reg_0] [get_bd_pins Block_QControl/cfg] [get_bd_pins PAC_PLL/cfg] [get_bd_pins PS_data_transport/cfg0]
  connect_bd_net -net PS_cfg_data_reg_2 [get_bd_pins PS/cfg_data_reg_2] [get_bd_pins PS_data_transport/cfg2]
  connect_bd_net -net PS_cfg_data_reg_3 [get_bd_pins PS/cfg_data_reg_3] [get_bd_pins SPM_control_logic/cfg3]
  connect_bd_net -net PS_data_transport_enable [get_bd_pins PS_data_transport/enable] [get_bd_pins led_connect_0/led7]
  connect_bd_net -net PS_data_transport_finished_state [get_bd_pins PS_data_transport/McBSP_Frame] [get_bd_pins led_connect_0/led8]
  connect_bd_net -net PS_data_transport_mon_control [get_bd_pins PS_data_transport/mon_control] [get_bd_pins PS/gpio_io_6_x13]
  connect_bd_net -net PS_data_transport_writeposition [get_bd_pins PS_data_transport/writeposition] [get_bd_pins PS/gpio_io_5_x12]
  connect_bd_net -net SPM_control_logic_M_AXIS_PASS_tdata [get_bd_pins SPM_control_logic/M_AXIS_PASS_tdata] [get_bd_pins PS/gpio_io_6_x14]
  connect_bd_net -net SPM_control_logic_M_AXIS_XSMON_tdata [get_bd_pins SPM_control_logic/M_AXIS_XSMON_tdata] [get_bd_pins PS/gpio_io_0_x1]
  connect_bd_net -net SPM_control_logic_M_AXIS_ZSMON_tdata [get_bd_pins SPM_control_logic/M_AXIS_ZSMON_tdata] [get_bd_pins PS/gpio_io_9_x19]
  connect_bd_net -net SPM_control_logic_dbg_status [get_bd_pins SPM_control_logic/dbg_status] [get_bd_pins xlslice_0/Din]
  connect_bd_net -net SPM_control_logic_enable [get_bd_pins SPM_control_logic/enable] [get_bd_pins xlconcat_spmc_status/In0]
  connect_bd_net -net SPM_control_logic_gvp_finished [get_bd_pins SPM_control_logic/gvp_finished] [get_bd_pins xlconcat_spmc_status/In1]
  connect_bd_net -net SPM_control_logic_gvp_hold [get_bd_pins SPM_control_logic/gvp_hold] [get_bd_pins xlconcat_spmc_status/In2]
  connect_bd_net -net SPM_control_logic_last_write_addr [get_bd_pins SPM_control_logic/last_write_addr] [get_bd_pins PS/gpio_io_10_x21]
  connect_bd_net -net adc_clk_n_i_1 [get_bd_ports adc_clk_n_i] [get_bd_pins axis_red_pitaya_adc_0/adc_clk_n]
  connect_bd_net -net adc_clk_p_i_1 [get_bd_ports adc_clk_p_i] [get_bd_pins axis_red_pitaya_adc_0/adc_clk_p]
  connect_bd_net -net adc_dat_a_i_1 [get_bd_ports adc_dat_a_i] [get_bd_pins axis_red_pitaya_adc_0/adc_dat_a]
  connect_bd_net -net adc_dat_b_i_1 [get_bd_ports adc_dat_b_i] [get_bd_pins axis_red_pitaya_adc_0/adc_dat_b]
  connect_bd_net -net amplitude_controller_mon_signal [get_bd_pins PAC_PLL/mon_signal] [get_bd_pins PS/gpio_io_1_x4]
  connect_bd_net -net axis_dc_filter_0_dbg_m [get_bd_pins PAC_PLL/dbg_m] [get_bd_pins PS/gpio_io_1_x3]
  connect_bd_net -net axis_dc_filter_0_dbg_mdc [get_bd_pins PAC_PLL/dbg_mdc] [get_bd_pins PS/gpio_io_2_x5]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_clk1 [get_bd_pins axis_red_pitaya_adc_0/adc_clk] [get_bd_pins Block_QControl/a_clk] [get_bd_pins PAC_PLL/aclk] [get_bd_pins PS_data_transport/a_clk] [get_bd_pins SPM_control_logic/a_clk] [get_bd_pins VolumeAdjuster16_14/a_clk] [get_bd_pins VolumeAdjuster16_14/adc_clk] [get_bd_pins Volume_QControl_Mixer/a_clk] [get_bd_pins Volume_QControl_Mixer/adc_clk] [get_bd_pins axis_red_pitaya_dac_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins axis_sc26_to_14_0/a_clk]
  connect_bd_net -net axis_red_pitaya_adc_0_adc_csn [get_bd_pins axis_red_pitaya_adc_0/adc_csn] [get_bd_ports adc_csn_o]
  connect_bd_net -net axis_red_pitaya_dac_0_dac_clk [get_bd_pins axis_red_pitaya_dac_0/dac_clk] [get_bd_ports dac_clk_o]
  connect_bd_net -net axis_red_pitaya_dac_0_dac_dat [get_bd_pins axis_red_pitaya_dac_0/dac_dat] [get_bd_ports dac_dat_o]
  connect_bd_net -net axis_red_pitaya_dac_0_dac_rst [get_bd_pins axis_red_pitaya_dac_0/dac_rst] [get_bd_ports dac_rst_o]
  connect_bd_net -net axis_red_pitaya_dac_0_dac_sel [get_bd_pins axis_red_pitaya_dac_0/dac_sel] [get_bd_ports dac_sel_o]
  connect_bd_net -net axis_red_pitaya_dac_0_dac_wrt [get_bd_pins axis_red_pitaya_dac_0/dac_wrt] [get_bd_ports dac_wrt_o]
  connect_bd_net -net cfg_axis_phaseinc_status [get_bd_pins PAC_PLL/enable] [get_bd_pins led_connect_0/led4]
  connect_bd_net -net cfg_axis_volume_status [get_bd_pins PAC_PLL/enable1] [get_bd_pins led_connect_0/led1]
  connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins axis_red_pitaya_dac_0/ddr_clk]
  connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins axis_red_pitaya_dac_0/locked]
  connect_bd_net -net daisy_n_i_1 [get_bd_ports daisy_n_i] [get_bd_pins util_ds_buf_1/IBUF_DS_N]
  connect_bd_net -net daisy_p_i_1 [get_bd_ports daisy_p_i] [get_bd_pins util_ds_buf_1/IBUF_DS_P]
  connect_bd_net -net gpio2_io_9_x20_1 [get_bd_pins SPM_control_logic/M_AXIS_Z0MON_tdata] [get_bd_pins PS/gpio2_io_9_x20]
  connect_bd_net -net gpio2_io_i_1 [get_bd_pins PAC_PLL/mon_signal1] [get_bd_pins PS/gpio_io_4_x10]
  connect_bd_net -net gpio2_io_i_2 [get_bd_pins SPM_control_logic/M_AXIS_Z_tdata] [get_bd_pins PS/gpio_io_10_x22]
  connect_bd_net -net gpio_io_0_x2_1 [get_bd_pins SPM_control_logic/M_AXIS_YSMON_tdata] [get_bd_pins PS/gpio_io_0_x2]
  connect_bd_net -net gpio_io_3_x7_1 [get_bd_pins PAC_PLL/mon_control] [get_bd_pins PS/gpio_io_3_x7]
  connect_bd_net -net gpio_io_3_x8_1 [get_bd_pins PAC_PLL/mon_control1] [get_bd_pins PS/gpio_io_3_x8]
  connect_bd_net -net gpio_io_4_x9_1 [get_bd_pins PAC_PLL/mon_control_lower33] [get_bd_pins PS/gpio_io_4_x9]
  connect_bd_net -net gpio_io_5_x11_1 [get_bd_pins PS_data_transport/delta_frequency_monitor] [get_bd_pins PS/gpio_io_5_x11]
  connect_bd_net -net gpio_io_7_x15_1 [get_bd_pins SPM_control_logic/mon3] [get_bd_pins PS/gpio_io_7_x15]
  connect_bd_net -net gpio_io_7_x16_1 [get_bd_pins SPM_control_logic/mon0] [get_bd_pins PS/gpio_io_7_x16]
  connect_bd_net -net gpio_io_8_x17_1 [get_bd_pins SPM_control_logic/mon1] [get_bd_pins PS/gpio_io_8_x17]
  connect_bd_net -net gpio_io_8_x18_1 [get_bd_pins SPM_control_logic/mon2] [get_bd_pins PS/gpio_io_8_x18]
  connect_bd_net -net led_connect_0_leds [get_bd_pins led_connect_0/leds] [get_bd_ports led_o]
  connect_bd_net -net lms_phase_amplitude_detector_0_zero_spcp [get_bd_pins PAC_PLL/zero_spcp] [get_bd_pins PS_data_transport/zero_spcp]
  connect_bd_net -net util_ds_buf_1_IBUF_OUT [get_bd_pins util_ds_buf_1/IBUF_OUT] [get_bd_pins util_ds_buf_2/OBUF_IN]
  connect_bd_net -net util_ds_buf_2_OBUF_DS_N [get_bd_pins util_ds_buf_2/OBUF_DS_N] [get_bd_ports daisy_n_o]
  connect_bd_net -net util_ds_buf_2_OBUF_DS_P [get_bd_pins util_ds_buf_2/OBUF_DS_P] [get_bd_ports daisy_p_o]
  connect_bd_net -net xlconcat_spmc_status_dout [get_bd_pins xlconcat_spmc_status/dout] [get_bd_pins PS/gpio_io_2_x6]
  connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_spmc_status/In8]

  # Create address segments
  assign_bd_address -offset 0x40000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_bram_reader_0/s00_axi/reg0] -force
  assign_bd_address -offset 0x50000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_bram_reader_1/s00_axi/reg0] -force
  assign_bd_address -offset 0x42000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_cfg_register_0/s_axi/reg0] -force
  assign_bd_address -offset 0x43000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_cfg_register_1/s_axi/reg0] -force
  assign_bd_address -offset 0x42002000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_0/S_AXI/Reg] -force
  assign_bd_address -offset 0x4200C000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_10/S_AXI/Reg] -force
  assign_bd_address -offset 0x42003000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_1/S_AXI/Reg] -force
  assign_bd_address -offset 0x42004000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_2/S_AXI/Reg] -force
  assign_bd_address -offset 0x42005000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_3/S_AXI/Reg] -force
  assign_bd_address -offset 0x42006000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_4/S_AXI/Reg] -force
  assign_bd_address -offset 0x42007000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_5/S_AXI/Reg] -force
  assign_bd_address -offset 0x42008000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_6/S_AXI/Reg] -force
  assign_bd_address -offset 0x42009000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_7/S_AXI/Reg] -force
  assign_bd_address -offset 0x4200A000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_8/S_AXI/Reg] -force
  assign_bd_address -offset 0x4200B000 -range 0x00001000 -target_address_space [get_bd_addr_spaces PS/processing_system7_Zynq/Data] [get_bd_addr_segs PS/axi_gpio_9/S_AXI/Reg] -force

  # Perform GUI Layout
  regenerate_bd_layout -layout_string {
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"1.6245",
   "Default View_TopLeft":"4508,182",
   "ExpandedHierarchyInLayout":"/PS_data_transport|/SPM_control_logic",
   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
#  -string -flagsOSRD
preplace port DDR -pg 1 -lvl 9 -x 9880 -y 1010 -defaultsOSRD
preplace port FIXED_IO -pg 1 -lvl 9 -x 9880 -y 1180 -defaultsOSRD
preplace port Vaux0 -pg 1 -lvl 0 -x -10 -y 20 -defaultsOSRD
preplace port Vaux1 -pg 1 -lvl 0 -x -10 -y 50 -defaultsOSRD
preplace port Vaux8 -pg 1 -lvl 0 -x -10 -y 80 -defaultsOSRD
preplace port Vaux9 -pg 1 -lvl 0 -x -10 -y 110 -defaultsOSRD
preplace port Vp_Vn -pg 1 -lvl 0 -x -10 -y 140 -defaultsOSRD
preplace port gpio_rtl_0 -pg 1 -lvl 9 -x 9880 -y 50 -defaultsOSRD
preplace port spi_rtl_0 -pg 1 -lvl 9 -x 9880 -y 240 -defaultsOSRD
preplace port gpio_rtl_1 -pg 1 -lvl 9 -x 9880 -y 80 -defaultsOSRD
preplace port gpio_rtl_2 -pg 1 -lvl 9 -x 9880 -y 110 -defaultsOSRD
preplace port port-id_adc_clk_n_i -pg 1 -lvl 0 -x -10 -y 1410 -defaultsOSRD
preplace port port-id_adc_clk_p_i -pg 1 -lvl 0 -x -10 -y 1380 -defaultsOSRD
preplace port port-id_adc_csn_o -pg 1 -lvl 9 -x 9880 -y 1210 -defaultsOSRD
preplace port port-id_adc_enc_n_o -pg 1 -lvl 9 -x 9880 -y 140 -defaultsOSRD
preplace port port-id_adc_enc_p_o -pg 1 -lvl 9 -x 9880 -y 210 -defaultsOSRD
preplace port port-id_dac_clk_o -pg 1 -lvl 9 -x 9880 -y 1250 -defaultsOSRD
preplace port port-id_dac_rst_o -pg 1 -lvl 9 -x 9880 -y 1280 -defaultsOSRD
preplace port port-id_dac_sel_o -pg 1 -lvl 9 -x 9880 -y 1310 -defaultsOSRD
preplace port port-id_dac_wrt_o -pg 1 -lvl 9 -x 9880 -y 1340 -defaultsOSRD
preplace port port-id_reset_rtl_0 -pg 1 -lvl 0 -x -10 -y 170 -defaultsOSRD
preplace portBus adc_dat_a_i -pg 1 -lvl 0 -x -10 -y 1440 -defaultsOSRD
preplace portBus adc_dat_b_i -pg 1 -lvl 0 -x -10 -y 1470 -defaultsOSRD
preplace portBus dac_dat_o -pg 1 -lvl 9 -x 9880 -y 1370 -defaultsOSRD
preplace portBus dac_pwm_o -pg 1 -lvl 9 -x 9880 -y 20 -defaultsOSRD
preplace portBus daisy_n_i -pg 1 -lvl 0 -x -10 -y 1520 -defaultsOSRD
preplace portBus daisy_n_o -pg 1 -lvl 9 -x 9880 -y 1130 -defaultsOSRD
preplace portBus daisy_p_i -pg 1 -lvl 0 -x -10 -y 1340 -defaultsOSRD
preplace portBus daisy_p_o -pg 1 -lvl 9 -x 9880 -y 1100 -defaultsOSRD
preplace portBus exp_n_io -pg 1 -lvl 9 -x 9880 -y 600 -defaultsOSRD
preplace portBus exp_p_io -pg 1 -lvl 9 -x 9880 -y 320 -defaultsOSRD
preplace portBus led_o -pg 1 -lvl 9 -x 9880 -y 180 -defaultsOSRD
preplace inst Block_QControl -pg 1 -lvl 6 -x 8995 -y 1090 -defaultsOSRD
preplace inst PAC_PLL -pg 1 -lvl 3 -x 920 -y 360 -defaultsOSRD
preplace inst PS -pg 1 -lvl 3 -x 920 -y 1070 -defaultsOSRD
preplace inst PS_data_transport -pg 1 -lvl 4 -x 1780 -y 562 -defaultsOSRD
preplace inst SPM_control_logic -pg 1 -lvl 5 -x 4865 -y 522 -defaultsOSRD
preplace inst VolumeAdjuster16_14 -pg 1 -lvl 6 -x 8995 -y 1280 -defaultsOSRD
preplace inst Volume_QControl_Mixer -pg 1 -lvl 7 -x 9310 -y 1280 -defaultsOSRD
preplace inst axis_red_pitaya_adc_0 -pg 1 -lvl 2 -x 390 -y 1430 -defaultsOSRD
preplace inst axis_red_pitaya_dac_0 -pg 1 -lvl 8 -x 9680 -y 1310 -defaultsOSRD
preplace inst led_connect_0 -pg 1 -lvl 8 -x 9680 -y 180 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 7 -x 9310 -y 1450 -defaultsOSRD
preplace inst util_ds_buf_1 -pg 1 -lvl 7 -x 9310 -y 1100 -defaultsOSRD
preplace inst util_ds_buf_2 -pg 1 -lvl 8 -x 9680 -y 1100 -defaultsOSRD
preplace inst xlconcat_spmc_status -pg 1 -lvl 2 -x 390 -y 960 -defaultsOSRD
preplace inst xlslice_0 -pg 1 -lvl 1 -x 130 -y 1040 -defaultsOSRD
preplace inst axis_sc26_to_14_0 -pg 1 -lvl 5 -x 4865 -y 2654 -defaultsOSRD
preplace inst PS_data_transport|PulseFormer -pg 1 -lvl 6 -x 4050 -y 1312 -defaultsOSRD
preplace inst PS_data_transport|controller_dfreq -pg 1 -lvl 3 -x 2820 -y 1882 -defaultsOSRD
preplace inst PS_data_transport|blk_mem_gen_pacpll -pg 1 -lvl 4 -x 3260 -y 1582 -defaultsOSRD
preplace inst PS_data_transport|const_zero1 -pg 1 -lvl 2 -x 2300 -y 1832 -defaultsOSRD
preplace inst PS_data_transport|const_zero -pg 1 -lvl 2 -x 2300 -y 1932 -defaultsOSRD
preplace inst PS_data_transport|axis_4s_combine_decimate -pg 1 -lvl 2 -x 2300 -y 1482 -defaultsOSRD
preplace inst PS_data_transport|McBSP_io_connect_0 -pg 1 -lvl 4 -x 3260 -y 842 -defaultsOSRD
preplace inst PS_data_transport|McBSP_controller_0 -pg 1 -lvl 5 -x 3720 -y 902 -defaultsOSRD
preplace inst PS_data_transport|cfg18_19_to_transport_auxcenter -pg 1 -lvl 1 -x 1830 -y 1962 -defaultsOSRD
preplace inst PS_data_transport|cfg_to_transport_channel_select -pg 1 -lvl 1 -x 1830 -y 1682 -defaultsOSRD
preplace inst PS_data_transport|cfg_to_transport_control -pg 1 -lvl 1 -x 1830 -y 1562 -defaultsOSRD
preplace inst PS_data_transport|cfg_to_transport_decimation -pg 1 -lvl 1 -x 1830 -y 1802 -defaultsOSRD
preplace inst PS_data_transport|cfg_to_transport_nsamples -pg 1 -lvl 1 -x 1830 -y 2082 -defaultsOSRD
preplace inst PS_data_transport|axis_bram_push2ch64 -pg 1 -lvl 3 -x 2820 -y 1582 -defaultsOSRD
preplace inst PS_data_transport|axis_FIR_CH1 -pg 1 -lvl 4 -x 3260 -y 1342 -defaultsOSRD
preplace inst PS_data_transport|axis_FIR_CH2 -pg 1 -lvl 4 -x 3260 -y 482 -defaultsOSRD
preplace inst PS_data_transport|axis_FIR_CH3 -pg 1 -lvl 4 -x 3260 -y 622 -defaultsOSRD
preplace inst PS_data_transport|axis_FIR_CH4 -pg 1 -lvl 4 -x 3260 -y 1062 -defaultsOSRD
preplace inst PS_data_transport|axis_splitter_dFreqCrtl -pg 1 -lvl 4 -x 3260 -y 1202 -defaultsOSRD
preplace inst SPM_control_logic|xlslice_cfg_dac_mode -pg 1 -lvl 7 -x 7355 -y 1942 -defaultsOSRD
preplace inst SPM_control_logic|xlslice_cfg_dac_send -pg 1 -lvl 7 -x 7355 -y 1172 -defaultsOSRD
preplace inst SPM_control_logic|xlslice_gvp_reset -pg 1 -lvl 2 -x 5165 -y 662 -defaultsOSRD
preplace inst SPM_control_logic|xlslice_gvp_setvec -pg 1 -lvl 2 -x 5165 -y 862 -defaultsOSRD
preplace inst SPM_control_logic|xlslice_cfg_dac_axis -pg 1 -lvl 7 -x 7355 -y 1842 -defaultsOSRD
preplace inst SPM_control_logic|controller_zservo -pg 1 -lvl 6 -x 6875 -y 932 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_cfg_dac_axis -pg 1 -lvl 7 -x 7355 -y 1732 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_cfg_dac_control -pg 1 -lvl 6 -x 6875 -y 1752 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_gvp_program_vector -pg 1 -lvl 2 -x 5165 -y 1072 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_gvp_setvector -pg 1 -lvl 1 -x 4885 -y 992 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_rotmxx -pg 1 -lvl 6 -x 6875 -y 1322 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_rotmxy -pg 1 -lvl 6 -x 6875 -y 1172 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_slope_x -pg 1 -lvl 6 -x 6875 -y 1612 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_slope_y -pg 1 -lvl 6 -x 6875 -y 1872 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_x0 -pg 1 -lvl 6 -x 6875 -y 2112 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_y0 -pg 1 -lvl 6 -x 6875 -y 2232 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_z0 -pg 1 -lvl 6 -x 6875 -y 2472 -defaultsOSRD
preplace inst SPM_control_logic|xlslice_gvp_pause -pg 1 -lvl 2 -x 5165 -y 762 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_bias -pg 1 -lvl 6 -x 6875 -y 1462 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_xy_move_step -pg 1 -lvl 6 -x 6875 -y 1992 -defaultsOSRD
preplace inst SPM_control_logic|cfg3_to_z_move_step -pg 1 -lvl 6 -x 6875 -y 2352 -defaultsOSRD
preplace inst SPM_control_logic|xlslice_gvp_reset_options -pg 1 -lvl 2 -x 5165 -y 962 -defaultsOSRD
preplace inst SPM_control_logic|AD5791_io_connect_0 -pg 1 -lvl 9 -x 8265 -y 1322 -defaultsOSRD
preplace inst SPM_control_logic|axis_AD5791_0 -pg 1 -lvl 8 -x 7905 -y 1372 -defaultsOSRD
preplace inst SPM_control_logic|blk_mem_gen_spmc -pg 1 -lvl 6 -x 6875 -y 702 -defaultsOSRD
preplace inst SPM_control_logic|gvp_main -pg 1 -lvl 3 -x 5495 -y 782 -defaultsOSRD
preplace inst SPM_control_logic|axis_bram_stream_srcs -pg 1 -lvl 5 -x 6435 -y 542 -defaultsOSRD
preplace inst SPM_control_logic|axis_spm_control -pg 1 -lvl 7 -x 7355 -y 1452 -defaultsOSRD
preplace inst SPM_control_logic|axis_splitter_U -pg 1 -lvl 4 -x 5915 -y 1302 -defaultsOSRD
preplace inst SPM_control_logic|axis_splitter_Z -pg 1 -lvl 4 -x 5915 -y 1162 -defaultsOSRD
preplace inst SPM_control_logic|axis_splitter_Y -pg 1 -lvl 4 -x 5915 -y 922 -defaultsOSRD
preplace inst SPM_control_logic|axis_splitter_X -pg 1 -lvl 4 -x 5915 -y 762 -defaultsOSRD
preplace inst SPM_control_logic|axis_splitter_CH0_S16_to_S32 -pg 1 -lvl 4 -x 5915 -y 432 -defaultsOSRD
preplace inst SPM_control_logic|axis_splitter_ZControlSignalPass -pg 1 -lvl 8 -x 7905 -y 892 -defaultsOSRD
preplace netloc Net 1 5 4 8780J 600 NJ 600 NJ 600 NJ
preplace netloc Net1 1 5 4 8770J 320 NJ 320 NJ 320 NJ
preplace netloc PS_Amplitude_Controller_status_max 1 3 5 1180J 12 NJ 12 NJ 12 NJ 12 9530
preplace netloc PS_Amplitude_Controller_status_min 1 3 5 1290J 82 NJ 82 NJ 82 NJ 82 9520
preplace netloc PS_Dout 1 2 3 620 1420 1350 332 4545J
preplace netloc PS_Phase_Controller_mon_control_B 1 3 1 N 480
preplace netloc PS_Phase_Controller_status_max 1 3 5 1210J 22 NJ 22 NJ 22 NJ 22 9480
preplace netloc PS_Phase_Controller_status_min 1 3 5 1230J 32 NJ 32 NJ 32 NJ 32 9470
preplace netloc PS_cfg_data 1 2 4 610 1430 1170 42 NJ 42 8790
preplace netloc PS_cfg_data_reg_2 1 3 1 1110 1120n
preplace netloc PS_cfg_data_reg_3 1 3 2 1430 270 4585J
preplace netloc PS_data_transport_enable 1 4 4 4515 232 NJ 232 NJ 232 9530J
preplace netloc PS_data_transport_finished_state 1 4 4 4525 242 NJ 242 NJ 242 9460J
preplace netloc PS_data_transport_mon_control 1 2 3 740 1330 1450J 322 4400
preplace netloc PS_data_transport_writeposition 1 2 3 720 1340 1490J 342 4420
preplace netloc SPM_control_logic_M_AXIS_PASS_tdata 1 2 4 710 1350 1240J 92 NJ 92 8640
preplace netloc SPM_control_logic_M_AXIS_XSMON_tdata 1 2 4 650 720 1360J 142 NJ 142 8660
preplace netloc SPM_control_logic_M_AXIS_ZSMON_tdata 1 2 4 600 2750 NJ 2750 NJ 2750 8680
preplace netloc SPM_control_logic_dbg_status 1 0 6 20 710 NJ 710 NJ 710 1390J 202 NJ 202 8680
preplace netloc SPM_control_logic_enable 1 1 5 270 2760 NJ 2760 NJ 2760 NJ 2760 8710
preplace netloc SPM_control_logic_gvp_finished 1 1 5 250 2790 NJ 2790 NJ 2790 NJ 2790 8720
preplace netloc SPM_control_logic_gvp_hold 1 1 5 260 2770 NJ 2770 NJ 2770 NJ 2770 8700
preplace netloc adc_clk_n_i_1 1 0 2 NJ 1410 240J
preplace netloc adc_clk_p_i_1 1 0 2 NJ 1380 240J
preplace netloc adc_dat_a_i_1 1 0 2 NJ 1440 NJ
preplace netloc adc_dat_b_i_1 1 0 2 10J 1460 NJ
preplace netloc amplitude_controller_mon_signal 1 2 2 690 730 1110
preplace netloc axis_dc_filter_0_dbg_m 1 2 2 740 740 1160
preplace netloc axis_dc_filter_0_dbg_mdc 1 2 2 730 800 1150
preplace netloc axis_red_pitaya_adc_0_adc_clk1 1 2 6 590 1440 1190 362 4485 2740 8845 1190 9150 1190 9530
preplace netloc axis_red_pitaya_adc_0_adc_csn 1 2 7 NJ 1450 1420J 102 NJ 102 NJ 102 NJ 102 9500J 30 9850J
preplace netloc axis_red_pitaya_dac_0_dac_clk 1 8 1 9860J 1250n
preplace netloc axis_red_pitaya_dac_0_dac_dat 1 8 1 9830J 1350n
preplace netloc axis_red_pitaya_dac_0_dac_rst 1 8 1 9830J 1280n
preplace netloc axis_red_pitaya_dac_0_dac_sel 1 8 1 NJ 1310
preplace netloc axis_red_pitaya_dac_0_dac_wrt 1 8 1 9860J 1330n
preplace netloc cfg_axis_phaseinc_status 1 3 5 1270J 112 NJ 112 NJ 112 NJ 112 9460
preplace netloc cfg_axis_volume_status 1 3 5 1310J 122 NJ 122 NJ 122 NJ 122 9510
preplace netloc clk_wiz_0_clk_out1 1 7 1 9460 1320n
preplace netloc clk_wiz_0_locked 1 7 1 9530 1340n
preplace netloc daisy_n_i_1 1 0 7 NJ 1520 NJ 1520 NJ 1520 1460J 152 NJ 152 NJ 152 9160J
preplace netloc daisy_p_i_1 1 0 7 NJ 1340 NJ 1340 520J 1360 1220J 162 NJ 162 NJ 162 9150J
preplace netloc gpio2_io_9_x20_1 1 2 4 630 2780 NJ 2780 NJ 2780 8690
preplace netloc gpio2_io_i_1 1 2 2 720 790 1100
preplace netloc gpio_io_0_x2_1 1 2 4 650 2180 NJ 2180 4440J 2570 8640
preplace netloc gpio_io_3_x7_1 1 2 2 630 750 1140
preplace netloc gpio_io_3_x8_1 1 2 2 640 760 1130
preplace netloc gpio_io_4_x9_1 1 2 2 700 770 1120
preplace netloc gpio_io_5_x11_1 1 2 3 710 780 1440J 352 4410
preplace netloc gpio_io_7_x15_1 1 2 4 700 1370 1260J 172 NJ 172 8670
preplace netloc gpio_io_7_x16_1 1 2 4 690 1380 1280J 182 NJ 182 8750
preplace netloc gpio_io_8_x17_1 1 2 4 680 1390 1480J 212 NJ 212 8650
preplace netloc gpio_io_8_x18_1 1 2 4 670 1400 1510J 222 NJ 222 8730
preplace netloc led_connect_0_leds 1 8 1 NJ 180
preplace netloc lms_phase_amplitude_detector_0_zero_spcp 1 3 1 1330 660n
preplace netloc util_ds_buf_1_IBUF_OUT 1 7 1 N 1100
preplace netloc util_ds_buf_2_OBUF_DS_N 1 8 1 9830J 1120n
preplace netloc util_ds_buf_2_OBUF_DS_P 1 8 1 NJ 1100
preplace netloc xlconcat_spmc_status_dout 1 2 1 N 960
preplace netloc xlslice_0_Dout 1 1 1 NJ 1040
preplace netloc SPM_control_logic_last_write_addr 1 2 4 640 2800 NJ 2800 NJ 2800 8660
preplace netloc gpio2_io_i_2 1 2 4 660 1410 1470J 192 NJ 192 8740
preplace netloc PS_Amplitude_Controller_M_AXIS_CONTROL 1 3 3 1220 72 NJ 72 8760J
preplace netloc PS_Amplitude_Controller_M_AXIS_CONTROL2 1 3 1 1250 120n
preplace netloc PS_Amplitude_Controller_M_AXIS_PASS2 1 3 1 1380 200n
preplace netloc PS_BRAM_PORTA 1 3 1 1390 1000n
preplace netloc PS_Phase_Controller_M_AXIS_CONTROL2 1 3 1 1300 140n
preplace netloc PS_Phase_Controller_M_AXIS_PASS2 1 3 1 1400 220n
preplace netloc PS_data_transport_M_AXIS_ADC2 1 3 2 NJ 280 4595
preplace netloc PS_data_transport_M_AXIS_aux 1 4 1 4430 632n
preplace netloc QControl_M_AXIS 1 6 1 9140 1090n
preplace netloc S_AXIS1_1 1 3 1 1410 240n
preplace netloc VolumeAdjuster16_14_M_AXIS 1 6 1 9160 1270n
preplace netloc Volume_QControl_Mixer_0_M_AXIS 1 7 1 N 1280
preplace netloc axis_dc_filter_0_M_AXIS_AC16 1 3 3 1200 52 NJ 52 8690J
preplace netloc axis_dc_filter_0_M_AXIS_ACDC 1 3 1 1200 80n
preplace netloc axis_red_pitaya_adc_0_M_AXIS 1 2 1 510 330n
preplace netloc axis_sc26_to_14_0_M_AXIS 1 5 1 8855 1270n
preplace netloc lms_phase_amplitude_detector_0_M_AXIS_SC 1 3 2 1340J 2190 4410
preplace netloc processing_system7_0_DDR 1 3 6 1370J 132 NJ 132 8730J 52 NJ 52 9490J 40 9860J
preplace netloc processing_system7_0_FIXED_IO 1 3 6 1320J 62 NJ 62 NJ 62 NJ 62 9520J 50 9840J
preplace netloc PS_BRAM_PORTA1 1 3 2 1500J 372 4555
preplace netloc S_AXIS_ch9s_1 1 4 1 4495 512n
preplace netloc PS_data_transport_M_AXIS3 1 4 1 4505 532n
preplace netloc S_AXIS_chBs_1 1 4 1 4535 552n
preplace netloc PS_data_transport_M_AXIS5 1 4 1 4555 572n
preplace netloc PS_data_transport_M_AXIS6 1 4 1 4575 592n
preplace netloc PAC_PLL_M_AXIS2 1 3 2 NJ 300 4565
preplace netloc PS_data_transport|McBSP_controller_0_mcbsp_data_clkr 1 3 3 3110 702 NJ 702 3890
preplace netloc PS_data_transport|McBSP_controller_0_mcbsp_data_frm 1 3 4 3110 972 3430J 1092 3930 1122 4200J
preplace netloc PS_data_transport|McBSP_controller_0_mcbsp_data_fsx 1 3 3 3100 982 3420J 1082 3890
preplace netloc PS_data_transport|McBSP_controller_0_mcbsp_data_tx 1 3 3 3090 1452 NJ 1452 3910
preplace netloc PS_data_transport|McBSP_controller_0_trigger 1 1 5 2070 1992 NJ 1992 NJ 1992 NJ 1992 3900
preplace netloc PS_data_transport|McBSP_io_connect_0_McBSP_clk 1 4 1 3510 812n
preplace netloc PS_data_transport|McBSP_io_connect_0_McBSP_fs 1 4 1 3490 832n
preplace netloc PS_data_transport|McBSP_io_connect_0_McBSP_nrx 1 4 1 3440 872n
preplace netloc PS_data_transport|McBSP_io_connect_0_McBSP_rx 1 4 1 3470 852n
preplace netloc PS_data_transport|Net 1 4 3 3420 692 NJ 692 4190J
preplace netloc PS_data_transport|Net1 1 4 3 3440 722 NJ 722 4180J
preplace netloc PS_data_transport|axis_4s_combine_0_BR_ch1s 1 2 1 2590 1542n
preplace netloc PS_data_transport|axis_4s_combine_0_BR_ch2s 1 2 1 2600 1562n
preplace netloc PS_data_transport|axis_4s_combine_0_BR_reset 1 2 1 2640 1602n
preplace netloc PS_data_transport|axis_4s_combine_0_bram_porta_addr 1 3 1 N 1542
preplace netloc PS_data_transport|axis_4s_combine_0_bram_porta_clk 1 3 1 3070 1522n
preplace netloc PS_data_transport|axis_4s_combine_0_bram_porta_en 1 3 1 3020 1582n
preplace netloc PS_data_transport|axis_4s_combine_0_bram_porta_we 1 3 1 3010 1602n
preplace netloc PS_data_transport|axis_4s_combine_0_bram_porta_wrdata 1 3 1 3060 1562n
preplace netloc PS_data_transport|axis_4s_combine_0_writeposition 1 2 5 2570 1462 NJ 1462 NJ 1462 NJ 1462 NJ
preplace netloc PS_data_transport|axis_4s_combine_decimate_BR_next 1 2 1 2620 1582n
preplace netloc PS_data_transport|axis_4s_combine_decimate_FIR_next 1 2 2 2560J 1412 3040
preplace netloc PS_data_transport|axis_4s_combine_decimate_delta_frequency_monitor 1 2 5 2550 1302 3020J 712 NJ 712 NJ 712 4240J
preplace netloc PS_data_transport|axis_bram_push2ch64_last_write_addr 1 1 3 2080 1712 NJ 1712 3000
preplace netloc PS_data_transport|axis_bram_push_0_ready 1 1 3 2060 2002 NJ 2002 3010
preplace netloc PS_data_transport|axis_red_pitaya_adc_0_adc_clk 1 0 6 1690 1492 2030 1732 2630 1432 3060 1432 3530 1292 NJ
preplace netloc PS_data_transport|cfg18_19_to_transport_auxcenter_data 1 1 1 2000 1512n
preplace netloc PS_data_transport|cfg2_1 1 0 6 1660J 1882 2010J 1752 2640J 1702 NJ 1702 3550J 1432 3920
preplace netloc PS_data_transport|cfg_1 1 0 3 1700 1892 2050J 1772 2520
preplace netloc PS_data_transport|cfg_2 1 0 3 1660J 1462 1990J 1742 2550
preplace netloc PS_data_transport|cfg_to_channel_select_data 1 1 1 1980 1592n
preplace netloc PS_data_transport|cfg_to_transport_channel_select1_data 1 1 1 2040 1572n
preplace netloc PS_data_transport|cfg_to_transport_control_data 1 1 1 1960 1532n
preplace netloc PS_data_transport|cfg_to_transport_data 1 1 1 1970 1552n
preplace netloc PS_data_transport|const_zero1_dout 1 2 1 2530J 1832n
preplace netloc PS_data_transport|const_zero_dout 1 2 1 NJ 1932
preplace netloc PS_data_transport|controller_dfreq_enable 1 3 4 3100 1712 3540J 1232 NJ 1232 4170J
preplace netloc PS_data_transport|controller_dfreq_mon_control 1 3 4 3110 1722 NJ 1722 NJ 1722 4240J
preplace netloc PS_data_transport|zero_spcp_1 1 0 6 NJ 1872 2020J 1762 2610J 1442 NJ 1442 NJ 1442 3930
preplace netloc PS_data_transport|Conn1 1 0 2 NJ 1452 N
preplace netloc PS_data_transport|Conn2 1 0 2 NJ 1472 N
preplace netloc PS_data_transport|Conn3 1 0 2 NJ 1432 N
preplace netloc PS_data_transport|PS_Amplitude_Controller_M_AXIS_CONTROL2 1 0 2 NJ 1352 N
preplace netloc PS_data_transport|PS_Amplitude_Controller_M_AXIS_PASS2 1 0 2 NJ 1412 N
preplace netloc PS_data_transport|PS_BRAM_PORTA 1 0 4 NJ 1232 NJ 1232 2560J 1322 3050
preplace netloc PS_data_transport|PS_Phase_Controller_M_AXIS_CONTROL2 1 0 2 NJ 1372 N
preplace netloc PS_data_transport|PS_Phase_Controller_M_AXIS_PASS2 1 0 2 NJ 1392 N
preplace netloc PS_data_transport|PulseForm_0_M_AXIS 1 6 1 4210 632n
preplace netloc PS_data_transport|axis_4s_combine_decimate_M_AXIS_CH1 1 2 2 N 1332 3070J
preplace netloc PS_data_transport|axis_4s_combine_decimate_M_AXIS_CH2 1 2 2 2520J 1282 3000
preplace netloc PS_data_transport|axis_4s_combine_decimate_M_AXIS_CH3 1 2 2 2530J 1292 3010
preplace netloc PS_data_transport|axis_4s_combine_decimate_M_AXIS_CH4 1 2 2 2540J 1312 3050
preplace netloc PS_data_transport|axis_4s_combine_decimate_M_AXIS_DFREQ_DEC 1 2 3 2520J 1422 NJ 1422 3520
preplace netloc PS_data_transport|axis_4s_combine_decimate_M_AXIS_DFREQ_DEC2 1 2 1 2580 1432n
preplace netloc PS_data_transport|axis_FIR_CH1_M_AXIS 1 4 1 3480 782n
preplace netloc PS_data_transport|axis_FIR_CH2_M_AXIS 1 4 1 3540 472n
preplace netloc PS_data_transport|axis_FIR_CH3_M_AXIS 1 4 1 3520 612n
preplace netloc PS_data_transport|axis_FIR_CH4_M_AXIS 1 4 1 3460 842n
preplace netloc PS_data_transport|controller_dfreq_M_AXIS_CONTROL2 1 1 3 2050 1722 NJ 1722 3000
preplace netloc PS_data_transport|lms_phase_amplitude_detector_0_M_AXIS_SIGNAL 1 0 2 NJ 1312 N
preplace netloc PS_data_transport|axis_FIR_CH1_M_AXIS2 1 4 3 3450 682 NJ 682 4220J
preplace netloc PS_data_transport|axis_FIR_CH2_M_AXIS2 1 4 3 3550 662 NJ 662 4240J
preplace netloc PS_data_transport|axis_FIR_CH3_M_AXIS2 1 4 3 3530 672 NJ 672 4230J
preplace netloc PS_data_transport|axis_FIR_CH4_M_AXIS2 1 4 3 3410 1132 NJ 1132 NJ
preplace netloc PS_data_transport|controller_dfreq_M_AXIS_CONTROL 1 3 1 3080 1192n
preplace netloc PS_data_transport|axis_splitter_0_M_AXIS 1 4 1 3500 922n
preplace netloc PS_data_transport|axis_splitter_0_M_AXIS2 1 4 3 N 1202 NJ 1202 NJ
preplace netloc SPM_control_logic|Net 1 9 1 8435 1202n
preplace netloc SPM_control_logic|Net1 1 9 1 N 632
preplace netloc SPM_control_logic|PS_cfg_data_reg_3 1 0 7 4745 1082 5035 1382 NJ 1382 NJ 1382 NJ 1382 6715 1682 7035J
preplace netloc SPM_control_logic|a_clk 1 0 8 4755 1062 5025 602 5295 602 5755 1002 6245 932 6705 1102 7085 1102 7585
preplace netloc SPM_control_logic|axis_AD5791_0_mon0 1 8 2 8115 1242 NJ
preplace netloc SPM_control_logic|axis_AD5791_0_mon1 1 8 2 8095 1402 8465J
preplace netloc SPM_control_logic|axis_AD5791_0_mon2 1 8 2 8085 1222 8425J
preplace netloc SPM_control_logic|axis_AD5791_0_mon3 1 8 2 8105 1212 8445J
preplace netloc SPM_control_logic|axis_AD5791_0_wire_PMD_clk 1 8 1 N 1302
preplace netloc SPM_control_logic|axis_AD5791_0_wire_PMD_dac 1 8 1 N 1342
preplace netloc SPM_control_logic|axis_AD5791_0_wire_PMD_sync 1 8 1 N 1322
preplace netloc SPM_control_logic|axis_spm_control_0_M_AXIS_X0MON_tdata 1 7 3 7595 1122 NJ 1122 NJ
preplace netloc SPM_control_logic|axis_spm_control_0_M_AXIS_XSMON_tdata 1 7 3 7615 1142 NJ 1142 NJ
preplace netloc SPM_control_logic|axis_spm_control_0_M_AXIS_YSMON_tdata 1 7 3 7665 1162 NJ 1162 NJ
preplace netloc SPM_control_logic|axis_spm_control_0_M_AXIS_Z0MON_tdata 1 7 3 7695 1182 NJ 1182 NJ
preplace netloc SPM_control_logic|axis_spm_control_0_M_AXIS_ZSMON_tdata 1 7 3 7635 1102 NJ 1102 NJ
preplace netloc SPM_control_logic|cfg1_1 1 0 6 NJ 1142 NJ 1142 NJ 1142 5765J 1022 NJ 1022 6645
preplace netloc SPM_control_logic|cfg3_to_bias1_data 1 6 1 7125 1582n
preplace netloc SPM_control_logic|cfg3_to_bias2_data 1 6 1 7145 1602n
preplace netloc SPM_control_logic|cfg3_to_bias_data 1 6 1 7035 1472n
preplace netloc SPM_control_logic|cfg3_to_cfg_dac_axis_data 1 7 3 7655 1002 NJ 1002 NJ
preplace netloc SPM_control_logic|cfg3_to_cfg_dac_control_data 1 6 1 7095 1172n
preplace netloc SPM_control_logic|cfg3_to_gvp_program_vector_data 1 2 1 5305 812n
preplace netloc SPM_control_logic|cfg3_to_gvp_setvector_data 1 1 1 5035 662n
preplace netloc SPM_control_logic|cfg3_to_rotmxx_data 1 6 1 7045 1332n
preplace netloc SPM_control_logic|cfg3_to_rotmxy_data 1 6 1 7055 1182n
preplace netloc SPM_control_logic|cfg3_to_slope_x_data 1 6 1 7045 1462n
preplace netloc SPM_control_logic|cfg3_to_slope_y_data 1 6 1 7055 1482n
preplace netloc SPM_control_logic|cfg3_to_x0_data 1 6 1 7105 1502n
preplace netloc SPM_control_logic|cfg3_to_y0_data 1 6 1 7115 1522n
preplace netloc SPM_control_logic|cfg3_to_z0_data 1 6 1 7135 1542n
preplace netloc SPM_control_logic|controller_zservo_enable 1 6 4 NJ 942 7595J 972 NJ 972 NJ
preplace netloc SPM_control_logic|gvp_0_options 1 3 3 5705J 842 NJ 842 6635J
preplace netloc SPM_control_logic|gvp_main_dbg_i 1 9 1 N 1042
preplace netloc SPM_control_logic|gvp_main_dbg_status 1 3 7 5675J 1052 6045J 1072 NJ 1072 NJ 1072 NJ 1072 NJ 1072 8465J
preplace netloc SPM_control_logic|gvp_main_gvp_finished 1 3 7 5685J 1082 NJ 1082 NJ 1082 NJ 1082 NJ 1082 NJ 1082 8435J
preplace netloc SPM_control_logic|gvp_main_gvp_hold 1 3 7 5705J 1042 NJ 1042 NJ 1042 7055J 1022 NJ 1022 NJ 1022 NJ
preplace netloc SPM_control_logic|gvp_main_section 1 9 1 N 1062
preplace netloc SPM_control_logic|xlslice_cfg_dac_axis_Dout 1 7 1 7725J 1432n
preplace netloc SPM_control_logic|xlslice_cfg_dac_mode_Dout 1 7 1 7715J 1412n
preplace netloc SPM_control_logic|xlslice_cfg_dac_send_Dout 1 7 1 7605J 1172n
preplace netloc SPM_control_logic|xlslice_gvp_reset1_Dout 1 2 1 5315J 832n
preplace netloc SPM_control_logic|xlslice_gvp_reset_Dout 1 2 3 5315 612 NJ 612 6105
preplace netloc SPM_control_logic|xlslice_gvp_setvec_1_Dout 1 2 1 5295J 762n
preplace netloc SPM_control_logic|xlslice_gvp_setvec_Dout 1 2 1 5295J 792n
preplace netloc SPM_control_logic|axis_bram_stream_srcs_0_BRAM_PORTA_addr 1 5 1 6665 512n
preplace netloc SPM_control_logic|axis_bram_stream_srcs_0_BRAM_PORTA_clk 1 5 1 6675 492n
preplace netloc SPM_control_logic|axis_bram_stream_srcs_0_BRAM_PORTA_din 1 5 1 6635 532n
preplace netloc SPM_control_logic|axis_bram_stream_srcs_0_BRAM_PORTA_we 1 5 1 6625 552n
preplace netloc SPM_control_logic|gvp_main_store_data 1 3 2 5765J 662 6095
preplace netloc SPM_control_logic|axis_bram_stream_srcs_last_write_addr 1 5 5 6645 592 NJ 592 NJ 592 NJ 592 8455J
preplace netloc SPM_control_logic|axis_splitter_Z_monitor 1 4 6 NJ 1182 6625J 1252 7045J 1232 NJ 1232 NJ 1232 8415J
preplace netloc SPM_control_logic|axis_splitter_ZControlSignalPass_monitor 1 8 2 N 912 NJ
preplace netloc SPM_control_logic|S_AXIS_1 1 0 6 NJ 292 NJ 292 NJ 292 NJ 292 NJ 292 6655
preplace netloc SPM_control_logic|axis_spm_control_0_M_AXIS1 1 7 1 7625 1292n
preplace netloc SPM_control_logic|axis_spm_control_0_M_AXIS2 1 7 1 7675 1312n
preplace netloc SPM_control_logic|cfg3_to_cfg_dac_axis_M_AXIS 1 7 1 7705 1372n
preplace netloc SPM_control_logic|controller_zservo_M_AXIS_CONTROL 1 6 1 7115 882n
preplace netloc SPM_control_logic|BRAM_PORTB_1 1 0 6 4745J 502 NJ 502 NJ 502 5765J 522 6115J 792 6625
preplace netloc SPM_control_logic|gvp_main_M_AXIS_SRCS 1 3 2 NJ 672 N
preplace netloc SPM_control_logic|gvp_main_M_AXIS_index 1 3 2 5715J 652 N
preplace netloc SPM_control_logic|S_AXIS_ch9s_1 1 0 5 NJ 512 NJ 512 NJ 512 NJ 512 N
preplace netloc SPM_control_logic|S_AXIS_chAs_1 1 0 5 NJ 532 NJ 532 NJ 532 NJ 532 N
preplace netloc SPM_control_logic|S_AXIS_chBs_1 1 0 5 NJ 552 NJ 552 NJ 552 NJ 552 N
preplace netloc SPM_control_logic|S_AXIS_chCs_1 1 0 5 NJ 572 NJ 572 NJ 572 NJ 572 N
preplace netloc SPM_control_logic|gvp_main_M_AXIS_gvp_time 1 3 2 5705J 642 6075
preplace netloc SPM_control_logic|S_AXIS_chEs_1 1 0 5 NJ 592 NJ 592 NJ 592 NJ 592 6135
preplace netloc SPM_control_logic|gvp_main_M_AXIS_X 1 3 1 5775 712n
preplace netloc SPM_control_logic|gvp_main_M_AXIS_Y 1 3 1 5725 732n
preplace netloc SPM_control_logic|axis_splitter_U_M_AXIS 1 4 1 6125 412n
preplace netloc SPM_control_logic|axis_splitter_X_M_AXIS 1 4 1 6045 352n
preplace netloc SPM_control_logic|axis_splitter_Y_M_AXIS 1 4 1 6065 372n
preplace netloc SPM_control_logic|axis_splitter_X_M_AXIS2 1 4 3 6045J 812 NJ 812 7145
preplace netloc SPM_control_logic|axis_splitter_Y_M_AXIS2 1 4 3 NJ 922 6625J 1092 7105
preplace netloc SPM_control_logic|gvp_main_M_AXIS_Z 1 3 4 5695J 1392 NJ 1392 NJ 1392 7035J
preplace netloc SPM_control_logic|axis_splitter_Z_M_AXIS 1 4 1 6085 392n
preplace netloc SPM_control_logic|axis_spm_control_M_AXIS3 1 3 5 5775 1032 NJ 1032 NJ 1032 NJ 1032 7575
preplace netloc SPM_control_logic|axis_splitter_Z_M_AXIS2 1 4 4 NJ 1162 6645J 1242 NJ 1242 7645
preplace netloc SPM_control_logic|gvp_main_M_AXIS_U 1 3 4 5725J 682 6055J 822 NJ 822 7135J
preplace netloc SPM_control_logic|axis_spm_control_M_AXIS4 1 3 5 5785 1062 NJ 1062 NJ 1062 NJ 1062 7565
preplace netloc SPM_control_logic|axis_splitter_U_M_AXIS2 1 4 4 6135J 1052 NJ 1052 NJ 1052 7685
preplace netloc SPM_control_logic|controller_zservo_M_AXIS_PASS 1 6 2 NJ 922 7575
preplace netloc SPM_control_logic|axis_splitter_ZControlSignalPass_M_AXIS 1 4 5 6245 282 NJ 282 NJ 282 NJ 282 8085
preplace netloc SPM_control_logic|S_AXIS_ch5s_1 1 0 4 4755J 492 NJ 492 NJ 492 5705
preplace netloc SPM_control_logic|axis_splitter_0_M_AXIS 1 4 1 6115J 412n
levelinfo -pg 1 -10 130 390 920 1780 4865 8995 9310 9680 9880
levelinfo -hier PS_data_transport * 1830 2300 2820 3260 3720 4050 *
levelinfo -hier SPM_control_logic * 4885 5165 5495 5915 6435 6875 7355 7905 8265 *
pagesize -pg 1 -db -bbox -sgen -180 0 10040 4250
pagesize -hier PS_data_transport -db -bbox -sgen 1630 402 4270 2152
pagesize -hier SPM_control_logic -db -bbox -sgen 4715 272 8495 2542
"
}

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
common::send_gid_msg -ssname BD::TCL -id 2050 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."

  close_bd_design $design_name 
}
# End of cr_bd_system()
cr_bd_system ""
set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ] 
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ] 

set idrFlowPropertiesConstraints ""
catch {
 set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
 set_param runs.disableIDRFlowPropertyConstraints 1
}

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
    create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2023} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  set_property flow "Vivado Synthesis 2023" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {

}

puts "INFO: Project created:${_xil_proj_name_}"
# Create 'drc_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
create_dashboard_gadget -name {drc_1} -type drc
}
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj

# Create 'methodology_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
create_dashboard_gadget -name {methodology_1} -type methodology
}
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj

# Create 'power_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
create_dashboard_gadget -name {power_1} -type power
}
set obj [get_dashboard_gadgets [ list "power_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj

# Create 'timing_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
create_dashboard_gadget -name {timing_1} -type timing
}
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj

# Create 'utilization_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
create_dashboard_gadget -name {utilization_1} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
set_property -name "run.step" -value "synth_design" -objects $obj
set_property -name "run.type" -value "synthesis" -objects $obj

# Create 'utilization_2' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
create_dashboard_gadget -name {utilization_2} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj

move_dashboard_gadget -name {utilization_1} -row 0 -col 0
move_dashboard_gadget -name {power_1} -row 1 -col 0
move_dashboard_gadget -name {drc_1} -row 2 -col 0
move_dashboard_gadget -name {timing_1} -row 0 -col 1
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
